Computer Architecture and

Organization
Course Code CSE2003

Subject Guide: Dr. Aprna Tripathi

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Course Objectives:
• The objectives of this course are:
• to provide basic concepts of computer architecture and
organization
• to impart the knowledge of implementation of arithmetic
operations in the computer.
• to develop a deeper understanding of the hardware
environment upon which all processing are carried out.
• to provide knowledge about internals of memory system,
interfacing techniques and subsystem devices.

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Course Outcomes:
• A student who successfully fulfills the course
requirements will be able to:
1. Identify and explain the building blocks of computer.
2. Recognize addressing modes, and data/instruction
formats.
3. Perform the arithmetic operations using various
algorithms and number systems.
4. Design the single cycle data path for an instruction
format for a given architecture.
5. Compare various cache memory mapping techniques.
6. Explain memory control, direct memory access,
interrupts, and memory organization.
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Student Outcomes (SO):
a) An ability to apply the knowledge of mathematics,
science and computing appropriate to the discipline
b) An ability to analyze a problem, identify and
define the computing requirements appropriate to
its solution.
c) An ability to design, implement and evaluate a
system / computer‐based system, process,
component or program to meet desired needs

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Assessment Pattern:
• At least one assignment for each Module
• At least one tutorial per module
• At least four quiz
• Quiz can be conducted before announcement
• In final assessment
• Tutorial- 10
• Assignment- 10
• Quiz – 10
• Group Activity – 05

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Text Books:
The main text books are:
1. Computer Organization Authors: Carl Hamacher, Zvonko
Vranesic and Safwat Zaky Publisher: McGraw Hill
2. Computer Organization and Architecture: Designing for
Performance Authors: William Stallings Publisher:
Prentice-Hall India

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Reference Books:
1. David A. Patterson and John L. Hennessy “Computer
Organization and Design-The Hardware/Software
Interface”, Morgan Kaufmann, 5th edition, 2011.
2. James P Hayes, “Computer Architecture and Organization”,
Mc Graw Hill, 3rd Edition, 2012, ISBN:9781259028564.

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Module-2
(Data Representation and Computer Arithmetic )
• In this Module, we have lectures on
• Data Representation and Computer Arithmetic
• Fixed point representation of numbers
• algorithms for arithmetic operations:
• Addition
• subtraction
• multiplication
• division (restoring and non-restoring)-
• Floating point representation with IEEE standards and
algorithms for common arithmetic operations
• conversion between integer and real numbers.

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Exercise

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Solution
• For the first operand,
• It uses indexed addressing mode.
• Thus, one memory cycle will be needed to fetch the operand.
•
• For the second operand,
• It uses indirect addressing mode.
• Thus, two memory cycles will be needed to fetch the operand.
•
• After fetching the two operands,
• The operands will be added and result is stored back in the memory.
• Thus, one memory cycle will be needed to store the result.
•
• Total number of memory cycles needed
• =1+2+1
• =4

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 Lecture -1
Data Representation and Computer Arithmetic

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 Lecture 7
Objectives & Teaching Learning Material
• Session Objectives
• To tell about importance of each representation of data such
as signed, unsigned, 1’s complement and 2’s complement
• Teaching Learning Material
• Online teaching learning tools, Presentation slides
 Binary

Octal
Fixed Point
Instructions

Numerical Decimal
Information
Floating Point
Data Hexa
Non Numeric Decimal
Recap Exercise
FF and AB ( hexadecimal number system )
F X B = ? ()16 = () 8 = ()10 = () 2

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Integer /Fixed point representations
there are different binary representations for integers
possible qualifications:
1. positive numbers only
2. positive and negative numbers
3. ease of human readability
4. speed of computer operations
there are 4 commonly known (1 not common) integer representations.
All have been used at various times for various reasons.
1. unsigned
2. sign magnitude
3. one's complement
4. two's complement
5. biased (not commonly known)
Question: virtually all modern computers operate based on 2's complement
representation. why?
1. hardware is faster
2. hardware is simpler (which makes it faster)
Unsigned
the standard binary encoding already given only positive values range:
0 to 2n -1 for n bits Unsigned binary numbers are, by definition,
positive numbers and thus do not require an
example: 4 bits, values 0 to 15
arithmetic sign
n=4, 24 -1 is 15
 Sign Magnitude
A human readable way of getting both positive and negative integers.

The hardware that does arithmetic on sign magnitude integers is not fast, and it is
more complex than the hardware that does arithmetic on 1's comp. and 2's comp.
integers.
Use 1 bit of integer to represent the sign of the integer
let sign bit of 0 be positive, 1 be negative.
The rest of the integer is a magnitude, using same encoding as unsigned
integers Signed numbers, on the other hand, require an
example: 4 bits arithmetic sign. The most significant bit of a
0101 is 5 binary number is used to represent the sign bit.
1101 is -5 If the sign bit is equal to zero, the signed binary
number is positive; otherwise, it is negative.

To get the additive inverse of a number, just flip (not, invert, complement,
negate) the sign bit.
Sign Magnitude
• The most significant bit (MSB) represents the sign.
• A 1 in the MSB bit position denotes a negative number; a 0
denotes a positive number.
• The remaining n 1 bits are preserved and represent the magnitude
of the number.
• The following examples illustrate the sign–magnitude
representation:

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 range: -2n-1 + 1 to 2 n-1 -1
where n is the number of bits 4 bits, -7 to +7
n=4,
- 23 + 1 to 23 - 1
-8 + 1 to 8 - 1

Things to Notice:
Because of the sign bit, there are 2 representations for 0.This is a problem for
hardware. . .
0000 is 0, 1000 is 0

The computer must do all calculations such that they come out correctly and
the same whichever representation is used.
One's Complement
historically important, and we use this representation to get 2's complement
integers.
Now, nobody builds machines that are based on 1's comp. integers.

In the past, early computers built by Semour Cray (while at CDC) were
based on 1's comp. integers.

positive integers use the same representation as unsigned.

00000 is 0
00111 is 7, etc.

negation (finding an additive inverse) is done by taking a bit wise

complement of the positive representation.
One's Complement

• In the one’s-complement form, the MSB represents the sign.

• The remaining bits are inverted for negative numbers only.
• Positive numbers are represented in the same way as in the
sign–magnitude method.
• The following examples illustrate the one’s complement
representation:

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 One's Complement
COMPLEMENT. INVERT. NOT. FLIP. NEGATE.
a logical operation done on a single bit
the complement of 1 is 0.
the complement of 0 is 1.

EXAMPLES: 11100
This must be a negative number.
To find out which, find the additive inverse!
00011 is +3 by sight,
so 11100 must be -3

Things to notice:
1. any negative number will have a 1 in the MSB.
2. there are 2 representations for 0,
00000 and 11111.
 Two's Complement
• In the two’s-complement method, the negative numbers are
inverted and augmented by one.
• The MSB is the sign bit.
• The positive numbers are similar to those of the sign–magnitude
method.
• The following examples illustrate the one’s-complement
representation:

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Exercise

Find the value of +36 and -36 using 1’s complement

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 Two's Complement
A variation on 1's complement that does NOT have 2 representations for 0.
This makes the hardware that does arithmetic faster than for the other
representations.
A 3 bit example:
bit pattern: 100 101 110 111 000 001 010 011
1's comp: -3 -2 -1 0 0 1 2 3
2's comp.: -4 -3 -2 -1 0 1 2 3

the negative values are all "slid" down by one, eliminating the extra zero
representation
how to get an integer in 2's comp. representation:

positive values are the same as for sign/mag and 1's comp.

They will have a 0 in the MSB (but it is NOT a sign bit!) positive:
just write down the value as before negative:

To get the additive inverse of a 2's comp integer,

1. take the 1's comp.
2. add 1
EXAMPLE:
What decimal value does the two's complement 110011 represent?

It must be a negative number, since the most significant bit is a 1.Therefore,

find the additive inverse:

Therefore, it's additive inverse (110011) must be -13.

Exercise

Find the value of +36 and -36 using 2’s complement

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A Number circle representation for 3-bit two’s
complement number
Negative Number Representation

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Summary

Data Representations
Unsigned
Signed Magnitude
1’s Complement
2’s Complement
Assignment
• Submit a Case Study report on “ Calculator
Arithmetic Using Binary Coded Decimal”
• Ref: Vincent .P. Heuring, Harry F. Jordan “ Computer
System design and Architecture” Pearson, 2nd Edition,
2003
Lecture : Addition & Subtraction
 Re-Cap
1. Tell, how many number unsigned numbers can be generated
from 4 bits.
2. Specify the common issue in signed numbers and I’s
complement representation
3. State a reason why modern computers are using 2’s
complement representation for their arithmetic operations

4. List various representations of Data

 Lecture -8
Objectives & Teaching Learning Material
• Session Objectives
• To provide knowledge on character representations
• To teach procedure for addition and subtraction
• To provide knowledge on differences between
overflow/underflow
• Teaching Learning Material
• Online teaching learning tools, Presentation slides
Character Representation
Everything represented by a computer is represented by binary sequences.

A common non-integer needed to be represented is characters.

A standard code ASCII (American Standard for Computer Information

Interchange) defines what character is represented by each sequence.

examples:
0100 0001 is 41 (hex) or 65 (decimal). It represents `A'
0100 0010 is 42 (hex) or 66 (decimal). It represents `B'
 Algorithm: character string  integer

Integer = 0 the steps:

While there are more characters for `3' `5' `4'
get character read `3'
digit character - 48 translate `3' to 3
integer  integer * 10 + digit read `5'
translate `5' to 5
integer = 3 * 10 + 5 = 35
read `4'
translate `4' to 4
integer = 35 * 10 + 4 = 354
Addition
Rules for the addition

0+0=0
1+0=1

1 + 1 = 2 which is 10 in binary, sum is 0 and carry the 1

1 + 1 + 1 = 3 sum is 1, and carry a 1

a 0011
+b +0 0 0 1
sum 0100
Unsigned vs. Signed Addition
Hardware is identical for result bits all between unsigned and signed
adder.
Difference in the is only detection of overflows, that is of results which
cannot be represented in the given format

Two’s complement addition is extremely Two s similar to unsigned

addition
Overflows for Unsigned Addition

1 1 0 0 1 0 0 1 20110

1 1 0 0 1 0 0 0 20010

1 1 0 0 1 0 0 0 1 40110
Addition Using the One’s-Complement
Method
This method uses the simplicity of one’s complement in representing the
negative of a number.
The process of addition using the one’s-complement method may be simple
or complicated, depending on the numbers being used.
In certain cases, an additional correction may need to be carried out to arrive
at the correct answer.
The following examples illustrate one’s-complement additions for four cases

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2’s Complement Addition
• Just like normal positive binary addition
• You MUST restrict the number of bits
• IGNORE any overflow bits
• maintain bit-size restriction
Addition Using the Two’s-Complement
Method
• Using the same examples as above, the two’s-complement
method is implemented.
• Addition by this method is always correct when the carryout
from the sign bit is ignored.
• This is illustrated by examples showing four cases of
addition for the same numbers from previous examples of
one’s-complement method addition.

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Positive Addition Example
1210 + 410 = 1610

Assuming 2’s complement

000010102 1210
+000000102 + 410
000011002 1610
Negative Addition Example
-1210 + -410 = -1610

111101002 -1210
+111111002 + -410
111100002 -1610

NOTE: We ignored the last overflow bit

on the left!
Hardware for Addition and Subtraction
Addition and Subtraction of Signed- Magnitude number

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 Solve the following
• Show the binary addition of -14 + -3 = -17
Subtraction
• To subtract one number (subtrahend) from another
(minuend), take the omplementof the subtrahend
and add it to the minuend.
• If the numbers are ones (twos) complement
numbers, take the ones (twos) complement of the
subtrahend and add it to the minuend.
Subtraction Using the Two’s-
Complement Method
• The process of subtraction is carried out similarly to
the addition process.
• The two’s complement of the subtrahend is
computed and added to the minuend.
• The results desired are obtained after ignoring the
carryout from the sign bit.

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Subtraction Example
1610 – 410 = 1610 + -410 = 1210

000100002
+111111002
000011002

NOTE: We ignored the last overflow bit

on the left!
 Solve the following
• Show the binary subtraction of 23 – 10 = 13
Overflow / Underflow Problem
• Addition and bit-size restriction allow for possible
overflow / underflow
• Overflow – when the addition of two binary
numbers yields a result that is greater than the
maximum possible value
• Underflow – when the addition/subtraction of two
binary numbers yields a result that is less than the
minimum possible value
Overflow

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Overflow / Underflow Problem

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How to check overflow/ underflow
Carry out Sign bit condition
0 0 No overflow and
underflow
1 1 No overflow and
underflow
0 1 Overflow
1 0 underflow

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Overflow Example
• Assume 4-bit restriction and 2’s complement
• Maximum possible value: 24-1 – 1 = 7

610 + 310 = 910

01102 610
+00112 +310
10012 -710  not good!
Underflow Example
• Assume 4-bit restriction and 2’s complement
• Minimum possible value: -(24-1) = -8

-510 + -510 = -1010

10112 -510
+10112 +-510
01102 610  not good!
Exercise based on overflow/underflow
• Add the following using 2’s complement
representation in 8-bit register. Also check
overflow/underflow
i. -27 + (-101)
ii. +45 + (-65)
iii. +27 + 101
iv. -103 +(-69)

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 -27 +(-101)

• Carry into sign bit =1

• Carry out of sign bit =1
• No overflow
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+45 +(-65)

• Carry into sign bit =0

• Carry out of sign bit =0
• No overflow
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-103 + (-69)

• Carry into sign bit =0

• Carry out of sign bit =1
• Underflow
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+27 +101

• Carry into sign bit =1

• Carry out of sign bit =0
• Overflow
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Signed Overflow

carry and overflow

carry generated, but no overflow

no carry and overflow

no carry and no overflow
Summary

Character representation
 Addition
Subtraction
Over flow/Under flow
Assignment
• Submit a Case Study report on “ Calculator
Arithmetic Using Binary Coded Decimal”
• Ref: Vincent .P. Heuring, Harry F. Jordan “ Computer
System design and Architecture” Pearson, 2nd Edition,
2003
References
Text Book
• M. M. Mano, Computer System Architecture,
Prentice-Hall,2004
Lecture : Binary Multiplication
 Re-Cap

1. Tell, how many number unsigned numbers can be generated

from 4 bits.
2. Specify the common issue in signed numbers and I’s
complement representation
3. State a reason why modern computers are using 2’s
complement representation for their arithmetic operations

4. List various representations of Data

 Objectives & Teaching Learning Material

• Session Objectives
• To provide knowledge on character representations
• To teach procedure for addition and subtraction
• To provide knowledge on differences between
overflow/underflow
• Teaching Learning Material
• LCD, White board Marker, Presentation slides
Multiplication
0x0=0
0x1=0
1x0=0
1x1=1
 Multiply (unsigned)

• Paper and pencil example (unsigned):

Multiplicand 1000
Multiplier 1001
1000
0000
0000
1000
Product 01001000
• m bits x n bits = m+n bit product
• various versions of multiply hardware & algorithm:
•successive refinement
Hardware for multiply operation

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Flowchart for Multiply Operation

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A Serial Multiplier
Perform multiplication for 11 x 13 using unsigned integer 2's
compliment multiplication algorithm
Multiplicand = 11  Binary equivalent is 1011M
Multiplier = 13  Binary equivalent is 1101Q

When LSB of Q is 0 only Shift, otherwise A <- A + M and then Shift Right CAQ
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 Multiplying Negative Numbers
Sign extension is
shown in blue For a negative multiplier, a
straightforward solution is to form the 2’s-
complement of both the multiplier and the
10011 (-13) multiplicand and proceed as in the case
Multiplicand M of a positive multiplier.
X 01011 (+11)
Multiplier Q This is possible because
complementation of both operands does
------------------------------------------------- not change the value or the sign of the
1111110011 product.
111110011
00000000 A technique that works equally well for
1110011 both negative and positive multipliers –
000000 Booth algorithm.
--------------------------------------------------
1 1 0 1 1 1 0 0 0 1 (-143) Product P

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Multiplying Negative Numbers

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Examples
• Multiply the following using serial multiplier
algorithm
• 15 x 20
• 55 x 60
• 7 x 3 using 8 bit multiplier
Summary

Multiplication
 Serial Multiplier flow chart
 Example 11 x 13
 Examples
Assignment
• Show that 7x3 =3x7 using Unsigned serial
multiplier algorithm
Lecture : Binary Multiplication-Booth’s
Algorithm
 Objectives & Teaching Learning Material

• Session Objectives
• To provide knowledge on Signed multiplications
• To teach procedure for binary multiplication using Booth’s
Algorithm
• To solve the problems on Booth’s multiplication
• Teaching Learning Material
• LCD, White board Marker, Presentation slides
 Re-Cap
1. What is the name of unsigned multiplication algorithm

2. In Serial multiplier, If Qo =1 what would be the next task to be

performed?
3. In Serial multiplier, If Qo =0 what would be the next task to be
performed?

4. Where will be add and shift or shift loop process stopped?

Andrew Donald Booth

was a British electrical

engineer, physicist and computer
scientist who led the invention of
the magnetic drum memory for
computers and invented Booth's
multiplication algorithm.[Wikipedia]

(February 11, 1918 – November 29, 2009)

Booth Multiplication Algorithm

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Hardware of Booth Multiplication Algorithm

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Booth
Algorithm for
Multiplication
of signed 2’s
complement

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 Multiplication Example
The sign bit of
accumulator not
changed after
shift operation

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Examples
• Multiply the following using Booth’s algorithm
7 x -3
-7 x 3
-7 x -3
11 x 13
-11 x 13
11 x -13
-11 x -13
Summary

Multiplication
 Booth’s flow chart
 Example 7 x 3
 Examples
Programming Assignment
• Develop a Simulator to perform multiplication
operation two signed number and display the step
by step result.
Lecture : 2’s Complement Division
 Re-Cap

1. Name the algorithm which is used for singed multiplication

using 2’s Complement
2. Tell something about Booth
3. What are the two bits are required to make decision after the
initialization
 Objectives & Teaching Learning Material

• Session Objectives
• To provide knowledge on Signed multiplications
• To teach procedure for binary multiplication using Booth’s
Algorithm
• To solve the problems on Booth’s multiplication
• Teaching Learning Material
• LCD, White board Marker, Presentation slides
Division of Unsigned Binary Integers

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 Introduction
 More complex than multiplication

 Negative numbers are really bad!

 Based on long division

Division algorithms are based on the following relation:

D = V*Q + R
where :
D = dividend
V = divisor
Q = quotient
R = remainder
 The algorithm can be summarized as follows

1. Load the divisor into the M register and the dividend into the A , Q registers. The
Dividend must be expressed as a 2n- bit two's compliment numbers. Several
examples of this approch are shown in following example.
2. Shift A, Q left 1 bit position.
3. If M and A have the same signs , Perform AA-M ; oterwise ,A A+M.
4. The above operation is successful if the sign of A is the same before and after
the operation.
a) If the operation is successful or (A=0 AND Q= 0) ,then Set Q0  1
b) If the operation is unsuccessful and (A!=0 or Q!=0),then Q00 and restore
the privious value of A.
5. Repeat steps 2 through 4 as many as there are bit positions in Q.
6. The reminder is in A. If ht e signs if the divisor and dividend were the same,
Then the quotient is in Q; Otherwise, the correct quotient is the two's
complement of Q.
 -7/ 3

A Q Action
1111 1001 Initial Value
1111 0010 Shift
0010 Add
1111 0010 Restore
1110 0100 Shift
0001 Add
1110 0100 Restore
1100 1000 Shift
1111 Add
1111 1001 Set Q0 =1
1111 0010 Shift
0010 Add
1111 0010 Restore
Examples
• Divide the following using 2’s Complement
Division Algorithm
7 / -3
-7 / 3
-7 /-3
11 / 13
-11 / 13
11 / -13
-11 / -13
Summary

 Unsigned Division
 Introduction to Unsigned division algorithm
 Flow Chart
Interpretation of an example to flowchart
 Sample problems & Solutions
Programming Assignment
• Develop a Simulator to perform Division algorithm
using 2’s complement division algorithms display
the step by step result.
Lecture: Floating Point Numbers
 Re-Cap
1. Distinguish between Binary multiplication and division in the
perspective of implementation
2. In Binary Division, If A>0 then what would be the next step ?

3. 2. In Binary Division, If A<0 then what would be the next step

?
4. This algorithm uses which kind shift?
 Objectives & Teaching Learning Material

• Session Objectives
• To teach the difference between fixed point and floating
point
• To provide knowledge on various floating point
representations
• To introduce the terms for the various parts floating point
representation

• Teaching Learning Material

• Online learning tools Presentation slides
Introduction
Numbers with fractions Could be done in pure
binary
1001.1010 = 24 + 20 +2-1 + 2-3 =9.625

Where is the binary point?

Fixed?
Very limited
Moving?
How do you show where it is?
Fractional Binary Numbers
• Representation
– Bits to right of “binary point” represent
fractional powers of 2
– Represents rational number:

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Floating-Point Representation

+ 6132.789 is represented in floating-point with

a fraction and an exponent as follows:

Fraction Exponent
+0.6132789 +04

Scientific notation : + 0.6132789  10+4

Floating-Point Representation

Floating point is always interpreted as: m  re

Floating point binary number uses base 2 for the exponent.

For example:
Binary number +1001.11
Fraction(8 bits) Exponent (6 bits)
01001110 000100

The fraction has a 0 in the leftmost position to denote positive.

m  2e = + (.1001110)2  2+4
• +/- .significand x 2exponent
• Point is actually fixed between sign bit and body of
mantissa
• Exponent indicates place value (point position)

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 • Convert the following number;37.75 into floating point format to fit
in 32 bit register.
– Convert the number from decimal into binary
• 100101.11
– Normalize all digits including the fraction to determine the
exponent.
• 1.0010111 x 25

0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0

sign EXP Significant

 Floating-Point Representation
• 32-bit floating point format.
• Leftmost bit = sign bit (0 positive or 1 negative).
• Exponent in the next 8 bits. Use a biased representation.
• Final portion of word (23 bits in this example) is the significand
(sometimes called mantissa).
Signs for Floating Point

Mantissa is stored in 2s compliment

Exponent is in excess or biased notation
e.g. Excess (bias) 128 means 8 bit exponent
field Pure value range 0-255
Subtract 128 to get correct value Range -128 to
+127
Normalization

• FP numbers are usually normalized

• i.e. exponent is adjusted so that leading bit (MSB) of
mantissa is 1
• Since it is always 1 there is no need to store it
• (Scientific notation where numbers are normalized to give
a single digit before the decimal point
e.g. 3.123 x 103)
FP Ranges

For a 32 bit number

8 bit exponent
+/- 2256  1.5 x 1077
Accuracy
The effect of changing lsb of mantissa
23 bit mantissa 2-23  1.2 x 10-7
About 6 decimal places
Expressible Numbers
Density of Floating Point Numbers
IEEE standard for Floating-Point Arithmetic (IEEE
754)
• The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a
technical standard for floating-point computation which was
established in 1985 by the Institute of Electrical and Electronics
Engineers (IEEE).
• IEEE 754 has 3 basic components:
• The Sign of Mantissa –
This is as simple as the name. 0 represents a positive number
while 1 represents a negative number.
• The Biased exponent –
The exponent field needs to represent both positive and negative
exponents. A bias is added to the actual exponent in order to get
the stored exponent.
• The Normalized Mantissa –
The mantissa is part of a number in scientific notation or a
floating-point number, consisting of its significant digits. Here we
have only 2 digits, i.e. O and 1. So a normalized mantissa is one
with only one 1 to the left of the decimal.

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IEEE 754
Standard for floating point storage
32 and 64 bit standards
8 and 11 bit exponent respectively
Extended formats (both mantissa and exponent) for
intermediate results
Exercise

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Exercise

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Exercise

Computer Architecture and Organization (CSE-

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Exercise

• Answer should be –1.5 × 2–7 = –0.01171875

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Special Values
• Special Values: IEEE has reserved some values that can
ambiguity.
• Zero –
Zero is a special value denoted with an exponent and mantissa of 0. -
0 and +0 are distinct values, though they both are equal.
• Denormalised –
If the exponent is all zeros, but the mantissa is not then the value is a
denormalized number. This means this number does not have an
assumed leading one before the binary point.
• Infinity –
The values +infinity and -infinity are denoted with an exponent of
all ones and a mantissa of all zeros. The sign bit distinguishes
between negative infinity and positive infinity. Operations with
infinite values are well defined in IEEE.
• Not A Number (NAN) –
The value NAN is used to represent a value that is an error. This is
represented when exponent field is all ones with a zero sign bit or a
mantissa that it not 1 followed by zeros. This is a special value that
might be used to denote a variable that doesn’t yet hold a value.

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Special Numbers

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Exercise
• Find more special operations

Computer Architecture and Organization (CSE-

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Exercise
• Find more
special
operations

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Assignment
• Represent the following numbers into various
IEEE754 formats
• 12312.132131
• 3483.343
• 23232.32492
FP Arithmetic +/-
• Check for zeros
• Align significands (adjusting exponents)
• Add or subtract significands
• Normalize result
FP Arithmetic +/-
When adding or subtracting floating-point numbers, their mantissas must be shifted
with respect to each other if their exponents differ.

2.9400 × 102 0.0294 × 104

+ 4.3100 × 104 + 4.3100 × 104
------------------------------- ----------------------------------

4.3100 × 104

Add/Subtract Rule
1.Choose the number with the smaller exponent and shift its mantissa right a number of
steps equal to the difference in exponents.
2.Set the exponent of the result equal to the larger exponent.
3.Perform addition/subtraction on the mantissas and determine the sign of the result.
4.Normalize the resulting value, if necessary.
FP Addition & Subtraction Flowchart
FP Addition & Subtraction Flowchart

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FP Addition & Subtraction Flowchart

This is a block diagram of a hardware

implementation for the addition and
subtraction of 32-bit floating-point
operands.

The first step is to compare exponents to

determine how far to shift the mantissa of
the number with the smaller exponent.

The shift-count value, n, is determined by

the 8-bit subtractor circuit in the upper
left corner of the figure.

The magnitude of the difference E’A− E’B,

or n, is sent to the SHIFTER unit.

If n is larger than the number of

significant bits of the operands, then the
answer is essentially the larger operand
(except for guard and sticky-bit
considerations in rounding), and shortcuts
can be taken in deriving the result.
FP Addition & Subtraction Flowchart

The sign of the difference that results from

comparing exponents determines which
mantissa is to be shifted.

Therefore, in step 1, the sign is sent to the

SWAP network in the upper right corner.

If the sign is 0, then E’A≥ E’B and the

mantissas MA
and MB are sent straight through the SWAP
network. This results in MB being sent to
the SHIFTER, to be shifted n positions to
the right. The other mantissa, MA, is sent
directly to the mantissa adder/subtractor.

If the sign is 1, then E’A < E’B and the

mantissas are swapped before they are sent
to the SHIFTER.
FP Addition & Subtraction Flowchart

Step 2 is performed by the two-way

multiplexer, MUX, near the bottom
left corner of the figure.

The exponent of the result, E, is

tentatively determined as E’A if E’A≥
E’B, or
E’B if E’A < EB, based on the sign of
the difference resulting from
comparing exponents in step 1.
FP Addition & Subtraction Flowchart

Step 3 involves the major component, the

mantissa adder/subtractor in the middle of the
figure.

The CONTROL logic determines whether the

mantissas are to be added or subtracted. This
is decided by the signs of the operands (SA and
SB) and the operation (Add or Subtract) that is
to be performed on the operands.

The CONTROL logic also determines the sign

of the result, SR. For example, if A is negative
(SA = 1), B is positive (SB = 0), and
the operation is A − B, then the mantissas are
added and the sign of the result is negative (SR
= 1).
On the other hand, if A and B are both positive
and the operation is A − B, then the mantissas
are subtracted.
FP Addition & Subtraction Flowchart

The sign of the result, SR, now depends

on the mantissa subtraction operation.
For instance, if E’A > E’B, then M = MA −
(shifted MB) and the resulting number is
positive. But if E’B > E’A, then M = MB −
(shifted MA) and the result is negative.

This example shows that the sign from

the exponent comparison is also
required as an input to the CONTROL
network. When E’A = E’B and the
mantissas are subtracted, the sign of the
mantissa adder/subtractor output
determines the sign of the result.
FP Addition & Subtraction Flowchart

Step 4 of the Add/Subtract rule consists of

normalizing the result of step 3 by shifting M
to the right or to the left, as appropriate.
The number of leading zeros in M determines
the number of bit shifts, X , to be applied to M.

The normalized value is rounded to generate

the 24-bit mantissa, MR, of the result.

The value X is also subtracted from the

tentative result exponent E’ to generate the
true result exponent, E’R.

Note that only a single right shift might be

needed to normalize the result. This would be
the case if two mantissas of the form 1.xx . . .
were added. The vector M would then have
the form 1x.xx . . . .
FP Arithmetic x/
• Check for zero
• Add/subtract exponents
• Multiply/divide significands (watch sign)
• Normalize
• Round
• All intermediate results should be in double length
storage
Floating Point Multiplication Example
• Consider multiplying: 1.0102 × 2–1 by –1.1102 × 2–2
• As before, we assume 4 bits of precision (or 3 bits of
fraction)
• Unlike addition, we add the exponents of the
operands
• Result exponent value = (–1) + (–2) = –3
• Using the biased representation: EZ = EX + EY – Bias
• EX = (–1) + 127 = 126 (Bias = 127 for SP) 1.010
• EY = (–2) + 127 = 125 ×
1.110
• EZ = 126 + 125 – 127 = 124 (value = –3) 0000
• Now, multiply the significands: 1010
1010
(1.010)2 × (1.110)2 = (10.001100)2 1010
3-bit fraction 3-bit fraction 6-bit fraction 10001100
Multiplication Example – cont’d
• Since sign SX ≠ SY, sign of product SZ = 1 (negative)
• So, 1.0102 × 2–1 × –1.1102 × 2–2 = –10. 0011002 × 2–3
• However, result: –10. 0011002 × 2–3 is NOT normalized
• Normalize: 10. 0011002 × 2–3 = 1.00011002 × 2–2
• Shift right by 1 bit and increment the exponent
• At most 1 bit can be shifted right … Why?
• Round the significand to nearest:
1.000 1100
1.00011002 ≈ 1.0012 (3-bit fraction) + 1
Result ≈ –1. 0012 × 2–2 (normalized) 1.001
• Detect overflow / underflow
• No overflow / underflow because exponent is within range
 Floating Point Multiplication
Start
Biased Exponent Addition
1. Add the biased exponents of the two numbers, subtracting EZ = EX + EY – Bias
the bias from the sum to get the new biased exponent
Result sign SZ = SX xor SY can be
2. Multiply the significands. Set the result sign to positive if computed independently
operands have same sign, and negative otherwise

Since the operand significands 1.FX

3. Normalize the product if necessary, shifting its significand and 1.FY are ≥ 1 and < 2, their
right and incrementing the exponent product is ≥ 1 and < 4.
To normalize product, we need to
4. Round the significand to the appropriate number of bits, and shift right by 1 bit only and
renormalize if rounding generates a carry increment exponent

Rounding either truncates

Overflow or yes
Exception fraction, or adds a 1 to least
underflow?
significant fraction bit
no
Done
Floating Point Multiplication
Floating Point Division
Assignment
• Represent the following numbers into various
IEEE754 formats
• 12312.132131
• 3483.343
• 23232.32492
Summary

 Introduction
 Floating point Representation
 Examples
 Normalization
 IEEE formats
Floating point Arithmetic
 Floating point Addition & Subtraction
Floating point Multiplication & Division
References
Text Book
• William Stallings “Computer Organization and
architecture” Prentice Hall, 7th edition, 2006
References
Text Book
• M. M. Mano, Computer System Architecture,
Prentice-Hall,2004