213722, 9:08 AM. Chapter 6 Parallel VO ports Chapter 6; Parallel 1/0 ports SonathanValvano and Ramesh Verbal ew zee 0 reps na Sn emer We wilt pny single epfng ett nde wil hee he og ‘prom ing lye Learning Objectives: ‘Know whats parallel port {now how api ean be ether input or output as specified by the direction register + wth steps oquied tint Know how 1 acess 10 registers na tiendly manner no how read dala or inp port ie a parallel port ‘Knowhow to write data to an ouput port ‘Koss how to use the lagi analyzer in the silat i 6 nmi Pr Pr, Men eden 6.0. Introduction ‘ur Sanguine will he pull prc GPLO, abawing so eshags dg! ntmatin wih se extemal worl Frm he ey exigent th ton wl beeen th Caer ine reer we baggage tat te voy ast or sein rp operon oo system eve etuging hl edge no he se Da Pr tft se aera aechd oie soem eri bal Inc hg epee he 0 pa coninaons ote TACT rca. The ear fntn of pn 8 pec pat 1. es pbs ale een Fo un, pet FA nd PO i leet i {lan ouput panne, hr ac iu! gan art hrs prow of coon Tis Te Acie Covey TAG), Storie athe EEE 116 1, aad et ses pr ed ogra ad deb he actoerair bee ach mcweanellet Use ive por ifthe JTAG ete. orn En ghia pon AG pn ee gg ne wb ss + usr Univra arynchronoussccbr/tanemiter fs Synchronous seal iterace +e Iveraugented tet ne etd erp i cp 2 pt compare tape “Analog to digital comer, measure analog egos * Analog Comparator Compare to analog signals a) (Quaarore encoder nterace 2 Use Univeral veil bos 1 here Highspeed network tan Controller res nework “Te WARE as ewe far sel eration teres computes 8 anemia len fo sinners cosmnieton ot ete The SH lel sel perl trace (SPD) ane ae seed 10 dee so ‘teil we tierce «pice ply We cot we Si sane il snl sever DAC) eae Spt a (S00. PC single 10 banat we wile tite low ped psp! device. lp apr and tp compare wl bdo ‘rat pect and meas pt, ple wih She, an Hegcncy PWM wl be te To apy vale pow! ote nce, Ina ype ir ental, nul ar mess tao Sen, bd PWM cates pot A PWM output cen so fe wed tenes DAC. The ADE oil be wad Yo meat ample f talog signi nd wl pont nds quo ‘ens. Toe saag comput nker to sao np and pode gal sup Spending om nich aaa ape preset Tae {GET cmb se neice trasess DC mtr. USB sa highspeed sal consmsron cane! The here cat te ed 0 ee te anne tt Inet + eal een newt The CAN cet higeaped cimannien chanel bevece tern slog al ge ABC DAC snegconpann, PHIL GE pt open operon 6.1. Stollaris LM4F120 and Tiva TM4C123 LaunchPad VO pins ze 61 dis he 10 pot stata fo the LMIFI20HSOR ad TMECIZSGHSPM, Thee meceotels se Sed on te EK ‘weve, pin on the LMSE/TMAC fry canbe atine to as many at eigh diferent LO fonctions. Pins can be configured fr git hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him ane213722, 9:08 AM. Chapter 6 Parallel VO ports amg ps i 0 ei Fos al ania UO np Tha no ee 0, Th ial ‘tall cn perm 10 bs ls sans wt msrcon faces Aas ROM The (NG S0HSGR ht cig UART post ur Sl pry 12 pots Ist AD, ove ty, CAN pr sala USB erie Tie TMACTRICHSPM sup o Te PHO eu Ter we 0 ne Thre ove ADC apts ek ADC ca covet po IM ales pee. Tae 8 Cortex M4 Systick’ System Bus Interface NVIC GPIO Ponta GEO Pon B rar [rer Pao —| 7 Evi racsxote eae Bet Eis: PAd'SSIORX —} iS _ [— Pea Passings —| E etacospa PAD ssiock | Fa FE remenscr Parvors —| ed CAN 20 tet PaotoRs | Ftp ver Gro Fone > [aro row boo E bbe pe USB 20 Twelve Eps pea Timers FE rps vextmosswo —] | Eps restpr—| |} six Em: PCLTMS'SWDIO je} TA 64-bit wide [PDL poorer swerk | Fine GPO Fone GO PORE, ves ves ADC TwoAnaloz] | [vrs PES 2 channels Comparators: }- PES re: | 12 inputs Eve rms 12 bits ‘Two PWM PEL re ‘Modules tro Advanced High Performance Bus Advanced Peripheral Bus a 110 et pif LMAPEROHSOR | TOMCICEM mienti, ach pin hase configuration it ithe GPIOANSEL reper, Wea thisi canet he pr pint te ADC or ang compar Pot ‘ea tus, ec nls aso ithe GPIOPCTL ei, wih We to spe he atin asa fost pa ee ‘etl VO pr ol rey pica be eared eey lca facto See Tae Pits BC3~ PCO wore ef off Tal 6 Beas hese four pins eres he TAG debugger soa ot eu ela, Nate most ton res eg, URS) oes onan on PAD, Wie ther cons cal We mapped wow ose or example if we wid ose UART on pits PBD ent PEI, we wool Sts 1.0 i he GPO_PORTE.DENLR fxs be tiga), der bs 01 be GO POREE_ ANSEL reir ble log) Sette PMC isin he GTO. PORTH RCTL, rege fer DEO, Pt Ul (eae UART con and ti 0a he GPO, FORTE AFSEL Reiter ester ae) 1 ‘Pe wided to amples malo sialon PDD, we wold it in te sleet slr egal bk Ot he aga ale "riser able els he alg tne it ree (tableau) and act one te ADC pe hae hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him ane213/22, 908 AM Chapter 6 Parallel VO ports “Tle PG bi he GPLOPCTL ec on the LMAETMAC opel skeen anon. FDAand PS ar baled he US device Bae Ba ar hae he el port PM ot on GFL ‘Te LachPadevshton toed (Fe 62) owcot dept sed ese wt pat suber ERCLMAFIOXL a EK TMCI2IGXL fom. his can and in he US fom rau secon dirbuor Ie Dig, Mose, Arow, Newark, and ‘Atel For etal iastacon for ovine hb hi, eer oho vussusweuaceds-ashauasiX The meal bad Poids een Cet Detu re (CDN, nse ios porting dete te obey LAPT or TACI2S ‘urocontaler Ooe US cate me bythe dtuger QCD and he er USD allows he ues develop USD met (deve). "he ter san ale tos powers cme um ite be Senge ICD) he Sais cove) sting he eer slcon wich USBICDI Debugger LM4FI20H5QR, TMACI23GHOPM Swi gr 62 Tie aie bd of UE 20H GOR or TMACIECHP Ping PAL PAD cet eral por, whic ind hough be hogar BC. The sl inks a ply UART as seen by he [FSF BOTMaC and mapped aval COM pron he PC. The USB ev eriae ss PD and YS. TReJTAG degree pins PC3-PC0. Toe aunhPa ome PBS oP, 2 78570 PD. yea who se al PBS and PDO You wl eo wre the “Te Tis LaaehPaeaaion ba sth and one ose LED, Se Figs 63. The switches ae nepal ad wil ie station of he al plhp sn. ica. you Milt bit aod 4 GPYO_PORT_PUR_R rp. Toe LED Ire on FS ~ PFT we psn log Toe he LED, ak he 3 PFI pi a cup. To tate ere once ae PFI Tac bu clr PP nthe pre clr costed ty P¥3The Oo este, R, RI, 213, Rs 2S and) ca be eovado some he oespading pn he cera he ‘pi ota nase oth an em cc Th nc tak bn oar eas red ‘nem Team inst a pis Boor aks, wich ae pone al devs wl lino th 07cm The ‘ime: Pc re MSP Ltd me cnet ith a Oe gly pase nme fe MSP ban ‘toh acer wo row, Teina lpn cane 9s 1 opal Sls ve Done Paks hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him ana213722, 9:08 AM. Chapter 6 Parallel VO ports TMACI23 PFOLw PFA Serial [PAL PAO me +5] rity fe cont [Ras] ry /PBO- Lhe “NN 7 PDO ROWE IPBS PF] W—— PDL DTCHA4EETIG Ape ag Stand Dn i eed na Th hte rd nic di rr “Tare ae «mabe of el mtd connect extend. One et io pre +t fae unger (SS (eg tom mane 26 sama). Ascsond cod it ld aed wef sok (og He DF 2 IDESCA) eine ele tw male par oe B uooR apes FRR Gaul 2 Gna 3 PE? 3 Lene FES PED appr Ped PRO s pp: BCS Reset ors PCG FB" > pet PCO PR's 3 re EDs. PAL o [pes ED, Pas torr PEI. PAZ Fag 64 I cmt Tn LAMUEIQO/TMICEDS Lead nati Bad Sele pins nth GOP ve, tet er nr PO Vale Oro Vi 62 Lanai ming starr ast hbo 6.2, Basic Concepts of Input and Output Ports hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him ana213722, 9:08 AM. Chapter 6 Parallel VO ports ‘Tepe UO pr ena ite pee tA ee LO prs hn: at sow hf Te extemal il sal st oly. That mane ead ese cv fo pars ret he aes extn oe ne tat te I icc ae er (wale toed cl fs Figae65) wl deve tpt uta oto he a ard od {Spin be mioconl wher esol exes red fom the pot mse Thee ae toil pony pro Se {Met ise family ot rcconelsw the MATE fay of mereseolen hr sere cil inp Pangan pe bias al canbe any wager 201030. Onde Stine STNG ON fly, se pts eV lone nd tee Read fiom port address Processor Input Port igre 5A adapt oli fa ar dl al ‘ekpeint 1} wha gp itive wc ong pr be Fig 5 Wl a int devi ssl ut nas the st ad she po, a op ys a paisa uh the ed ad wie Ne surpt port Awe jlo th pr nies wil fet helo safest Read fiom portaddress Processor Output Port White to port address Fie 5A ont eli eer aa nr! el ((Gheskpent 2 3 whe pp ite sore ed man cuc porte ze To mate themiron more make, st por ca be step o be rnp aus Marcel ee ence dein rego serine heb ps su spa (recon ste i) oo up etn rept te). ‘hal wftre auc deco tse por tes kets mpy nd if mate etn i ne emt a Fase ‘pt por. ach dpa por i ss es. Tis mts some pas on 9 ote be ps Whe tes we capt To digi po Read fiom port addiess Processor > Input‘Output Post Write to port address Direction bits a 1 means output Omeans input ID a) Ee ‘Write to port direction register Fn 7A tpt insane ar t hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him en2213722, 9:08 AM. Chapter 6 Parallel VO ports 6.3. /0 Programming and the Direction Register amt en icin 10 pt ey spe Ts fae ne ppl by tuys the UO profes DO NOT a ikem Fr xn, sme ae enn me ae wren fe cn al Ue cleed, te nl be ei soe iy en emote. To make owe mae tae We eee se eae Ferbe UO pers Went the dcon eter(eg, GBI POREP_DIR Rta wish pn oe nl sd wh on Ind fur pisses ho gnc pupae VO (GPO) or wey alate Eavoas We wl eb ote she hac ice (ee ‘Grud poten APSR, K) hen me wish ase the skate fn itd Table, For each UO pine wh ue whee “arte facon we must cle th dial cvs by Sting be itt he ele epee, GPT0_ PORTE DEN, “ypc me wef th cnn a tenon reste one ding he salon poe We ie th a ester (Grzo_ forse BATA It perm apo! othe pa Canverscy me ed and we the eres male meso Pee utd nt peely dye using pane Table 2 shower fe paral por reper forte MAPIONTMACISS. The ‘nero ane th Sars an a hese ember opr a eee sin eh po, a Fett Ee es See Ea (es ee Sas S Se i Se se Table 6 JTAG sean do at ute ete plane do it “yin on UO pt for peter wie we pe seven ses Ses 0 Cough or te seeded only fr the LASERS ‘eromble. Fal we atthe ck fr por Sota, ek pc wig ceded only iat PC, POT FPO oe ISELMAP 2d TAC. Td we dale ie snl Econ ote pi, ere well be igh or el LO. Feu we Ce ietde PCT ible 61) tlt regu gl ncn iy wes dec reper Sin we ca he ses cos ‘ee diay tablet ital pr We eds as hort Sey beeen sang the land eng te port ep The Acetone pis it for i wheter he comes ee poop AIR o0 moos apt and ne up Common Bor Yui ges f os eet sprint ening dock Inch et xanple we wil make PP ad PO put. a ne wl ake PP PA and PF oa bmn a Prop 61. To we por we fit matte lek ee SYSCTG_ RECA” Reps The sont Sp wc oe por, y NEw pila he proce Th rd sep so ale the ao acy by cng in he AME eter The Et ccs, by sleing Hr nie PCTL oir ented Tee The ih ep eo pei wheter hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him enz213722, 9:08 AM Chapter 6 Parallel VO ports ‘Rta arte reunite APSE repiner Tela ep in msl the coepocing 10 piney wing ons he DE "ser Tune xa nh asncPa, els et nb PUR reine fre two otk Fp 5) hae ral the vaue writen tthe port The fancton Pore Output will wite new vals to he lc ouput pms The #Lnelude will fine ‘Hinctude "ntox23geepe. Sugned long in)" // snpat fron ore Snelgned long Outs // output to PF2 (blue LED) 17" *ranction Prototype ota Borst inteiwoial 11 sat: Maniatery for ac Program to be executable Siveatn (void (7 snitialite PFO and PPA and ake them inputs ortr'aniet); {make BF out (erat buritean ooo (GPL0_PORTR_DATA.REOK30; // road FPA into Se? woot 1 Ee Ren ma SeraRGT DATA = out // oatput 1 17 Sobroutine to initialize port F pine for input and output ‘Srsctiadacz.f [= 000000020" //"2) activate clock for fort F Geiay 2 s¥seth, acces ae Uf same thas tor chock to atart Gtre!sonme week n= Datctrasea; // 3) aniock crio fore F Uf only PEO naeds 0 be unlocked, othar Size can't be locked Gre Ponoe atsrL R= x00 U7°S) aietvie’ analog on BF ‘Sera_rowre-ert,® = ox00000000; // 4) feta cro an Fre Gero-ronse-brm 8 = Ox0e U1 3) bearet0 ta, arsed ove PATSEL,K = 0x00 11 6) aistbie ate force on 77-0 eat Uf snabie poli'ap on 950° and Fre one, U1 Wy entnbe digital 170 on PFe-0 Peg 1A fn ig PEO a pt a PS tt (Chau ([Ghetpat 3) nese ei prt ad oe do ea up se pie ep hl ie a up? (Checkpoint 64 How dowe change Program 6 trun using Port A? ‘The ftoming tol tows yout test your undestanang of what happens when you WRITE tothe DATA rele! or Part Not wrt mp pine Paso eect Se what happens you exon ae tthe a ates ei Ep. 8 ao a ter aS bit number to write to GPIO PORTF DATA.R, bits 4 though [te] hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him m2213722, 9:08 AM Chapter 6 Parallel VO ports vitioks_at_ 202028 bitioks_2t_ 202028 biliokt_at_20_ 208 bitfele:_a1 202928 vitfols_o1_ 202928 ite i a ea ale nPop he empton wash sofware ae a acral of Prt Fath wade sata ed al i of Pox Fn cocz_R |= 0x00090002; // 2) activate clock for Port A ‘syscer nece®R: Uf siazw tine’ tor" clock to stare 11 3) aleabie anu Serc_ponan vers % em ~DuP0000000; // ¢} Sens cae an 2A 11 5) tad owe 11} ateabie ate tonct on 9.2 11-3) Snabie digivat 3/0 on PA? eR aE TT ea RS ot wo, i), ‘Sbras ona DATA R |= 0x00 Soe RO, Tey eR RAE TT ake PAT Toe ok no te Ppreviour | GPOLPORTALDATALR &= =O! Bre nO, HD, ¥oxgo } Glaae bit 2 hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him ana213722, 9:08 AM. Chapter 6 Parallel VO ports “hme th ae ning The AFT ay pn» ee wy a pt po hi {isn apr. We deine ight ade fc cnr in Tale 63 Bailly we need in bit he esta 2° There 2 poushe bt comnts we ght be teed nwa, fom al of he ene hm. Exch ble tombs ha feprme ec er aceing at rbot exch we te rete we op conespnding cant Fn Tae 63 iene P&I tnd The sera Po A DCO 000 ah cons ae CO, TE 3020, The ‘eee wo i ares aly 123 willbe oie ” Tareas [TGS Ate te ed apa nl a pone ‘Tetase leer Pr Ai x4 400, Ife wan o edad wt 8 is of hi prt he contacts wil ad up to EBFC. Notice ‘ate vam tbe ee dh rst lsh naOOs3FC des wo Tale 62 and ror ater wad ed ‘eon Soe ca dete te ado fdetine BAS (+((volatile unatgned tong +) x40006080)) aS EOD Oxeo004080 PAS = 0x20; // maka PAS Nigh Asp wie eens wil set PAS The lion oe ey, Bas = ox00 U1 ake 23 00 Are a AS wilt 02 oreo wt enero rps IPAS le lig de as = aseox20; _// toggle Eas Note that ae ares wen computing te spec ates Pa 4400, te owing li et abe fo ‘eae pons ran sense ‘ible. Base Aes or bape aessing of pris AF ‘hekpaint wha hen we we ee na a0 (eps pt incr acid i ([Chesknci Specter ee csi 2,08 Pe Ue hf mei 6 Lad Do Poe ih “Toundermnd te or defensin, we reemer Bdetine snl ony pte Ee. data = (+((volatile unaigned tong +)0x40004080)) ‘Tamed wy we lie ors hs yes rea hp desi io peo. Fe OOOO ithe ates Po A i 5. wersja fdettne a Get 004080 iwi ce data = (+0xt0004000) ; Thi wl ava ord hc a ION, doe wht tek 1032 bi Sots ges yx enor ‘ue the eof ta dvs ot uch th pe of (OONHS0). To sae spe marae nC we pees pags ep) em of he jet me wih cover We wih Fre he ype core eifed 32 owe nd he dean alee es hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him onz213722, 9:08 AM. Chapter 6 Parallel VO ports fdatine TAS (¢{(wolacite unsigned Jong +) 0x48006080)) ‘Theo aed case tele af ort can cage toon he eel aso othe sofas Ice eC compe rea neva each eho oo an ot ey nthe rv va 6.4. Debugging monitor using an LED ‘arf te inparint naisdetuging «ye toate when and wire ur sfwae is cncting. A dugg to at mek wll fereaine tere ihe orn ean pier, we eed te ecto ie fe Sepa be oll pope oe ‘esto ine fe pop il Tnravens Seid the ern whch he egg Sd Hse he ‘prom teint A wor eh depend xt poo cat ser oth in ema eat exces moh aes arses nae: An LED sche To uu ort of be coon nm etme of 2 BOOLEAN ros You an [pacer en ansed spt pins Soares ee LD wet yu now where and whe your pop raming Ane a LED FRatuced to PartPb42 Popam 62 willl te LED, We sete beri sen conta erat PF TER TOTES TSEiae FE TRS aI TRG FT OTOSTSCTOTT "Sper Seanad) coggte ao Page 52 ARTE a Aare sping cpt ht ot eid fr he crac opersion of he tn, bat flo ae whe he roam TaningInprtesyou dak Toggle enc a ee ple win sae syom ely as bur eyer ts ext Pot ub ital at 2 an eptoforethdureng ep Yon ca ther Obsrethe LED dy lk at he LE cot ‘eal with shipped ccllovere ote mula An LCD cn ee eee ox fr cal aa neat. nee Deca dyin ocr afr ae abot 0p ecu sac charset oh we of snc suse ht e mv ening LED notoriety he ne ening thr a an ay Jo a ate ana Leb aator 6.5. Hardware debugging tools Misocompter eld robes en eure the wif wpe pt deb te ys brad sft Two ery sf Ilsa th ng analy ne niencope. A lope raysetall pean pl sre sap ray ao ‘Paper sc pie 8 Ara soblshosing a tallow he experince to bere mame dal see ans pos a oe an thas make eos based upon sch ebserestns As wi ary epg poses, mcs) ost wc formation Yo herve ‘oof vit sof posi Ay dp sil the se cn bce eae ale ip 88 shows mime! oe er, Wi ge mp ts Sgn ena) we mat ry nha te al eto feof ui tough vmes of ou Senet eet 10 pone wrote, ted for html person Ge {pn (hows eh bats no ea Fre 64) fi tt wet comet te paw pc scaly, edd sare dceag LMBS Logic Analyzer TMAC + Distal ‘ut Intertace oat foo fron Digital foo Interface poe PBI Ao PBO Pye A igi sand mp at. ‘An entlnope in do ape vous vera ie dt, You ca a he vote ange nd ie sae Te oo ee rand when he at wi be ez In ora ae, este puters eps ster ado ol We See gbre PSNE Sips se sa ce Sy ay son ee ed 6.6. Chapter 6 Quiz 6.1 To make a pin a digital input, what value do you lod into corresponding bits the following restr Assume i foes not need an intel plop hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him sone213722, 9:08 AM Chapter 6 Parallel VO ports 62 To make a pina digital output, what value do you load ito coresponding bits the following epsters. Assume it Aes not needa inter plop 13 Which line of © code is friendly way to set Port I bit 2 assuming this pin hs already been initialized as an (@to_ponre-parnk wri" Which line of C code is afiendly way to clear Por B bit? assuming this pin es already boon intilized as ax ua Pens Which dcbuginginstument an measure voltage vers ime? Capt tiger 64 Which debugging instrument can measure mutple digital signals versus time? ‘Reprinted wit approval from Embedded Sytem: ntoduetion to ARM C 1477508992, hues ee tesa edu valvano/arm/ouline] bi LM Micraconoller, 2014, ISBN: 978 hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him se213722, 9:08 AM Chapter 6 Parallel VO ports Enedded Systems Jonathan Valvano and Ramesh Yerba is eensed under a Creative Commons hitps:users.oce.utexas edul~valvano'Volume VE-Book/C8_MicrocontrollerPorts him rane