Unit-4 PLC
Unit-4 PLC
LOGIC CONTROLLER
Architecture of PLC
CP MEMORY
U
The architecture consists of
• CPU
• Memory
• I/O Processing Device
Input/Output Processing
Device
Architecture of PLC
1. CPU
• ALU – Responsible for Data Manipulation and Arithmetic and Logical Operations.
• Memory Registers – Store information involves in the program execution.
• Control Unit – Control timing operation to ensure the execution of operation in correct order.
Functions of CPU
• Control and process all the operations of memory and I/O Data.
• Holds Communication circuits and power supply.
• It provide with clock signal to sequence its internal operations.
2. Buses
• The internal paths used for communication are called buses.
• Data Buses – Communicating data between elements.
• Address Buses – Read address of locations for accessing stored data.
• Control Buses – Control actions carried by CPU.
• System Buses – Communication between input/output ports and input/output unit.
Architecture of PLC
3. Memory
• Memory devices – where the programs are stored in the controller.
• Sectors to store the status of inputs and outputs.
• Sectors to store system information such as scan time, fault status, fault codes and watchdog timer.
1. RAM (Random Access Memory) – User’s program and data storage. Volatile memory which lose
information when the power is off.
2. ROM (Read Only Memory) – Permanent storage to store OS and fixed data.
• PROM (Programmable Read Only Memory) – special type ROM, allows information to be written in
the chip only once.
• EPROM (Erasable PROM) – Programmable using dedicated programmer. Information can be erased
with the use of UV light source and can reprogrammed.
• EEPROM (Electrically Erasable PROM) – Information erased using electrical pulses. It can be over
written electrically with new data.
Architecture of PLC
4. Input & Output Processing
• It provides the interface between the system and the outside world.
• Allowing connections through input/output channels to input/output devices such as sensors, motors, etc.
• Every I/O point has a unique address which can be used by CPU.
• It also provides isolation and signal conditioning functions to connect sensors and actuators without need
for interfacing circuitry.
Consider a motor controlled by stop and start push button switches and
for which one signal light must be illuminated when the power is applied to
the motor and another when it is not applied.
PLC Programming
• Ladder diagram is a graphical method for representing and programming an event driven sequential process.
• The schematic representation of hardware elements and its connection used to make combination of hardware and
description of sequence of events is called ladder diagram.
• It consist of two parallel lines which indicates the power supply lines called as rails.
• The rails are connected by a number of horizontal lines which defines a specific operations are called as rungs.
• The ladder diagram must be read from left – to – right and top – to – bottom which is the scanning process.
• RUN Mode – PLC goes through entire ladder program to the end, the process is called cycle.
• Each rung – must start with atleast one input and one output.
• Inputs – control action : Closing contact of switch
• Outputs – Motor
• Particular device can appear more than one rung in a ladder, where some identification number is used.
• Inputs and outputs are identified by their addresses, depending on the PLC Manufacturer.
PLC Logic Functions
1. AND Gate
For the purpose of this discussion, the outcome or output is
called Y and the signal inputs are called A and B. Also, binary 1
represents the presence of a signal or the occurrence of some event,
and binary 0 represents the absence of the signal or nonoccurrence
of the event.
• An AND gate is a device with two or more inputs and one output. The AND gate output is 1 only if all inputs are 1.
PLC Logic Functions
2. OR Gate
An OR gate can have any number of inputs but only one output.
The OR gate output is 1 if one or more inputs are 1.
PLC Logic Functions
3. NOT Gate
Unlike the AND and OR functions, the NOT function can
have only one input. The NOT output is 1 if the input is 0. The
output is 0 if the input is 1. The result of the NOT operation is
always the inverse of the input, and the NOT function is,
therefore, called an inverter.
The logical NOT function can be performed on a contact input simply by using a normally closed instead of a
normally open contact.
The NOT symbol placed at the output of an AND gate would invert the normal output result. An AND gate with an
inverted output is called a NAND gate.
PLC Logic Functions
4. NAND, NOR, EXOR Gate
Timers
• There are tasks which involve time delays and event counting.
• These requirement can be met by the timers and counters which are the features of PLC.
• Timer circuit is specified by starting the interval to be timed and the conditions or events that are to stop/start the
timer.
• They are commonly regarded as relays with coils which when energized, result in the closing or opening of input
contacts after some preset timer.
• Delay ON Timer
• Delay OFF Timer
• Cascaded Timer
• ON – OFF cycle Timer
Delay ON Timer
• When there is an input, the timer energized and
start timing, after some preset value the timer
contacts are closed to output.
Delay OFF Timer
• It switches OFF an output after a time delay from
being energised.
• When the input contacts are closed the output
energised and the timer started.
Cascaded Timer
• Timers can be linked together using cascaded
connection, to give larger delay times than with
just one timer.
• First rung – input arrangement to control the coil of internal relay IR1.
• Second rung – arrangement to control the coil of internal relay IR2.
• Third rung – contact of the two relays are then put in an OR simulation to control the
output.
Counters
• Counters are used when there is a need to count a specified number of contact operations.
• Up counter
• Down Counter
• Up counter is used to count the value from zero to preset value and trigger the event after the required number of
counts.
• Down counter count the value from preset value to zero and then triggers.
• Counter is represented as,
• One line is the reset which is used to reset the counter
• Other line is the outline, and the K 10 indicates that the counter contact will
change the state on the 10th pulse.
• When the input 1 closes momentarily it will reset the counter.
• Counter will count the number of pulses resulting from input 2 closing and opening.
• When this reaches the value 10, the counter closes which switched ON the output.
Shift Register
• Shift registers can be used where sequence of operation is required or simulates movement or it tracks the
flow of parts and information.
• Number of internal relays can be grouped together to form a register which can provide a storage area for a series
sequence of individual bits.
• 4 bit register can be formed by using four internal registers.
• Shift register is used because the bits can be shifted along by one bit where there is a suitable input to the register.
• All the bits shift along one place and the last bit overflows.
• Forming of shift register is done by PLC when shift register
function is selected at the control panel.
• 3 inputs – One to load data into the first element of the register (OUT), One as the shift command (SFT) and One for
resetting (RST).
• OUT – Logic 0 or 1 is loaded into the first element of the shift register.
• SFT – Pulse move the content by one bit, last bit being lost.
• RST – Pulse of closure of the contact resets the registers contents to all 0.
• M140 – First relay of the register.
• When X400 is ON, logic 1 is loaded into the first element of shift register –
10000000.
• M140 contact closes and Y430 is switched ON.
• When X401 closes, bits in the register shifts by one place – 1100 0000.
• M140 contact closes and Y430 is switched ON.
• Each bit is shifted along the outputs are energized in turn.
• When X402 contact closes, M140 resets to zero (0000 0000).
• Applications:
• Tracking parts through an assembly line.
• Controlling machine operations.
• Inventory counter.
• System diagnostics.
Jump
• An output instruction enabling part of a ladder program to be jumped over.
• With jump instruction, the processor scan time can be reduced by jumping over instruction.
Data Register
• A register where the data instructions in the PLC are stored.
• Data instructions required memory addresses and location in the PLC memory.
• Data register can store a binary word of 8 or 16 bits.
• Each instruction has to specify the form of operation, the source of data used in terms of its data register and the
destination data register of the data.
Data Movement
• Instruction will contain the move data instruction (MOV), the source address of data and the destination address of
the data.
• The data at the source address is in BCD and converted to binary and placed at the destination address.
PLC Manufacturers
AMERICAN 1. Allen Bradley EUROPEAN 1. Siemens
2. Gould Modicon 2. Klockner & Mouller
3. Texas Instruments 3. Festo
4. General Electric 4. Telemechanique
5. Westinghouse JAPANESE 1. Toshiba
6. Cutter Hammer 2. Omron
7. Square D 3. Fanuc
4. Mitsubishi
Advantages Applications
• Enhanced reliability • Material Handling
• Online repair facility • Conveyor system
• Reliable components • Pick and place robot control
• Computational ability • Power station plant
• Trouble shooting aids • Building automation
• I/O forcing through software • Water treatment