COMPUTER ORGANIZATION

UNIT-3
Processor and Control Unit

Fundamental Concepts:

 Processor fetches one instruction at a time and perform the operation

specified.
 Instructions are fetched from successive memory locations until a branch or a
jump instruction is encountered.
 Processor keeps track of addresses of the memory location using Program
Counter (PC). PC stores the address of the next instruction to be fetched.
 After fetching an instruction the contents of the PC are updated to point to the
next instruction in the sequence. A branch instruction may load different
values into the PC.

Executing an Instruction:

 Fetch the contents of the memory location pointed to by the PC and load the
content of memory location into the Instruction Register (IR).

IR  [PC]

 Assume memory is byte addressable, increment the contents of the PC by 4.

PC  PC + 4

 Carry out the actions specified by the instruction in the IR.

Single Bus CPU Organization:

Several components of a CPU namely ALU, control unit, general purpose register,
instruction register, etc., are connected via a single common bus. The organization
discussed below.
 CPU bus is internal to CPU and is used to transfer the information between
different components of the CPU.
 External memory bus is connected to the CPU via the memory dat and
address register MDR and MAR

 Instruction decoder and control unit is responsible for issuing the control
signals to all the units inside the processor.
 The number and function of processor registers R0 to R(n-1) vary considerably
from one machine to another. They may be used for general purpose or
 some may be dedicated as special purpose registers such as index register or
stack pointers.
 ALU
o “A” gets the operand from the output of the multiplexer (MUX).
o “B” input gets the operand directly from the processor bus.
o There are two options provided for “A” input of the ALU. Mux is used
to select one of the 2 inputs. MUX selects either output of Y or
constant value 4 (which is used to increment PC content).
 Program Counter (PC) is used to store the address of the next instruction to
be executed.
 Memory Address Register (MAR) holds the address generated by processor
where operation is being performed.
 Memory Data Register (MDR) holds the data on which the operation is being
performed. It holds the data that is being transferred from memory to
processor and from processor to memory.
 Register Y, Z, Temp are used by the processor for temporary storage during
the instruction execution.
 ALU control lines activate one of the operations such as Add, Sub… The
activated operation is performed by ALU and result is placed in Z.
e.g., If Add=1, then ALU performs addition operation.
 Result stored in Z is transferred to specified destination (memory location or
general purpose register)
 Whenever an instruction is fetched it is stored in instruction register (IR).
Note:- The connection between ALU, register and the internal processor is
known as data path.
This bus organization is the simplest and least expensive, but it limits the
amount of data transfer that can be done in the same clock cycle, which will
slow down the overall performance.

Bus System for four Registers

 A bus structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at a time. Control
signals determine which register is selected by the bus during each particular
register transfer. One way of constructing a common bus system is with
multiplexers. Construction of a bus system for four registers is shown in the figure.
 Each register has four bits, numbered 0 through 3. The bus consists of four
4x1 multiplexers each having four data inputs, 0 through 3, and two selection
inputs, S1 and S0 .
 Labels are used to show the connections from the outputs of the registers to
the inputs of the multiplexers. For example, output 1 of register A is
connected to input 0 of MUX 1 because this input is labelled A1.
 The bits in the same significant position in each register are connected to the
data inputs of one multiplexer to form one line of the bus. Example, MUX 0
multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits
of the registers, and similarly for the other two bits.

 The two selection lines S1 and S0 are connected to the selection inputs of all
four multiplexers. The selection lines choose the four bits of one register and
transfer them into the four-line common bus. When S1S0 = 00, the 0 data
inputs of all four multiplexers are selected and applied to the outputs that
form the bus. This causes the bus lines to receive the content of register A.
  The transfer of information from a bus into one of many destination registers
can be accomplished by connecting the bus lines to the inputs of all
destination registers and activating the load control of the particular
destination register selected. For example: transfer register C content to
register A. This transfer is represented as follows:
 CBus
 BusA
Three-State Bus Buffers
 A Tri-state Buffer can be thought of as an input controlled switch with an
output that can be electronically turned “ON” or “OFF” by means of an
external “Control” or “Enable” ( EN ) signal input. Tri-state Buffer being in
one state allowing its output to operate normally producing the required
output or in another state were its output is blocked or disconnected.
 A three-state gate is a digital circuit that exhibits three states. The three
states are logic 1 and 0, high–impedance state. The high-impedance state
behaves like an open circuit, which means that the output is disconnected
and does not have a logic significance.
 The control input determines the output state. When the control input is
equal to 1, the output is enabled and the gate behaves like any conventional
buffer, with the output equal to the normal input. When the control input is
 0, the output is disabled and the gate goes to a high-impedance state,
regardless of the value in the normal input.
 They allow multiple logic devices to be connected to the same wire or bus
without damage or loss of data.

Single input digital buffer

Tri-state buffer
 To construct a common bus for four registers of n bits each using three- state
buffers, n circuits with four buffers in each is needed as shown in Fig.
 Each group of four buffers receives one significant bit from the four registers.
Each common output produces one of the lines for the common bus for a
total of n lines.
 The decoder is used to to select between the four registers.

Bus line with three state-buffers

 When the enable input of the decoder is 0, all of its four outputs are 0, and
the bus line is in a high-impedance state because all four buffers are disabled.
 When the enable input is active, one of the three-state buffers will be active,
depending on the binary value in the select inputs of the decoder.
Operations Performed to Execute an Instructions
 Register Transfer: Transfer a word of data from one register to another or to
the ALU.
 Perform arithmetic or a logic operation and store the result in a register.
 Fetch the contents of a given memory location and load them into a register.
 Store a word of data from a register into a given memory location.
Register Transfer
 Instruction execution involves a sequence of steps in which data are
transferred from one register to another.
 For each register two control signals are used: Ri in and Ri out. Depending on
these control signal values the content will be transferred to or from the
register.
 Ri in =1 Data on bus is loaded into Ri
 Ri out =1 Data of Ri is placed on bus
 Ri out =0 bus can be used for transferring data from other registers.

Example: Transfer the content (data) of register R1 to register R4

The steps followed for transferring process are as follows
 Enable the output of register R1 by setting R1 out =1. This places the contents
of R1 on the processor bus.
 Enable input of register R4 by setting R4 in =1. This loads data from the
processor bus into register R4.

Performing an Arithmetic or Logic Operation

 ALU performs arithmetic operations on the two operands applied to its A and
B inputs.
 Example: Add R3, R1, R2 meaning R3  R1+R2 . The sequence of
operations are
 R1out, Yin: Contents from register R1 are loaded into register Y.
 R2out, SelectY, Add, Zin: Contents from Y and from register R2 are
applied to the A and B inputs of ALU; Addition is performed and result
is stored in the Z register.
 Zout, R3in: The contents of Z registers is stored in the R3 register.
The signals are activated for the duration of the clock cycle corresponding to that
step. All other signals are inactive.
Memory Transfer
 To fetch a word from the memory, processors places the memory address of
the data on the MAR and activates read operation.
 When the read operation is completed, the requested data is placed on the
MDR, from where it can be transferred to any other processor registers.
 MDR has four control signals. MDRin and MDRout control the connection to
the internal processor data bus. MDRinE and MDRoutE control the
connection to the memory data bus.
 MAR register has two control signals. MARin controls the connection to the
internal processor address bus and MARout controls the connection to the
memory address bus.
 To accommodate variation in response time of various memory access (cache
miss, memory mapped I/O…), processor waits for an indication that the
requested operation has been completed (MFC). MFC is a signal sent by the
addressed device to processor which informs the processor that the requested
operation has been completed by addressed device.
 Fetching a word from Memory:
 Mov (R1), R2 meaning R2 M[R1]. Various control signals used for
this operation are
 R1out, MARin, Read: Content of register R1 is loaded into MAR and
Read operation is initiated.
 MDRinE, WMFC: Load MDR from memory bus and wait for MFC
response from memory.
 MDRoutE, R2in: Load R2 from MDR.
  Storing a word in Memory:
 Example: Mov R2, (R1) means M[R1]  R2. Various control signals
used for this operation are
 R1out, MARin: Desired address is loaded into MAR, i.e, the content
of R1.
 R2out, MDRin, and Write: Content of R2 is loaded into MDR and
write operation is initiated.
 MDRoutE, WMFC: Load data into memory location pointed by R1
from MDR where WMFC control signal that causes processor’s control
circuitry to wait for arrival of MFC signal.
Execution of a complete Instruction
Execution of an instruction requires the following actions:
 Fetch the instruction
 Fetch the operand
 Perform the operation
 Load the result in desired location

 Example:- Add (R3), R1

 PCout, MARin, Read, select4, Add, Zin: PC  bus, bus  MARin. Read
indicate memory read operation. Constant 4 will be selected by MUX
 and PC value will be incremented by 4. The new PC value will be placed
in Register Z.
 Zout, PCin, WMFC: From Register Z new PC value placed on bus and
from bus to PC. Zout  bus, bus  PC. Wait for MFC signal for read
operation to complete.
 MDRout, IRin: From memory instruction go to MDR and, then from
MDR to Instruction Register (IR). Instruction is decoded and the
required operations are carried out.
 R3out, MARin, Read: R3  bus, bus  MAR. Memory read operation
is initiated.
 R1out, Yin, WMFC: R1bus. Second operand of ALU in register Y.
Wait for memory read operation.
 MDRout, select Y, Add, Zin: The content of memory location is
transferred to MDR. The Y input of ALU is chosen and add operation is
performed. The output of the addition is stored in register Z.
 Zout, R1in, End: From register Z result is transferred to register R1.
End the operation and ready for the next fetch instruction.
Execution of an Unconditional Branch Instruction
 A branch instruction replaces the contents of the Pc with the branch target
address. Control sequence to implement an unconditional branch instruction
is
 Example: Goto target_address
 PCout, MARin, Read, select4, Add, Zin: PC  bus, bus  MAR,
Memory read operation is initiated. Constant 4 will be selected by MUX
and PC value will be incremented by 4. The new PC value will be placed
in Register Z.
 Zout, PCin, WMFC: From Register Z new PC value placed on bus and
from bus to PC. Zout  bus, bus  PC. Wait for MFC signal for read
operation to complete.
 MDRout, IRin: From memory instruction go to MDR and, then from
MDR to Instruction Register (IR). Instruction is decoded and the required
operations are carried out.
  Offset_field_of_IRout, PCout, Yin, selectY: The offset value is
extracted from the IR by the instruction decoder circuit. IR  bus, PC 
bus, bus  Y. MUX select Y input.
 Add, Zin: The offset value extracted from the IR is added with PC value
to generate the branch target address. The result is stored in register Z.
 Zout, PCin, End: Z bus, bus  PC. End the operation and ready for
next fetch instruction.

Multiple Bus Organization

 In single bus organization only on data item can be transferred over the bus in
a clock cycle. To reduce the number of steps needed, commercial processors
provide multiple internal paths that enable several transfers to take place in
parallel.
 Three bus structure
 All general purpose registers are combined into a single block called
the register file. The register file has two outputs allowing contents of
two different registers to be accessed simultaneously and contents
placed on buses A and B. The third port allows the data on bus C to be
loaded into a third register during the same clock cycle.
 Buses A and B are used to transfer the source operands to the A and B
inputs of the ALU when an arithmetic or logic operation may be
 performed. The result is transferred to the destination over bus C.
Sometimes ALU may simply pass one of its two input operands
unmodified to bus C. Such operations are represented by control signals
R=A or R=B.
 Incrementer unit is used to increment the PC by C. The source for the
constant 4 at the ALU input multiplexer is used to increment other
addresses, such as the memory addresses in LoadMultiple and
StoreMultiple instructions.

 Example: Add R4, R5, R6

 PCout, R=B, MARin, Read, IncPC: Content of PC are passed through
the ALU using A=B control signal and loaded into the MAR to start a
memory read operation. At the same time the PC is incremented.
 WMFC: Wait for MFC signal for read operation to complete.
 MDRoutB, R=B, IRin: Loads the data (memory operand) into MDR (Bus
B). Instruction fetched from the memory is placed in IR. Instruction
decoded.
 R4outA,R5outB, SelectA, Add,R6in, End : Place the content of R1 in
bus A and content of R5 in bus B. ALU take one input from bus A and
other from bus B and perform add operation. The result of the addition
operation is stored in register R6. End the operation and ready for next
fetch instruction
Micro operations
 The operations executed on data stored in registers are called micro-
operations.
 Examples:-
 A bidirectional shift register is capable of performing the shift right and
shift left micro operations.
 The internal hardware organization of a digital computer is best defined by
specifying:
 The set of registers it contains and their function.
 The sequence of micro operations performed on the binary information
stored in the registers.
 The control that initiates the sequence of micro operations.
 Types of Micro operations
The micro-operations in digital computers are of 4 types:
 Register transfer micro-operations transfer binary information from
one register to another.
 Arithmetic micro-operations perform arithmetic operations on data
stored in registers.
 Logic micro-operations perform bit manipulation operation on data
stored in registers.
 Shift micro-operations perform shift micro-operations on data.
 Register Transfer Micro operations
The symbolic notation used to describe the micro operation transfers among
registers is called a register transfer language.
 Symbols for Register Transfers
 Arithmetic Micro operations

 Hardware Implementation (Arithmetic): The diagram of 4 bit

arithmetic circuit is shown below.

The various functions performed on above circuit are as follows

 Logic Micro operations

A one stage logic circuit with its function table is given below
 Shift Microoprations

A 4 bit Combinational Circuit Shifter with its function table is given

below.
Control Unit
 The control unit is the main component of a central processing unit (CPU) in
computers that can direct the operations during the execution of a program by
the processor/computer.
 It receives the input instruction/information from the user and converts it into
control signals, which are then given to the CPU for further execution. The
control signals operate the functioning of the processor’s hardware.
 The components of this unit are instruction registers, control signals within
the CPU, control signals to/from the bus, control bus, input flags, and clock
signals.
 There are two types of control unit
 Hardwired Control
 Microprogrammed Control
 The Hardwired Control organization, the control logic is implemented with
gates, flip-flops, decoders, and other digital circuits (i.e., Circuitry
approach).
 The Microprogrammed Control organization is implemented by using the
programming approach. The control information is stored in a control
memory. The control memory is programmed to initiate the required
sequence of microoperations.
Block Diagram of Hardwired Control Unit
 An instruction read from memory is placed in the instruction register (IR).
 The instruction register is divided into three parts: the I bit, operation code,
and address part.
 LSB 12-bits (0-11) to specify an address, and are applied to control
logic gates.
 Next 3-bits specify the operation code (opcode) field of the
instruction. The operation code in bits 12 through 14 are decoded with
a 3 x 8 decoder (D0-D7).
 Left most bit (MSB) specify the addressing mode I.
 I = 0 for direct address
 I = 1 for indirect address
 The outputs of the 4-bit sequence counter are decoded into 16 timing signals
T0 through T15. The sequence counter SC can be incremented (INR) or
cleared (CLR) synchronously.
Exa

 Example: Let at time T4, SC is cleared if decoder output D3 is active. The

symbolic representation is as follows:
D3T4: SC  0
 The timing diagram shows the time relationship of the control signals.
Advantages and Disadvantages of Hardwired Control Unit
Advantages
 Hardwired Control Unit is fast because control signals are generated by
combinational circuits.
Disadvantages
 Modifications in control signal requires rearranging of wires in the hardware
circuit, which is a difficult task.
 The delay in generation of control signals depends upon the number of gates.
More is the control signals required by CPU; more complex will be the design
of control unit.
Micro programmed Control Unit
 The program that creates the ‘control signals’ is called Microprogram.
 This microprogram is placed on the processor chip which is fast memory, it
is also called control memory or control store.
 A microprogram has a set of microinstructions, or it is also termed as control
word (string of 1's and 0's). The microinstructions specifies the
microoperations of the system.
 Each microinstruction is ‘n’ bit word. Each control signal differs from other
control signal depending on the bit pattern of the control word.
 A sequence of microinstructions required to execute a particular instruction
is called microroutine.
 The Microprogrammed control organization diagram is shown below.
Microprogrammed Control Organization

 The control memory is assumed to be a ROM (Alterations of microprogram

are not needed once the control unit is in operation), where all the control
information is stored permanently.
 The control memory address register specifies the address of the
microinstruction, and the control data register holds the microinstruction
read from memory.
 The microinstruction contains a control word that specifies one or more
microoperations for the data processor. Once these operations are
executed, the control must determine the next address.
 The next address generator is sometimes called a microprogram sequencer,
as it determines the address sequence that is read from control memory.
 Types of Microprogrammed Control Unit

 Example: - Let control unit contains 64 control signals. What is the size of
control word used in bits a) Horizontal Programming b) Vertical
programming
  Sol: - a) Horizontal: 1 control signal=1 bit, so 64 control signals= 64bits.
b)Vertical: n control signals = log2n bits, 64 control signals = log264 bits = 6
bits
Microinstruction Format

 Three bits in each field are encoded to specify seven distinct

microoperations. So total number of microoperations is 21.
 One or more of the fields will use the binary code 000 for no operation.
 Example: DR  M[AR] with F2 = 100 and PCPC + 1 with F3 = 101, none
from F1.
 Two or more conflicting microoperations cannot be specified
simultaneously.
 Example: - Memory Read and Memory write cannot be specified
simultaneously.
Microprogram Example