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Process Corners: Semiconductor Design-Of-Experiments (Doe) Integrated Circuit Wafer

Process corners refer to variations in fabrication parameters that can cause integrated circuits to function faster or slower than specified. To test for robustness, manufacturers produce "corner lots" with adjusted parameters representing extremes and test devices under varying conditions like voltage and temperature. Results are plotted on "shmoo plots" showing parameter combinations where devices begin to fail. Accounting for process corners is important for digital electronics, as variations can impact transistor switching speeds and potentially cause logic failures.

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Madan R Honnalagere
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90 views

Process Corners: Semiconductor Design-Of-Experiments (Doe) Integrated Circuit Wafer

Process corners refer to variations in fabrication parameters that can cause integrated circuits to function faster or slower than specified. To test for robustness, manufacturers produce "corner lots" with adjusted parameters representing extremes and test devices under varying conditions like voltage and temperature. Results are plotted on "shmoo plots" showing parameter combinations where devices begin to fail. Accounting for process corners is important for digital electronics, as variations can impact transistor switching speeds and potentially cause logic failures.

Uploaded by

Madan R Honnalagere
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Process corners

From Wikipedia, the free encyclopedia

In semiconductor manufacturing, a process corner is an example of


a design-of-experiments (DoE) technique that refers to a variation of
fabrication parameters used in applying anintegrated circuit design to a
semiconductor wafer. Process corners represent the extremes of these
parameter variations within which a circuit that has been etched onto the
wafer must function correctly. A circuit running on devices fabricated at
these process corners may run slower or faster than specified and at
lower or higher temperatures and voltages, but if the circuit does not
function at all at any of these process extremes the design is considered
to have inadequate design margin.[1]
In order to verify the robustness of an integrated circuit design,
semiconductor manufacturers will fabricate corner lots, which are
groups of wafers that have had process parameters adjusted according
to these extremes, and will then test the devices made from these
special wafers at varying increments of environmental conditions, such
as voltage, clock frequency, and temperature, applied in combination
(two or sometimes all three together) in a process
called characterization.[2] The results of these tests are plotted using a
graphing technique known as a shmoo plot[3] that indicates clearly the
boundary limit beyond which a device begins to fail for a given
combination of these environmental conditions.
Corner-lot analysis is most effective in digital electronics because of the
direct effect of process variations on the speed of transistor switching
during transitions from one logic state to another, which is not relevant
for analog circuits, such as amplifiers. Analog techniques rely more on
over-design and simulation software tools such as SPICE, or Monte
Carlo analysis.[4]
Contents
 [hide]

1 Significance to Digital
Electronics
2 Types of Corners
3 Accounting for Corners
4 References
5 External links

[edit]Significance to Digital Electronics


In Very-Large-Scale Integration (VLSI) integrated
circuit microprocessor design and semiconductor fabrication, a process
corner represents a three or six sigma
variation from nominaldoping concentrations (and other parameters[5]) in
transistors on a silicon wafer. This variation can cause significant
changes in the duty cycle and slew rate of digital signals, and can
sometimes result in catastrophic failure of the entire system.
Variation may occur for many reasons, such as minor changes in the
humidity or temperature changes in the clean-room when wafers are
transported, or due to the position of the dierelative to the center of the
wafer.
[edit]Types of Corners
One naming convention for process corners is to use two-letter
designators, where the first letter refers to the NMOS corner, and the
second letter refers to the PMOS corner. In this naming convention,
three corners exist: typical, fast and slow. Fast and slow corners
exhibit carrier mobilities that are higher and lower than normal,
respectively. For example, a corner designated as FS denotes fast
NFETs and slow PFETs.
There are therefore five possible corners: typical-typical (TT) (not really a
corner of an n vs. p mobility graph, but called a corner, anyway), fast-fast
(FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three
corners (TT, FF, SS) are called even corners, because both types of
devices are affected evenly, and generally do not adversely affect the
logical correctness of the circuit. The resulting devices can function at
slower or faster clock frequencies, and are often binned as such. The
last two corners (FS, SF) are called "skewed" corners, and are cause for
concern. This is because one type of FET will switch much faster than
the other, and this form of imbalanced switching can cause one edge of
the output to have much less slew than the other edge. Latching devices
may then record incorrect values in the logic chain.
In addition to the FETs themselves, there are more on-chip variation
(OCV) effects that manifest themselves at smaller technology nodes.
These include process, voltage and temperature (PVT) variation effects
on on-chip interconnect, as well as via structures.
[edit]Accounting for Corners
To combat these variation effects, modern technology processes often
supply SPICE or BSIM simulation models for all (or, at the least, TT, FS,
and SF) process corners, which enables circuit designers to detect
corner skew effects before the design is laid out, as well as post-layout
(through parasitics extraction), before it is taped out.
[edit]

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