Fusion Compiler: Predictable RTL-to-GDSII Implementation System Delivers Up To 20% Better Quality of Results
Fusion Compiler: Predictable RTL-to-GDSII Implementation System Delivers Up To 20% Better Quality of Results
Fusion Compiler
Predictable Overview
RTL-to-GDSII Fusion Compiler™ is the next generation RTL-to-GDSII implementation system
architected to address the complexities of advanced process node design and deliver
implementation up to 20% improved quality-of-results (QoR) while reducing time-to-results (TTR) by
system delivers up 2X. Fusion Compiler is built on a compact, single data model that allows seamless
sharing of Fusion Technology across the RTL-to-GDSII flow to enable hyper-convergent
to 20% better quality design closure. Fusion Compiler was built from the ground-up using best-in-class RTL
of results synthesis, place-and-route, and signoff technologies for designing state-of-the-art SoCs
that deliver unmatched power, performance, and area (PPA), QoR, and fast design
convergence. Fusion Compiler’s integrated cockpit (Figure 1) provides a comprehensive
platform for design including RTL physical synthesis, design planning, placement, clock
tree synthesis (CTS), advanced routing, physical synthesis-based optimization, chip
finishing, signoff quality analysis and ECO optimization.
Key Benefits
• Comprehensive RTL-to-GDSII design system delivers up to 20% better PPA
and 2X TTR
• Fusion data model architecture for unmatched capacity, scalability, and
productivity
• Unified physical synthesis optimizations for best QoR
• Common placement and 2D legalization engines for fast DRC convergence and
design closure
• Accurate congestion estimation and prediction using route-driven estimate for
overall convergence
• Complete flow power optimization including unique power-driven re-synthesis and
knee-based optimization
• Physically-aware synthesis and advanced CTS to drive highest frequencies
• Leading foundry process certified FinFET and multi-patterning aware design
• Signoff timing, parasitic extraction, and power analysis eliminate design iterations
• Advanced area recovery algorithm from synthesis to post-route for best utilization
• Pervasive parallelization with multi-threaded and distributed processing
technologies for maximum throughput
synopsys.com
Figure 1: Integrated Fusion Compiler RTL-to-GDSII cockpit
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