MAX3243E

www.ti.com SLLS657D – APRIL 2005 – REVISED SEPTEMBER 2011

3-V TO 5.5-V MULTICHANNEL RS-232 LINE DRIVER/RECEIVER

WITH ±15-kV IEC ESD PROTECTION
Check for Samples: MAX3243E

1FEATURES
DB, DW, OR PW PACKAGE
2• Single-Chip and Single-Supply Interface for (TOP VIEW)
IBM™ PC/AT™ Serial Port
• ESD Protection for RS-232 Bus Pins C2+ 1 28 C1+
– ±15-kV Human-Body Model (HBM) C2− 2 27 V+
– ±8-kV IEC61000-4-2, Contact Discharge V− 3 26 VCC
RIN1 4 25 GND
– ±15-kV IEC61000-4-2, Air-Gap Discharge
RIN2 5 24 C1−
• Meets or Exceeds Requirements of RIN3 6 23 FORCEON
TIA/EIA-232-F and ITU v.28 Standards RIN4 FORCEOFF
7 22
• Operates With 3-V to 5.5-V VCC Supply RIN5 8 21 INVALID
• Always-Active Noninverting Receiver Output DOUT1 9 20 ROUT2B
(ROUT2B) DOUT2 10 19 ROUT1
• Designed to Transmit at a Data Rate up to DOUT3 11 18 ROUT2
500 kbit/s DIN3 12 17 ROUT3
• Low Standby Current . . . 1 μA Typ DIN2 13 16 ROUT4
DIN1 14 15 ROUT5
• External Capacitors . . . 4 × 0.1 μF
• Accepts 5-V Logic Input With 3.3-V Supply
• Designed to Be Interchangeable With Maxim QFN PACKAGE
(TOP VIEW)
MAX3243E

C2+
C1+
C2–

VCC
NC

NC
V+
V–

• Serial-Mouse Driveability
• Auto-Powerdown Feature to Disable Driver
32 31 30 29 28 27 26 25
Outputs When No Valid RS-232 Signal Is
Sensed RIN1 1 24 GND
• Package Options Include Plastic Small-Outline RIN2 2 23 C1–
(DW), Shrink Small-Outline (DB), and Thin RIN3 3 22 FORCEON
Shrink Small-Outline (PW) Packages
RIN4 4 21 FORCEOFF
RIN5 INVALID
APPLICATIONS 5 20

DOUT1 6 19 ROUTB2
• Battery-Powered Systems
DOUT2 7 18 ROUT1
• PDAs
DOUT3 8 17 ROUT2
• Notebooks
• Laptops 9 10 11 12 13 14 15 16

• Palmtop PCs
DIN3
DIN2
DIN1
NC

NC
ROUT5
ROUT4
ROUT3

• Hand-Held Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 IBM, PC/AT are trademarks of International Business Machines Corporation.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MAX3243E

SLLS657D – APRIL 2005 – REVISED SEPTEMBER 2011 www.ti.com

DESCRIPTION
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with
±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)
protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides the
electrical interface between an asynchronous communication controller and the serial-port connector. This
combination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, or
compatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V
supply. In addition, the device includes an always-active noninverting output (ROUT2B), which allows
applications using the ring indicator to transmit data while the device is powered down. The device operates at
data signaling rates up to 250 kbit/s and a maximum of 30-V/μs driver output slew rate.
Flexible control options for power management are available when the serial port is inactive. The
auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of
operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF is
set low, both drivers and receivers (except ROUT2B) are shut off, and the supply current is reduced to 1 μA.
Disconnecting the serial port or turning off the peripheral drivers causes the auto-powerdown condition to occur.
Auto-powerdown can be disabled when FORCEON and FORCEOFF are high, and should be done when driving
a serial mouse. With auto-powerdown enabled, the device is activated automatically when a valid signal is
applied to any receiver input. The INVALID output is used to notify the user if an RS-232 signal is present at any
receiver input. INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than –2.7 V
or has been between –0.3 V and 0.3 V for less than 30 μs. INVALID is low (invalid data) if all receiver input
voltages are between –0.3 V and 0.3 V for more than 30 μs. Refer to Figure 5 for receiver input levels.
The MAX3243EC is characterized for operation from 0°C to 70°C. The MAX3243EI is characterized for operation
from –40°C to 85°C.

ORDERING INFORMATION
TA PACKAGE (1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
MAX3243ECDW
SOIC – DW Tape and reel MAX3243EC
MAX3243ECDWR
MAX3243ECDB
SSOP – DB Tape and reel MAX3243EC
0°C to 70°C MAX3243ECDBR
MAX3243ECPW
TSSOP – PW Tape and reel MP243EC
MAX3243ECPWR
QFN – RHB Tape and reel MAX3243ECRHBR MP243E
MAX3243EIDB
SSOP – DB Tape and reel MAX3243EI
MAX3243EIDBR
MAX3243EIDW
SOIC – DW Tape and reel MAX3243EI
–40°C to 85°C MAX3243EIDWR
MAX3243EIPW
TSSOP – PW Tape and reel MP243EI
MAX3243EIPWR
QFN – RHB Tape and reel MAX3243EIRHBR MR243E

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

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 MAX3243E

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FUNCTION TABLES
ABC
Each Driver (1)
INPUTS OUTPUT
VALID RIN DRIVER STATUS
DIN FORCEON FORCEOFF DOUT
RS-232 LEVEL
X X L X Z Powered off
L H H X H Normal operation with
H H H X L auto-powerdown disabled
L L H Yes H Normal operation with
H L H Yes L auto-powerdown enabled
Powered off by auto-powerdown
X L H No Z
feature

(1) H = high level, L = low level, X = irrelevant, Z = high impedance

Each Receiver (1)

INPUTS OUTPUT
RECEIVER STATUS
RIN FORCEON FORCEOFF ROUT
X X L Z Powered off
L X H H
Normal operation with
H X H L
auto-powerdown disabled/enabled
Open X H H

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off

(1)
ROUT2B and Outputs INVALID
INPUTS OUTPUTS
VALID RIN OUTPUT STATUS
RIN2 FORCEON FORCEOFF INVALID ROUT2B
RS-232 LEVEL
Yes L X X H L
Yes H X X H H
Always active
Yes Open X X H L
No Open X X L L

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off

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LOGIC DIAGRAM (POSITIVE LOGIC)

14 9
DIN1 DOUT1

13 10
DIN2 DOUT2

12 11
DIN3 DOUT3

22
FORCEOFF
21
Auto-powerdown INVALID
23
FORCEON

19 4
ROUT1 RIN1
20
ROUT2B

18 5
ROUT2 RIN2

17 6
ROUT3 RIN3

16 7
ROUT4 RIN4

15 8
ROUT5 RIN5

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 MAX3243E

www.ti.com SLLS657D – APRIL 2005 – REVISED SEPTEMBER 2011

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(2)
VCC Supply voltage range –0.3 6 V
V+ Positive output supply voltage range (2) –0.3 7 V
V– Negative output supply voltage range (2) 0.3 –7 V
V+ – V– Output supply voltage difference (2) 13 V
Driver (FORCEOFF, FORCEON) –0.3 6
VI Input voltage range V
Receiver –25 25
Driver –13.2 13.2
VO Output voltage range V
Receiver (INVALID) –0.3 VCC + 0.3
DB package 62
θJA Package thermal impedance (3) (4)
DW package 46 °C/W
PW package 62
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network GND.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) - TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS (1)

See Figure 6
MIN NOM MAX UNIT
VCC = 3.3 V 3 3.3 3.6
Supply voltage V
VCC = 5 V 4.5 5 5.5
VCC = 3.3 V 2
VIH Driver and control high-level input voltage DIN, FORCEOFF, FORCEON V
VCC = 5 V 2.4
VIL Driver and control low-level input voltage DIN, FORCEOFF, FORCEON 0.8 V
VI Driver and control input voltage DIN, FORCEOFF, FORCEON 0 5.5 V
VI Receiver input voltage –25 25 V
MAX3243EC 0 70
TA Operating free-air temperature °C
MAX3243EI –40 85

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.

ELECTRICAL CHARACTERISTICS (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
II Input leakage current FORCEOFF, FORCEON ±0.01 ±1 μA
No load,
Auto-powerdown disabled 0.3 1 mA
FORCEOFF and FORCEON at VCC
Powered off No load, FORCEOFF at GND 1 10
Supply current
ICC
(TA = 25°C) No load, FORCEOFF at VCC,
FORCEON at GND, μA
Auto-powerdown enabled 1 10
All RIN are open or grounded,
All DIN are grounded

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

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DRIVER SECTION

Electrical Characteristics (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
VOH High-level output voltage All DOUT at RL = 3 kΩ to GND 5 5.4 V
VOL Low-level output voltage All DOUT at RL = 3 kΩ to GND –5 –5.4 V
Output voltage DIN1 = DIN2 = GND, DIN3 = VCC, 3-kΩ to GND at DOUT3,
VO ±5 V
(mouse driveability) DOUT1 = DOUT2 = 2.5 mA
IIH High-level input current VI = VCC ±0.01 ±1 μA
IIL Low-level input current VI at GND ±0.01 ±1 μA
Vhys Input hysteresis ±1 V
VCC = 3.6 V, VO = 0 V
IOS Short-circuit output current (3) ±60 mA
VCC = 5.5 V, VO = 0 V
ro Output resistance VCC, V+, and V– = 0 V, VO = ±2 V 300 10M Ω
Ioff Output leakage current FORCEOFF = GND, VO = ±12 V, VCC = 0 to 5.5 V ±25 μA

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.

Switching Characteristics (1)

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted) (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
CL = 1000 pF, RL = 3 kΩ
Maximum data rate 250 500 kbit/s
One DOUT switching, See Figure 1
tsk(p) Pulse skew (3) CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ, See Figure 2 100 ns
VCC = 3.3 V, CL = 150 pF to 1000 pF 6 30
Slew rate, transition region
SR(tr) RL = 3 kΩ to 7 kΩ, V/μs
(see Figure 1) CL = 150 pF to 2500 pF 4 30
PRR = 250 kbit/s

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V + 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.

ESD Protection
PARAMETER TEST CONDITIONS TYP UNIT
HBM ±15 kV
Driver outputs (pins 9–11) IEC61000-4-2, Air-Gap Discharge ±15 kV
IEC61000-4-2, Contact Discharge ±8 kV

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RECEIVER SECTION

Electrical Characteristics (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V
VOL Low-level output voltage IOH = 1.6 mA 0.4 V
VCC = 3.3 V 1.6 2.4
VIT+ Positive-going input threshold voltage V
VCC = 5 V 1.9 2.4
VCC = 3.3 V 0.6 1.1
VIT– Negative-going input threshold voltage V
VCC = 5 V 0.8 1.4
Vhys Input hysteresis (VIT+ – VIT– ) 0.5 V
Ioff Output leakage current (except ROUT2B) FORCEOFF = 0 V ±0.05 ±10 μA
ri Input resistance VI = ±3 V or ±25 V 3 5 7 kΩ

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

Switching Characteristics (1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TYP (2) UNIT
tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 3 150 ns
tPHL Propagation delay time, high- to low-level output 150 ns
ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 4 200 ns
tdis Output disable time 200 ns
tsk(p) Puse skew (3) See Figure 3 50 ns

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH - tPHL| of each channel of the same device.

ESD Protection
PARAMETER TEST CONDITIONS TYP UNIT
HBM ±15 kV
Driver outputs (pins 4–8) IEC61000-4-2, Air-Gap discharge ±15 kV
IEC61000-4-2, Contact Discharge ±8 kV

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AUTO-POWERDOWN SECTION

Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Receiver input threshold FORCEON = GND,
VIT+(valid) 2.7 V
for INVALID high-level output voltage FORCEOFF = VCC
Receiver input threshold FORCEON = GND,
VIT–(valid) –2.7 V
for INVALID high-level output voltage FORCEOFF = VCC
Receiver input threshold FORCEON = GND,
VT(invalid) –0.3 0.3 V
for INVALID low-level output voltage FORCEOFF = VCC
IOH = -1 mA, FORCEON = GND,
VOH INVALID high-level output voltage VCC – 0.6 V
FORCEOFF = VCC
IOL = 1.6 mA, FORCEON = GND,
VOL INVALID low-level output voltage 0.4 V
FORCEOFF = VCC

Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)
PARAMETER TEST CONDITIONS TYP (1) UNIT
tvalid Propagation delay time, low- to high-level output VCC = 5 V 1 μs
tinvalid Propagation delay time, high- to low-level output VCC = 5 V 30 μs
ten Supply enable time VCC = 5 V 100 μs

(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

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PARAMETER MEASUREMENT INFORMATION

3V
RS-232 Input
Output 0V
Generator
50 Ω
(see Note B) CL tTHL tTLH
RL (see Note A)
VOH
3V 3V 3V
FORCEOFF Output
−3 V −3 V VOL
SR(tr) + 6V
TEST CIRCUIT t THL or tTLH VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 1. Driver Slew Rate

3V
RS-232 Input 1.5 V 1.5 V
Output 0V
Generator
50 Ω
(see Note B) CL tPHL tPLH
RL (see Note A)
VOH
3V
Output 50% 50%
FORCEOFF
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 2. Driver Pulse Skew

3 V or 0 V
3V
FORCEON Input 1.5 V 1.5 V
−3 V
Output
Generator tPHL tPLH
50 Ω
(see Note B) CL
3V (see Note A)
VOH
FORCEOFF Output 50% 50%
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 3. Receiver Propagation Delay Times

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PARAMETER MEASUREMENT INFORMATION

3V
Input 1.5 V 1.5 V
VCC GND
3 V or 0 V −3 V
S1
FORCEON tPHZ tPZH
RL (S1 at GND) (S1 at GND)

3 V or 0 V Output VOH
Output 50%
CL 0.3 V
FORCEOFF (see Note A)
tPLZ tPZL
(S1 at VCC) (S1 at VCC)
Generator
50 Ω
(see Note B)
0.3 V
Output 50%
VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
C. tPLZ and tPHZ are the same as tdis.
D. tPZL and tPZH are the same as ten.

Figure 4. Receiver Enable and Disable Times

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PARAMETER MEASUREMENT INFORMATION

3V
2.7 V 2.7 V
Receiver 0V
Input 0V

ROUT −2.7 V −2.7 V

−3 V
Generator
50 Ω
(see Note B) tinvalid tvalid

VCC
50% VCC 50% VCC
INVALID 0V
Output
Auto- ten
INVALID
powerdown
CL = 30 pF V+ ≈V+
(see Note A) 0.3 V
Supply VCC
FORCEOFF Voltages 0V
0.3 V
DIN DOUT
FORCEON V− ≈V−

TEST CIRCUIT
ÎÎÎÎÎÎÎÎÎÎÎ
VOLTAGE WAVEFORMS

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Valid RS-232 Level, INVALID High

ÎÎÎÎÎÎÎÎÎÎÎ
2.7 V

ÎÎÎÎÎÎÎÎÎÎÎ
Indeterminate

ÎÎÎÎÎÎÎÎÎÎÎ
0.3 V
If Signal Remains Within This Region

ÎÎÎÎÎÎÎÎÎÎÎ
0V For More Than 30 µs, INVALID Is Low†

ÎÎÎÎÎÎÎÎÎÎÎ
−0.3 V

ÎÎÎÎÎÎÎÎÎÎÎ
Indeterminate
−2.7 V
Valid RS-232 Level, INVALID High

† Auto-powerdown disables drivers and reduces supply

current to 1 µA.

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 5. INVALID Propagation Delay Timnes and Supply Enabling Time

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APPLICATION INFORMATION

28
C1+
27
1 V+
+ C2+ +
C2 C3† +
− 2 −
C2− 26 C1
VCC −
+ CBYPASS
3
V− 25 − = 0.1 µF
− GND
C4
+ 24
C1−
4 23
RIN1 FORCEON
5
RIN2

powerdown
6

Auto-
RS-232 Inputs RIN3 22
FORCEOFF
7
RIN4
8
RIN5
21
INVALID

9 20
DOUT1 ROUT2B

10 19
RS-232 Outputs DOUT2 ROUT1

5 kΩ

11 18
DOUT3 ROUT2
5 kΩ
Logic Outputs

12 17
DIN3 ROUT3
5 kΩ

13 16
Logic Inputs DIN2 ROUT4
5 kΩ

14 15
DIN1 ROUT5
5 kΩ

† C3 can be connected to V
CC or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or
VCC vs CAPACITOR VALUES
electrolytic capacitors are used, they should be connected as shown.
VCC C1 C2, C3, and C4

3.3 V ± 0.3 V 0.1 µF 0.1 µF

5 V ± 0.5 V 0.047 µF 0.33 µF
3 V to 5.5 V 0.1 µF 0.47 µF

Figure 6. Typical Operating Circuit and Capacitor Values

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APPLICATION INFORMATION

ESD Protection
TI MAX3243E devices have standard ESD protection structures incorporated on the pins to protect against
electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver
outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures
were designed to successfully protect these bus pins against ESD discharge of ±15-kV in all states: normal
operation, shutdown, and powered down. The MAX3243E devices are designed to continue functioning properly
after an ESD occurrence without any latchup.
The MAX3243E devices have three specified ESD limits on the driver outputs and receiver inputs, with respect to
GND:
• ±15-kV Human Body Model (HBM)
• ±15-kV IEC61000-4-2, Air-Gap Discharge (formerly IEC1000-4-2)
• ±8-kV IEC61000-4-2, Contact Discharge

ESD Test Conditions

ESD testing is stringently performed by TI, based on various conditions and procedures. Please contact TI for a
reliability report that documents test setup, methodology, and results.

Human Body Model (HBM)

The Human Body Model of ESD testing is shown in Figure 7, while Figure 8 shows the current waveform that is
generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the
ESD voltage of concern, and subsequently discharged into the DUT through a 1.5k-Ω resistor.
RD

1.5 kΩ

+ CS 100 pF
VHBM DUT
−

Figure 7. HBM ESD Test Circuit

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APPLICATION INFORMATION
1.5

VHBM = 2 kV

1.0
I DUT (A)

0.5

DUT = 10-V 1-Ω Zener Diode

0.0
0 50 100 150 200

Time (ns)

Figure 8. Typical HBM Current Waveform

IEC61000-4-2 (Formerly Known as IEC1000-4-2)

Unlike the HBM, MM, and CDM ESD tests that apply to component level integrated circuits, the IEC61000-4-2 is
a system-level ESD testing and performance standard that pertains to the end equipment. The MAX3243E is
designed to enable the manufacturer in meeting the highest level (Level 4) of IEC61000-4-2 ESD protection with
no further need of external ESD protection circuitry. The more stringent IEC test standard has a higher peak
current than the HBM, due to the lower series resistance in the IEC model.
Figure 9 shows the IEC61000-4-2 model, and Figure 10 shows the current waveform for the corresponding
±8-kV Contact-Discharge (Level 4) test. This waveform is applied to a probe that has been connected to the
DUT. On the other hand, the corresponding ±15-kV (Level 4) Air-Gap Discharge test involves approaching the
DUT with an already energized probe.

50−100 MΩ 330 Ω

RC RD

High-Voltage + CS 150 pF DUT

DC Source −

Figure 9. Simplified IEC61000-4-2 ESD Test Circuit

14 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated

Product Folder Link(s): MAX3243E

 MAX3243E

www.ti.com SLLS657D – APRIL 2005 – REVISED SEPTEMBER 2011

APPLICATION INFORMATION

(30A) 100%

90% (Vcontact = 8 kV)

I Peak

(16A)

(8A)

10%

30 ns t
60 ns
tr = 0.7 ns to 1 ns

Figure 10. Typical Current Waveform of IEC61000-4-2 ESD Generator

Machine Model
The Machine Model (MM) ESD test applies to all pins using a 200-pF capacitor with no discharge resistance.
The purpose of the MM test is to simulate possible ESD conditions that can occur during the handling and
assembly processes of manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins.
However, after PC board assembly, the MM test is no longer as pertinent to the RS-232 pins.

Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): MAX3243E
MAX3243E

SLLS657D – APRIL 2005 – REVISED SEPTEMBER 2011 www.ti.com

REVISION HISTORY

Changes from Revision C (February 2009) to Revision D Page

• Deleted "VALID RIN RS-232 LEVEL" from INPUTS. ........................................................................................................... 3

• Deleted "ROUT2B is active" RECEIVER STATUS and combined ROUT outputs. .............................................................. 3
• Added New Table "ROUT2B and INVALID Outputs" defining truth table for ROUT2B and INVALID outputs. ................... 3
• Changed “VALID_RIN” entry from “YES” to “NO.” ............................................................................................................... 3

16 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated

Product Folder Link(s): MAX3243E

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MAX3243ECDB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3243EC

MAX3243ECDBG4 ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3243EC

MAX3243ECDBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3243EC

MAX3243ECDW ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3243EC

MAX3243ECDWR ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3243EC

MAX3243ECPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP243EC

MAX3243ECPWE4 ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP243EC

MAX3243ECPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP243EC

MAX3243ECPWRG4 ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP243EC

MAX3243ECRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 70 MP243E

MAX3243EIDB ACTIVE SSOP DB 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3243EI

MAX3243EIDBR ACTIVE SSOP DB 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3243EI

MAX3243EIDW ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3243EI

MAX3243EIDWR ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3243EI

MAX3243EIDWRG4 ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3243EI

MAX3243EIPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

MAX3243EIPWE4 ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

MAX3243EIPWG4 ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

MAX3243EIPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

MAX3243EIPWRE4 ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MAX3243EIPWRG4 ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP243EI

MAX3243EIRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 MR243E

MAX3243EIRHBRG4 ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 MR243E

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MAX3243ECDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
MAX3243ECDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
MAX3243ECPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MAX3243ECRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
MAX3243EIDBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
MAX3243EIDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
MAX3243EIPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MAX3243EIRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MAX3243ECDBR SSOP DB 28 2000 853.0 449.0 35.0
MAX3243ECDWR SOIC DW 28 1000 350.0 350.0 66.0
MAX3243ECPWR TSSOP PW 28 2000 853.0 449.0 35.0
MAX3243ECRHBR VQFN RHB 32 3000 853.0 449.0 35.0
MAX3243EIDBR SSOP DB 28 2000 853.0 449.0 35.0
MAX3243EIDWR SOIC DW 28 1000 350.0 350.0 66.0
MAX3243EIPWR TSSOP PW 28 2000 853.0 449.0 35.0
MAX3243EIRHBR VQFN RHB 32 3000 853.0 449.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DB0028A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1

2X
10.5
8.45
9.9
NOTE 3

14
15
0.38
28X
0.22
5.6 0.15 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214853/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0028A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

28X (1.85) SYMM

1 (R0.05) TYP

28X (0.45) 28

26X (0.65)

SYMM

14 15

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214853/B 03/2018
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0028A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

28X (1.85) SYMM

(R0.05) TYP
1
28X (0.45) 28

26X (0.65)

SYMM

14 15

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214853/B 03/2018
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224745/A

www.ti.com
 PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.1 B
A
4.9

PIN 1 INDEX AREA

5.1 (0.1)
4.9

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
20.000

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17 SEE SIDE WALL
DETAIL

2X SYMM
33
3.5

0.3
32X
0.2
24 0.1 C A B
1
0.05 C

32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.25)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17

(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.25)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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