Microprocessor

Microcontroller Systems

Chapter 4
CPU Architecture

‫ ﻭﺟﺩﻱ ﺳﻠﻳﻣﺎﻥ ﺍﻟﺣﻠﺑﻲ‬.‫ ﻡ‬.‫ ﺩ‬:‫ﻣﺩﺭﺱ ﺍﻟﻣﺳﺎﻕ‬

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 Outline of the Chapter

 1. CPU Architecture
 2. The Microprocessor unit
 2.1 Basic Microcomputer architecture
 2.2 the purpose of the major components of a computer
system
 2.3 The role of the CPU in computer systems
 2.4 Internal working of CPUs
 3. Harvard and von Neumann architectures

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 CPU ARCHITECTURE

 Introduction.
 In this section we will examine the inside of a CPU.
 Then, we will compare the
 Harvard and von Neumann architectures.

 Inside CPU_1.
 A program stored in memory provides instructions to the CPU to
perform an action.
 The action can simply be adding data such as payroll data or controlling a
machine such as a robot.
 The function of the CPU is to fetch these instructions from memory and
execute them.

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 CPU ARCHITECTURE

 Inside CPU_1.

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 CPU ARCHITECTURE

 Inside CPU_2.
 To perform the actions of fetch and execute, all CPUs are equipped with
resources such as the following:
1. Registers
 The CPU uses registers to store information temporarily.
» Two values to be processed,
» or the address of the value needed to be fetched from memory.

 Registers inside the CPU can be 8-bit, 16-bit, 32-bit, or even 64-bit
registers, depending on the CPU.
 In general, the more and bigger the registers, the better the CPU.
 The disadvantage of more and bigger registers is the increased cost of
such a CPU.

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 CPU ARCHITECTURE

 Inside CPU_3.
2. ALU (arithmetic/logic unit).
 The ALU section of the CPU is responsible for performing arithmetic
functions such as add, subtract, multiply, and divide, and logic
functions such as AND, OR, and NOT.
3. a Program Counter
 The function of the program counter is to point to the address of the
next instruction to be executed.
 As each instruction is executed, the program counter is incremented
to point to the address of the next instruction to be executed.
 The contents of the program counter are placed on the address bus to
find and fetch the desired instruction.
 In the IBM PC, the program counter is a register called IP, or the
instruction pointer.

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 CPU ARCHITECTURE

 Inside CPU_4.
4. Instruction decoder
 The function of the instruction decoder is to interpret the instruction
fetched into the CPU.
 One can think of the instruction decoder as a kind of dictionary,
storing the meaning of each instruction and what steps the CPU
should take upon receiving a given instruction.
 Just as a dictionary requires more pages the more words it defines, a
CPU capable of understanding more instructions requires more
transistors to design.

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 Internal working of CPUs

 Figure shows the steps that the CPU goes through to execute an instruction..

Assume that CPU has :

 Registers called A, B, C, and D.
 an 8-bit data bus
 and a 16-bit address bus.
 Therefore, the CPU can access memory from
addresses 0000 to FFFFH (for a total of
10000H locations).
 The action to be performed by the CPU is:
 to put hexadecimal value 21 into register
A,
 and then add to register A the values 42H
and 12H.

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 Internal working of CPUs

 The action to be performed by the CPU is:

 to put hexadecimal value 21 into register A,
 and then add to register A the values 42H and 12H.
Assume that:
• the code for the CPU to move a value to register A is 1011 0000
(B0H).
• and the code for adding a value to register A is 0000 0100 (04H).
The necessary steps and code to perform these operations are as follows.
Action Code Data
Move value 21H into register A B0H 21H
Add value 42H to register A 04H 42H
Add value 12H to register A 04H 12H

If the program to perform the actions listed above is stored in memory

locations starting at 1400H, the following would represent the contents
for each memory address location:

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 Internal working of CPUs

Action Code Data

Move value 21H into register A B0H 21H
Add value 42H to register A 04H 42H
Add value 12H to register A 04H 12H

If the program to perform the actions listed above is stored in memory

locations starting at 1400H, the following would represent the contents
for each memory address location:
Memory address Contents of memory address
1400 (B0) code for moving a value to register A
1401 (21) value to be moved
1402 (04) code for adding a value to register A
1403 (42) value to be added
1404 (04) code for adding a value to register A
1405 (12) value to be added
1406 (F4) code for halt

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 Internal working of CPUs

 The actions performed by the CPU to run the program above would
be as follows_1:
 The CPU’s program counter can have a value between 0000 and
FFFFH.
 The program counter must be set to the value 1400H, indicating
the address of the first instruction code to be executed.
 After the program counter has been loaded with the address of the
first instruction, the CPU is ready to execute.
 The CPU puts 1400H on the address bus and sends it out.
 The memory circuitry finds the location while the CPU activates
the READ signal, indicating to memory that it wants the byte at
location 1400H.
 This causes the contents of memory location 1400H, which is B0,
to be put on the data bus and brought into the CPU.

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 Internal working of CPUs

 The actions performed by the CPU to run the program above would be as
follows_2:
 The CPU decodes the instruction B0 with the help of its instruction
decoder dictionary.
 When it finds the definition for that instruction it knows it must bring the
byte in the next memory location into register A of the CPU.
 Therefore, it commands its controller circuitry to do exactly that.
 When it brings in value 21H from memory location 1401, it makes sure
that the doors of all registers are closed except register A.
 Therefore, when value 21H comes into the CPU it will go directly into
register A.
 After completing one instruction, the program counter points to the
address of the next instruction to be executed, which in this case is 1402H.
 Address 1402 is sent out on the address bus to fetch the next instruction..

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 Internal working of CPUs

 The actions performed by the CPU to run the program above would be as
follows_3:
 From memory location 1402H the CPU fetches code 04H.
 After decoding, the CPU knows that it must add the byte sitting at the
next address (1403) to the contents of register A.
 After the CPU brings the value (in this case, 42H) into register A, it
provides the contents of register A along with this value to the ALU to
perform the addition.
 It then takes the result of the addition from the ALU’s output and puts it
into register A.
 Meanwhile the program counter becomes 1404, the address of the next
instruction.
 Address 1404H is put on the address bus and the code is fetched into the
CPU, decoded, and executed. This code again is adding a value to register
A.
 The program counter is updated to 1406H.

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 Internal working of CPUs

 The actions performed by the CPU to run the program above would be as
follows_3:
 Finally, the contents of address 1406 are fetched in and executed. This
HALT instruction tells the CPU to stop incrementing the program counter
and asking for the next instruction.
 Without the HALT, the CPU would continue updating the program
counter and fetching instructions.
Now suppose that address 1403H contained value 04 instead of 42H. How would
the CPU distinguish between data 04 to be added and code 04?
Remember that code 04 for this CPU means “adds the next value into register A.”
Therefore, the CPU will not try to decode the next value. It simply adds the
contents of the following memory location into register A, regardless of its value.

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 Harvard and von Neumann
architectures
 Every microprocessor must have memory space to store program (code) and
data. While code provides instructions to the CPU, the data provides the
information to be processed.
 The CPU uses buses (wire traces) to access the code ROM and data RAM
memory spaces.
 The early computers used the same bus for accessing both the code and data.
 Such an architecture is commonly referred to as von Neumann (Princeton)
architecture.
 That means for von Neumann
computers, the process of
accessing the code or data
could cause them to get in
each other’s way and slow
down the processing speed of
the CPU, because each had
to wait for the other to
finish fetching.
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 Harvard and von Neumann
architectures
 To speed up the process of program execution, some CPUs use what is called
Harvard architecture.
 In Harvard architecture, we have separate buses for the code and data
memory.
 That means that we need four sets of buses:
 (1) a set of data buses for carrying data into and out of the CPU,
 (2) a set of address buses for accessing the data,
 (3) a set of data buses
for carrying code into
the CPU,
 and (4) an address
bus for accessing the
code.

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 Harvard and von Neumann
architectures
 Harvard architecture is easy to implement inside an IC chip such as a
microcontroller where both ROM code and data RAM are internal (on-chip)
and distances are on the micron and millimeter scale.
 But implementing Harvard architecture for systems such as x86 IBM PC-type
computers is very expensive because the RAM and ROM that hold code and
data are external to the CPU.
 Separate wire traces for data and code on the motherboard will make the
board large and expensive.
 For example, for a Pentium microprocessor with a 64-bit data bus and a
 32-bit address bus we will need about 100 wire traces on the motherboard if it
is von Neumann architecture (96 for address and data, plus a few others for
control signals of read and write and so on). But the number of wire traces will
double to 200 if we use Harvard architecture.
 A large number of pins coming out of the microprocessor itself.

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 Harvard and von Neumann
architectures

 For this reason you do not see Harvard architecture implemented in the world
of PCs and workstations.
 This is also the reason that microcontrollers such as AVR use Harvard
architecture internally,
 but they still use von Neumann architecture if they need external memory for
code and data space.
 The von Neumann architecture was developed at Princeton University, while
the Harvard architecture was the work of Harvard University.

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