Unit-2: ARM Instruction Set

Course content and pattern of marks for SEE

Unit Questions to be set for SEE Marks Weightage

Unit Name Hour
No. R U A AN E C Weightage (%)
ARM Instruction
2 10 -- 05 05 05 05 05 25 20
Set

Semester End-exam Evaluation (SEE)

No. of Questions for End
Study
UNIT Exam
Unit Name Duration
No. 5 Marks 10 Marks
(Hrs.)
Part - A Part – B
2 ARM Instruction Set 10 1 2

5Marks
Understanding
1. Explain conditional execution with an example.
2. Explain MAC unit with an example.
3. Explain Barrel shifter with a neat sketch.
4. Explain 5 different shift operations that can be used with Barrel shifter.
5. List compare instructions & Write the useful of AND, ORR, EOR
instructions
6. Describe the difference between ADR & ADRL
Application
1. List the data processing instructions with one example each.
2. Explain stack operation using STM & LDM instructions.
3. Explain SWAP & SWI instructions with example
4. Explain AND & EOR instructions with example
5. Explain TST & TEQ instructions with example
6. Write a note on software interrupt instruction.
Analyse
1. Predict the operation performed by the execution of each compare
instruction
2. Calculate the effective address of the following instructions if register
R3=0x4000
and register R4=0x20
(i) STRH R9,[R3,R4]
(ii) LDRB R8,[R3,R4,LSL #3]
(iii)LDR R7,[R3],R4
(iv)STRB R6,[R3],R4,ASR #2
(v) LDR R0,[R3,-R4,LSL #3]
Evaluate
1. Distinguish between post & pre indexed addressing mode with an
example
Create
1. Test whether the following instruction are pre or post indexed addressing
mode
(i) STR R6,[R4,#4]
(ii) LDR R3,[R12],#6
(iii)LDRB R4,[R3,R2]
(iv)LDR R6,[R0,R1,ROR #6]
(v) STR R3,[R0,R5,LSL #3]
2. Write the instruction to perform the following operations
(i) Add number 256 to R1, place the sum in register R2
(ii) Place a 2’s complement of -1 into register R3
(iii)ANDing , R1 content with the complement of 256,place the result in
register R2
(iv)To returning from subroutine
(v) Copy a complement of 4 into R1
 UNIT 2: ARM INSTRUCTION SET

Different ARM architecture versions support different instructions. However, new versions
usually add instructions and remain backwardly compatible. Some instructions have extended
functionality in later architectures.

The ARM7-TDMI CPU provide two instruction sets:

 ARM Instruction Set: Executes 32-bit, word aligned ARM instructions. The ARM
instruction set is selected after CPU reset or an interrupt

 Thumb instruction set: 16-bit, half-word-aligned Thumb instructions. The Thumb

Instruction set allows maximum code density. On Flash based Embedded systems it
even provides a higher execution speed (due to smaller BUS width required).

The ARM and Thumb Instruction set is changed using the BX instruction. The Thumb
instruction set is indicated by the Thumb bit in the Program Status Register.
The ARM CPU supports the following data types by the instruction set:
 Double word (64-bit) are accessed via the instructions LDRD and STRD
 Word (32-bit) are accessed via the instructions LDR and STR
 Halfword (16-bit) are accessed via the instructions LDRH, LDRSH and STRH
 Byte (8-bit) are accessed via the instructions LDRB, LDRSB and STRB
Condition Code:
The hexadecimal numbers are prefixed with 0x and binary numbers with the prefix 0b.
Arm instructions process data held in registers and only access memory with load and store
instructions. Arm instructions commonly take two or three operands.

Most ARM instructions and the Thumb Branch instructions include a condition field.
This field is marked in the CPU instructions with {cond}.
A conditional instruction is only executed on match of the condition flags in the
Program Status Register. For example BEQ (B Instruction with EQ condition) branches only
if the Z flag is set. If the {cond} field is empty the instruction is always executed.

Table 1:
{cond} Suffix Tested Status Flags Description
EQ Z set Equal
NE Z clear Not equal
CS/HS C set Unsigned higher or same
CC/LO C clear Unsigned lower
MI N set Negative
PL N clear Positive or zero
VS V set overflow
VC V clear No overflow
HI C set and Z clear Unsigned higher
LS C clear or Z set Unsigned lower or same
GE N equals V Signed greater or equal
LT N not equal to V Signed less than
GT Z clear AND (N equals V) Signed greater than
LE Z set OR (N equal to V) Signed less than or equal
AL (ignored) Always (usually omitted)
Data processing Instructions :
The data processing instructions manipulate data within registers. They are move
instructions, arithmetic instructions, logical instructions, comparison instructions, and
multiply instructions. Most data processing instructions can process one of their operands
using the barrel shifter.
If ‘S’ Suffix is used on a data processing instructions, then it updates the flags in the
cpsr. Move and logical operations update the carry flag C, negative flag N, and zero flag Z.
the carry flag is set from the result of the barrel shift as the last bit shifted out. The N flag is
set to bit 31 of the result. The Z flag is set if the result is zero.

MOVE Instructions:
Move is the simplest Arm instruction. It copies N into a destination register Rd, where N is a
register or immediate value. This instruction is useful for setting initial values and
transferring data between registers.

Syntax:
<instruction>{<cond>} Rd, N

MOV Move a 32-bit value into a register Rd=N

MVN Move the NOT of the 32-bit value into a register Rd=~N

Table (2) gives a full description of the values allowed for the second operand N for all data
processing. Usually it is a register Rm or a constant preceded by #.

Barrel Shifter:-
In MOV instruction where N is a simple register. But N can be more than just a register or
immediate value; it can also be a register Rm that has been preprocessed by the barrel shifter
prior to being used by a data processing instruction.
Data processing instructions are processed within the arithmetic logic unit (ALU). A
unique and powerful feature of the ARM processor is the ability to shift the 32-bit binary
number pattern in one of the source registers left or right by a specific number of positions
before it enters the ALU. This shift increases the power and flexibility of many data
processing operations.
There are data processing instructions that do not use the barrel shift, for example the
MUL (multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add)
instructions.
Preprocessing or shift occurs within the cycle time of the instruction. This is particularly
useful for loading constants into a register and achieving fast multiplies or divisions by a
power of 2.

Rn
Rn

Pre-processing
No pre-processing
Barrel Shifter

Result N

Arithmetic logic unit

Rd

Figure : Barrel shifter and ALU.

Table(2): Barrel Shift operation syntax for data processing instructions.
N Shift operations Syntax
Immediate #immediate
Register Rm
Logical shift left by immediate Rm, LSL # shift_imm
Logical shift left by register Rm, LSL Rs
Logical shift right by immediate Rm, LSR #shift_imm
Logical shift right with register Rm, LSR Rs
Arithmetic shift right by immediate Rm, ASR #shift_imm
Arithmetic shift right by register Rm, ASR Rs
Rotate right by immediate Rm, ROR #Shift_imm
Rotate right by register Rm, ROR Rs
Rotate right with extend Rm, RRX
Arithmetic Instructions:-
The arithmetic instructions implement addition and subtraction of 32-bit signed and unsigned
values.
Syntax:
<instruction>{<cond>}{S} Rd, Rn, N
ADC Add two 32-bit values and carry Rd=Rn+N+carry
ADD Add two 32-bit values Rd=Rn+N
RSB Reverse subtract of two 32-bit values Rd=N-Rn
RSC Reverse subtract with carry of two 32bit values Rd=N-Rn-!(carry flag)
SBC Subtract with carry of two 32-bit values Rd=Rn-N-!(carry flag)
SUB Subtract two 32-bit values Rd=Rn-N

N is the result of the shifter operation.

Using Barrel Shifter with Arithmetic instructions:

The wide range of second operand shifts available on arithmetic and logical instructions is a
very powerful feature of the ARM instruction set. Example 1. Shows the use of the inline
barrel shifter with an arithmetic instruction. The instruction multiplies the value stored in
register r1.

Example 1: Register r1 is first shifted one location to the left to give the value of twice r1.
The ADD instruction then adds the result of the barrel shifter operation to register r1. The
final result transferred into register r0 equal to three times the value stored in register r1.
PRE r0 = 0x00000000
r1 = 0x00000005

ADD r0, r1, r1, LSL #1

POST r0 = 0x0000000f
r1 = 0x00000005

Logical instructions:
Logical instructions perform bitwise logical operations on the two source registers.

Syntax:
<instruction>{<cond>}{S} Rd, Rn, N
AND Logical bitwise AND of two 32-bit values Rd = Rn & N
ORR Logical bitwise OR of two 32-bit values Rd = Rn | N
EOR Logical exclusive OR of two 32 – bit values Rd = RnˆN
BIC Logical bit clear (AND NOT) Rd = Rn & ~N
Example 2: This example shows logical OR between registers r1 and r2. r0 holds the result
PRE r0 = 0x00000000
r1 = 0x02040608
r2 = 0x10305070
ORR r0, r1, r2

POST r0 = 0x121345678

Example 3: This example shows a more complicated logical instruction called BIC, which
carries out a logical bit clear.
PRE
r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2

POST r0 = 0b1010

This is equivalent to
Rd = Rn AND NOT (N)
In this example , register r2 contains a binary bit pattern where every binary 1 in r2 clears a
corresponding bit location in register r1. This instruction is particularly useful when clearing
status bits and is frequently used to change interrupt masks in the cpsr.
The logical instructions update the cpsr flags only if the suffix S is present. These
instructions can use barrel-shifted second operands in the same way as the arithmetic
instructions.

Comparison instructions:
The comparison instructions are used to compare or test a register with a 32-bit value. They
update the cpsr flag bits according to the result, but do not affect other registers. After the bits
have been set, the information can then be used to change program flow by using conditional
execution.
Note:- No need to apply the S suffix for comparison instructions to update the flags.

Syntax:
<instruction>{<cond>} Rn, N
CMN Compare signed Flags set as a result of Rn+N
CMP Compare Flags set as a result of Rn-N
TEQ Test for equality of two 32-bit values Flags set as a result of RnˆN
TST Test bits of a 32-bit value Flags set as a result of Rn & N
N is the result of the shifter operation.
Example 4: This example shows a CMP instruction. Both registers r0 and r9 are equal before
executing the instruction. The value of the z lag prior to execution is 0 and is represented by a
lower case z. after execution the z flag changes to 1 or an uppercase Z. This change indicates
equality.

PRE cpsr = nzcvqiFt_USER

r0 = 4
r9 = 4
CMP r0, r9

POST cpsr = nZcvqiFt_USER

The CMP is effectively a subtract instruction with the result discarded; similarly the TST
instruction is a logical And operation, and TEQ is a logical exclusive OR operation. For each,
the results are discarded but the condition bits re updated in the cpsr.
It is important to understand that comparison instructions only modify the condition flags of
the cpsr and do not affect the registers being compared.

Multiply instructions:
The multiply instructions multiply the contents of a pair of registers and depending upon the
instruction, accumulate the results in with another register. The long multiplies accumulate
onto a pair of registers representing a 64-bit value. The final result is placed in a destination
register or a pair of registers.

Syntax:
MLA{<cond>}{S} Rd, Rm, Rs, Rn
MUL{<cond>}{S} Rd, Rm, Rs

MLA Multiply and accumulate Rd = (Rm * Rs) + Rn

MUL Multiply Rd = Rm * Rs

Syntax:
<instruction>{<cond>{S} RdLo, RdHi, Rm, Rs

SMLAL Signed multiply accumulate long [Rdhi,RdLo]=[RdHi,RdLo]+(Rm*Rs)

SMULL Signed multiply long [RdHi, RdLo]=Rm*Rs
UMLAL Unsigned multiply accumulate long [RdHi, RdLo]= [RdHi,RdLo]+(Rm*Rs)
UMULL Unsigned multiply long [RdHi, RdLo]=Rm*Rs
The number of cycles taken to execute a multiply instruction depends on the processor
implementation. For some implementations the cycle timing depends on the value in Rs.
Branch instructions:
A branch instruction changes the flow of execution or is used to call a routine. This type of
instruction allows programs to have subroutines, if-then-else structures, and loops. The
change of execution flow forces the program counter pc to point to a new address. The
ARMv5E instruction set includes four different branch instructions.
Syntax:-
B {<cond>} label
BL{<cond>} label
BX{<cond>} Rm
BLX {<cond>} label | Rm

B Branch pc=label
BL Branch with link pc=label
lr=address of the next instruction after the BL
BX Branch exchange pc=Rm & 0xfffffffe, T=Rm & 1
BLX Branch exchange with pc=label, T =1
link pc = Rm & 0xfffffffe, T = Rm & 1
lr = address of the next instruction after the BLX

The address label is stored in the instruction as a signed pc-relative offset and must be within
approximately 32 MB of the branch instruction. T refers to the Thumb bit in the cpsr. When
instruction set T, the ARM switches to Thumb state.
Branches are used to change execution flow. Most assembler hide the details of a
branch instruction encoding by using labels.

Load – Store Instructions:

Load- store instructions transfer data between memory and processor registers. There
are three types of load-store instructions: single-register transfer, multiple-register and swap.

Single-Register Transfer :-
These instructions are used for moving a single data item in and out of a register. The data
types supported are signed and unsigned words (32-bit), half words(16-bit) and bytes.
The various load-store single-register transfer instructions.

Syntax:
<LDR | STR > {<cond>} {B} Rd, addressing
LDR{<cond>}SB |H| SH Rd, addressing
STR{<cond>}H Rd, addressing
LDR Load word into a register Rd<-mem32[address]
STR Save byte or word from a register Rd->mem32[address]
LDRB Load byte into a register Rd<-mem8[address]
STRB Save byte from a register Rd->mem8[address]
LDRH Load halfword into a register Rd<-mem16[address]
STRH Save halfword into a register Rd ->mem16[address]
LDRSB Load signed byte into a register Rd<- Sign extend (mem8[address])
LDRSH Load signed halfword into a register Rd<- Sign extend (mem16[address])

Multiple register transfer:-

Load-store instructions can transfer multiple registers between memory and the processor in a
single instruction. The transfer occurs from a base register Rn pointing into memory. Multiple
register transfer instructions are more efficient from a single register transfers for moving
blocks of data around memory and saving and restoring context and stacks.

LDM – Load Multiple

There are three distinct variants of the LDM instruction. Two of them are for use in
conjunction with exception processing.

Syntax:

LDM{<cond>}<addressing mode>Rn{!},<registers>
if (cond)
start_address ←Rn
for i=0 to 14
if(register_list[i] = = 1)
Ri ← memory[next_address]
If(register_list[15] = = 1)
PC ← memory [next_address] & 0xFFFFFFFC
if (writeback)
Rn ← end_address

Flags updated: None

The LDM instruction permits block moves of memory to the registers and enables efficient
stack operations. The registers may be listed in any order, but the registers are always loaded
in order with the lowest numbered register getting the value from the lowest memory address.
If Rn is also listed in the register list and register writeback (W bit) is set, the final value is
unpredictable.
The addressing_mode field determines how next_address is calculated (bits P and W),
which controls how the address is updated in conjunction with each register load.
The four addressing modes values are
 IA – increment address by 4 after each load (post increment)
 IB – increment address by 4 before each load (pre-increment)
 DA –decrement address by 4 after each load (post decrement)
 DB – decrement address by 4 before each load (pre-decrement)

STM – Store Multiple

There are two distinct variants of the STM instruction. One of them are for use in
conjunction with exception processing.

Syntax:
STM{<cond>}<addressing mode>Rn{!},<registers>
if (cond)
start_address . Rn
for i=0 to 15
if(register_list[i] = = 1)
memory[next_address] . Ri
if (writeback)
Rn . end_address

Flags updated: None

The STM instruction permits block moves of registers to the memory and enables efficient
stack operations. The registers may be listed in any order, but the registers are always stored
in order with the lowest numbered register going to the lowest memory address. If Rn is also
listed in the register list and register writeback (W bit) is set, the final value is unpredictable.
The addressing_mode field determines how next_address is calculated (bits P and W),
which controls how the address is updated in conjunction with each register load. The four
addressing modes values are

 IA – increment address by 4 after each load (post increment)

 IB – increment address by 4 before each load (pre-increment)
 DA –decrement address by 4 after each load (post decrement)
 DB – decrement address by 4 before each load (pre-decrement)

Stack Operations using STM and LDM instructions:-

For use in conjunction with stack addressing, four alternative names can be used for the
addressing modes. These names are based on the type of stack being used instead of the
addressing mode being used. This eliminates confusion in coding stack push and pop
operations, since the type of stack will be the same for both LDM and STM instructions. In
ARM syntax, a full stack is one where the stack pointer points to the last used(full) location.
An empty stack is one where the stack pointer points to the next available (empty) stack
location. As well a stack can grow through increasing memory addresses(ascending) or
downward through decreasing memory addresses(descending)
 FA (full ascending) – post decrement (DA) on pop
 FD (full descending) – post increment(IA) on pop
 EA (empty ascending) – pre-decrement(DB) on pop
 Ed (empty descending)-pre increment on(IB) on pop

SWAP Instruction
The swap instruction is a special case of a load-store instruction. It swaps the contents of
memory with the contents of a register. This instruction is an atomic operation – it reads and
writes a location in the same bus operation, preventing any other instructions from reading or
writing to that location until it completes.

Syntax:
SWP {B} {<Cond>} Rd, Rm, [Rn]

SWP Swap a word between memory and tmp=mem32[Rn]

a register mem32[Rn] = Rm
Rd=tmp
SWPB Swap a bye between memory and a tmp=mem8[Rn]
register mem8[Rn] = Rm
Rd=tmp

Swap cannot be interrupted by any other instruction or any other bus access. The system
“holds the bus” until the transaction is complete.
Software interrupt instruction
A software interrupt instruction(SWI) causes a software interrupt exception, which provides a
mechanism for applications to call system routines.

Syntax:
SWI {<cond>} SWI_number

SWI Software interrupt lr_svc=address of instruction following the SWI

spsr_svc=cpsr
pc=vectors+0x8
cpsr mode = SVC
cpsr I = 1 (mask IRQ interrupts)

When the processor executes an SWI instruction, it sets the program counter pc to the offset
0x8 in the vector table. The instruction also forces the processor mode to SVC, which allows
an operating system routine to be called in a privileged mode.
Each SWI instruction has an associated SWI number, which is used to re[present a
particular function or feature.

Loading Constants with Pseudo Instructions:

There are no Arm instructions to move a 32-bit constant into a register. Since ARM
instructions are 32 bits in size, they obviously cannot specify a general 32-bit constant. To aid
programming there are two pseudo instructions to move a 32-bit value into a register.
Syntax:
LDR Rd, =constant
ADR Rd, label

LDR Load constant pseudoinstruction Rd = 32-bit constant

ADR Load address pseudoinstruction Rd = 32-bit relative address
The first instruction writes a 32-bit constant to a register using whatever instructions
are available. It defaults to a memory read if the constant cannot be encoded using other
instructions.
The second pseudoinstruction writes a relative address into a register, which will be
encoded using a pc-relative expression.

ADR – Load Address (Short range)

Syntax:
ADR{cond}<Rd>, label
The ADR pseudo-instruction assembles to a single ADD or SUB instruction normally
with the PC as an operand. This produces position-independent code. The assembler will
report an error if it cannot create a valid instruction to load the address. If the label is
program-relative, it must be in the same assembler area as the ADR instruction. (The ADRL
psedu-instruction can reach a wider address range.)
ADRL – Load Address (medium range)

Syntax:
ADRL{cond} <Rd>, <label>

The ADRL pseudo-instruction will always generate a two instruction sequence to load the
address of the given label into the destination register, giving it a wider target range than the
ADR instruction. The code is position-independent. The assembler will report an error if it
cannot create a valid instruction sequence. (The LDR pseudo-instruction with a label
argument can reach any address.)

ASR – Arithmetic Shift Right

Syntax:
ASR{cond}{S}<Rd>, <Rm>, <Rs>
ASR{cond}{S}<Rd>,<Rm>,<#shift_count>

ASR is a synonym for the MOV instruction with an ASR-shifted register operand. If an
immediate shift count is used, it is limited to the range 1-32. If Rm is not included, the
assembler will assume it is the same as Rd.

ASR r0, r1 is equivalent to MOV r0, r0, ASR r1

ASR r0, r1, r2 is equivalent to MOV r0, r1, ASR r2

LSL – Logical Shift Left

Syntax:
LSL{cond}{S}<Rd>, <Rm>, <Rs>
LSL{cond}{S}<Rd>, <Rm>, <#shift_count>

LSL is a synonym for the MOV instruction with an LSL shifter operand. If an immediate
shift count is used, it is limited to the range 0-31. If Rm is not included, the assembler will
assume it is the same as Rd.
LSL r0, r1 is equivalent to MOV r0, r0, LSL r1
LSL r0, r1, r2 is equivalent to MOV r0, r1, LSL r2

LSR – Logical Shift Right

Syntax:
LSR{cond}{S}<Rd>, <Rm>, <Rs>
LSR{cond}{S}<Rd>, <Rm>, <#shift_count>
LSR is a synonym for the MOV instruction with an LSR shifter operand. If an shift count is
used, it is limited to the range 1-32. If Rm is not included, the assembler will assume it is the
same as Rd.
LSR r0, r1 is equivalent to MOV r0, r0, LSR r1
LSR r0, r1, r2 is equivalent to MOV r0, r1, LSR r2
NOP – No operation
Syntax:
NOP
There are numerous ways to encode a NOP (no operation) instruction for the ARM7TDMI
processor, such as adding 0 to a register, ORing a register with 0, branching to the next
instruction etc. the actual encoding of the NOP is assembler –dependent.

POP – Pop
Syntax:
POP{cond} reg_list
POP is a pseudonym for the LDMIA instruction, with R13 specified for the base register
(Rn). The PUSH/POP instructions assume a full descending (FD) stack organization.

PUSH – Push
PUSH is a pseudonym for the STMDB instruction, with R13 specified for the base
register (Rn). The PUSH/POP instructions assume a full descending (FD) stack organization.

ROR – Rotate Right

Syntax:
ROR{cond}{S}<Rd>, <Rm>, <Rs>
ROR{cond}{S}<Rd>, <Rm>, <#shift_count>
ROR is a synonym for the MOV instruction with an ROR shifter operand. If an immediate
shift count is used, it is limited to the range 1-31. If Rm is not included, the assembler will
assume it is the same as Rd.
ROR r0, r1 is equivalent to MOV r0, r0, ROR r1
ROR r0, r1, r2 is equivalent to MOV r0, r1, ROR r2

RRX – Rotate Right with Extend

Syntax:
RRX{cond}{S}<Rd>, <Rm>
RRX is a synonym for the MOV instruction with an RRX shifter operand. If Rm is not
included, the assembler will assume it is same as Rd.
RRX r0 is equivalent to MOV r0, r0, RRX
RRX r0, r1 is equivalent to MOV r0, r1, RRX
Program Status Register Instructions
The ARM instruction set provides two instructions to directly control a program status
register (psr). The MRS instruction transfers the contents of either the cpsr or spsr into a
register; in the reverse direction, the MSR instruction transfers the contents of a register into
the cpsr or spsr. Together these instructions are used to read and write the cpsr and spsr.
In the syntax you can see label called fields. This can be any combination of control(c),
extension(x), status(s) and flags(f). These fields relate to particular byte regions in a cpsr as
shown in figure.
Syntax:
MRS {<cond>} Rd,<cpsr|spsr>
MSR {<cond>} <cpsr|spsr>_<fields>, Rm
MSR{<cond>} <cpsr|spsr>_<fields>,#immediate

MRS Copy program status register to a general-purpose register Rd=psr

MSR Move a general-purpose register to a program status register psr[field]=Rm
MSR Move an immediate value to a program status register psr[field]=immediate

The c field controls the interrupt masks, thumb state, and processor mode.

Example: The MSR first copies the cpsr into register r1. The BIC instruction clears bit 7 of
r1. Register r1 is then copied back into the cpsr, which enables IRQ interrupts. This example
code preserves all the other settings in the cpsr and only modifies the I bit in the control field.
PRE cpsr = nzcvqIFt_SVC
MRS r1, cpsr
BIC r1, r1, #0x80 ;0b01000000
MSR cpsr_c, r1
POST cpsr = nZcvqiFt_SVC
This example is in SVC mode. In user mode you can read all cpsr bits, bur you can only
update the conditional flag field f.
Conditional Execution
Most ARM instructions are conditionally executed i.e. you can specify that the
instruction only executes if the condition code flags pass a given condition or test, by using
conditional execution instructions you can increase performance and code density.
The condition field is a two letter mnemonic appended to the instruction mnemonic.
The default mnemonic is AL, or always exec ute.
Conditional execution reduces the number of branches, which also reduces the
number of pipeline flushes and thus improves the performance of the executed code.
Conditional execution depends upon two components: the condition field and condition flags.
The condition field is located in the instruction and the conditional flags are located in the
cpsr.
Example: This example shows an ADD instruction with the EQ condition appended. This
instruction will only be executed when the zero flag in the cpsr is set to 1.
;r0 = r1+r2 if zero flag is set
ADDEQ r0, r1, r2
Only comparison instructions and data processing instructions with the S suffix appended to
the mnemonic update the condition flags in the cpsr.
Example: To help illustrate the advantage of conditional execution, we will take the simple C
code fragment shown in this example and compare the assembler output using nonconditional
and conditional instructions.
While(a!=b)
{
If (a>b) a-= b; else b-=a;
}
Let register r1 represent a and register r2 b. The following code fragment shows the same
algorithm written in ARM assembler. This example only uses conditional execution on the
branch instructions:
:Greatest Common Divisor Algorithm
gcd
CMP r1, r2
BEQ complete
BLT lessthan
SUB r1, r1, r2
B gcd
Lessthan
SUB r2, r2, r1
B gcd
Complete
...
Now compare the same code with full conditional execution. As you can see this dramatically
reduces the number of instructions:
gcd
CMP r1, r2
SUBGT r2, r2, r1
BNE gcd