1

EECE211 Fall 2021

Chapter 6. Field-Effect Transistor (FET)
- FET is a three-terminal device consisting of
Source: supplies carriers
Drain: collects carriers
Gate: controls carrier flow

- The Generic FET

 2

• In the generic FET

- A PN junction exists between the FET and the substrate
- The junction should not be forward biased (often the substrate is connected to the source)
- Virtually no DC current flows into or out of the gate
- Applying a voltage to the gate produces an electric field that affects the conductance of the channel, but
the gate itself does not conduct

• In an n-channel FET
- The channel carriers are electrons
- The drain voltage with respect to the source, VDS, is positive
- Electrons flow from source to drain
- The current ID by convention is defined as positive going from drain to source and is therefore positive.

• In a p-channel FET
- The channel carriers are holes
- The drain voltage with respect to the source, VDS, is negative
- Holes flow from source to drain
- So, the current ID is negative
 3

- I-V Characteristic

n-FET p-FET

n-FET in a circuit
 4

- Example: CMOS (complementary Metal-Oxide-Semiconductor) Inverter

 5
6.2 The Junction FET(JFET)
1. Types of FET
JFET: Junction FET; using depletion region of a reverse biased junction

MESFET: Metal-Semiconductor FET; using reverse biased Schottky barrier

MISFET: Metal-Insulator-Semiconductor FET

MOSFET: Metal-Oxide-Semiconductor FET

2. JFET

Figure 6–3 Simplified cross-sectional view of a junction FET: (a) transistor geometry; (b) detail of the channel
and voltage variation along the channel with VG = 0 and small ID.
 6
6.2 The Junction FET
- Typical I-V Characteristic of JFET

Figure 6–4 Depletion regions in the channel of a JFET

with zero gate bias for several values of VD: (a) linear
range; (b) near pinch-off; (c) beyond pinch-off.

* Pinch-off

* Saturation

* Gate Control

* Input impedance;
high because of reverse biased
pn junction

Figure 6–5 Effects of a negative gate bias: (a)

increase of depletion region widths with VG
negative; (b) family of current–voltage curves for
the channels as VG is varied.
 7
6.2 The Junction FET
- Pinch-off Voltage
For a reverse biased p+-n junction, the depletion width is given by (From Eq. 5-57)
1/2 1/2
2𝜀(𝑉0 − 𝑉) 𝑁𝐴 + 𝑁𝐷 2𝜀 1/2
𝑊 𝑥 = ≈ −𝑉𝐺𝐷
𝑞 𝑁𝐴 𝑁𝐷 𝑞𝑁𝐷

for V0 | V | & N A  N D

(V; + for forward bias, - for reverse bias)

With VG  0, VS  0, VD  VD ,
sourcelocated at x  0
& drain located at x  L,
the depletion width W at x  L is
1/2
2𝜀 −𝑉𝐺𝐷
𝑊 𝑥=𝐿 = ← (𝑉𝐺𝐷 = 𝑉𝐺 − 𝑉𝐷 )
𝑞𝑁𝐷

Pinch-off occurs at
h 𝑥 =𝐿 =𝑎−𝑊 𝑥 =𝐿
i. 𝑒. , 𝑊 𝑥 = 𝐿 = 𝑎
𝑞𝑁𝐷 𝑎2 Figure 6-6 Simplified diagram of the channel
→ 𝑉𝑃 = ∶ 𝐩𝐢𝐧𝐜𝐡 − 𝐨𝐟𝐟 𝐯𝐨𝐥𝐭𝐚𝐠𝐞
2𝜀 with definitions of dimensions and differential
volume for calculations.
 8
6.2 The Junction FET
- I-V Characteristics
Let the width (depth) of channel in the z-direction is Z.
dx
Resistance of the volume element in x ~ x  dx : : ,  : resistivit y of the n - type material
Z 2h( x )
Since voltage difference across x ~ x  dx is dV x , the drain current is given by

2 Zh ( x) dVx
ID  ( = constant along x )
 dx
1/ 2
 2(VGx ) 
h( x )  a  W ( x )  a   
 qN D 
  V  V 1 / 2 
 a 1   x  
G 
(VGx  VG  Vx )
  VP  

2Za   Vx  VG  
1/ 2
L VD
 o
I D dx  I D L  
0
1
   V p  
dVx
 
VD

2Za  
3/ 2
2V p  Vx  VG 
 Vx    
  3  V  
  p  0

2Za VD 2   VG 
3/ 2 3/ 2
 2  V V 
 ID  Vp     D G 
L  V p 3  V p 
 3  V p  
 
 9
6.2 The Junction FET
- I-V Characteristics
The drain current equation:

3/2 3/2
𝑉𝐷 2 𝑉𝐺 2 𝑉𝐷 − 𝑉𝐺
𝐼𝐷 = 𝐺0 𝑉𝑃 + − −
𝑉𝑃 3 𝑉𝑃 3 𝑉𝑃
2𝑍𝑎
𝐺0 = :conductacne of the channel at low ID
𝜌𝑙

At saturation (pinch-off), VD  VG  Vp
3/2
𝑉𝐺 2 𝑉𝐺 1 𝑉𝐷 𝑉𝐺
𝐼𝐷 𝑠𝑎𝑡 = 𝐺0 𝑉𝑃 + − + ← =1+
𝑉𝑃 3 𝑉𝑃 3 𝑉𝑃 𝑉𝑃
1/2
𝜕𝐼𝐷 (𝑠𝑎𝑡) 𝑉𝐺
𝑔𝑚 𝑠𝑎𝑡 = = 𝐺0 𝑉𝑃 1 − −
𝜕𝑉𝐺 𝑉𝑃

Empirical I D (sat .) for diffusion channel JFET

2
𝑉𝐺
𝐼𝐷 𝑠𝑎𝑡 ≈ 𝐼𝐷𝑆𝑆 1+ where IDSS is the saturation drain current when VG = 0
𝑉𝑃
 10
6.3 The Metal-Semiconductor FET(MESFET)
- GaAs MESFET

HEMT (high electron mobility transistor) / MODFET (modulation doped FET)

Figure 6–8 (a) Simplified view of modulation doping, showing only the conduction band.
Electrons in the donor-doped AIGaAs fall into the GaAs potential well and become trapped.
As a result, the undoped GaAs becomes n type, without the scattering by ionized donors
which is typical of bulk n-type material. (b) Use of a single AIGaAn/GaAn heterojunction to
trap electrons in the undoped GaAs. The thin sheet of charge due to free electrons at the
interface forms a two-dimensional electron gas (2-DEG), which can be exploited in HEMT
devices.
 11
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
Figure 6–10 An enhancement-type n-channel MOSFET: (a) isometric view of device and equilibrium band
diagram along channel; (b) drain current–voltage output characteristics as a function of gate voltage.

Enhanced mode
Depletion mode

p-channel
n-channel
 12
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)

Circuit Symbol
 13
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Basic Operation

Figure 6-11 n-channel MOSFET cross sections under

different operating conditions: (a) linear region for VG
> VT and VD < (VG – VT); (b) onset of saturation at
pinch-off, VG > VT and VD = (VG – VT); strong
saturation, VG > VT and VD > (VG – VT).
 14
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor
• The heart of the MOSFET is the metal-oxide-semiconductor
capacitor which can be considered as parallel-plate capacitor.

• With the top plate being the positive plate, a positive charge
exists on the top plate, a negative charge exists on the bottom
plate, and an electric field is induced between the two plates.
  Q
• Gauss’ law:   E    E ds   dv 
 v  
• Gauss’ law
- If there is a net electric field entering a region, there
must be negative charges in that region
- The integral of the electric field over a closed surface is
proportional to the charge within the enclosed volume

D
S
S  dS   v dv  Q
vol
 15
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor
dE    ( x' )
E ( x) x

• Gauss’ law in 1-D:   E    dE  dx 

dx   0
dE  W  s dx'
m
x V ( x)
dV
E   Edx    dV '
dx Wm 0
E (x )
V (x)
 (x)
Wm
0
x x
Wm x
 qN A Wm

• Boundary conditions:

 E dS   E 1 S   2 E N 2 S  Qinside
N1
if Qinside  0, then  1 E N 1S   2 E N 2 S  0
 E N 1 / E N 2   2 /  1 : E is discontinuous.
 DN 1  D N 2 : D is continuous.

ESi  r , SiO2 3.9 1

    ESiO2  3ESi
ESiO2  r , Si 11.8 3
 16
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor
For  m   s
ECox : Oxide conduction level
q m : Modified work-function
for the metal-oxide
interface (energy
difference between ECox
and E Fm )
q s : Modified work-function
at the semiconductor-
oxide interface

Bandgap of oxide: ~ 8eV

Ei  EF
p  ni exp
kT
N 
qF  kT ln  A 
 ni 
 17
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor

At x
n  ni exp[(EF  Ei ) / kT ]
 ni exp[q(F   ) / kT ]
 n0 exp(q / kT )
p  p0 exp(q / kT )

Strong Inversion:

Figure 6–13 Bending of the semiconductor kT N A

bands at the onset of strong inversion: The s (inv.)  2F  2 ln
surface potential ϕs is twice the value of ϕF in q ni
the neutral p material.

(The surface should be as strongly n-type

as the substrate is p-type.)

 q ( x)  Ei , Bulk -Ei ( x) : representing the extent of band bending at x


qs  Ei , Bulk -Ei (0) : representing the extent of band bending at the surface
 q  E
 F i , Bulk -EF , Bulk : relating to the bulk doping
 18
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor
Given n  n0 exp( q / kT ) n0  ni exp(  q F / kT )

p  p0 exp(  q / kT ) p0  ni exp(qF / kT)  N A

 2( x) ( x) q
Solve for (x) using Poisson’s equation    ( N D  N A  p  n)
x 2
s s

 
Because N D  N A  n0  p0 , we rewrite the above equation as
𝜕 2 𝜙(𝑥) 𝜕 𝜕𝜙 𝑞 −
𝑞𝜙 𝑞𝜙
= = − 𝑝 (𝑒 𝑘𝑇 − 1) − 𝑛 (𝑒 𝑘𝑇 − 1) (∗)
𝜕𝑥 2 𝜕𝑥 𝜕𝑥 𝜀𝑆 0 0

Multiplyin g both sides of (*) with 2( / x); the left side can be recognized as ( / x)(  / x) 2 .
𝑞 𝑞𝜙 𝑞𝜙
𝐸𝑑𝐸 = − 𝑝0 (𝑒 − 𝑘𝑇 − 1) − 𝑛0 (𝑒 𝑘𝑇 − 1) 𝜕𝜙 𝜕 𝜕𝜙 𝜕𝜙 𝜕𝜙
𝜀𝑆 2 =[ " ]2
𝜕𝑥 𝜕𝑥 𝜕𝑥 𝜕𝑥
2
Integrate from the bulk, where E  0 and   0 𝜕 𝜕𝜙 𝜕𝜙
=[ " ]2
𝜕𝑥 𝜕𝑥 𝜕𝑥
2𝑘𝑇𝑝0 𝑞𝜙 𝑞𝜙 𝑛0 𝑞𝜙 𝑞𝜙 Multiplying both sides with 𝜕𝑥
𝐸2 = (𝑒 − 𝑘𝑇 −1 + )+ (𝑒 𝑘𝑇 − 1 − ) 2
𝜀𝑆 𝑘𝑇 𝑝0 𝑘𝑇 𝜕𝜙
𝜕 = [ " ]2𝜕𝜙
𝜕𝑥
At the surface (x=0) 2𝐸𝑑𝐸 = [ " ]2𝜕𝜙
𝐸𝑑𝐸 = [ " ]𝜕𝜙
1/2
2𝑘𝑇 𝑞𝜙𝑠 𝑞𝜙𝑠 𝑛0 𝑞𝜙𝑠 𝑞𝜙𝑠
𝐸𝑠 = (𝑒 − 𝑘𝑇 −1 + )+ (𝑒 𝑘𝑇 − 1 − ) : Surface Electric Field due to Qs
𝑞𝐿𝐷 𝑘𝑇 𝑝0 𝑘𝑇

𝑄𝑠 = −𝜀𝑠 𝐸𝑠 : 𝐓𝐨𝐭𝐚𝐥 𝐜𝐡𝐚𝐫𝐠𝐞𝐬 𝐢𝐧 𝐭𝐡𝐞 𝐬𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 from bulk to the surface

𝜀𝑠 𝑘𝑇
𝐿𝐷 = : 𝐃𝐞𝐛𝐲𝐞 𝐒𝐜𝐫𝐞𝐞𝐧𝐢𝐧𝐠 𝐋𝐞𝐧𝐠𝐭𝐡,
𝑞 2 𝑝0
representing the distance for screening the charge imbalance
 19
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor : Charge Distribution

At the surface (x=0)

1/2
2𝑘𝑇 𝑞𝜙𝑠 𝑞𝜙𝑠 𝑛0 𝑞𝜙𝑠 𝑞𝜙𝑠
𝐸𝑠 = (𝑒 − 𝑘𝑇 −1 + )+ (𝑒 𝑘𝑇 − 1 − )
𝑞𝐿𝐷 𝑘𝑇 𝑝0 𝑘𝑇

𝑄𝑠 = −𝜀𝑠 𝐸𝑠

Figure 6–14 Variation of space-charge

density in the semiconductor as a function
of the surface potential ϕs for p-type silicon
with Na = 4 × 1015 cm–3 at room
temperature. ps and ns are the hole and
electron concentrations at the surface, ϕF is
the potential difference between the Fermi
level and the intrinsic level of the bulk.
(Garrett and Brattain, Phys. Rev., 99, 376
(1955).)
 20
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor : Distribution of charge, electric field, and electrostatic potential
 21
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor : Charge Distribution and Threshold Voltage

Qm  Qs  qN AW  Qn , Qs : total charges in the semiconduc tor

Voltage across the insulator:

Qs d Q  Qs
Vi    s  Es  , V  Ed
i Ci i

Voltage across the semiconductor:  s  Gate voltage: V  Vi   s

1/ 2
 2  
Depletion layer width: W   s s  from Eq. 5-21 for n+ - p junction
 qN A 

After reaching strong inversion(s=2F), further increases in V results in stronger inversion rather than in more depletion:
1/ 2 1/ 2
 2  (inv.)    kT ln( N A / ni ) 
 Wm   s s   2 s  : maximum value of the depletion width
 qN A   q2 N A 

  2 q 2 N A2 2F 
1/ 2

Qd  qN AWm    s   2( s qN AF )1/ 2 : the max. depletion charge[C/cm2 ]

 qN A 

qF : difference between Ei & EF

Qd
Threshold voltage for strong inversion: VT  s (inv.)  Vi  2F 
Ci
 22
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor : C-V Characteristics

Figure 6–16 Capacitance–voltage

relation for an n-channel (p-substrate)
MOS capacitor. The dashed curve for V >
VT is observed at high measurement
frequencies. The flat band voltage VFB will
be discussed in Section 6.4.3. When the
semiconductor is in depletion, the
semiconductor capacitance Cs is denoted
as Cd.

dQ dQs
Cs: normalized small signal capacitance of semiconductor  
dV ds
s
Cd  : depletion layer capacitance
W At the surface
 1/ 2
Ci  i : insulator (oxide) capacitance 2kT   q s / kT q  n  q  
d Es   e  1  s   0  e q s / kT  1  s 
qLD  kT  p0  kT 
2CiCd min
At VT : C  Qs    s E s
Ci  2Cd min
(the change of charge on the semiconductor is the sum of the charge on depletion region and the mobile
inversion charge, where the two are equal in magnitude at the onset of strong inversion.)
 23
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- Ideal MOS Capacitor : C-V Characteristics

• Example: For an ideal MOS capacitor having NA=1017 cm-3 and d=5nm, calculate the minimum capacitance. The
relative dielectric constant of SiO2 is 3.9.

1/ 2
  kT ln( N A / ni )  11.8  8.85 1014  0.026 ln(1017 / 1010 )
Wm  2 s  2  0.1m.
 q2 N A  1.6 1019 1017

Qd  qN AWm  1.6 1019 1017 105  1.6 107 C/cm2

2kT
s  2F  ln( N A / ni )  2  0.026 ln(10 17 / 10 10 )  0.84 V.
q
Ci   SiO2 / d  (3.9  8.851014 ) /(5 107 )  6.9 107 F/cm2
 SiO2 3.9  8.85 1014
Cmin    9.1108 F/cm2
d  ( SiO2 /  S )Wm 5 10  (3.9 / 11.9)(10 )
7 5

 Calculate the VFB for an n  - poly/SiO 2 /p - Si. Assume Q f /q  5 1011 C/cm 2 .

Q f  Qit  Qot  Qm 1.6 1019  5 1011
VFB  ms   0.1   1.1V
Ci 6.9 107
 Calculate the VT :
2  s qN AF
VT  VFB  2F   1.1  0.84  0.23  0.03V
Ci
 Find ' B' dose for increasing VT to 0.6V :
(qFB )
0.6  0.03   FB  0.63 6.9 107 /(1.6 1019 )  2.7 1012 /cm2
Ci
 24
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: Effects of Real Surfaces; Work Function Difference

For  m   s

Figure 6–17 Variation of the

metal–semiconductor work function
potential difference Φms with
substrate doping concentration, for
n+ poly-Si.
 25
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- NMOS capacitor: Effects of Real Surfaces; Work Function Difference

For  ms  0 (  m   s )

At Equilibriu m Flat Band Accumulation Depletion Inversion

V  VG  0 VG  VFB VG  VFB VFB  VG  VTH VG  VTH

 (x)  (x)  (x)  (x)  (x)

W W Wm

0 x 0 x 0 x 0 x 0 x

V (x) V (x) V (x) V (x) V (x)

x x x x x
-tox 0 W
-tox 0 W -tox 0 -tox 0 W
-tox 0 Wm
 26
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- NMOS capacitor: Effects of Real Surfaces; Work Function Difference

 Accumulation ( VG < VFB )  Depletion ( VFB < VG < VTH )

𝑉𝐺 = 𝑉𝐹𝐵 + 𝑉𝑆𝑖𝑂2 , 𝜙𝑆 ≈ 0 𝑄𝐷𝑒𝑝
𝑉𝐺 = 𝑉𝐹𝐵 + 𝜙𝑆 + 𝑉𝑆𝑖𝑂2 = 𝑉𝐹𝐵 + 𝜙𝑆 −
𝑄𝐴𝐶𝐶 𝐶𝑖
𝐸𝑆𝑖𝑂2 = −
𝜀𝑆𝑖𝑂2
𝑄𝐷𝑒𝑝 = − 2𝑞𝜀𝑆𝑖 𝑁𝐴 𝜙𝑆 = −𝑞𝑁𝐴 𝑊𝐷𝑒𝑝
𝑄𝐴𝐶𝐶
𝑉𝑆𝑖𝑂2 = 𝐸𝑆𝑖𝑂2 × 𝑡𝑆𝑖𝑂2 =−
𝐶𝑖
→ 𝑄𝐴𝐶𝐶 = −𝐶𝑖 (𝑉𝐺 − 𝑉𝐹𝐵 )

 When VG = VTH  Strong Inversion ( VG > VTH , 𝜙𝑆 ≈ 2𝜙𝐹 , 𝑊𝐷𝑒𝑝 =𝑊𝐷𝑒𝑝_𝑀𝑎𝑥 )

2𝜀𝑆𝑖 (2𝜙𝐹 ) 𝑉𝐺 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝑉𝑆𝑖𝑂2

𝑊𝐷𝑒𝑝 = 𝑊𝐷𝑒𝑝_𝑀𝑎𝑥 = 𝑄𝐷𝑒𝑝𝑀𝑎𝑥 + 𝑄𝐼𝑁𝑉
𝑞𝑁𝐴 𝑄𝐼𝑁𝑉
= 𝑉𝐹𝐵 + 2𝜙𝐹 − = 𝑉𝑇𝐻 −
𝑄𝐷𝑒𝑝_𝑀𝑎𝑥 𝐶𝑖 𝐶𝑖
𝑉𝐺 = 𝑉𝑇𝐻 = 𝑉𝐹𝐵 + 2𝜙𝐹 −
𝐶𝑖
→ 𝑄𝐼𝑁𝑉 = −𝐶𝑖 (𝑉𝐺 − 𝑉𝑇𝐻 )
2𝑞𝜀𝑆𝑖 𝑁𝐴 (2𝜙𝐹 )
= 𝑉𝐹𝐵 + 2𝜙𝐹 +
𝐶𝑖

𝑄𝐷𝑒𝑝_𝑀𝑎𝑥 = −2 𝑞𝜀𝑆𝑖 𝑁𝐴 𝜙𝐹
 27
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
 28
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: Effects of Real Surfaces: Interface Charges

Q f  Qit  Qm  Qot
VFB  ms 
Ci
• Positive charges shift VFB in the negative direction.
 29
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: Threshold Voltage
Work function difference Interface charge Depletion charge

For strong inversion

To achieve flatband condition

VT < 0 V
 difficult to fabricate an enhancement mode
n-MOSFET
Use a shallow B+ ion implantation for VT
adjustment
•Negatively charged B ions serve to reduce
the effects of positive charges
 Positive shift of VT

2  s qN AF
VT  VFB  2F 
Ci
 30
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS C-V Analysis: interface traps

1  Ci CLF CC 
Dit    i HF 
q  Ci  CLF Ci  CHF 
[cm2eV -1 ]
 31
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS C-V Analysis: mobile ions

− +
𝑄𝑚 = 𝐶𝑖 (𝑉𝐹𝐵 − 𝑉𝐹𝐵 )
 32
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: Time-dependent Capacitance Measurement (Zerbst Plots)

• Deep depletion
-If the gate bias is varied rapidly from accumulation, the depletion width can momentarily
become greater than the theoretical max. for gate biases beyond VTH.
- After the minority carrier lifetime, the depletion width collapses back to the theoretical
maximum.

Figure 6–23 Time-dependent

MOS capacitance (CHF) due to
the application of a step voltage
VA (which puts the capacitor in
accumulation) to VI (which puts
the capacitor in inversion).

Reference: MOS physics & Technology, Nicollian & Brews, p. 412

 33
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: IV Characteristics of MOS Gate Oxide
 34
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- MOS capacitor: IV Characteristics of MOS Gate Oxide

Figure 6–25 Time-dependent dielectric

breakdown of oxides: Band diagram of a MOS
device showing the band edges in the polysilicon
gate, oxide, and Si substrate. Trapped holes and
electrons in the oxide distort the band edges, and
increase the electric field in the oxide near the
gate. The tunneling barrier width is seen to be
less than if there were no charge trapping
(dashed line).
 35
6.4 The Metal-Oxide-Semiconductor FET(MOSFET)
- PMOS capacitor: p+-poly/Oxide/ n-sub.

• Ideal low-frequency CV of an PMOS capacitor

 36
6.5 The MOS Field-Effect Transistor (MOSFET)
- Output Characteristics: square law model

p-type

 Q 
 Qn  Ci VG  (VFB  s  d )
 Ci 
 2q S N a (2F  Vx ) 
 Ci VG  VFB  2F  Vx  
 Ci 
 Ci [VG  VT  Vx ] At threshold VT
With drain bias, s = 2 F + Vx
Qm  Qs  qN AW  Qn , Qs : charges on semiconduc tor 2 F for strong inversion
The channel current: Vx : source-to-channel voltage
Voltage across the insulator:
I D   ZQn ( x)v( x), where v( x)   n EL ( x)
Qs d Q  Qs
Vi    s  E , V  Ed  I D dx    n ZQn ( x)dVx ,
i Ci i
Z : width of channel,  n : surfacemobility,
EL  dVx / dx
 37
6.5 The MOS Field-Effect Transistor (MOSFET)
- Channel potential and charge density along the channel

• Channel Potential Variation

– If the drain is biased at higher potential than
the source, the channel potential increases
from the source to the drain.

– The potential difference between the gate and

channel decreases to the drain.
 38
6.5 The MOS Field-Effect Transistor (MOSFET)
- Channel potential and charge density along the channel

• Charge Density along the channel

– The channel potential varies along the
channel.
𝑄𝐷𝐸𝑃
𝑄𝑛 = −𝐶𝑖 𝑉𝐺 − 𝑉𝐹𝐵 + 𝜙𝑆 −
𝐶𝑖

2𝑞𝜀𝑆𝑖 𝑁𝐴 (2𝜙𝐹 +𝑉𝑥 )

= −𝐶𝑖 𝑉𝐺 − 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝑉𝑥 +
𝐶𝑖

≅ −𝐶𝑖 (𝑉𝐺 − 𝑉𝑇 − 𝑉𝑥 )

– The current flowing in the channel is

𝐼𝐷 = 𝑍𝑄𝑛 𝑥 𝑣(𝑥) → 𝐼𝐷 𝑑𝑥 = 𝑍𝜇𝑛 𝑄𝑛 𝑥 𝑑𝑉𝑥

– The carrier drift velocity at position x is

𝑑𝑉𝑥
𝑣 𝑥 = 𝜇𝑛 𝐸 𝑥 = 𝜇𝑛
𝑑𝑥
where n is the electron field-effect mobility
 39

- Basis for Deriving the ID-VDS Characteristics of a FET

Suppose there are n(x,y) charges per unit
volume in the channel.
The charge per unit area, Qch(y) in the
channel at position y is given by
xC ( y )

Qch ( y )  q  n( x, y)dx
0
(Channel chargein dy )  Qch ( y )Wdy

The channel current:

I D  WQch ( y )v( y )
v( y )   ( y ) EL ( y )
 I D  WQch ( y )  ( y ) EL ( y )

Because
EL  dVch / dy

we have
dVch ( y )
I D  WQch ( y )  ( y )
dy
or I D dy  WQch ( y )  ( y )dVch ( y )
 40
6.5 The MOS Field-Effect Transistor (MOSFET)
- Output Characteristics: square law model

→ 𝐼𝐷 𝑑𝑥 = −𝑍𝜇ҧ𝑛 𝑄𝑛 𝑥 𝑑𝑉𝑥

𝐿 𝑉𝐷
→ න 𝐼𝐷 𝑑𝑥 = 𝐼𝐷 𝐿 = 𝜇ҧ𝑛 𝑍𝐶𝑖 න 𝑉𝐺 − 𝑉𝑇 − 𝑉𝑥 𝑑𝑉𝑥 = 𝑍𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2
0 0

𝑍
→ 𝐼𝐷 = 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2 𝑓𝑜𝑟 𝑉𝐷 ≤ 𝑉𝐺 − 𝑉𝑇 ∶ 𝐿𝑖𝑛𝑒𝑎𝑟 𝑜𝑟 𝑇𝑟𝑖𝑜𝑑𝑒 𝑟𝑒𝑔𝑖𝑚𝑒
𝐿

𝜕𝐼𝐷 𝑍 𝑍
𝑔𝑑 ≡ = 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 − 𝑉𝐷 ≅ 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 𝑤𝑖𝑡ℎ 𝑉𝐷 ≪ 𝑉𝐺 − 𝑉𝑇 : 𝑂𝑢𝑡𝑝𝑢𝑡 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒
𝜕𝑉𝐷 𝐿 𝐿
𝜕𝐼𝐷 𝑍
𝑔𝑚 ≡ = 𝜇ҧ 𝐶 𝑉 𝑤𝑖𝑡ℎ 𝑉𝐷 ≪ 𝑉𝐺 − 𝑉𝑇 ∶ 𝑇𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒
𝜕𝑉𝐺 𝐿 𝑛 𝑖 𝐷
 41
6.5 The MOS Field-Effect Transistor (MOSFET)
- Output Characteristics: square law model

𝑍
𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2 𝑓𝑜𝑟 𝑉𝐷 ≤ 𝑉𝐺 − 𝑉𝑇 ∶ 𝐿𝑖𝑛𝑒𝑎𝑟 𝑟𝑒𝑔𝑖𝑚𝑒
𝐿
𝐼𝐷 =
𝑍 2
𝜇ҧ 𝐶 𝑉 − 𝑉𝑇 𝑓𝑜𝑟 𝑉𝐷 ≥ 𝑉𝐺 − 𝑉𝑇 ∶ 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝑟𝑒𝑔𝑖𝑚𝑒
2𝐿 𝑛 𝑖 𝐺
 42
6.5 The MOS Field-Effect Transistor (MOSFET)
- Output Characteristics: square law model
• When VD = VG-VT, Qn = 0 at the drain end of the channel: pinched-off
• As VD increases above VG-VT, the pinch-off point (where Qn = 0) moves toward the source.
– At the pinch-off point, the channel potential Vx is always equal to VG-VT
– ID saturates at a maximum value

→ 𝑉𝐷 (𝑠𝑎𝑡. ) ≅ 𝑉𝐺 − 𝑉𝑇

𝑍 𝑍
→ 𝐼𝐷 𝑠𝑎𝑡. = 𝜇ҧ 𝐶 𝑉 − 𝑉𝑇 2
= 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐷2 (𝑠𝑎𝑡. ) 𝑓𝑜𝑟 𝑉𝐷 ≥ 𝑉𝐺 − 𝑉𝑇 ∶ 𝑆𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝑟𝑒𝑔𝑖𝑚𝑒
2𝐿 𝑛 𝑖 𝐺 2𝐿

𝜕𝐼𝐷 𝑠𝑎𝑡. 𝑍 𝑍
𝑔𝑚 𝑠𝑎𝑡. ≡ = 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐷 𝑠𝑎𝑡. = 𝜇ҧ 𝐶 𝑉 − 𝑉𝑇
𝜕𝑉𝐺 𝐿 2𝐿 𝑛 𝑖 𝐺
 43
6.5 The MOS Field-Effect Transistor (MOSFET)
- Electrical Characteristics: Linear and Saturation regimes
Figure 6–27 Drain current–voltage characteristics for
enhancement transistors: (a) for n-channel VD, VG, VT, and ID are
𝑍 positive; (b) for p-channel all these quantities are negative.
𝐼𝐷 (𝑙𝑖𝑛𝑒𝑎𝑟) = 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2
𝐿

𝑍 𝑍
𝐼𝐷 𝑠𝑎𝑡. = 𝜇ҧ 𝐶 𝑉 − 𝑉𝑇 2
= 𝜇ҧ 𝐶 𝑉 2 (𝑠𝑎𝑡)
2𝐿 𝑛 𝑖 𝐺 2𝐿 𝑛 𝑖 𝐷
 44
6.5 The MOS Field-Effect Transistor (MOSFET)
- Field Dependent Mobility (at Low Electric Field)
Effect of ET on the low-field mobility:
𝜇ҧ𝑛
𝜇𝐿𝐹 𝑉𝐺 =
1 + 𝜃(𝑉𝐺 − 𝑉𝑇 )
𝑍𝜇ҧ𝑛 𝐶𝑖
𝐼𝐷 𝑙𝑖𝑛𝑒𝑎𝑟 = 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2
𝐿 1 + 𝜃 𝑉𝐺 − 𝑉𝑇
𝜃[1/V]: empirical parameter, 0.03-0.2
y
Effect of EL on the low-field mobility:
𝜇𝐿𝐹 𝐸𝐿 𝑓𝑜𝑟 𝐸𝐿 < 𝐸𝐿 (𝑠𝑎𝑡. )
𝜐ҧ = ൞
𝜐𝑆ҧ 𝑓𝑜𝑟 𝐸𝐿 < 𝐸𝐿 (𝑠𝑎𝑡. )

For small VG –VT: on the low-field mobility:

𝜇𝐿𝐹 𝑉𝐺 ≈ 𝜇ҧ𝑛 1 − 𝜃 𝑉𝐺 − 𝑉𝑇
𝑍𝜇ҧ𝑛 𝐶𝑖 1 − 𝜃 𝑉𝐺 − 𝑉𝑇
𝐼𝐷 𝑙𝑖𝑛𝑒𝑎𝑟 = 𝑉𝐺 − 𝑉𝑇 𝑉𝐷 − 12𝑉𝐷2
𝐿
𝜕𝐼𝐷 𝑍𝜇ҧ𝑛 𝐶𝑖 1 − 2𝜃 𝑉𝐺 − 𝑉𝑇 𝑉𝐷
= 𝑓𝑜𝑟 𝑉𝐺 − 𝑉𝑇 ≫ 12𝑉𝐷
𝜕𝑉𝐺 𝐿

Figure 6–30 Inversion layer electron mobility vs. effective transverse

field, at various temperatures. The triangles, circles, and squares refer
to different MOSFETs with different gate oxide thicknesses and channel
dopings. (After Sabnis and Clemens, IEEE IEDM, 1979.)
 45
6.5 The MOS Field-Effect Transistor (MOSFET)
- Short Channel MOSFET I-V Characteristics

• In a short channel devices, for very high longitudinal electric fields in the pinch-off region, the carrier velocity
saturates. That is, If VDS > Esat×L, the carrier velocity will saturate and hence the drain current will saturate:

• Id(sat.) is proportional to (VG-VT) rather than (VG-VT)2, not dependent on L, and dependent on Z.

I D ( sat.)  ZCi (VG  VT )vsat

I ( sat.)
gm  D  ZCi vsat
VG

0 0 0
 , vsat  ,v  E
1  bE b 0 E
1
vsat
 46
6.5 The MOS Field-Effect Transistor (MOSFET)
- Channel Length Modulation

𝐿𝑒𝑓𝑓 = 𝐿 − ∆𝐿

𝑍 𝐼𝐷 (𝑠𝑎𝑡. )
𝐼𝐷 = 𝜇ҧ𝑛 𝐶𝑖 𝑉𝐷2 𝑠𝑎𝑡. =
2 𝐿 − ∆𝐿 (1 − ∆𝐿Τ𝐿)

∆𝐿 𝑍𝜇ҧ𝑛 𝐶𝑖
≈ 1+ 𝐼𝐷 𝑠𝑎𝑡. = 𝑉𝐺 − 𝑉𝑇 2 [1 + 𝜆 𝑉𝐷𝑆 − 𝑉𝐷𝑠𝑎𝑡 ]
𝐿 2𝐿

∆𝐿
= 𝜆∆𝑉𝐷𝑆 , 𝜆: 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝑙𝑒𝑛𝑔𝑡ℎ 𝑚𝑜𝑑𝑢𝑙𝑎𝑡𝑖𝑜𝑛 𝑝𝑎𝑟𝑎𝑚𝑒𝑡𝑒𝑟
𝐿
 47
6.5 The MOS Field-Effect Transistor (MOSFET)
- Substrate Bias Effect (Body Effect)
• VT is increased by reverse-biasing the body-source junction:

• With a VB(<0), the depletion region is widened and thus VT

should be increased to accommodate the larger Qd.

• The substrate bias effect (body effect) increases VT for either

type of device.

2qN A Si (2B  VB )
VTH  VFB  2B 
Cox
2qN A Si (2B ) 2qN A Si (2B ) 2qN A Si (2B  VB )
 VFB  2B   
Cox Cox Cox

 VTH 0 
2qN A Si
Cox
 2B  VB  2B 
VTH 0  

 
2B  VB  2B : n  channel
 Figure 6–37 Threshold voltage dependence
V  
 TH 0  
2B  VB  2B : p  channel on substrate bias resulting from application of
a voltage VB from the substrate (i.e., bulk) to
where  is the body effect parameter the source. For n channel, VB must be zero or
negative to avoid forward bias of the source
junction. For p channel, VB must be zero or
positive.
 48
6.5 The MOS Field-Effect Transistor (MOSFET)
- Subthreshold Characteristics
• Below threshold voltage, there is a drain conduction due to weak
inversion in the channel ( 0<s<2F), which leads to a diffusion current
from the source to drain.
• In the depletion (subthreshold ) operation, the channel potential is
capacitively coupled to the gate potential:

 Ci 
VC  VG   
 Ci  Cd  Cit 
•The subthreshold current is given by
𝜙𝑆 −𝜙𝐵 𝜙𝑆 −𝜙𝐵 −𝜙𝐷
𝑛 0 −𝑛 𝐿 𝑛𝑖 𝑒 𝑘𝑇 −𝑒 𝑘𝑇
𝐼𝐷 = −𝑞𝐴𝐷𝑛 = −𝑞𝐴𝐷𝑛
𝐿 𝐿
2 −𝑞(𝑉𝐺 −𝑉𝑇 )
𝑍 𝑘𝑇 −𝑞𝑉𝐷
𝐶𝑟 𝑘𝑇
= 𝜇 𝐶𝐷 + 𝐶𝑖 1 − 𝑒 𝑘𝑇 1−𝑒
𝐿 𝑇
−𝑞(𝑉𝐺 −𝑉𝑇 ) 𝐶𝐷 + 𝐶𝑖𝑡
∝ 𝑒 𝐶𝑟 𝑘𝑇 𝑤ℎ𝑒𝑟𝑒 𝐶𝑟 = 1 +
𝐶𝑖

• The subthreshold slope, S is also given by

𝑑𝑉𝐺 𝑑𝑉𝐺 𝑘𝑇 𝐶𝐷 + 𝐶𝑖𝑡
𝑆= = 𝑙𝑛10 × = 2.3 1+
𝑑(𝑙𝑜𝑔𝐼𝐷 ) 𝑑(𝑙𝑛𝐼𝐷 ) 𝑞 𝐶𝑖

Figure 6–38 Subthreshold conduction in MOSFETs :

(a) semilog plot of ID vs. VG; (b) equivalent circuit
showing capacitor divider which determines
subthreshold slope.
 49
6.5 The MOS Field-Effect Transistor (MOSFET)
- Equivalent Circuit for the MOSFET
At high frequencies

Neglecting the source and drain resistances

COS , COD : overlap capacitance
CGS , CGD : gate - to - source/drain capacitance
g m  id / vgs  I D / VGS : transconductance
(Z/L)CiVDS ( tride)

(Z/L)Ci (VGS  VT ) (sat.)
g d  id / vds  I D / VDS : output conductance At low frequencies

Qi
Cij 
V j
 50
6.5 The MOS Field-Effect Transistor (MOSFET)
- Equivalent Circuit for the MOSFET

Input impedance at high frequency Neglecting the source and drain resistances
ig  jCGS vgs  jCGD (vgs  vds ) : at input node,
vds g d  g m vgs  jCGD (vds  vgs )  0 : at output node
 ig  j[CGS  CGD (1  g m / g d ) /(1  jCGD / g d )]vgs
 j[CGS  CGD (1  g m / g d )]vgs
 j[CGS  CM ]vgs  CM : Millar capacitance

Cutoff frequencyf T : ( when thecurrent gain, id /ig is unity, with short - circuited output)
ig  j[CGS  CGD (1  g m / g d )]v gs and id  g m vgs
 id /ig  g m /[2fT (CGS  CGD (1  g m / g d )]  1
 fT  g m /[2 (CGS  CGD (1  g m / g d )]  g m /(2Ci ZL)
 (Z/L)Ci (VGS  VT ) /(2Ci ZL) : at sat.
  (VGS  VT ) /(2L2 )

Short - channel device

fT  g m /(2Ci ZL)  ZCi vsat /(2Ci ZL)  vsat /(2L)
 51
6.5 The MOS Field-Effect Transistor (MOSFET)
- MOSFET Scaling
• Reduce all dimensions and voltage by a scaling factor (>1), so that the internal electric fields are the same as
those of a long-channel MOSFET: constant-field scaling

• Table 6-1 summaries the scaling rules of constant-field scaling for various device parameters and circuit
performance factors. The circuit performance can be enhanced as the device dimensions are scaled down.

• In practice, the electric fields inside the device increase mainly due to the limitation in scaling of the voltage factor
(e.g., power supply voltage, threshold voltage).
 52
6.5 The MOS Field-Effect Transistor (MOSFET)
- Drain Induced Barrier Lowering (DIBL)

• In a short-channel MOSFET, as the drain voltage

increases, the drain depletion region widens.
– The barrier to carrier diffusion from the source
into the channel is reduced.
– VTH decreases with increasing drain bias.
– ID increases with increasing drain bias.
 53
6.5 The MOS Field-Effect Transistor (MOSFET)
- Short Channel Effect (SCE) and Narrow Width Effect

• Short channel effect(SCE): VT decreases with L for

very small geometries due to the sharing of the
depletion charges with the source and drain regions.

• Narrow width effect: VT goes up as the channel

width Z is reduced. This is because of some depletion
charges under the isolation regions is increased. Those
charges electrically belongs to the gate.
 54
6.5 The MOS Field-Effect Transistor (MOSFET)

Figure 6–48 Gate-induced drain leakage in MOSFETs.

The band diagram for the location shown in color is
plotted as a function of depth in the gate–drain overlap
region, indicating band-to-band tunneling and creation of
electron–hole pairs in the drain region in the Si substrate.