108  Vlsi design

Therefore, Eqn (4.5) can be written as

γ
gmb = gm = ηgm  (4.7)
2 −2ϕ F + VSB

We have seen in Chapter 2 that MOS devices have associated capacitances between
its four terminals. Thus, the complete small signal model of MOSFET, including
the capacitances is shown in Fig. 4.2.

CGD

G D
CGS +
VGS rds
gmVGS gmbVBS
−
CDB
CGB
− S CSB
VBS
+
B
Figure 4.2  Complete small signal model of MOSFET

4.3  MOSFET as a Switch

MOS devices can be used as simple switches where the switch can be made ON or
OFF by applying voltage to the gate terminal. MOS switches are used in several
analog designs, such as, switched capacitor circuits, multiplexers, and modulators.
The MOS switch is a voltage-controlled resistor, as shown in Figs 4.3 (a) and (b).
When gate voltage (VGS) is above the threshold voltage (Vt) of the MOSFET, the
source and drain terminals are connected, and they are isolated if VGS< Vt.

Gate Control

Source Drain In Out

(a) (b)
Figure 4.3  (a) MOS switch; (b) voltage-controlled resistor

The controlled switch or resistor has two resistances, RON and ROFF , where RON
is the ON resistance and ROFF is the OFF resistance of the MOSFET. Ideally, in a
switch, RON should be zero and ROFF should be infinite. The MOS switch has very
small ON resistance and very high OFF resistance, and thus can be used as a switch.
Let us now find out the expression for ON resistance of the MOS switch. When the
switch is ON, the voltage across the switch must be small, i.e., VDS is small. For
small VDS, the MOS device operates in the linear region; hence, we must consider
the linear region of the MOSFET. The I–V equation in the linear region is given by

µnCoxW  V2 
ID = × (VGS − Vt )VDS − DS   (4.8)
L  2 

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 Analog CMOS Design  109

The ON resistance can be derived as

1 L
RON = =  (4.9)
∂I D ∂VDS µnCoxW (VGS − Vt − VDS )

Example 4.1  Calculate the ON resistance of the MOSFET having the following
parameters:

µnCox = 40 µA / V 2 W / L = 10
Vt = 0.7 V VGS = 1.8 V
VDS = 1 V
  

Solution

L
RON =
µnCoxW (VGS − Vt − VDS )
1
= = 25 kΩ
40 × 10 −6 × 10 × (1.8 − 0.7 − 1.0)

The variation of RON vs. VGS is shown in Fig. 4.4.

60.00
Vt = 0.4 V
50.00
RON (MΩ)

VDS = 0 V
40.00

30.00
VDS = 1 V
20.00

10.00

0.00
0.45 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
VGS (V)

Figure 4.4  RON vs. VGS

4.4  MOS Diode/Resistor

The MOS device can act as resistor when the drain and gate terminals are connected
to each other. This gate-drain connected MOS device is called MOS diode, as
shown in Figs 4.5 (a) and (b). In VLSI circuits, the resistors are replaced by MOS
diodes as fabricating a resistor would require a large area in the chip.
When the gate and drain are connected, we can write,VGS = VDS, and the
transistor operates in the saturation region. The small signal model of an nMOS

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 110  Vlsi design

IX VDD

+ +
VDS G + D
− − VGS rds
gmVGS gmbVBS
−
+ IX
+ V
VX +S
− − VX
−
VB B
I

(a) (b) (c)

Figure 4.5  (a) nMOS diode; (b) pMOS diode; (c) small signal model of nMOS diode 

diode is shown in Fig. 4.5(c). We can write, VGS = -VX, VBS = -VX, and VDS = -VX.
Applying Kirchhoff’s current law at node S, we can write

VDS
gmVGS + + gmbVBS + I X = 0
rds
1
or −VX ( gm + + gmb ) = − I X
rds
VX 1 1
or rout = = ≅  (4.10)
I X gm + gds + gmb gm

Equation (4.10) gives the expression for the small signal resistance of the MOS
diode.

4.5  MOS Current Source and Sink

MOSFET can be used as a, current source or sink when it operates in the saturation
region. An nMOS can act as a current sink where the negative node is connected
to VSS. Alternately, a pMOS can act as a current source where the positive node is
connected to VDD.
An nMOS current sink and its I–V characteristics are shown in Fig. 4.6. For
nMOS to be operated in the saturation region, VDS ≥ VGS - Vt0 or, VOUT ≥ VGG - Vt0.
Hence, as long as the following condition is satisfied, the nMOS will behave like
a current sink.

VOUT ≥ VGG - Vt0  (4.11)

Similarly, a pMOS can act as a current source when it is operated in the

saturation region. A pMOS current source and its I–V characteristics are shown
in Fig. 4.7.
The pMOS acts as a current source as the following condition is satisfied:

VOUT ≤ VGG + |Vt0|  (4.12)

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 Timing Analysis  359

10.10  MOS Capacitances

The propagation delay of a gate is analysed using a simple but fairly accurate RC
delay model, where R is the effective resistance of the MOS transistors, and C is
the load capacitance. In Section 10.9, we have analysed the effective resistance of
the MOS transistors to design the logic functions with appropriate transistor W/L
ratios. Let us now analyse the capacitances in the circuit. There many components
of the load capacitance that contributes to the propagation delay. The main three
components of the load capacitance are as follows:
n Gate capacitances
n Junction capacitances
n Interconnect capacitances

10.10.1 Gate Capacitance

There are three components of the gate capacitance with respect to the other three
terminals of the MOSFET:
n Gate-to-source capacitance (Cgs )
 
n Gate-to-drain capacitance (Cgd )
 
n Gate-to-bulk capacitance (Cgb )
 
There are also gate-source and gate-drain overlap capacitances. As shown in Figs 10.10
(a) and (b), the gate terminal has some overlap at the source and drain end. This overlap
is required for the device to be fabricated properly considering the fabrication system
mask alignment tolerance. But because of the overlap, there are two capacitances:
gate-source overlap capacitance (CGSO ) and gate-drain overlap capacitance (CGDO ).
   
The value of the overlap capacitance is given by
CGSO = CGDO = Cox × W × xd (10.38)

Gate

n+ n+
Source Drain
xd xd

LS Ld
LD
(a)
oxide
Gate

W
tox
xj n+ n+
L
(b)
Figure 10.10 MOSFET: (a) top view; (b) cross-sectional view

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 360  Vlsi design

where
ε ox
Cox = (10.39)
t ox
Cox = gate oxide capacitance per unit area; eox = dielectric constant of the gate
oxide material; tox = gate oxide thickness; W = channel width; and xd = gate-
source/drain overlap length.
The overlap capacitances are independent of the terminal voltages and are fixed
for transistor dimensions.
When the MOS transistor operates under cut-off region, there is no channel
region. Hence, the gate-to-source and gate-to-drain capacitances are zero, i.e.,
Cgs = Cgd = 0. Hence, the gate capacitance is entirely determined by the gate-to-
bulk capacitance as given by

Cgb = Cox × W × L (10.40)

In the linear region of operation, the channel is formed and it shields the bulk
from the gate. Hence the gate-to-bulk capacitance is zero, i.e., Cgb = 0. The gate-
to-channel capacitance is shared equally by the gate-to-source and gate-to-drain
capacitances. Therefore, we can write
1
Cgs = Cgd ≅ W × L × Cox (10.41)
2
When the MOS transistor operates under the saturation region, the channel is
pinched off at the drain end. Hence, the gate-to-drain capacitance is zero (Cgd =
0). The gate-to-bulk capacitance is also zero (Cgb = 0) under this condition. The
gate capacitance is entirely determined by the gate-to-source capacitance which
is given by
2
Cgs ≅ W × L × Cox (10.42)
3

Hence, the gate capacitance and its components can be summarized as shown in
Table 10.2.

Table 10.2 Gate capacitances of the MOS transistor

Region of Cut-off Linear Saturation
operation
Cgb Cox × W × L 0 0
1 2
Cgs 0 W × L × Cox W × L × Cox
2 3

1
Cgd 0 W × L × Cox 0
2
CG (overlap) Cox × W × xd Cox × W × xd Cox × W × xd

2
CG (total) Cox × W × L + 2 × Cox × W × xd Cox × W × L + 2 × Cox × W × xd Cox × W × L + 2 × Cox × W × x d
3

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 Timing Analysis  361

10.10.2 Junction Capacitance

The junction capacitances are also called diffusion capacitances. In the MOS
transistor, there are two PN junctions between the source and bulk, and the drain
and bulk. These PN junctions have depletion layer capacitances. The depletion
layer capacitance again has two components. One is due to the bottom wall, and
other is due to the side wall, as illustrated in Fig. 10.11.

Bottom

n+ n+

p-sub

Figure 10.11 MOSFET junction capacitances

The vertical junctions form capacitances with the bottom plate of the source and
the drain regions which is given by

C jb = C j × W × LS = C j × W × LD (10.43)

where Cj is the vertical junction capacitance per unit area.

The lateral junctions also form capacitances with the side walls of the source
and drain regions which is given by

C jsw = C js x j × (W + 2 × LS ) = C js x j × (W + 2 × LD ) (10.44)

where Cjs is the side-wall junction capacitance per unit length.

Hence, the total junction capacitance is the sum of the vertical junction
capacitance and the side-wall junction capacitance. We can write

CS-junc = CS-diff = C jb × AREA + C jsw × Perimeter

(10.45)
= C jb × W × LS + C jsw × (2 × LS + W )

Equation (10.45) gives expression for the junction capacitance at the source end. A
similar expression can be written for the junction capacitance at the drain end just
by replacing LS with LD. Note that the side wall at the gate side is not considered for
side-wall junction capacitance as this side is not a PN junction, but rather a conducting
channel.

10.10.3 MOS Transistor Capacitance

The four terminal MOS transistor capacitance model is shown in Fig. 10.12.

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 362  Vlsi design

The gate capacitances and the junction capacitances are combined to form the
lumped capacitances between the four terminals of the MOS transistors. These
capacitances are given by
CGS = Cgs + CGSO
CGD = Cgd + CGDO
CGB = Cgb
CSB = CS-diff
(10.46)
CDB = CD-diff

CGD CDB

G B

CSB
CGS

S
CGB

Figure 10.12 MOS transistor capacitances

10.10.4 Effective Load Capacitance
The propagation delay of a logic gate is determined by the two factors: (1) the
effective resistance in the charging or discharging path and (2) the effective value
of load capacitance. Let us now consider a CMOS inverter driving another CMOS
logic gate, as shown in Fig. 10.13.
VDD

CGS CSB

CGD CDB

Vin Vout
CGB

CGD CDB

Cwire CG
CGS CSB

CGB

Figure 10.13  A CMOS inverter driving another CMOS logic 

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 Timing Analysis  363

The effective load capacitance at the output terminal of the CMOS inverter is
given by

Cl = CGD,NMOS + CGD,PMOS + CDB,NMOS + CDB,PMOS + Cwire + CG  (10.47)

where Cwire and CG are interconnect capacitance and the gate capacitance of the
NMOS connected at the output of the CMOS inverter.
Equation (10.47) shows that the effective load capacitance at the output of a
CMOS logic gate depends on the gate-to-drain and the drain-to-bulk capacitances.
These capacitances in turn depend on the width of the transistors according to Eqns
(10.41) and (10.45). So, when we increase the width of the transistor to reduce the
propagation delay through the gate, it increases the effective load capacitance.
Hence, continuously increasing the width of the transistors does not necessarily
reduce the propagation delay through the gate.

10.11 Dependency of Delay and Slew on

Power Supply Voltage
The propagation delay and slew values depend on the effective resistance and
capacitances. But the effective resistance has a dependency on the voltage
according to Eqn (10.1). To study the effect of VDD on the propagation delay
and slew, we create a SPICE netlist and vary VDD. The SPICE netlist is given
below:
* SPICE netlist to check propagation delay and slew
* variation with VDD
.include “E:\CMOS-CELLS\SPICE MODELS\tsmc018.md”
.option scale=0.18u
.param CL=1p
.param N=1
.param VDD=2.0
C1 y Gnd ‘CL’
M2 y a Gnd Gnd NMOS L=1 W=’2*N’ AD=’5*2*N’
+ PD=’2*2*N+10’ AS=’5*2*N’ PS=’2*2*N+10’
M3 y a Vdd Vdd PMOS L=1 W=’6*N’ AD=’5*6*N’
+ PD=’2*6*N+10’ AS=’5*6*N’ PS=’2*6*N+10’
v4 Vdd Gnd ‘VDD’
v5 a Gnd pulse(0.0 ‘VDD’ 0 10n 10n 100n 200n)
.tran 1n 250n
.plot tran v(a) v(y)
.measure tran TPHL trig v(a) val=’VDD/2’
+ cross=1 targ v(y) val=’VDD/2’ cross=1
.measure tran TPLH trig v(a) val=’VDD/2’
+ cross=2 targ v(y) val=’VDD/2’ cross=2
.measure tran Tfall trig v(y) val=’0.9*VDD’
+ cross=1 targ v(y) val=’0.1*VDD’ cross=1
.measure tran Trise trig v(y) val=’0.1*VDD’

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 Digital CMOS Logic Design  187

VDD VDD

PUN

Out
In
CLK
CLK

PDN

Figure 5.46  CMOS logic using TSPC logic with latched output

When CLK = 1, TSPC logic simply works as static CMOS logic. But when CLK = 0,
only the PUN is activated and the PDN is deactivated. Hence, the circuit just holds its
output logic level.

Example 5.8  Design a AND latch circuit using TSPC logic.

Solution  An AND latch using TSPC logic can be implemented as shown in Fig. 5.47.
The pull-up network (PUN) is implemented using two pMOS transistors in parallel,
whereas the pull-down network (PDN) is implemented using two nMOS transistors
in series.

VDD
VDD

Out

CLK
CLK

Figure 5.47  AND latch using TSPC logic

5.18 Pass Transistor Logic

In pass transistor logic, only nMOS transistors are used to design the logic. The
inputs signals are applied to both the gate and drain/source terminals. To illustrate
the pass transistor logic, let us consider the design of a two-input AND gate. The
truth table of two-input AND gate is shown in Fig. 5.48(a).

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 188  Vlsi design

A
A B F = AB F
0 0 0 When A = 0,
B
0 1 0 F=0
A
1 0 0 When A = 1, F = AB
1 1 1 F=B 0

(a) (b)
Figure 5.48  (a) Truth table two-input AND gate; (b) realization of two-input AND gate using
pass transistor logic
As seen from the truth table, the function (F) is evaluated for two cases: (i) when
A = 0, F = 0; (ii) when A = 1, F = B. This logic can be realized using two nMOS
transistors connected in parallel as shown in Fig. 5.48(b). When A = 1, the upper
nMOS is ON, so the output is B (F = B). When A = 0, the lower nMOS is ON, so
the output is 0 (F = 0).
This logic is known as pass transistor logic (PTL). This logic uses lesser number
of transistors as compared to conventional CMOS
logic. The disadvantage of the logic is that the VDD
logic high output is degraded as nMOS cannot
pass logic high perfectly. VDD

5.18.1 Degradation of Logic High Output Level

In x Out
The nMOS transistor cannot pass the logic high
level perfectly. To analyse this degradation, let
us consider a PTL circuit as shown in Fig. 5.49.
The voltage waveforms at nodes In, Out, and
x are shown in Fig. 5.50. Clearly, it shows that
the logic high output (at node x) of the PTL gate Figure 5.49  PTL circuit with
is degraded. CMOS inverter at the output

2.0
Vout Vin

1.5

Vx
Voltage (Volt)

1.0

0.5

0.0

0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 5.50  Output waveform of a PTL gate

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 Digital CMOS Logic Design  189

Due to the logic degradation, the PTL gates cannot be cascaded, as the logic
degradation gets carried over several stages, and the final output logic becomes
incorrect. To avoid the carry of degradation, a CMOS inverter is connected at the
output of the PTL gate as shown in Fig. 5.49.

5.18.2 Design of XOR Gate Using PTL

An XOR gate can be realized using PTL, as shown in Fig. 5.51.
A
A B F = A⊕B F

0 0 0 When A = 0,
F=B B
0 1 1
A
1 0 1 F = A⊕B
When A = 1,
1 1 0 F=B B

(a) (b)
Figure 5.51  (a) Truth table of XOR gate; (b) XOR gate implemented using PTL

The input and output waveforms of the XOR gate implemented using PTL is shown
in Fig. 5.52. It shows that the output waveform is a function of the input transition.
For example, when A = 1 and B = 0 → 1, output waveform falls from high to low.
Again, when B = 1 and A = 0 → 1, output waveform falls from high to low. But in
these two cases, the output waveform is different in shape. Thus, the PTL gate has
another issue of having transition-dependent output waveform.
2.0
VB

VA
1.5
Vout
Voltage (Volt)

1.0

0.5

0.0
0 50 100 150 200
Time (ns)
Figure 5.52 Input–output waveform of XOR gate using PTL

5.19 Complementary Pass Transistor Logic

In the complementary pass transistor (CPL) logic, the inputs are applied both in the true
and complement form, and the outputs are also evaluated in both true and complement
form, using pass transistor logic. This logic is also known as differential pass transistor
logic (DPL). An example of XOR/XNOR is illustrated in Fig. 5.53.

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 190  Vlsi design

B
A
A B F=A⊕B F F=A B F F=A⊕B
0 0 0 When A = 0, 1 When A = 0, B
0 1 1 F=B 0 F=B
A
1 0 1 When A = 1, 0 When A = 1,
1 1 0 F=B 1 F=B
B
A
F=A B
(a)
B
(b)
Figure 5.53  (a) Truth table for XOR/XNOR gate; (b) Realization of XOR/XNOR
function using CPL

5.19.1 Design of OR/NOR Gate Using CPL

Using CPL, the OR and NOR functions can be implemented as shown in Fig. 5.54.
The Boolean expression for an OR gate can be written as
F = A + B = A + AB = A × A + A × B

A B F=A+B F F=A+B F A
A
0 0 0 When A = 0, 1 When A = 0, F=A+B
F=B F=B B
0 1 1 0
1 0 1 0 A
When A = 1, When A = 1,
1 1 1 F=A 0 F=A
A
A
(a) F=A+B
B
(b)
Figure 5.54  (a) Truth table for OR/NOR gate; (b) Realization of OR/NOR function using CPL

Similarly, the Boolean expression for a NOR gate can be written as

F=A+B=A×B=A×A+A×B

5.19.2 Design of AND/NAND Gate Using CPL

Using CPL, the AND and NAND functions can be implemented as shown in Fig. 5.55.
The Boolean expression for an AND gate can be written as
F = AB = A × B + A × A

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 Digital CMOS Logic Design  191

A B F=AB F F=AB F B
A
0 0 0 When A = 0, 1 When A = 0, F=AB
F=A F=A A
0 1 0 1
1 0 0 1 A
When A = 1, When A = 1,
1 1 1 F=B 0 F=B
B
A
(a) F=AB
A
(b)
Figure 5.55  (a) Truth table for AND/NAND gate; (b) realization of AND/NAND
function using CPL
Similarly, the Boolean expression for a AND gate can be written as

F = AB = A + B = A + B × (A + A )
    = A + A × A + A × B = A × A + A × B

5.20  Differential CMOS Logic

In the differential CMOS logic, the inputs and outputs are to be given and derived AQ  The PDN
both in the true and complement form, respectively connected in parallel. The PUN consists
of two PDN
network is build using only two pMOS transistors. The structure of differential
CMOS logic is shown in Fig. 5.56. This logic is also known as cascode voltage
switch logic (CVSL) (Kan 1987).
VDD VDD

Vout Vout
Cload Cload
Inputs

Inputs

PDN1 PDN2

Figure 5.56 Differential CMOS logic

The advantages of differential logic are as follows:
n As the output is available in both the true and complement form, it eliminates
the use of extra inverter circuits where the inputs are required in both true and
complement form.

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 Digital CMOS Logic Design 5
Key topics
n Digital logic design n Dynamic CMOS logic
n CMOS logic design n Domino CMOS logic
n CMOS design methodology n NORA CMOS logic

n Design of CMOS inverter n Zipper CMOS logic

n Design of two-input NAND gate n True single-phase clock dynamic

n Design of two-input NOR gate CMOS logic

n Classification of CMOS digital logic n Pass transistor logic

circuit n Complementary pass transistor logic

n Combinational logic circuit n Differential CMOS logic

n Sequential logic circuit n Adiabatic logic

n Pseudo-nMOS logic n Dual-threshold CMOS logic

n CMOS transmission logic n Semiconductor memories

5.1 Introduction
In this chapter, we introduce the digital logic circuit design using CMOS transistors,
which are most popular because of low power dissipation and less area requirement
compared to any other logic circuits. It is worthwhile mentioning that almost 90% of
the total semiconductor devices are fabricated using silicon CMOS technology. Silicon
(Si) is the most suitable semiconductor material for VLSI circuit fabrication because
of its native oxide SiO2. CMOS logic is a combination of nMOS and pMOS logic.
The nMOS and pMOS transistors are both functionally and structurally complement.
Hence, the combination of nMOS and pMOS is known as complementary MOS or
CMOS.

5.2  Digital Logic Design

In digital logic, there are three primary logic operations: (a) NOT, (b) OR, and (c)
AND. Using these three primary logic, any other logic such as NAND, NOR, XOR,
or XNOR, can be derived.
In NOT logic, if the input (A) is TRUE, the output (F) is FALSE; and if the input
(A) is FALSE, the output (F) is TRUE. The NOT logic can be realized using a simple
circuit as shown in Fig. 5.1(a). When the switch S1 is ON, the bulb will not glow.
When the switch S1 is OFF, the bulb will glow.
In OR logic, if both the inputs are FALSE, the output is FALSE. Otherwise,
the output is TRUE. The OR logic can be realized using two switches S1 and S2
connected in parallel, as shown in Fig. 5.1(b). When both switches are OFF, the
bulb will not glow; otherwise, the bulb will glow.

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 164  Vlsi design

In AND logic, if both the inputs are TRUE, the output is TRUE. Otherwise, the
output is FALSE. The AND logic can be realized using two switches S1 and S2
connected in series as shown in Fig. 5.1(c).
The mechanical switches shown in Fig. 5.1 can be replaced by MOS transistors
as the MOS transistor behaves as a switch when it is operated between the cut-off
and saturation regions.

S1
S1 S2
S1 Bulb
Bulb S2 Bulb

(a) (b) (c)

Figure 5.1  (a) Realization of NOT logic using one switch; (b) realization of OR logic using
two switches; (c) realization of AND logic using two switches

As shown in Fig. 5.2(a), an nMOS transistor can be modelled as a switch connected

between the drain ( D) and source (S) and the switch is controlled by gate (G). When the
gate is logic high (H), the nMOS is ON and the switch is closed, and D is connected to S
[see Fig. 5.2 (b)]. When the gate is logic low (L), the nMOS is OFF and the switch
is open, and D is disconnected from S [see Fig. 5.2 (c)].

Source Gate = Logic high Gate = Logic low

Source
Source Source
Drain Drain
Gate Gate
Source
Source Drain
Drain Drain Drain

(a) (b) (c)

Figure 5.2  (a) nMOS transistor and its switch model; (b) ON nMOS modelled as closed
switch; (c) OFF nMOS modelled as open switch

Similarly, a pMOS can also be modelled as a switch as shown in Figs 5.3(a), (b),
and (c).

Source Source Gate = Logic low Gate = Logic high

Gate Gate Source Source

Drain Drain

Source Drain Source

Drain Drain Drain

(a) (b) (c)

Figure 5.3  (a) pMOS transistor and its switch model; (b) ON pMOS modelled as closed
switch; (c) OFF pMOS modelled as open switch

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 Digital CMOS Logic Design  165

In reality, an nMOS can pass logic low perfectly but cannot pass logic high perfectly.
On the other hand, a pMOS can pass logic high perfectly but cannot pass logic low
perfectly. This is illustrated in Figs 5.4 (a) and ( b).

VDD Gnd

Gnd Gnd VDD VDD

VDD Gnd
Vt = Threshold voltage

VDD VDD − Vt Gnd Gnd + Vt

(a) (b)
Figure 5.4  (a) Logic level passing through nMOS; (b) Logic level passing through pMOS

The logic degradation mechanism is explained in the following text with the help
of a circuit shown in Fig. 5.5.

A 5V VY
Logic 1
5V 5V
Logic 1 Y 5 V − Vt
Vt = 0.5 V
Cload
Time

Figure 5.5  Transfer of logic 1 through an nMOS transistor

Let us consider the case of transfer of logic 1 through an nMOS transistor having
threshold voltage Vt = 0.5 V, as shown in Fig. 5.5. To make the nMOS transistor
ON, we apply logic 1 (= 5 V) to its gate. At the input, we apply logic 1 to transfer
it to the output. Assume that the load capacitor is initially at logic 0 (= 0 V).
Hence, gate-to-source (VGS) potential difference is 5 V and gate-to-drain (VGD)
potential difference is 0 V. Therefore, the ON condition for the nMOS transistor is
satisfied. Current flows through the nMOS transistor from the drain to the source
and the load capacitor slowly gets charged. As the load capacitor gets charged, the
potential at node Y (VY) increases. As VY increases, VGS decreases. When VY reaches
(5 V–Vt), VGS is just Vt. Under this condition, the nMOS transistor is still ON. But
any further increase in VY causes VGS to become less than Vt, and makes the nMOS
transistor OFF. So no further increase in VY is possible. Hence, the maximum
voltage at the output is 5 V−Vt, and, thus we get a degraded logic 1 at the output.
In the case of logic 0 transfer through an nMOS transistor, the gate and drain
terminals are at 5 V and the source terminal is at 0 V. Note that in this case input node
is source and the output node is drain that is initially charged to logic 1. Readers must
keep in mind that the source and drain are mutually interchangeable due to symmetrical
structure of the MOSFET. Now VGS is 5 V and VY discharges through the nMOS
transistor keeping VGS at 5 V all the time. So the load capacitor can be fully discharged
making VY to become 0 V. Hence, an nMOS transistor can pass logic 0 perfectly.

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 166  Vlsi design

Similarly, we can explain that a pMOS transistor passes logic 1 perfectly but
passes degraded logic 0. Hence, the bottom line is that the pMOS should be used
for pulling a node to logic high, and nMOS should be used for pulling a node to
logic low.

5.3 CMOS Logic Design

Any Boolean logic function (F) has possible values: either logic 0 or logic 1. For
some of the input combinations, F = 1 and for all other input combinations, F = 0.
So in general, any Boolean logic function can be realized using a structure as shown
in Fig. 5.6. The switch S1 is closed and the switch S2 is open for input combinations
that produces F = 1. The switch S1 is open and the switch S2 is closed for other input
combinations that produces F = 0.
As shown in Fig. 5.6, the output (F) is either connected to VDD or to the ground,
where the logic 0 is represented by the ground and the logic 1 is represented by
VDD. So the basic requirement of digital logic design is to implement the pull-up
switch (S1) and the pull-down switch (S2). As the pMOS transistors can pass
logic 1 perfectly, they are used in pull-up switch realization. Similarly, as the
nMOS transistors can pass logic 0 perfectly, they are used in pull-down switch
realization.
A generalized CMOS logic circuit consists of a pull-up network (PUN) and a
pull-down network (PDN), as shown in Fig. 5.7. The PUN comprises pMOSFETs
and the PDN comprises nMOSFETs.

VDD

VDD

Switches S1
S1 and S2 Inputs PUN
are F
controlled
by inputs Vout
S2
Cload
Inputs PDN

Figure 5.6  Realization of any Boolean logic

function (F) Figure 5.7  A general CMOS logic circuit

Depending on the applied input logic, the PUN connects the output node to VDD,
and the PDN connects the output node to the ground.

5.4 CMOS Design Methodology

The basic CMOS design methodology involves three steps:
n Given the Boolean expression, take its complement
n Design PDN by realizing

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 Digital CMOS Logic Design  167

•  AND terms using series connected nMOSFETs

•  OR terms using parallel connected nMOSFETs
n Design PUN just reverse (or dual) of the PDN

5.5  Design of CMOS Inverter (NOT) Gate

A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS
transistor. The nMOS is used in PDN and the pMOS is used in the PUN, as shown
in Figs 5.8 (a), (b) and (c).

VDD

A Y pMOS

(a) A Y

A Y nMOS Cload
0 1
1 0

(b) (c)
Figure 5.8  (a) Symbol for inverter; (b) truth table of inverter; (c) CMOS realization of inverter

Operation  When input is low, the nMOS is OFF and the pMOS is ON. Hence,
the output is connected to VDD through pMOS. When the input is high, the nMOS
is ON and the pMOS is OFF. Hence, the output is connected to the ground through
nMOS. We can connect a capacitor at the output node as shown in Fig. 5.8 to represent
the load seen by the inverter. The load capacitor is charged to VDD through pMOS
when the input is low. The load capacitor is discharged to the ground through nMOS
when the input is high.

5.6  Design of Two-input NAND Gate

To illustrate the design methodology, let us consider a simple example of a two-
input NAND gate design.
The two-input NAND function is expressed by

Y = A • B (5.1)

Step 1:  Take complement of Y

Y = A• B = A• B  (5.2)

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 168  Vlsi design

Step 2:  Design the PDN

In this case, there is only one AND term. So there will be two nMOSFETs in series,
as shown in Fig. 5.9.
Step 3:  Design the PUN
In PUN, there will be two pMOSFETs in parallel, as shown in Fig. 5.10.

Figure 5.9  Pull-down networkcom- Figure 5.10  Pull-up network comprising

prising nMOSFETs pMOSFETs

Now join the PUN and PDN as shown in Fig. 5.11 (c). Note that we have realized
Y, rather than Y because the inversion is automatically provided by the nature of
the CMOS circuit operation.

A VDD
Y
B
A B
(a)

A B Y Y
A
0 0 1
0 1 1
1 0 1 B
1 1 0

(b) (c)

Figure 5.11  Two-input NAND gate: (a) Symbol; (b) Truth table; (c) CMOS realization

Operation  When A = 0 and B = 0, both the nMOS transistors are OFF and both
pMOS transistors are ON. Hence, the output is connected to VDD and we get logic
high at the output.
When A = 1 and B = 0, the upper nMOS is ON and lower nMOS is OFF. So,
output cannot be connected to the ground. Under this condition, left pMOS is OFF
but right pMOS is ON. Hence, the output is connected to VDD, and we get logic
high at the output.
When A = 0 and B = 1, the upper nMOS is OFF and lower nMOS is ON. So,
output cannot be connected to ground. Under this condition, left pMOS is ON but
right pMOS is OFF. Hence, the output is connected to VDD, and we get logic high
at the output.

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 Digital CMOS Logic Design  169

When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors AQ  Pls. verify
are OFF. Hence, the output is connected to the ground, and we get logic low at the citation for Fig.
5.11(a) and (c)
output. This is illustrated in Figs 5.11 (a) and (c).
This proves the truth table of NAND gate as shown in Fig. 5.11(b).

5.7  Design of Two-input NOR Gate

Let us consider another example of a two-input NOR gate. The two-input NOR
function is expressed by

Y = A+ B (5.3)
Step 1:  Take complement of Y

Y = A+ B= A+ B (5.4)
Step 2:  Design the PDN
Here, there is only one OR term. Hence, there will be two nMOSFETs connected
in parallel, as shown in Fig. 5.12.
Step 3:  Design the PUN
In the PUN, two pMOSFETs will be connected in series, as shown in Fig. 5.13.

Figure 5.12  Pull-down network Figure 5.13  Pull-up network

comprising nMOSFETs comprising pMOSFETs

Now, join the PUN and PDN as shown in Fig. 5.14 (c).

VDD
A
Y
B A

(a)
B
Y
A B Y
A B
0 0 1
0 1 0
1 0 0
1 1 0

(b) (c)
Figure 5.14  Two-input NOR gate: (a) Symbol; (b) Truth table; (c) CMOS realization

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 170  Vlsi design

Operation  When A = 0 and B = 0, both nMOS transistors are OFF and both
pMOS transistors are ON. Hence, the output is connected to VDD and we get logic
high at the output.
When A = 1 and B = 0, the upper pMOS is OFF and lower pMOS is ON. So,
output cannot be connected to the VDD. Under this condition, left nMOS is ON
and right nMOS is OFF. Hence, the output is connected to the ground and we get
logic low at the output.
When A = 0 and B = 1, the upper pMOS is ON and lower pMOS is OFF. So,
output cannot be connected to VDD. Under this condition, left nMOS is OFF and
right nMOS is ON. Hence, the output is connected to the ground and we get logic
low at the output.
When A = 1 and B = 1, both nMOS transistors are ON and both pMOS transistors
are OFF. Hence, the output is connected to VDD and we get logic low at the output.
This proves the truth table of NOR gate as shown in Fig. 5.14(b).

5.8  Classification of CMOS Digital Logic Circuit

CMOS logic circuits are mainly classified into two categories as follows:
n Combinational logic circuit
n Sequential logic circuit

In the combinational logic circuit, the output is determined by the present logic
inputs. However, in the sequential logic circuit, the output is determined by the
present, inputs and past outputs. The examples of combinational logic circuits
are Inverter, NAND gate, NOR gate, multiplexer, demultiplexer, decode, encoder,
half-adder, full-adder, etc. The examples of sequential logic circuits are flip-flops,
latches, registers, counters, etc.
There are other CMOS design styles as given below:
n CMOS transmission logic
n Complementary pass-transistor logic
n Dynamic CMOS logic
n Domino CMOS logic
n NORA CMOS logic
n Zipper CMOS logic

5.9 Combinational Logic Circuit

In this section, we discuss how the combinational logic circuit is designed with a few
examples. As we have discussed before, any CMOS logic circuit consists of a PUN
and a PDN. The PUN comprises only pMOSFETs, and the PDN only nMOSFETs.
There is a fundamental reason why pMOSFETs are used in PUN and the nMOSFETs
in PDN is also explained before.

5.9.1 Design of Complex Logic Circuit

Let us now design a complex Boolean function as follows.

Y = A( B + C ) + DE  (5.5)

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 Digital CMOS Logic Design  171

Step 1:  Take complement of Y

Y = A( B + C ) + DE = A( B + C ) + DE  (5.6)

Step 2:  Design of PDN

Let Z = B + C, then Eqn. (5.6) becomes

Y = AZ + DE  (5.7)

Now, Z (=B + C) is realized by two nMOSFETs connected in parallel. Let us call this
as sub-logic realizing Z. In Eqn. (5.7), there are two AND terms which are ORed.
AZ is realized by one nMOSFET connected in series with sub-logic realizing Z. The
term DE is realized by two nMOSFETs connected in series. Finally, two sub-logics
realizing AZ and DE are connected in parallel.
Step 3:  Design of PUN
We just do the reverse connection of nMOSFETs to realize the PUN using
pMOSFETs.
The complete CMOS logic is shown in Fig. 5.15.
The Boolean function given in Eqn (5.5) can also be realized, as shown in
Fig. 5.16. In this case, we expand Eqn (5.6) into:
Y = AB + AC + DE  (5.8)

VDD VDD

B A B
A
C A C

D E D E

Y Y

A
D A A D

B C E B C E

Figure 5.15  CMOS logic realizing the Figure 5.16  CMOS logic realizing the
Boolean function given in Eqn. (5.5) Boolean function given in Eqn. (5.8)

Comparing the realizations shown in Fig. 5.15 and in Fig. 5.16, we can see that in
Fig. 5.16, we need more transistors than in Fig. 5.15. This means that the CMOS
logic realization with the minimum number of transistors requires judicious
function optimization.

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 172  Vlsi design

5.9.2 Design of AND-OR-INVERT and OR-AND-INVERT Gate

Any Boolean function can be expressed either in the SOP (sum-of-products) or
POS (product-of-sum) form. The AND-OR-INVERT (AOI) gate is suitable for
realizing functions in the SOP form. Here a function is expressed as a summation
(OR) of product (AND) terms. For example, a function X in the SOP form with a
complement can be written as

X = AB + CD + EFG  (5.9)
The AOI implementation of the function X is shown in Fig. 5.17. Each AND
term is implemented by a series combination of nMOS transistors. The OR
operation between the AND terms is realized by a parallel connection of each
series connected nMOS transistors subcircuit. The PUN is implemented as a
dual of an nMOS network.

VDD

G F E

D C

A B

X = AB + CD + EFG

A C E

B D F

Figure 5.17  AOI gate realization using CMOS logic

Similarly, a function expressed in the POS form with a complement can be written as

Y = ( A + B)(C + D )( E + F + G )  (5.10)

The OR-AND-INVERT (OAI) realization of the function Y is shown in Fig. 5.18.

Each OR term is implemented by a parallel combination of nMOS transistors. The
AND operation between the OR terms is realized by series connection of each
parallel connected nMOS transistors subcircuit. The PUN is implemented as a dual
of the nMOS network.

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 Digital CMOS Logic Design  173

VDD

A C E

B D F

Y = (A + B)(C + D)(E + F + G)

G F E

D C

A B

Figure 5.18  OAI gate realization using CMOS logic

5.9.3 Design of XOR Gate

The Boolean expression for two-input XOR gate is given by

Y = AB + AB  (5.11)
Step 1:  Take complement of Y

Y = AB + AB = AB × AB = ( A + B) × ( A + B) = AB + AB  (5.12)

Step 2:  Design of PDN

Here, there are two AND terms and one OR term. Each of the AND terms is realized
by two series-connected nMOSFETs. The OR term
is realized by parallel connection of two series VDD
connected nMOSFETs realizing AND terms.
A B
Step 3:  Design of PUN
In PUN, we need four pMOSFETs connected in a
reverse manner. A B
Y=A⊕B
The complete CMOS circuit realizing two-input
XOR gate is shown in Fig. 5.19. A A
Note:  In realizing the two-input XOR gate, we
have assumed that the inputs are available both in B B
the normal and complemented form. This is a valid
assumption because in a full-chip design, the inputs
might come from the output of flip-flop or latch Figure 5.19  CMOS realization
where both the normal and complemented form of of two-input XOR gate

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 174  Vlsi design

the output (Q and Q ) is available. In case the complemented input is not available, an
inverter is to be used to generate the complemented input.

5.9.4 Design of Half-adder Circuit

A half-adder circuit has two inputs and two outputs: Sum and Carry. The truth
table of a half-adder circuit is shown in Table 5.1.

Table 5.1  Truth table of half-adder

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Boolean expressions for the sum and carry are given by

Sum = AB + AB  (5.13)

Carry = AB  (5.14)
CMOS realization of Sum is shown in Fig. 5.19 and the Carry is shown in Fig. 5.20.

VDD
VDD
A B

Carry
A
B

Figure 5.20  CMOS realization of carry function of half-adder circuit

5.9.5 Design of Full-adder Circuit

A full-adder circuit has three inputs: A, B, and Carry-in (C in) and two outputs: Sum
and Carry-out (Cout). The truth table of full-adder circuit is shown in Table 5.2.
Boolean expressions for the Sum and Cout are given by

Sum = ABCin + ABC in + ABC in + ABC in  (5.15)

Cout = AB + AC in + BC in  (5.16)

As shown in Table 5.3, taking Cout as input, we could simplify the expression for
Sum as:
Sum = AC out + BC out + C in C out + ABC in
 (5.17)

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 Digital CMOS Logic Design  175

Table 5.2  Truth table of full-adder

A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 5.3  Truth table of full-adder (modified to include Cout )

A B Cin Cout Cout Sum
0 0 0 0 1 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 1
1 0 1 1 0 0
1 1 0 1 0 0
1 1 1 1 0 1

The complete CMOS realization of full-adder is shown in Fig. 5.21.

VDD

A B Cin Cin
A B A Cout
B
Cin B A
Sum
Cout
A
Cin A
B
A B B A B Cin Cin

Figure 5.21  CMOS realization of full-adder circuit

Example 5.1  Design 2 × 2 input AND-OR gate to realize the following Boolean function:
Y = AB + CD
Solution  To realize the Boolean function, first we find out the complement of the AQ  Pls. verify
citation for Fig.
function.
5.22.
Complement of the function, Y = AB + CD = AB ×CD = ( A + B) ×(C + D).
We can see Y has two OR terms and one AND term. Realize each OR term by
parallel connection of two nMOS. Connect them in series to realize the AND term
as shown in Fig 5.22.

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 176  Vlsi design

Example 5.2  Realize a tri-state buffer. VDD

Solution  A tri-state buffer can be

A C
realized as shown in Fig. 5.23 (c).
The circuit implementation as shown
B D
in Fig. 5.23(d) is not recommended as
it suffers from dynamic charge sharing
Y
problem.

Example 5.3  Design a 2:1 multiplexer A B

using static CMOS logic.
C D
Solution  A 2:1 multiplexer can be
realized, as shown in Fig. 5.24 (c).
Figure 5.22 Schematic to realize function
Y = AB + CD

C A Y VDD VDD
0 0 0
0 1 1 VDD VDD
C
1 0 Z
1 1 Z C
(a) Y Y
A A
C
A Y
C
C
(b) (c) (d) Not
recommended

Figure 5.23  Tri-state buffer: (a) truth table; (b) symbol; (c) and (d) CMOS realization

VDD
S A B Y
0 0 0 0
0 0 1 0
0 1 0 1 A S VDD
0 1 1 1
1 0 0 0
1 0 1 1 B S
1 1 0 0 Y
1 1 1 1
(a) A B

A 0
Y = AS + BS S S
B 1

S (c)
(b)
Figure 5.24  2:1 Multiplexer: (a) truth table; (b) symbol; (c) CMOS realization

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 Digital CMOS Logic Design  177

5.10 Sequential Logic Circuit

In the combinational logic circuits, the output is determined by the input logic
levels. The combinational circuit lacks the storing capability of any previous
events. In the sequential logic circuits, the output is determined by the present
input logic level, as well as the past output logic level. In the sequential circuit,
there is a feedback connection between the output and the input.

5.10.1 Design of SR Latch Circuit

In the SR latch logic circuit, there are two inputs: S (Set) and R (Reset) and two
complementary outputs: Q and Q. The input and output relationship is described
in Table 5.4.
Table 5.4  Truth table of the NOR-based SR latch circuit
S R Qn+1 Qn+1 Operation
0 0 Qn Qn Hold
1 0 1 0 Set
0 1 0 1 Reset
1 1 0 0 Not allowed

The gate-level schematic of the SR latch circuit is shown in Fig. 5.25.

Figure 5.26 shows the CMOS realization of the NOR-based SR latch circuit.

VDD VDD

M1 M5
S
Q M2 M6
Q Q

S M3 M4 M7 M8 R

Q
R
Figure 5.25 Gate-level schematic Figure 5.26  CMOS realizations of NOR-
of SR latch realized using NOR gate based SR latch circuit

The next state of SR latch can be expressed as

Qn+1 = S + RQn   ( for SR = 0) (5.18)
The condition SR = 0 implies that both S and R cannot be 1 at the same time. An
equation that expresses the next state value of a latch in terms of its present state
and inputs is referred to as a ‘next-state equation’ or a ‘characteristic equation’.

Operation  When S = 0 and R = 0, the nMOS transistors M3 and M8 are OFF. The
pMOS transistors M1 and M5 are ON. This cannot determine the output logic. Let
us assume Q = 0, then M2 is ON and M4 is OFF. Thus, the node Q is connected to
VDD, i.e., Q = 1. As Q = 1, M7 is ON and M6 is OFF. Thus, node Q is connected

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 178  Vlsi design

to the ground, i.e., Q remains at logic 0 state. If we assume Q = 1, then M4 is ON

and M2 is OFF. Thus, node Q is connected to the ground, i.e., Q = 0. As Q = 0, M6
is ON and M7 is OFF. Thus, node Q is connected to VDD, i.e., Q remains at logic 1
state. This proves the first row of the truth table of SR latch.
When S = 0, R = 1, the transistor M8 is ON. Thus, irrespective of other input
and past output conditions, the node Q is connected to the ground, i.e., Q is in
logic 0 state.
When S = 1 and R = 0, the transistor M3 is ON. Thus, irrespective of other input
and past output conditions, the node Q is connected to
the ground, i.e., Q is in logic 0 state. This makes M5 S
and M6 ON; thus, node Q is connected to VDD, i.e., Q Q
is in logic 1 state.
If S and R inputs are zero at the same time, both
the outputs will be zero. Hence, this combination is
not allowed. Q
The SR latch circuit can also be realized using R
NAND gates as shown in Fig. 5.27. Figure 5.27 Gate-level
Table 5.5 shows the truth table of NAND-based schematic of SR latch real-
SR latch circuit. ized using NAND gate

Table 5.5  Truth table of the NAND-based SR latch circuit

S R Qn+1 Qn+1 Operation
0 0 1 1 Not allowed
0 1 1 0 Set
1 0 0 1 Reset
1 1 Qn Qn Hold

Figure 5.28 shows the CMOS realization of the NAND-based SR latch circuit.

VDD VDD

Q
Q

S R

Figure 5.28  CMOS realizations of NAND-based SR latch circuit

5.10.2 Design of Clocked Latch and Flip-flop Circuit

The SR latch circuits discussed in Section 5.10.1 is asynchronous in nature in which
the output changes as the input logic level changes. In a design, the inputs might
come from different paths encountering different path delays. Hence, depending on
which input comes first, the output might change accordingly, which might not be
the desirable output. To avoid this problem, a clock input is added such that the
output changes only in the active period of the clock signal. Generally, the clock signal
is a periodic square waveform applied simultaneously to all the gates in the system.

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 Digital CMOS Logic Design  179

Figure 5.29 shows the gate-level schematic of the clocked NOR-based SR

latch.

S
Q

CLK

Q
R

Figure 5.29 Schematic of the clocked NOR-based SR latch circuit

Figure 5.30 shows the CMOS design of the NOR-based SR latch circuit.

VDD VDD
CLK

Q Q

R S
CLK CLK

Figure 5.30  CMOS realization of the clocked NOR-based SR latch circuit

The NAND-based SR latch can also be realized with clock input. This is left as an
exercise to the readers.

5.10.3 Design of Clocked JK Latch

The JK latch is commonly known as JK flip-flop. It has three inputs: J, K, and CLK;
and two complementary outputs: Q and Q. JK flip-flop has no not-allowed inputs,
unlike SR latches. It allows all possible input combinations. The truth table is shown
in Table 5.6.

Table 5.6  Truth table of JK flip-flop

J K Qn Qn Qn+1 Qn+1 Operation
0 0 0 1 0 1 Hold
1 0 1 0
0 1 0 1 0 1 Reset
1 0 0 1
1 0 0 1 1 0 Set
1 0 1 0
1 1 0 1 1 0 Toggle
1 0 0 1

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 180  Vlsi design

Figure 5.31 shows the gate-level design of the JK flip-flop.

R
K
Q

CLK

S Q
J

Figure 5.31  Gate level design of JK flip-flop

Figure 5.32 shows the CMOS design of the JK flip-flop.
VDD CLK VDD

Q Q

K J
CLK CLK

Figure 5.32  CMOS design of JK flip-flop

5.11 Pseudo-nMOS Logic
In the pseudo-nMOS logic, the PDN is realized by a single pMOS transistor. The gate
terminal of the pMOS transistor is connected to the ground. It remains permanently
in the ON state. Depending on the input combinations, output goes low through the
PDN. An inverter realized using pseudo-nMOS logic is shown in Figs 5.33 (a), (b)
and (c). The PDN is realized using the process described in Section 5.4.
VDD
A Y
0 1
1 0
(a) Y

A
A Y

(b) (c)

Figure 5.33 Inverter: (a) Truth table; (b) Symbol; (c) Pseudo-nMOS realization
Example 5.4  Design an XNOR gate using pseudo-nMOS logic.

Solution  The pseudo-nMOS realization of two-input XNOR gate is shown in Fig. 5.34.

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 Digital CMOS Logic Design  181

VDD
A B Y
0 0 1
0 1 0 Y
1 0 0
1 1 1 A A

(a)
B B

Y = AB + A B
(b) (c)
Figure 5.34  XNOR gate: (a) Truth table; (b) Boolean expression;
(c) Pseudo-nMOS realization

5.12 CMOS Transmission Gate C

CMOS transmission gate ( TG) is a parallel connection of

nMOSFET and pMOSFET that realizes a simple switch. A B
The inputs to the gate of the nMOSFET and pMOSFET
are complementary to each other. It is also known as pass
gate and is abbreviated as TG. Figure. 5.35 shows a TG. C
When signal C is high, C is low, thus both nMOS and
Figure 5.35  CMOS
pMOS transistors are ON, and the node A and B is short-
transmission gate
circuited. So the input logic is transferred to the output.
When signal C is low, C is high, thus both nMOS and pMOS transistors are OFF,
and the node A and B are open-circuited, this is called high-impedance state.
Using CMOS TG logic, circuits can be designed, and it might require lesser
number of transistors as compared to the standard CMOS design. This will be clear
as we go through some examples in Section 5.12.1.

5.12.1 Design of Combinational Logic Circuits Using CMOS TGs

Example 5.5  Design a 2:1 Multiplexer.
Figure 5.36 shows the design of a two-input multiplexer circuit.

Y = AS + BS

Figure 5.36 Design of two-input MUX using CMOS TGs

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 182  Vlsi design

Example 5.6  Design a two-input XOR gate.

Figure 5.37 shows the design of a XOR gate.

A Y = AB + AB

Figure 5.37 Design of XOR gate using CMOS TGs

Example 5.7  Design of a Boolean function F = ABC + AC + BC.

Figure 5.38 shows the design of a Boolean function F = ABC + AC + BC.

A
Y = ABC + AC + BC
VDD
C

B
A

A C Y
C

B B

C
Figure 5.38 Design of 3-variable Boolean function using CMOS TGs

5.12.2 D-Latch and Edge-triggered Flip-flop

D J
Q
D-latch stores a logic level. This is often called
1-bit register or delay flip-flop. It has single JK Flip-flop
data input D and two outputs: Q and Q. This
is obtained simply by connecting an inverter
K Q
between the J and K inputs of the JK flip-flop. D
input is directly connected to the J input and, the
CLK
inverted D input is connected to the K input of
the JK flip-flop. Block diagram of the D-latch is
shown in Fig. 5.39. Figure 5.39  Block diagram of
Truth table of the D-latch is shown in Table 5.7. the D-latch

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 Digital CMOS Logic Design  183

Table 5.7  Truth table of D-latch

D Qn+1
0 0
1 1

Figure 5.40 shows the design of the D-latch using CMOS TGs

CLK VDD VDD

Q
D Q
CLK

CLK

CLK
Figure 5.40 Design of the D-latch using CMOS TGs

The D-latch discussed above is a level triggered flip-flop. This means that the
output of the flip-flop changes as long as the clock signal remains at logic high.
This has a serious problem in digital logic circuits where output might change
during the ON-state of the clock pulse several times if data input changes. But
we would like to have output that changes only once in a clock cycle. One way
of solving this problem is to design the clock such that it remains at an enabling
level for a very short time. In many situations, it may be found that the narrow
clock pulses are too narrow to trigger the flip-flop reliably. A better solution is to
design the flip-flop such that the output changes only when the clock input makes
a transition, rather than at the enabling level of the clock input. One such flip-flop,
where output changes only on the clock transitions is a master–slave flip-flop.
Figure 5.41 shows a master–slave flip-flop, which is designed by cascading two
D-latches. The clock signal is applied to the first stage (master) and the inverted
clock signal is applied to the second stage (slave).

CLK CLK VDD VDD CLK VDD VDD

Qm Qm Qs
D Qs

CLK CLK
CLK CLK
CLK

CLK
CLK CLK

Figure 5.41  CMOS edge-triggered master–slave D-flip-flop

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