DIGITAL VLSI DESIGN

Rekha S S
Department of Electronics and
Communication Engg.
DIGITAL VLSI DESIGN

Fabrication of MOSFETs & Circuit

Design Process
 Fabrication of MOSFETs & Circuit Design Process

Unit 2: Fabrication of MOSFETs & Circuit

Design Process
14-15 NMOS fabrication, CMOS
fabrication, p-well, n-well, twin-
tub process (2.2 & 2.3)
16 - 17 MOS layers, Lambda based design
R1:Chap 2 (2.1 –
rules, contact cuts (2.4)
2.5)
R1:Chap 7 (7.4) Stick diagrams and Layout
19 - 22 diagrams - nMOS design style 19% 41%
(simplenMOS
Circuits) (3.2)
23 - 24 Complex Logic Circuits (7.4)

Reference Books:
R1: CMOS Digital Integrated CircuitsAnalysis And Design, Sung-Mo (Steve) Kang

R2: Basic VLSI Design ,Douglas A. Pucknell & Kamran Eshraghian 3rd Edition.
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nMOS FABRICATION

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Fabrication of MOSFETs & Circuit Design Process

• Processing is carried out on a thin wafer cut from a

single crystal of silicon of high purity into which
the required p-impurities are introduced as the
crystal is grown.
• wafers are typically 75 to 150 mm in diameter and 0.4 mm thick
• impurity concentrations of 1015 /cm3 to 1016/cm3, giving resistivity in the
approximate range 25 ohm cm to 2 ohm cm.

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• A layer of silicon dioxide (Si02), typically 1 µm thick,

is grown all over the surface of the wafer to protect
the surface, act as a barrier to dopants during
processing, and provide a generally insulating
substrate on to which other layers may be
deposited and patterned.

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• The surface is now covered with a photoresist

which is deposited onto the wafer and spun to
achieve an even distribution of the required
thickness.

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• The photoresist layer is then exposed to ultraviolet

light through a mask which defines those regions
into which diffusion is to take place together with
transistor channels.
• areas exposed to ultraviolet radiation are polymerized
(hardened), but that the areas required for diffusion are
shielded by the mask and remain unaffected.

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• These areas are subsequently readily etched away

together with the underlying silicon dioxide so that the
wafer surface is exposed in the window defined by the
mask.

• In the fabrication of fine pattern devices, precise

control of thickness, impurity concentration, and
resistivity is necessary.
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• The remaining photoresist is removed and a thin

layer of Si02 (0.1 µm typical) is grown over the
entire chip surface and then polysilicon is
deposited on top of this to form the gate structure
• The polysilicon layer consists of heavily doped
polysilicon deposited by chemical vapour
deposition (CVD).

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Fabrication of MOSFETs & Circuit Design Process
• Further photoresist coating and masking allows the
polysilicon to be patterned and then the thin oxide is
removed to expose areas into which n-type impurities
are to be diffused to form the source and drain

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Fabrication of MOSFETs & Circuit Design Process
• Further photoresist coating and masking allows the
polysilicon to be patterned and then the thin oxide is
removed to expose areas into which n-type impurities
are to be diffused to form the source and drain

• Diffusion is achieved by heating the wafer to high

temperature and passing a gas containing the desired n-
type impurity

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• Thick oxide (sio2) is grown over all again and is

then masked with photoresist and etched to
expose selected areas of the polysilicon gate and
the drain and source areas where connections(i.e.
contact cuts) are to be made.

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• The whole chip then has metal (aluminium) deposited

over its surface to thickness typically of 1µm.
• This metal layer is then masked and etched to form
the required interconnections pattern.

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Fabrication of MOSFETs & Circuit Design Process

nMOS Fabrication Process

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CMOS FABRICATION
• There are a number of approaches to CMOS
fabrication, including the p-well, the n-well, the twin-
tub, and the silicon-on-insulator processes.
• The p-well Process

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The n-well Process

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Twin tub process

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CMOS Fabrication

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Latch-UP in CMOS Circuits

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Latch-UP in CMOS Circuits

• Latch up is a condition in which the parasitic components give rise to the

establishment of low-resistance conducting path between Vdd and Vss/GND
with unsuccessful results. Careful control during fabrication is required.

• Remedies for the latch-up problem include:

✓ an increase in substrate doping levels with a consequent drop in the
value of R5 ;
✓ reducing RP by control of fabrication parameters and by ensuring a
low contact resistance to Vss;
✓ other more elaborate measures such as the introduction of guard
rings.
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 Fabrication of MOSFETs & Circuit Design Process

•
Latch-UP in CMOS Circuits
Remedies for the latch-up problem include:
✓ an increase in substrate doping levels with a consequent drop in the
value of R5 ;
✓ reducing RP by control of fabrication parameters and by ensuring a
low contact resistance to Vss;
✓ other more elaborate measures such as the introduction of guard
rings.

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 Fabrication of MOSFETs & Circuit Design Process

Twin-Tub (Twin-Well) CMOS Process

• This technology provides the basis for separate optimization
of the nMOS and pMOS transistors, thus making it possible
for threshold voltage, body effect and the channel
transconductance of both types of transistors to be tuned
independently.

• Generally, the starting material is a n+ or p+ substrate, with

a lightly doped epitaxial layer on top.

• This epitaxial layer provides the actual substrate on which

the n-well and the p-well are formed. Since two independent
doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully
optimized to produce the desired device characteristics.
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 Fabrication of MOSFETs & Circuit Design Process

• The Twin-Tub process is shown below.

• In the conventional p & n-well CMOS process, the doping density of the
well region is typically about one order of magnitude higher than the
substrate, which, among other effects, results in unbalanced drain
parasitics. The twin-tub process avoids this problem
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 Fabrication of MOSFETs & Circuit Design Process
Silicon-on-Insulator (SOI) CMOS Process
• Rather than using silicon as the substrate material, technologists have
sought to use an insulating substrate to improve process characteristics
such as speed and latch-up susceptibility.
• The SOI CMOS technology allows the creation of independent,
completely isolated nMOS and pMOS transistors virtually side-by-side
on an insulating substrate.
• The main advantages of this technology are the higher integration
density (because of the absence of well regions), complete avoidance of
the latch-up problem, and lower parasitic capacitances compared to the
conventional p & n-well or twin-tub CMOS processes.
• A crosssection of nMOS and pMOS devices using SOI process is shown
below

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Silicon-on-Insulator (SOI) CMOS Process
• A crosssection of nMOS and pMOS devices using SOI
process is shown below

• The SOI CMOS process is considerably more costly than

the standard p & n-well CMOS process.
• Yet the improvements of device performance and the
absence of latch-up problems can justify its use, especially
for deep-sub-micron devices
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Fabrication of MOSFETs & Circuit Design Process

MOS Layers
• MOS design is aimed at turning a specification into
masks for processing silicon to meet the specification.
• MOS circuits are formed on four basic layers
• n-diffusion
• p- diffusion which are isolated from one another
• Polysilicon by thick or thin silicon dioxide
• Metal
• The thin oxide (thinox) mask region includes n-
diffusion, p-diffusion, and transistor channels.
• Polysilicon and thinox regions interact so that a
transistor is formed where they cross one another.

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Stick Diagram

• VLSI design aims to translate circuit concepts onto

silicon.
• Stick diagrams convey layer information through
color codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and
the actual layout.
• A stick diagram is a cartoon of a layout

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Capabilities of stick diagram

▪ Does show all components/vias.
▪ It shows relative placement of components.
▪ Goes one step closer to the layout.
▪ Helps in plan the layout and routing.

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Limitations of stick diagram

➢ Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitic.

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Color code for single metal nMOS process

Metal 1

Poly 1

ndiff

Contact Buried
cut Contact
nMOS
implant
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nMOS stick diagram

• draw the stick diagrams for the following
circuit.

1) nMOS inverter

2) Logic function

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nMOS Inverter

Vdd

output

input

Gnd

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Logic function

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Logic function

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Draw the circuit diagram for the stick diagram given

• Shift register cell

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Stick diagrams and corresponding mask layout examples

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Color code for double metal CMOS
process

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CMOS Inverter

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1 bit shifter

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2 input CMOS NAND gate

• Note: for all the layers hatching lines are not shown

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2 input CMOS NOR gate

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Draw the stick diagram and layout for the

following expressions

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Complex Logic Circuits

• 1st expression using nMOS Design style

• the equivalent driver

(W/L ) ratio of PD network
• consist of five nMOS
transistors is given

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Note

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• For calculating the logic-low voltage level VOL

• have to consider various cases, since the value of VOL actually
depends on the number and the configuration of the conducting
nMOS transistors in each case. All possible configurations are
tabulated below. Each configuration is assigned a class number which
reflects the total resistance of the current path from V0ut node to
ground.

The logic-low voltage levels corresponding to each class

have the following order, where each subscript numeral
represents the class number.

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The design objective is to determine the driver and load transistor sizes so
that the complex logic gate achieves the specified VOL value even in the worst
case. The given VOL value first allows us to find the (W/L)Ioad and (WIL)drive {
equivalent circuit similar to inverter circuit}

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1st expression using CMOS Design style

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Euler Path

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Stick diagram before

Euler path

Stick diagram after

Euler path

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Find an equivalent CMOS inverter circuit for simultaneous switching of all inputs,
assuming that (W/L)p = 15 for all pMOS transistors and (W/L) = 10 for all nMOS
transistors for the circuit given and also write the output Boolean expression.

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Find an equivalent CMOS inverter circuit for simultaneous switching of all inputs,
assuming that (W/L)p = 15 for all pMOS transistors and (W/L) = 10 for all nMOS
transistors for the circuit given and also write the output Boolean expression.

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DESIGN RULES
• Allow translation of circuits (usually in stick diagram or
symbolic form) into actual geometry in silicon
• Interface between the circuit designer and process
engineer
• Design rules must be followed to insure functional
structures on the fabricated chip
• Circuit designers in general want tighter, smaller layouts
for improved performance and decreased silicon area.
• Process engg. wants design rules that result in a
controlled and reproducible process.
• Generally we find that there has to be a compromise for
a competitive circuit to be produced at a reasonable
cost.

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• Design rules can be expressed in absolute physical

units… eg. Poly width .3µm
poly spacing .45µm
metal width .45µm
metal spacing .45µm
• Scalable design rules express dimensions in
normalized units called lambda (λ)

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• The design rules are usually described in two ways :

• Micron rules, in which the layout constraints such as
minimum feature sizes and minimum allowable
feature separations, are stated in terms of absolute
dimensions in micrometers..
• Lambda rules, which specify the layout constraints in
terms of a single parameter (λ) and, thus, allow linear,
proportional scaling of all geometrical constraints.
• Lambda-based layout design rules were originally
devised to simplify the industry-standard micron-
based design rules and to allow scaling capability for
various processes.
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Lambda Based Design Rules

• Design rules based on single parameter, λ

• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working
circuits
• Minimum feature size is defined as 2 λ
• Prevents shorting, opens, contacts from slipping out of area
to be contacted

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• Lambda design rules are based on a reference metric

λthat has units of um.
• All widths, spacing and distances are written in the
form ➔ Value = m λ
Where m is scaling multiplier.
<e.g.> λ= 1um ➔ w = 2 λ=2um
s = 3λ=3um
• Three major rules:
• Wire width: Minimum dimension associated
with a given feature.
• Wire separation: Allowable separation.
• Contact: overlap rules.
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Contact cuts

• When making contacts between polysilicon and

diffusion in nMOS circuits the possible approaches
➢Poly to metal, then metal to diffusion --- butting contact
➢Poly to diffusion --- buried contact

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Buried contact

• basically, layers are joined over a 2 x 2 area with

the buried contact cut extending by 1 in all
directions around the contact area except that the
contact extension is increased to 2 in diffusion
paths leaving the contact area. This is to avoid
forming unwanted transistors.

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Butting contact

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Double Metal MOS Process Rules

• This gives a much greater degree of freedom, for example, in
distributing global VDD and Vss (GND) rails in a system.
• metal 1 to metal 2 contacts, called vias

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• Use the second level metal for the global

distribution of power buses, that is, VDD and GND
( Vss), and for clock lines.
• Use the first level metal for local distribution of
power and for signal lines.
• Layout the two metal layers so that the conductors
are mutually orthogonal wherever possible.

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Write Boolean expression for the given

circuit

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Write Boolean expression for the given stick
diagram

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Write Boolean expression for the given stick
diagram

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Write Boolean expression for the given
layout

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