LAB 1-

Q- Write RTL description and test bench for full adder circuit using half adder and OR gate.

Source code-

Full adder:

module full_adder_tb();

//Testbench global variables

reg a,b,c;
wire sum,carry;
//Variable for loop iteration
integer i;

//Step1 : Instantiate the full adder with order based port mapping
full_adder uut (a,b,c,sum,carry);
//Process to initialize the variables at 0ns
initial
begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
end

//Process to generate stimulus using for loop

initial
begin
for (i=0;i<8;i=i+1)
begin
{a,b,c}=i;
#10;
end
end

//Process to monitor the changes in the variables

initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,c,sum,carry);

//Process to terminate simulation after 100ns

initial #100 $finish;
Endmodule

Half adder:

module half_adder(input a,b, output sum,carry);

assign sum = a ^ b;
assign carry = a & b;

endmodule

Test bench:

module full_adder_tb();

//Testbench global variables

reg a,b,c;
wire sum,carry;
 //Variable for loop iteration
integer i;

//Step1 : Instantiate the full adder with order based port mapping
full_adder uut (a,b,c,sum,carry);
//Process to initialize the variables at 0ns

initial
begin
a = 1'b0;
b = 1'b0;
c = 1'b0;
end

//Process to generate stimulus using for loop

initial
begin
for (i=0;i<8;i=i+1)
begin
{a,b,c}=i;
#10;
end
end

//Process to monitor the changes in the variables

initial
$monitor("Input a=%b, b=%b, c=%b, Output sum =%b, carry=%b",a,b,c,sum,carry);

//Process to terminate simulation after 100ns

initial #100 $finish;
endmodule

Output

# Input a=0, b=0, c=0, Output sum =0, carry=0

# Input a=0, b=0, c=1, Output sum =1, carry=0
# Input a=0, b=1, c=0, Output sum =1, carry=0
# Input a=0, b=1, c=1, Output sum =0, carry=1
# Input a=1, b=0, c=0, Output sum =1, carry=0
# Input a=1, b=0, c=1, Output sum =0, carry=1
# Input a=1, b=1, c=0, Output sum =0, carry=1
# Input a=1, b=1, c=1, Output sum =1, carry=1
# ** Note: $finish : C:/Users/saikr/Desktop/Verilog_labs/lab1/tb/full_adder_tb.v(35)
# Time: 100 ps Iteration: 0 Instance: /full_adder_tb

Waveform:
EX-1 Write RTL description & test bench for the 4-bit ripple carry adder using 1-bit full adder

Source code-
module ripple4(a,b,cin,s,carry);
input [3:0]a,b;
input cin;
output [3:0]s;
output carry;
wire w1,w2,w3;
full_adder fa1(.a(a[0]), .b(b[0]), .c(cin), .sum(s[0]), .carry(w1));
full_adder fa2(.a(a[1]), .b(b[1]), .c(w1), .sum(s[1]), .carry(w2));
full_adder fa3(.a(a[2]), .b(b[2]), .c(w2), .sum(s[2]), .carry(w3));
full_adder fa4(.a(a[3]), .b(b[3]), .c(w3), .sum(s[3]), .carry(carry));
endmodule

Test bench-

module full_adder_tb();
reg [3:0]a,b;
reg c;

wire [3:0]sum;
wire carry;
integer i;
ripple4 uut (a,b,cin,s,carry);
initial
begin
a=4'b0;
b=4'b0;
c=1'b1;
end
initial
begin

for(i=0;i<512;i=i+13)
begin
{a,b,c}=i;
#5;
end
end
initial
$monitor( "$time ,"input a[%d]=%b ,b[%d]=%b ,c[%d]=%b , sum[%d]=%b,
carry[%d]=%b",i,a,i,b,i,c,i,sum,i, carry);
initial #200
$finish;
endmodule
Output :

0input a=0000 ,b=0000 ,c=0 , sum=0000, carry=0

# 5input a=0000 ,b=0110 ,c=1 , sum=0110, carry=0
# 10input a=0000 ,b=1101 ,c=0 , sum=1101, carry=0
# 15input a=0001 ,b=0011 ,c=1 , sum=0100, carry=0
# 20input a=0001 ,b=1010 ,c=0 , sum=1011, carry=0
# 25input a=0010 ,b=0000 ,c=1 , sum=0010, carry=0
# 30input a=0010 ,b=0111 ,c=0 , sum=1001, carry=0
# 35input a=0010 ,b=1101 ,c=1 , sum=1111, carry=0
# 40input a=0011 ,b=0100 ,c=0 , sum=0111, carry=0
# 45input a=0011 ,b=1010 ,c=1 , sum=1101, carry=0
# 50input a=0100 ,b=0001 ,c=0 , sum=0101, carry=0
# 55input a=0100 ,b=0111 ,c=1 , sum=1011, carry=0
# 60input a=0100 ,b=1110 ,c=0 , sum=0010, carry=1
# 65input a=0101 ,b=0100 ,c=1 , sum=1001, carry=0
# 70input a=0101 ,b=1011 ,c=0 , sum=0000, carry=1
# 75input a=0110 ,b=0001 ,c=1 , sum=0111, carry=0
# 80input a=0110 ,b=1000 ,c=0 , sum=1110, carry=0
# 85input a=0110 ,b=1110 ,c=1 , sum=0100, carry=1
# 90input a=0111 ,b=0101 ,c=0 , sum=1100, carry=0
# 95input a=0111 ,b=1011 ,c=1 , sum=0010, carry=1
# 100input a=1000 ,b=0010 ,c=0 , sum=1010, carry=0
# 105input a=1000 ,b=1000 ,c=1 , sum=0000, carry=1
# 110input a=1000 ,b=1111 ,c=0 , sum=0111, carry=1
# 115input a=1001 ,b=0101 ,c=1 , sum=1110, carry=0
# 120input a=1001 ,b=1100 ,c=0 , sum=0101, carry=1
# 125input a=1010 ,b=0010 ,c=1 , sum=1100, carry=0
# 130input a=1010 ,b=1001 ,c=0 , sum=0011, carry=1
# 135input a=1010 ,b=1111 ,c=1 , sum=1001, carry=1
# 140input a=1011 ,b=0110 ,c=0 , sum=0001, carry=1
# 145input a=1011 ,b=1100 ,c=1 , sum=0111, carry=1
# 150input a=1100 ,b=0011 ,c=0 , sum=1111, carry=0
# 155input a=1100 ,b=1001 ,c=1 , sum=0101, carry=1
# 160input a=1101 ,b=0000 ,c=0 , sum=1101, carry=0
# 165input a=1101 ,b=0110 ,c=1 , sum=0011, carry=1
# 170input a=1101 ,b=1101 ,c=0 , sum=1010, carry=1
# 175input a=1110 ,b=0011 ,c=1 , sum=0001, carry=1
# 180input a=1110 ,b=1010 ,c=0 , sum=1000, carry=1
# 185input a=1111 ,b=0000 ,c=1 , sum=1111, carry=0
# 190input a=1111 ,b=0111 ,c=0 , sum=0110, carry=1
# 195input a=1111 ,b=1101 ,c=1 , sum=1100, carry=1
# ** Note: $finish : C:/Users/saikr/Desktop/xxxxxx/lab1/ripple_4_tb.v(27)
# Time: 200 ps Iteration: 0 Instance: /ripple_4_tb
E2- RTL description & test bench for 4:1 MUX using 2:1 MUX

Source Code-

4:1 MUX-

module mux4_1(input a,b,c,d,s0,s1, output out);

wire w1,w2 ;
mux2_1 m1(.a(a), .b(b),. s(s1), .out(w1));
mux2_1 m2(.a(c), .b(d), .s(s1), .out(w2));
mux2_1 m3(.a(w1), .b(w2), .s(s0), .out(out));
endmodule

2:1 MUX-

module mux2_1(input a,b,s, output out);

assign out = ((~s)*a)+(s*b);
endmodule

Test bench-

module mux4_1_tb();
reg a,b,c,d,s0,s1;
wire out;
integer i;
mux4_1 DUT(a,b,c,d,s0,s1,out);
initial begin
a=1'b1;
b=1'b0;
c=1'b1;
d=1'b0;
s0=1'b0;
s1=1'b0;
end
initial begin
for(i=0;i<4;i=i+1)
begin
{s0,s1}=i;
#10;
end
end
initial #100
$finish;
endmodule
WAVEFORM

Output :
# 0a=1,b=0,c=1,d=0 s0=0,s1=0,out=1
# 10a=1,b=0,c=1,d=0 s0=0,s1=1,out=0
# 20a=1,b=0,c=1,d=0 s0=1,s1=0,out=1
# 30a=1,b=0,c=1,d=0 s0=1,s1=1,out=0
# Time: 100 ps Iteration: 0 Instance: /mux4_1_tb
A1- Write RTL for 2x4 decoder using dataflow abstraction

Source code-

module decoder2_4(a,b,e,y);
input a,b,e;
output [3:0]y;
assign y[0]=(~a)*(~b)*e;
assign y[1]=(~a)*(b)*e;
assign y[2]=(a)*(~b)*e;
assign y[3]=(a)*(b)*e;
endmodule

Test bench-

module decoder2_4_tb();
reg a,b,en;
wire [3:0]y;
integer i;

decoder2_4 UUT(a,b,en,y);
initial begin
a=1'b0;
b=1'b0;
en=1'b1;
end
initial begin

for(i=0;i<4;i=i+1)
begin
en=1'b1;
{a,b}=i;
#10;
en=1'b0;
a=1'b1;
b=1'b0;
#10
end end

initial #100
$finish;
Endmodule
Waveform

Output

# 0 a=0.b=0,en=1,y[0]=0001
# 10 a=0.b=1,en=1,y[ 1]=0010
# 20 a=1.b=0,en=1,y[ 2]=0100
# 30 a=1.b=1,en=1,y[ 3]=1000
# 40 a=1.b=1,en=1,y[ 4]=1000
A2- Write RTL for 8x3 priority encoder using structural model

Source code-

module priority(y,i,idle);
input [7:0]i;
output [2:0]y;
wire [7:0]h;
output idle;
assign h[7]=i[7];
assign h[6]=i[6]*(~i[7]);
assign h[5]=(i[5])*(~i[6])*(~i[7]);
assign h[4]=(i[4])*(~i[5])*(~i[6])*(~i[7]);
assign h[3]=(i[3])*(~i[4])*(~i[5])*(~i[6])*(~i[7]);
assign h[2]=(i[2])*(~i[3])*(~i[4])*(~i[5])*(~i[6])*(~i[7]);
assign h[1]=(i[1])*(~i[2])*(~i[3])*(~i[4])*(~i[5])*(~i[6])*(~i[7]);
assign h[0]=(i[0])*(~i[1])*(~i[2])*(~i[3])*(~i[4])*(~i[5])*(~i[6])*(~i[7]);

assign idle=(~i[0])*(~i[1])*(~i[2])*(~i[3])*(~i[4])*(~i[5])*(~i[6])*(~i[7]);

assign y[0]=i[1]+i[3]+i[5]+i[7];
assign y[1]=i[2]+i[3]+i[6]+i[7];
assign y[2]=i[4]+i[5]+i[+6]+i[7];
assign id=idle;
Endmodule

Test bench-

module prioritytb();

reg [7:0]i;
wire idle;

wire [2:0]y;
integer a;

Priority uut (i,y,idle) ;

task initialize;
begin
{i}=0;
end
endtask

task inputs(input [7:0]x);

begin
i=x;
#10;
end
endtask
initial
begin

initialize;

for (a=0;a<256;a=a+1)
begin
inputs(a);
end
end

initial
$monitor ($time ," data=%b,output=%b,idle=%b ",i,y,idle);

initial
begin
#250 $finish;
end

endmodule

Waveform

Output:
0 data=00000000,output=000,idle=1
# 10 data=00000001,output=000,idle=0
# 20 data=00000010,output=001,idle=0
# 30 data=00000011,output=001,idle=0
# 40 data=00000100,output=010,idle=0
# 50 data=00000101,output=010,idle=0
# 60 data=00000110,output=010,idle=0
# 70 data=00000111,output=010,idle=0
# 80 data=00001000,output=011,idle=0
# 90 data=00001001,output=011,idle=0
# 100 data=00001010,output=011,idle=0
# 110 data=00001011,output=011,idle=0
# 120 data=00001100,output=011,idle=0
# 130 data=00001101,output=011,idle=0
# 140 data=00001110,output=011,idle=0
# 150 data=00001111,output=011,idle=0
# 160 data=00010000,output=100,idle=0
# 170 data=00010001,output=100,idle=0
# 180 data=00010010,output=100,idle=0
# 190 data=00010011,output=100,idle=0
# 200 data=00010100,output=100,idle=0
# 210 data=00010101,output=100,idle=0
# 220 data=00010110,output=100,idle=0
# 230 data=00010111,output=100,idle=0
# 240 data=00011000,output=100,idle=0
A3- Write RTL for 4X1 MUX using decoder & tri-state buffer and verify the same using a test bench

Source code-

4X1 MUX-

module mux4_dec(a,b,c,d,s0,s1,en, y);

input a,b,c,d,s0,s1,en;
output y;
wire [3:0]w;

decoder2_4 d1(s0,s1,en,w);
bufif1 b1(y, a, w[0]);
bufif1 b2(y, b, w[1]);
bufif1 b3(y, c, w[2]);
bufif1 b4(y, d, w[3]);

Endmodule

Decoder-

module decoder2_4(a,b,e,y);
input a,b,e;
output [3:0]y;
assign y[0]=(~a)*(~b)*e;
assign y[1]=(~a)*(b)*e;
assign y[2]=(a)*(~b)*e;
assign y[3]=(a)*(b)*e;
Endmodule

Test bench-

module mux4_dec_tb();
reg a,b,c,d,s0,s1,e;
wire out;
integer i;
mux4_dec DUT(a,b,c,d,s0,s1,e,y);
initial begin
a=1'b1;
b=1'b0;
c=1'b1;
d=1'b0;
s0=1'b0;
s1=1'b0;
e=1'b0;
end
initial begin
for(i=0;i<8;i=i+1)
begin
{e,s0,s1}=i;
#10;
end
end
initial #100
$finish;
endmodule

Waveform:

Output:
# 0a=1,b=0.c=1,d=0,s0=0,s1=0,e=0,out=z
# 10a=1,b=0.c=1,d=0,s0=0,s1=1,e=0,out=z
# 20a=1,b=0.c=1,d=0,s0=1,s1=0,e=0,out=z
# 30a=1,b=0.c=1,d=0,s0=1,s1=1,e=0,out=z
# 40a=1,b=0.c=1,d=0,s0=0,s1=0,e=1,out=1
# 50a=1,b=0.c=1,d=0,s0=0,s1=1,e=1,out=0
# 60a=1,b=0.c=1,d=0,s0=1,s1=0,e=1,out=1
# 70a=1,b=0.c=1,d=0,s0=1,s1=1,e=1,out=0
A4- Write RTL to design bidirectional buffer and verify the same using test bench

Source code-

module bi_buffer(a,b,c);
inout a,b;
input c;
bufif1 (b,a,c);
bufif0 (a,b,c);
endmodule

Test bench-

module bi_buffer_tb();
wire a,b;
reg c;
integer i,d;

bi_buffer uut(a,b,c);

assign a= (c==1)? d:1'bz;

assign b= (c==0)? 1'bx:1'bz;

initial begin
c=1'bx;
#10;
end
initial begin

for(i=0;i<8;i=i+1)
begin
{d,c}=i;
#10;
end
end
initial
$monitor( $time,"a=%b,b=%b,c=%b",a,b,c);

Endmodule

Waveform:
Output:

# 0a=x,b=x,c=0
# 10a=0,b=0,c=1
# 20a=x,b=x,c=0
# 30a=1,b=1,c=1
# 40a=x,b=x,c=0
# 50a=0,b=0,c=1
# 60a=x,b=x,c=0
# 70a=1,b=1,c=1
 LAB 2-

Write RTL description and test bench for an arithmetic logic unit using arithmetic and logical
operations.

Source code-

module operators();
reg [3:0]a,b,c,d;
reg [3:0]e,f,g,h;
reg signed x,y,z;

initial begin
a=5;
b=9;
c=4'b1010;
d=3'bx;
x=a&&b;
y=!a;
z=a||b;
$display ($time ,"x=%b,y=%b,z=%b",x,y,z);
#10
e=a&b;
f=a^b;
g=a|b;
$display ($time ,"e=%b,f=%b,g=%b",e,f,g);

#10;
e=^a;
f=~&(a);
g=a|b;

$display ($time ,"e=%b,f=%b,g=%b",e,f,g);

#10;
end
Endmodule

Test bench-

module alu_tb();
reg [7:0]a,b;
reg [3:0]command;
reg enable;
wire [15:0]out;

integer m,n,o;

parameter ADD = 4'b0000, // Add two 8 bit numbers a and b.

INC = 4'b0001, // Increment a by 1.
SUB = 4'b0010, // Subtracts b from a.
DEC = 4'b0011, // Decrement a by 1.
MUL = 4'b0100, // Multiply 4 bit numbers a and b.
DIV = 4'b0101, // Divide a by b.
SHL = 4'b0110, // Shift a to left side by 1 bit.
SHR = 4'b0111, // Shift a to right by 1 bit.
AND = 4'b1000, // Logical AND operation
OR = 4'b1001, // Logical OR operation
INV = 4'b1010, // Logical Negation
NAND = 4'b1011, // Bitwise NAND
NOR = 4'b1100, // Bitwise NOR
XOR = 4'b1101, // Bitwise XOR
XNOR = 4'b1110, // Bitwise XNOR
BUF = 4'b1111; // BUF

reg [4*8:0]string_cmd;
alu DUT (a,b,command,enable,out);

task initialize;
begin
{a,b,command,enable} = 0;
end
endtask

task en_oe(input i);

begin
enable=i;
end
endtask

task inputs(input [7:0]j,k);

begin
a=j;
b=k;
end
endtask

task cmd (input [3:0]l);

begin
command=l;
end
endtask

task delay();
begin
#10;
end
endtask

always@(command)
begin
case(command)
ADD : string_cmd = "ADD";
INC : string_cmd = "INC";
SUB : string_cmd = "SUB";
DEC : string_cmd = "DEC";
MUL : string_cmd = "MUL";
DIV : string_cmd = "DIV";
SHL : string_cmd = "SHL";
SHR : string_cmd = "SHR";
INV : string_cmd = "INV";
AND : string_cmd = "AND";
OR : string_cmd = "OR";
NAND : string_cmd = "NAND";
NOR : string_cmd = "NOR";
XOR : string_cmd = "XOR";
XNOR : string_cmd = "XNOR";
BUF : string_cmd = "BUF";
endcase
end

initial
begin
initialize;
en_oe(1'b1);
for (m=0;m<256;m=m+17)
begin
for (n=0;n<256;n=n+19)
begin
inputs(m,n);
for (o=0;o<8;o=o+1)
begin
command=o;
delay;
end
end
end
en_oe(0);
inputs(8'd20,8'd10);
cmd(ADD);
#10;
en_oe(1);
inputs(8'd25,8'd17);
cmd(ADD);
delay;
$finish;
end

initial
$monitor("Input oe=%b, a=%b, b=%b, command=%s, Output out=%b",enable,a,b,string_cmd,out);

Endmodule
Waveform:

Output:

# Input oe=1, a=00000000, b=00000000, command= ADD, Output out=0000000000000000

# Input oe=1, a=00000000, b=00000000, command= INC, Output out=0000000000000001
# Input oe=1, a=00000000, b=00000000, command= SUB, Output out=0000000000000000
# Input oe=1, a=00000000, b=00000000, command= DEC, Output out=1111111111111111
# Input oe=1, a=00000000, b=00000000, command= MUL, Output out=0000000000000000
# Input oe=1, a=00000000, b=00000000, command= DIV, Output out=xxxxxxxxxxxxxxxx
# Input oe=1, a=00000000, b=00000000, command= SHL, Output out=0000000000000000
# Input oe=1, a=00000000, b=00000000, command= SHR, Output out=0000000000000000
# Input oe=1, a=00000000, b=00010011, command= ADD, Output out=0000000000010011
# Input oe=1, a=00000000, b=00010011, command= INC, Output out=0000000000000001
# Input oe=1, a=00000000, b=00010011, command= SUB, Output out=1111111111101101
# Input oe=1, a=00000000, b=00010011, command= DEC, Output out=1111111111111111
# Input oe=1, a=00000000, b=00010011, command= MUL, Output out=0000000000000000
# Input oe=1, a=00000000, b=00010011, command= DIV, Output out=0000000000000000
# Input oe=1, a=00000000, b=00010011, command= SHL, Output out=0000000000000000
# Input oe=1, a=00000000, b=00010011, command= SHR, Output out=0000000000000000
# Input oe=1, a=00000000, b=00100110, command= ADD, Output out=0000000000100110
# Input oe=1, a=00000000, b=00100110, command= INC, Output out=0000000000000001
# Input oe=1, a=00000000, b=00100110, command= SUB, Output out=1111111111011010
# Input oe=1, a=00000000, b=00100110, command= DEC, Output out=1111111111111111
# ** Note: $finish : C:/Users/saikr/Desktop/Verilog_labs/lab2/solution/tb/alu_tb.v(118)
E2 operators

Source code :

module operators();
reg [3:0]a,b,c,d;
reg [3:0]e,f,g,h;
reg signed x,y,z;
integer j;

initial begin
a=5;
b=4'b1011;
c=4'b1010;
d=3'bx;
x=a&&b;
y=!a;
z=a||b;
$display ($time ,"x=%b,y=%b,z=%b",x,y,z);
#10
e=a&b;
f=a^b;
g=a|b;
$display ($time ,"e=%b,f=%b,g=%b",e,f,g);

#10;
e=^a;
f=~&(a);
g=a|b;

$display ($time ,"e=%b,f=%b,g=%b",e,f,g);

#10;

$display ("initial valuesa=%b,b=%b,c=%b,d=%b",a,b,c,d);

a=a<<1;
b=b>>2;
c=c>>>1;

$display ($time ,"a=%b,b=%b,c=%b,",a,b,c);

#10;

x=(a>=b);
y=(c<=a);
$display ($time ,"x=%b,y=%b",x,y);
#10
x=(a==b);
y=(a!=b);

end
Endmodule
Output
0x=1,y=0,z=1
# 10e=0001,f=1110,g=1111
# 20e=0000,f=0001,g=1111
# initial valuesof a=0101,b=1011,c=1010,d=0xxx
# 30a=1010,b=0010,c=0101,
# 40x=1,y=1
 LAB 3-

E1- Write RTL (Behavioral) description and test bench for a 4:1 multiplexer circuit.

Source code-

module mux4_1(data,sel,out);

input [3:0]data;
input [1:0]sel;
output reg out;

always@(data,sel)
begin
case(sel)
2'b00 : out=data[0];
2'b01 : out=data[1];
2'b10 : out=data[2];
2'b11 : out=data[3];
default :out=0;
endcase
end

endmodule

Test bench-

module mux4_1_tb();

reg [3:0]d;
reg [1:0]sel;
wire y;

mux4_1 DUT(d,sel,y);
task initialize;
begin
{d,sel} = 0;
end
endtask

task stimulus(input [3:0]i,input [1:0]j);

begin
#10;
d = i;
sel = j;
end
 endtask

initial
begin
initialize;
stimulus(4'd5,2'd2);
stimulus(4'd15,2'd3);
stimulus(4'd6,2'd1);
end

initial
begin
$monitor("Values of data=%b,sel=%b,Output=%b",d,sel,y);
end

initial
begin
100 $finish;
end

endmodule

Output:

# Values of data=0000,sel=00,Output=0
# Values of data=0101,sel=10,Output=1
# Values of data=1111,sel=11,Output=1
# Values of data=0110,sel=01,Output=1
# ** Note: $finish
# Time: 100 ps Iteration: 0 Instance: /mux4_1_tb
E2- Write RTL description and test bench for 3:8 decoder

Source code-

module decoder3_8(data,en,out);

input [2:0]data;
input en;
output reg [7:0]out;

always@(data)
begin
if(en)
begin
case(data)
3'b000 : out=8'b00000001;
3'b001 : out=8'b00000010;
3'b010 : out=8'b00000100;
3'b011 : out=8'b00001000;
3'b100 : out=8'b00010000;
3'b101 : out=8'b00100000;
3'b110 : out=8'b01000000;
3'b111 : out=8'b10000000;
default : out=8'b00000000;

endcase
end

else

out=8'bzzzzzzzz;

end

endmodule

Test bench-

module decoder3_8_tb();
reg [2:0]data;
reg en;
wire [7:0]out;
integer a;
 decoder3_8 uut(data,en,out);

task initialize ;
begin
{en,data}=0;
end
endtask

task inputs(input [2:0]i);

begin
#10;

data=i;
end
endtask

initial
begin
#10;
en=1'b1;
end

initial
begin

initialize;

inputs(3'b000);
inputs(3'b001);
inputs(3'b010);
inputs(3'b011);
inputs(3'b100);
inputs(3'b101);
inputs(3'b110);
inputs(3'b111);
inputs(3'b000);

end
initial
$monitor ($time ," data =%b,en=%b,output=%b",data,en,out);

Endmodule
Output :

# 0 data =000,en=0,output=zzzzzzzz
# 10 data =000,en=1,output=zzzzzzzz
# 20 data =001,en=1,output=00000010
# 30 data =010,en=1,output=00000100
# 40 data =011,en=1,output=00001000
# 50 data =100,en=1,output=00010000
# 60 data =101,en=1,output=00100000
# 70 data =110,en=1,output=01000000
# 80 data =111,en=1,output=10000000
# 90 data =000,en=1,output=00000001
E3- Write RTL description and test bench for 8:3 priority encoder

Source code-

module priority8_3(data ,en,out);

input [7:0]data;
input en;
output reg [2:0]out ;

always@(data,en)
begin
if (en==1'b1)

casex(data)
8'b00000000 :out=3'bxxx;
8'b00000001 :out=3'b000;
8'b0000001x :out=3'b001;
8'b000001xx :out=3'b010;
8'b00001xxx :out=3'b011;
8'b0001xxxx :out=3'b100;
8'b001xxxxx :out=3'b101;
8'b01xxxxxx :out=3'b110;
8'b1xxxxxxx :out=3'b111;
default :out=3'b000;

endcase
end

endmodule

Test bench-

module priority8_3_tb();

reg [7:0]data;
reg en;
wire [2:0]out;
integer a;

priority8_3 dut(data ,en,out);

task initialize;
begin
{data,en}=0;
end
endtask

task inputs(input [7:0]i);

begin
data=i;
#10;
end
endtask
task enable(input j);
begin
en=j;
end
endtask

initial
begin

initialize;
enable(1'b1);

for (a=0;a<256;a=a+1)
begin
inputs(a);
end
end

initial
$monitor ($time ," data=%b, en=%b,output=%b",data,en,out);

initial
begin
#250 $finish;
end

endmodule

Output:
 0 data=00000000, en=1,output=xxx
# 10 data=00000001, en=1,output=000
# 20 data=00000010, en=1,output=001
# 30 data=00000011, en=1,output=001
# 40 data=00000100, en=1,output=010
# 50 data=00000101, en=1,output=010
# 60 data=00000110, en=1,output=010
# 70 data=00000111, en=1,output=010
# 80 data=00001000, en=1,output=011
# 90 data=00001001, en=1,output=011
# 100 data=00001010, en=1,output=011
# 110 data=00001011, en=1,output=011
# 120 data=00001100, en=1,output=011
# 130 data=00001101, en=1,output=011
# 140 data=00001110, en=1,output=011
# 150 data=00001111, en=1,output=011
# 160 data=00010000, en=1,output=100
# 170 data=00010001, en=1,output=100
# 180 data=00010010, en=1,output=100
# 190 data=00010011, en=1,output=100
# 200 data=00010100, en=1,output=100
# 210 data=00010101, en=1,output=100
# 220 data=00010110, en=1,output=100
# 230 data=00010111, en=1,output=100
# 240 data=00011000, en=1,output=100