NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 6: BEHAVIORAL MODELING

Lecturer: Ho Ngoc Diem

Agenda
 Chapter 1: Introduction
 Chapter 2: Modules and hierarchical structure
 Chapter 3: Fundamental concepts
 Chapter 4: Structural modeling (Gate & Switch-level modeling)
 Chapter 5: Dataflow modeling
 Chapter 6: Behavioral modeling
 Chapter 7: Tasks and Functions
 Chapter 8: State machines
 Chapter 9: Testbench and verification
 Chapter 10: VHDL introduction

UIT Circuit Design with HDL - Chapter 6 2

 Verilog model for hardware design
Verilog design
RTL Design

Gate/Switch level modeling Dataflow modeling Behavioral modeling

- Primitive switch, gate -Continuous assignment - Procedural assignment

- User defined primitive (assign) - initial, always block
- Expression (operators) - Conditional statement…

 There are different ways of modeling a hardware design. Choose an

appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling as a separate modeling
type.

UIT Circuit Design with HDL - Chapter 6 3

Content
PART A: Behavioral modeling description (discussed today!)
 Behavioral model overview
 initial & always construct
 Procedural assignment
 Blocking and non-blocking assignment
 Sequential and Parallel blocks
 Timing control mechanism in Verilog
 Conditional, Case, Loop Statements
 Practical examples
PART B: Modeling techniques
………
UIT Circuit Design with HDL - Chapter 6 4
Behavioral model
 What is Behavioral model ?
– More like a procedure in a programming language, but NOT.
– Program describes input/output behavior of circuit, tell what
you want to have happen, NOT what gates to connect to make
it happen.
– Describe what a component does, not how it does
– Many structural models could have the same behavior
(different implementations of one expression)
– Synthesized into a circuit that has this behavior
– Result is only as good as the tools

UIT Circuit Design with HDL - Chapter 6 5

Behavioral model
 Why behavioral model?
– Good for more abstract models of circuits
– Easier to write
– More flexible
– Provide sequencing
– A much easier way to write testbenches
– Allow both model and the testbench to be described together

UIT Circuit Design with HDL - Chapter 6 6

Initial & Always
 Two basic components of behavioral
modeling: initial, always construct.
 Each initial and always construct starts
a separate activity flow in Verilog.
 initial and always can not be nested.
 In the code: initial and always start
together at simulation time 0, initial
executes once, always executes
repetitively.
 They contain behavioral statements
like: if…else, case, loop statements.

UIT Circuit Design with HDL - Chapter 6 7

Initial
 Variable and Net can be initialized when they are declared
module adder (sum, co, a, b, ci);

output reg [7:0] sum = 0; //Initialize 8 bit output sum

output reg co = 0; //Initialize 1 bit output co
input [7:0] a, b;
input ci;
…..
endmodule

module adder (output reg [7:0] sum = 0,

output reg co = 0,
input [7:0] a, b,
input ci );
//it is illegal to redeclare any ports of the module
//in the body of the module
…
endmodule

UIT Circuit Design with HDL - Chapter 6 8

Always
 always may be followed by timing control expression (@, #,
wait -> see later)
 Statement following always is executed repeatedly until
simulation stops. $stop or $finish to halt the simulation
module clock_gen (output reg clock);
//Initialize clock at time zero
initial
clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always
#10 clock = ~clock;
initial
#1000 $finish;
endmodule

UIT Circuit Design with HDL - Chapter 6 9

 Procedural Assignment
 Assign value to variable data types
Left-hand side Right-hand side
- reg, integer, time, real, realtime Net, variable, function
- Bit-select, part-select of reg, integer, time call (Any expression that
- Memory word evaluates a value)
- Concatenation of any of the above
 Occur in procedures: initial, always, task, and function
 Being thought of as “triggered” assignment
 Variable hold value until the next assignment
Examples: reg[3:0] a = 4'h4;
//This is equivalent to writing
reg[3:0] a;
initial a = 4'h4;

UIT Circuit Design with HDL - Chapter 6 10

Procedural assignment
 Difference between Continuous and Procedural assignment:

- Continuous assignments drive nets and are evaluated and

updated whenever an input operand changes value.
- Procedural assignments update the value of variables
under the control of the procedural flow constructs that
surround them

UIT Circuit Design with HDL - Chapter 6 11

Procedural assignment
 2 types of procedural assignment:
blocking and non-blocking procedural assignment
-> specify different flow in a sequential block
Blocking procedural assignment
a_sig = b_sig;
Procedural Execution of the next line is blocked
assignment until this assignment is done.

Nonblocking procedural assignment

Assignment is done a_sig <= b_sig;
depending on Execution of the next line is not
procedure. blocked by this line

UIT Circuit Design with HDL - Chapter 6 12

Procedural assignment
 Example

UIT Circuit Design with HDL - Chapter 6 13

Procedural assignment
 Blocking procedural assignment: generally used to describe
the combinational logic.
 Nonblocking procedural assignment: generally used to
described the sequential logic.
 Blocking assignment: is executed before the execution of
other statements that follow it in sequential block, but can
not prevent other statements in parallel block
o begin…end: sequential block
o fork……join: parallel block

UIT Circuit Design with HDL - Chapter 6 14

Procedural assignment
 The order of the execution of distinct non-blocking
assignments to a given variable shall be preserved

UIT Circuit Design with HDL - Chapter 6 15

 Procedural assignment
 Continuous assignment: assign values to nets
 Procedural assignment: assign values to variables
 Two additional forms: assign/deassign and force/release
-> Procedural continuous assignment

assign a = b force a = b
Left-hand • Variable, •Variable, Net,
side • Concatenation of variable • Concatenation of
• Memory word any of above.
• Bit-select, part-select of variable • Memory word
• Bit-select, part-
select of variable

UIT Circuit Design with HDL - Chapter 6 16

 Procedural assignment
 assign/deassign and force/release statement
-> are procedural statements that allow expression to be driven
continuously onto variables or net
-> Override all procedural assignments

assign – deassign
->apply to variables

UIT Circuit Design with HDL - Chapter 6 17

 Procedural assignment
 force statement : override
statements below until release
happens:
o assign (procedural continuous
assignment)
o gate output, module outputs,
& assign (continuous assignment)

Result:
force – release 0 d=0,e=0
-> apply to net and variable 10 d=1,e=1
20 d=0,e=0

UIT Circuit Design with HDL - Chapter 6 18

Sequential & Parallel block
 In structured procedure, if there are more than one
statement to execute, they must be grouped in one block.
 “begin…end”: sequential block, statements are executed in
serial, in the order they are written
 “fork…join”: parallel block, statements are executed
concurrently

UIT Circuit Design with HDL - Chapter 6 19

Sequential & Parallel block
 Sequential block

 Parallel block

UIT Circuit Design with HDL - Chapter 6 20

 Sequential &Parallel block
 Nested blocks: Sequential and Parallel block can be embedded
within each other. begin
fork
@Aevent;
@Bevent;
join
areg = breg;
end

 Named blocks: If a block is named,

- local variable, parameter can be declared for the clock
- the execution of the block can be disabled from anywhere in the
design.
- named blocks can be referenced by hierarchical names.

UIT Circuit Design with HDL - Chapter 6 21

 Sequential &Parallel block
 Named blocks
//Example: Find the first bit with a value 1 in flag
reg [15:0] flag;
integer i; //integer to keep count
initial
begin
flag = 16'b 0010_0000_0000_0000;
i = 0;
begin: block1 //The main block inside while is named block1
while(i < 16)
begin
if (flag[i])
disable block1; //disable block1 because you found true bit.
i = i + 1;
end
end
end

UIT Circuit Design with HDL - Chapter 6 22

Statements
 Conditional statement
if-else-if

UIT Circuit Design with HDL - Chapter 6 23

Statements
 Case statement
case (op)
2’b00: y = a + b; case :compare each bit
2’b01: y = a – b; casez :treat z or ? as do-not-care value
2’b10: y = a ^ b; (? is a shorthand for z)
default: y = ‘hxxxx; casex :treat x ,z,? as do-not-care value
endcase

What is the result if r = 8'b01100110?

UIT Circuit Design with HDL - Chapter 6 24
 Statements
 Loop statement: forever, repeat, while, for
Control the execution of a statement zero, one, or more times

 Forever, repeat, while: In many cases, these are not

synthesizable or there may be heavy tool dependency.
Therefore, avoid using these statements in a synthesizable
code.

UIT Circuit Design with HDL - Chapter 6 25

Statement
 For (var_assign; expression; var_assign) statement
//an increasing sequence of values on an output
reg [3:0] i, output;

for ( i = 0 ; i <= 15 ; i = i + 1 ) begin

output = i;
#10;
end

• If loop instructions are used in a module which has to be

synthesized, care must be taken.
• Be aware what structure will be generated with loop
instructions. (They are different from C programing language.)

UIT Circuit Design with HDL - Chapter 6 26

Statements
 while (expression) statement:
execute statement while expression is true

-> Count the number of

logic 1 values in reg a

UIT Circuit Design with HDL - Chapter 6 27

Statements
 repeat (expression) statement:
execute statement a fixed number of times

-> Implement
a multiplier

UIT Circuit Design with HDL - Chapter 6 28

Statements
 forever statement: execute statement forever
Example 1: Clock generation , use forever loop instead of always block
reg clock;
initial begin
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
end

Example 2: Synchronize two register values at every positive edge of lock

reg clock;
reg x, y;
initial
forever @(posedge clock) x = y;

UIT Circuit Design with HDL - Chapter 6 29

 Procedural timing control
 How does the behavioral model advance time?
 Delay control #: delay a specific amount of time
 Event control @: delay until an event occurs (“posedge”,
“negedge”, or any change)
- edge-sensitive timing control
 Statement wait: delay until an event occur
- level-sensitive timing control
 In Verilog, if there are no timing control statements, the
simulation time does not advance.

UIT Circuit Design with HDL - Chapter 6 30

Procedural timing control
 Examples
//delay-based timing control
#10 rega = a+b;
reg a = #10 a+b; //intra-assignment delay

//event-based timing control

• @(clock) q = d; //q = d is executed whenever signal clock changes value
• @(posedge clk) q=d;
• q = @(posedge clock) d;
• @(a, b, c) y = (a & b) | (b & c) | (a & c); //equivalent @(a or b or c)
• @(*) // or @*, equivalent to @ (a or b or c or d or f)
y = (a & b) | (c & d) | myfunction(f);

//wait control
wait(!enable) #10 a = b;

UIT Circuit Design with HDL - Chapter 6 31

Procedural timing control
waiting for signal in the
 Using with always statement: sensitivity list change.
always @ (………..)
always begin
begin

sensitive list

end end
always creates By adding “@ ( )” to always statement: means
an infinite loop “wait for change of signals listed in the sensitivity
list” and when the change takes place, sequential
block ( from begin to end ) is executed.
UIT Circuit Design with HDL - Chapter 6 32
Procedural timing control
 Using with always statement:
negedge: transition from 1 to x, z, or 0,
always @ (………..) and from x or z to 0
posedge: transition from 0 to x, z, or 1,
begin sensitive list and from x or z to 1

description timing
always @ ( posedge clk ) when signal clk rises

always @ ( negedge rst_n ) when signal rst_n falls

always @ ( a or b ) when signal a or b change

end
Do not mix single-edge
(posedge / negedge) and
double-edge event in an always @ ( a or posedge clk )
event control.
UIT Circuit Design with HDL - Chapter 6 33
Procedural timing control
 Examples
fork
begin: event_expr
@ev1; //named-event
repeat(3) @trig;
#d action (areg, breg);
end
@reset disable event_expr;
join

• The event_expr block waits for one occurrence of event ev1 and
three occurrences of event trig; plus a delay of d time units, the task
action executes.
• When event reset occurs, regardless of events within the sequential
block, the fork-join block terminates
UIT Circuit Design with HDL - Chapter 6 34
Examples
 4 to 1 mux module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;
//output declared as register
reg out;

//All input signals that cause a recomputation of out to

//occur must go into the always @(...) sensitivity list.
always @(s1 or s0 or i0 or i1 or i2 or i3) begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule

UIT Circuit Design with HDL - Chapter 6 35

Examples
 4-bit counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)

begin
if (clear)
Q <= 4'd0; //Nonblocking assignments are recommended
//for creating sequential logic such as flipflops
else
Q <= Q + 1; // Modulo 16 is not necessary because Q is a
// 4-bit value and wraps around.
end
endmodule

UIT Circuit Design with HDL - Chapter 6 36

 Summary
 Behavioral model describes a circuit in terms of the algorithm
it implements
 initial & always: two basic structures in behavioral modeling
 Procedural assignment: assign value to variables
 3 ways of timing control in Verilog:
- Delay-based
- Event-based (edge-sensitive)
- Wait statement (level-sensitive)

UIT Circuit Design with HDL - Chapter 6 37

 Summary
 All procedures in Verilog HDL are specified within one of these
statement:
- initial construct
- always construct
- Task
- Function
(next chapter will discuss Task & function)

UIT Circuit Design with HDL - Chapter 6 38

 Part B:
Some modeling techniques

UIT Circuit Design with HDL - Chapter 6 39

 Logic synthesis
 RTL coding -> Simulation (Functional) -> Synthesis
 An important concern of any designer: translate his or her
code into hardware
 It’s not ensure that what the designer gets after synthesis is
what has been verified by (functional) simulation; or his/her
RTL code is ok for simulation, but non-synthesizable (unable
to implement on hardware)
 What RTL code are synthesizable? Depends on:
- coding style
- standard cell library (tool dependable): and, or, not, adder, mux,
memory, flip-flop…
- target hardware

UIT Circuit Design with HDL - Chapter 6 40

 Logic synthesis
 Non-synthesizable verilog construct

UIT Circuit Design with HDL - Chapter 6 41

Blocking vs. Nonblocking assignment

 Blocking procedural assignment: generally used to

describe the combinational logic.
 Nonblocking procedural assignment: generally used
to described the sequential logic.

UIT Circuit Design with HDL - Chapter 6 42

 Race condition
 The term, race condition, originates with the idea of two
signals racing each other to influence the output first.

- Feedback oscillator with

blocking assignments
- Race condition can occur

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 43

Race condition

- Feedback oscillator with

nonblocking assignments

* From a users perspective, the execution of these two

nonblocking statements happen in parallel.
Ref: Clifford E. Cummings
UIT Circuit Design with HDL - Chapter 6 44
 Coding guidelines
 Guideline 1: When modeling sequential logic, use
nonblocking assignments.
 Simple sequential verilog code:

Using blocking assignment – it works here! It’s better to use nonblocking assignment.
But more complex sequential always blocks,
will exhibit the race condition.
Ref: Clifford E. Cummings
UIT Circuit Design with HDL - Chapter 6 45
Coding guidelines
 Guideline 2: When modeling combinational logic with an
always block, use blocking assignments

Bad combinational logic coding style using

nonblocking assignments

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 46

 Coding guidelines
 Guideline 2 (cont’d)

Inefficient multi-pass combinational logic coding style with nonblocking assignments.

Degrade simulation performance

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 47
 Coding guidelines
 Guideline 2 (cont’d):

Efficient combinational logic coding style using

blocking assignments

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 48

 Coding guidelines
 Guideline 3: When modeling both sequential and combinational
logic within the same always block, use nonblocking assignments

equivalent:

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 49
Coding guidelines
 Guideline 4: Do not mix blocking and nonblocking
assignments in the same always block

-> Simulate and synthesis is ok, but discourage this coding style
Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 50

Coding guidelines
 Guideline 4 (cont’d)

-> Synopsis report a syntax error.

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 51

 Coding guidelines
 Guideline 4 (cont’d) Do not mix!!!
reg wk1, wk2, wk3, wk4, y;
Synthesis tool may report error.
begin
a a1 a2 a3 a4 a5 a6 This simulation
wk1 = a;
(1)
wk2 <= wk1; wk1 a1 a2 a3 a4 a5 a6 result shows the
(2) latches in the logic.
wk3 = wk2; wk2 a1 a2 a3 a4 a5 a6
(3) a1 a2 a3 a4 a5 Some synthesis
wk4 <= wk3; wk3 x
tools may not
y = wk4;
wk4 x a1 a2 a3 a4 a5
create a latch.
end y x x a1 a2 a3 a4
Because execution of (2)
3rd time
is blocked by (1), and the 2nd time
evaluation of (3)’s right- 1st time
hand side is not blocked wk1 wk2 wk3 wk4
by (2), wk3 becomes a
unknown (x)

UIT Circuit Design with HDL - Chapter 6 52

 Coding guidelines
 Guideline 5: Do not make assignments to the same
variable from more than one always block.

-> Race condition coding style using nonblocking assignments

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 53

 Coding guidelines
 When modeling sequential logic, use nonblocking assignments.
 When modeling combinational logic with an always block, use
blocking assignments.
 When modeling both sequential and combinational logic within
the same always block, use nonblocking assignments.
 Do not mix blocking and nonblocking assignments in the same
always block.
 Do not make assignments to the same variable from more than
one always block.

Ref: Clifford E. Cummings

UIT Circuit Design with HDL - Chapter 6 54

Model combinational logic
 Using procedural assignment

UIT Circuit Design with HDL - Chapter 6 55

Model combinational logic

UIT Circuit Design with HDL - Chapter 6 56

Model combinational logic

UIT Circuit Design with HDL - Chapter 6 57

Model combinational logic

UIT Circuit Design with HDL - Chapter 6 58

 Model combinational logic
 Using @ to model combinational logic
reg a, b, c, d, y;
reg wk1, wk2;
This will create logic shown
always @ ( a or b or c or d or wk1 or wk2 ) below
begin
wk1 <= a | b; a
wk1
wk2 <= c & d; b
y
y <= wk1 ^ wk2;
end
c
d wk2
equivalent
always @ ( a or b or c or d ) Synthesis tool may create above gate even if we
missed wk1 and wk2 in a sensitivity list, however do
begin
not omit them. If omitted, the result of RTL simulation
y <= (a | b) ^ (c & d); may be different from the result of gate level
end simulation.
UIT Circuit Design with HDL - Chapter 6 59
 Model combinational logic a
wk1
b
 Using @ to model combinational logic y
c
To generate combinational logic as shown on the
d wk
right, Style 1 is recommended compared to Style 2
because of the simulation efficiency. 2
Style 2
Style 1
reg a, b, c, d, y;
reg a, b, c, d, y; reg wk1, wk2;
multiple passes
reg wk1, wk2;
always @ ( a or b or c or d or wk1 or wk2 )
always @ ( a or b or c or d ) begin
begin wk1 <= a | b;
wk1 = a | b; wk2 <= c & d;
wk2 = c & d; y <= wk1 ^ wk2;
y = wk1 ^ wk2; end
end
Always statement is executed whenever wk1 or wk2
change their values, causing slow simulation time.
4/15/2
60 013
Model combinational logic
 Using @ to model combinational logic
Best style
always @ not recommended style
*
begin always @ ( a or b or c or d or wk1 or wk2)
wk1 = a | b; begin
wk2 = c & d; wk1 <= a | b;
y = wk1 ^ wk2; wk2 <= c & d;
end y <= wk1 ^ wk2;
Acceptable style end
Wrong / buggy style
always @ ( a or b or c or d )
begin always @ ( a or b or c or d)
wk1 = a | b; begin
wk2 = c & d; wk1 <= a | b;
y = wk1 ^ wk2; wk2 <= c & d;
end y <= wk1 ^ wk2;
end 4/15/2
61 013
Coding guidelines
always @( event-expression )
begin
statements
end
 If event-expression contains posedge or negedge, flip-flop
(register) will be synthesized.
 A variable assigned within an always @ block that is not
fully specified will result in latches synthesized.
 In all other cases, combinational logic will be synthesized.

UIT Circuit Design with HDL - Chapter 6 62

Model sequential logic
Some points:
 Most often modeled with always block
 Verilog code in initial block can not be synthesized
 Using @ construct
– Sensitivity list contains clock edge
– Reset optional.
– Output changes synchronised to clock edge:
Use <= assignments

UIT Circuit Design with HDL - Chapter 6 63

Model sequential logic
 Latch
 Flip-flop
 Register
 Counter
 Timing generator
 …..

UIT Circuit Design with HDL - Chapter 6 64

Model sequential logic
 How would you model D latch and D flip-flop?
- asynchronous reset D-type flip-flop
- synchronous reset D type flip-flop
- D latch

UIT Circuit Design with HDL - Chapter 6 65

 Model sequential logic
 How would you model a D flip-flop and D latch?
// asynchronous reset D-type flip-flop // synchronous reset D-type flip-flop
module DFF_async_reset (clk, reset_n, d, q); module DFF_sync_reset (clk, reset, d, q);
input clk, reset_n, d; input clk, reset, d;
output reg q; output reg q;
always @(posedge clk or negedge reset_n) always @(posedge clk)
if (!reset_n) q <= 0; if (reset) q <= 0;
else q <= d; else q <= d;
endmodule endmodule
module D_latch (enable, d, q); //D latch
input enable, d;
output reg q;
always @(enable or data)
if (enable) q <= data;
endmodule
UIT Circuit Design with HDL - Chapter 6 66
Model sequential logic
 Data register
// an n-bit data register
module register(clk, din, qout);
parameter N = 4; // number of bits
input [N-1:0] din;
output reg [N-1:0] qout;
always @(posedge clk) qout <= din;
endmodule

UIT Circuit Design with HDL - Chapter 6 67

Model sequential logic
 Data register

// an N-bit data register with synchronous load and

// asynchronous reset
parameter N = 4; // number of bits
input clk, load, reset_n;
input [N-1:0] din;
output reg [N-1:0] qout;
always @(posedge clk or negedge reset_n)
if (!reset_n) qout <= {N{1'b0}};
else if(load) qout <= din;

UIT Circuit Design with HDL - Chapter 6 68

Coding guidelines
always @( event-expression )
begin
statements
end
 If event-expression contains posedge or negedge, flip-flop
(register) will be synthesized.
 A variable assigned within an always @ block that is not
fully specified will result in latches synthesized.
 In all other cases, combinational logic will be synthesized.

UIT Circuit Design with HDL - Chapter 6 69

 Synthesizable coding
 Always keep in mind what sort of implementation your design
could map to. If you don’t know, chances are synthesis doesn’t
either.
- No case statements without default case
- No if statements without an else case
- If you assign to a net in one case it must be assigned to in all cases (no
implicit storage)
 Limited loops
 No initial blocks
 Limited operators
- + and – are the only arithmetic operators allowed
- Try to avoid relational operators (>, ==) in favor of simpler logic
 Use assign statements when possible

70
Summary
 Suggested coding guidelines
 Modeling Combinational Circuit
 Modeling Sequential Circuit
 Synthesizable coding

UIT Circuit Design with HDL - Chapter 6 71