EXAMEN PRACTICO

JOEL FLORES JANCO

1. A

entity fd is

Port (

A0: in STD_LOGIC ;

B0: in STD_LOGIC

);

end fd;

architecture Behavioral of fd is

component and2_1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end component and2_1;

component fjk is

Port ( J:in STD_LOGIC;

K:in STD_LOGIC;

CLOCK: in STD_LOGIC;

Q: out STD_LOGIC;

QB: out STD_LOGIC);

end component fjk;

component not1_1 is

Port ( a : in STD_LOGIC;

z : out STD_LOGIC);

end component not1_1;

component or2_1 is

Port ( b : in STD_LOGIC;
 qq : in STD_LOGIC;

k : out STD_LOGIC);

end component or2_1;

signal temp: std_logic;

signal temp1: std_logic;

signal temp2: std_logic;

signal temp3: std_logic;

signal temp4: std_logic;

begin

uut: not1_1 port map(a=>A0,z=>temp);

uut1: and2_1 port map(a=>temp,b=>temp1,c=>temp2);

uut2: or2_1 port map(b=>B0,qq=>temp3,k=>temp4);

uut3: fjk port map(J=>temp2,K=>temp4,Q=>temp1,QB=>temp3,CLOCK=>'0');

end Behavioral;

CODIGO DEL FLIP FLOP JK

entity fjk is

Port ( J:in STD_LOGIC;

K:in STD_LOGIC;

CLOCK: in STD_LOGIC;

Q: out STD_LOGIC;

QB: out STD_LOGIC);

end fjk;

architecture Behavioral of fjk is

begin

PROCESS(CLOCK)

variable TMP: std_logic;

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(J='0' and K='0')then

TMP:=TMP;

elsif(J='1' and K='1')then

TMP:= not TMP;

elsif(J='0' and K='1')then

TMP:='0';

else

TMP:='1';

end if;

end if;

Q<=TMP;

Q <=not TMP;

end PROCESS;

end Behavioral;
1. B

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity rs is

Port(A0 : in STD_LOGIC;

B0 : in STD_LOGIC;

C0 : out STD_LOGIC;

D0 : out STD_LOGIC

);
end rs;

architecture Behavioral of rs is

component ffsr is

PORT( S,R,CLOCK: in std_logic;

Q, QBAR: out std_logic);

end component ffsr;

component nor2_1 is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end component nor2_1;

signal temp: std_logic;

begin

uut: nor2_1 port map(a=>A0,b=>B0,c=>temp);

uut1: ffsr port map(S=>temp,R=>A0,CLOCK=> '0',Q=>C0,QBAR=>D0);

end Behavioral;

CODIGO DEL FLIP FLOP RS

entity ffsr is

PORT( S,R,CLOCK: in std_logic;

Q, QBAR: out std_logic);

end ffsr;

architecture Behavioral of ffsr is

begin
PROCESS(CLOCK)

variable tmp: std_logic;

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(S='0' and R='0')then

tmp:=tmp;

elsif(S='1' and R='1')then

tmp:='Z';

elsif(S='0' and R='1')then

tmp:='0';

else

tmp:='1';

end if;

end if;

Q <= tmp;

QBAR <= not tmp;

end PROCESS;

end Behavioral;
 SIMULACION

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity TB is

end TB;

architecture Testbench of TBis

component rs

port( A : in std_logic;

B : in std_logic;

CLK: in std_logic;

Q : inout std_logic;

Qneg: inout std_logic);

end component;
signal A: std_logic:='0';

signal B: std_logic:='0';

signal CLK: std_logic:='0';

signal Q,Qneg: std_logic;

begin

UUT: rs port map (A=>A,B=>B,CLK=>CLK,Q=>Q,QBAR=>QBAR);

process

begin

wait for 100ns;

CLK<='1';

A<= '0';

B<= '0';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK <= '1';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK<='1';

A<= '0';

B<= '1';

wait for 50ns;

CLK<= '0';
wait for 50 ns;

CLK <= '1';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK<='1';

A<= '1';

B<= '0';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK <= '1';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK<='1';

A<= '1';

B<= '1';

wait for 50ns;

CLK<= '0';

wait for 50 ns;

CLK <= '1';

wait for 50ns;

CLK<= '0';

end process;
end Testbench;

2. A

f(x,y,z)=Σ(1,2,3,4)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mx is

port (

in : in std_logic_vector(2 downto 0);

E: in std_logic;

salida : out std_logic);

end mx;

architecture Behavioral of mux is

begin

process (in,E)

begin

if E= '1' then
 case i is

when "001" => salida <= '1';

when "010" => salida <= '1';

when "011" => salida <= '1';

when "100" => salida <= '1';

when others => salida <= '0';

end case;

else salida <= '0';

end if;

end process;

end Behavioral;

SIMULACION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
end mux;
architecture testbench of mux is
component mux
port (
i : in std_logic_vector(2 downto 0);
e : in std_logic;
salida : out std_logic);
 end component;
signal in : std_logic_vector (2 downto 0) := (others => '0');
signal E : std_logic;
signal salida : std_logic;
begin
uut : mux port map(in=>in,E=>E,salida=>salida);
process
begin
e <= '1';
i<="000";
wait for 10ns;
i<="001";
wait for 10ns;
i<="010";
wait for 10ns;
i<="011";
wait for 10ns;
i<="100";
wait for 10ns;
i<="101";
wait for 10ns;
i<="110";
wait for 10ns;
i<="111";
wait for 10ns;
end process;
end testbench;

B.

f(x,y,z)=Σ(2,3,5,7)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
port (
i : in std_logic_vector(2 downto 0);
e : in std_logic;
salida : out std_logic);
end mux;

architecture Behavioral of mux is

begin
process (i,e)
begin
 if e = '1' then
case i is
when "0010" => salida <= '1';
when "0011" => salida <= '1';
when "0101" => salida <= '1';
when "0111" => salida <= '1';
when others => salida <= '0';
end case;
else salida <= '0';
end if;
end process;

end Behavioral;

SIMULACION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity firstTB is
end firstTB;
architecture testbench of firstTB is
component first
port (
i : in std_logic_vector(2 downto 0);
e : in std_logic;
salida : out std_logic);
end component;
signal i : std_logic_vector (2 downto 0) := (others => '0');
signal e : std_logic;
signal salida : std_logic;
begin
uut : first port map(i=>i,e=>e,salida=>salida);
 process
begin
e <= '1';
i<="000";
wait for 50ns;
i<="001";
wait for 50ns;
i<="010";
wait for 50ns;
i<="011";
wait for 50ns;
i<="100";
wait for 50ns;
i<="101";
wait for 50ns;
i<="110";
wait for 50ns;
i<="111";
wait for 50ns;
end process;
end testbench;

C.

f(x,y,z)=Σ(3,4)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux is
port (
i : in std_logic_vector(2 downto 0);
e : in std_logic;
salida : out std_logic);
end mux;

architecture Behavioral of mux is

begin
process (i,e)
begin
if e = '1' then
case i is
when "0011" => salida <= '1';
 when "0100" => salida <= '1';
when others => salida <= '0';
end case;
else salida <= '0';
end if;
end process;
end Behavioral;

3. a
library IEEE;
use IEEE.std_logic_1164.all;

entity flipFlopD is
port (
status, notStatus : out std_logic;
clock, d : in std_logic
);
end entity;

architecture arch_flipFlopD of flipFlopD is

signal internalQ : std_logic;

begin

status <= internalQ;

notStatus <= not internalQ;

main_process : process (clock)

begin
 if rising_edge (clock) then
report "Procesando tic tac.. clock=" & std_logic'image(clock);
report " d=" & std_logic'image(d);

internalQ <= d;

end if;
report " internalQ=" & std_logic'image(internalQ);

end process;
SIMULACION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simulacion is
-- Port ( );
end simulacion;

architecture Behavioral of simulacion is

component circ
port (
d: in std_logic;
clk : in std_logic;
q: out std_logic

);
end component ;
signal d: std_logic := '0';
signal clk: std_logic :='0';
signal q: std_logic ;
constant clk_period: time:= 10 ns;
begin
UUT: circ port map (d,clk,q);
clock_process: process
begin
clk<='0';
wait for clk_period/2;
clk <='1';
wait for clk_period/2;
end process;

stim_proc: process
begin
wait for clk_period*10;
 d<='0';
wait for 100 ns;
d<='1';
wait for 200 ns;
d<= '0';
wait for 50 ns;
d<= '1';
wait;
end process;

end Behavioral

FLIP FLOP SR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ff_reset is
port(
clk, reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end d_ff_reset;

architecture arch_dffreset of d_ff_reset is

begin
process(clk,reset)--tanto un cambio en clk como reset disparan el proceso
 begin
if (reset='1') then -- el reset tiene prioridad al ser asíncrono
q<='0';
elsif (clk'event and clk='1') then-- si no existe un reset y el cambio de clk=1
q<=d;-- funcionamiento normal del ffd
end if;
end process;
end arch_dffreset;

4. A
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux1 is
Port ( A0 : in STD_LOGIC;
B0 : in STD_LOGIC;
C0 : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC);
end demux1;
architecture Behavioral of demux1 is
component Not1 is
Port ( x : in STD_LOGIC;
y : out STD_LOGIC);
end component Not1;
component not2 is
Port ( x1 : in STD_LOGIC;
y1 : out STD_LOGIC);
end component not2;
component not3 is
Port ( x2 : in STD_LOGIC;
y2 : out STD_LOGIC);
end component not3;
component and2_1 is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
c1 : out STD_LOGIC);
end component and2_1;
component and3_1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
z : out STD_LOGIC);
end component and3_1;
component or2_1 is
Port ( x3 : in STD_LOGIC;
y3 : in STD_LOGIC;
z3 : out STD_LOGIC);
end component or2_1;
component dm is
port(

F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);

end component dm;

signal temp: std_logic;
signal temp1: std_logic;
signal temp2: std_logic;
signal temp3: std_logic;
signal temp4: std_logic;
signal temp5: std_logic;
begin
uut: Not1 port map(x=>A0,y=>temp);
uut1: not2 port map(x1=>B0,y1=>temp1);
uut2: not3 port map(x2=>C0,y2=>temp2);
uut3: and2_1 port map(a1=>temp,b1=>C0,c1=>temp3);
uut4: and3_1 port map(a=>A0,b=>temp1,c=>temp2, z=>temp4);
uut5: or2_1 port map(x3=>temp3,y3=>temp4,z3=>temp5);
uut6: dm port map(F=>temp5,S0=>B0,S1=>C0,A=>Q0,B=>Q1,C=>Q2,D=>Q3);
end Behavioral;
CODIGO DEL DEMUX
entity dm is
port(

F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);

end dm;

architecture Behavioral of dm is

begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;
else
D <= F;
end if;

end process;

end Behavioral;
 SIMULACION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux_tb is
-- Port ( );
end demux_tb;

architecture Behavioral of demux_tb is

component demux1 is
Port ( A0 : in STD_LOGIC;
B0 : in STD_LOGIC;
C0 : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC);
end component demux1;
signal A0: std_logic:='0';
signal B0: std_logic:='0';
signal C0: std_logic:='0';
signal Q0: std_logic:='0';
signal Q1: std_logic:='0';
signal Q2: std_logic:='0';
signal Q3: std_logic:='0';
begin
uut:demux1 port map (A0=>A0,B0=>B0,C0=>C0,Q0=>Q0,Q1=>Q1,Q2=>Q2,Q3=>Q3);
STIMULUS_ROCESS:process
begin
A0<='0';
B0<='0';
C0<='0';
wait for 10ns;
A0<='0';
B0<='0';
C0<='1';
wait for 10ns;
A0<='0';
B0<='1';
C0<='0';
wait for 10ns;
A0<='0';
B0<='1';
C0<='1';
wait for 10ns;
A0<='1';
B0<='0';
C0<='0';
wait for 10ns;
 A0<='1';
B0<='0';
C0<='1';
wait for 10ns;
A0<='0';
B0<='0';
C0<='0';
wait for 10ns;
A0<='1';
B0<='1';
C0<='1';
wait for 10ns;

end process
end Behavioral;

B.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux2 is
Port ( A0 : in STD_LOGIC;
B0 : in STD_LOGIC;
C0 : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC);
end demux2;

architecture Behavioral of demux2 is

component not1 is
Port ( f : in STD_LOGIC;
 g : out STD_LOGIC);
end component not1;
component and1 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end component and1;
component and2 is
Port ( x1 : in STD_LOGIC;
y1 : in STD_LOGIC;
z1: out STD_LOGIC);
end component and2;
component or2_1 is
Port ( x3 : in STD_LOGIC;
y3 : in STD_LOGIC;
z3 : out STD_LOGIC);
end component or2_1;
component dm1 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end component dm1;
signal temp: std_logic;
signal temp1: std_logic;
signal temp2: std_logic;
signal temp3: std_logic;
signal temp4: std_logic;
signal temp5: std_logic;
begin
uut: not1 port map(f=>C0,g=>temp);
uut1: and1 port map(x=>B0,y=>C0,z=>temp1);
uut2: and2 port map(x1=>A0,y1=>temp,z1=>temp2);
uut3: or2_1 port map(x3=>temp1,y3=>temp2,z3=>temp3);
uut4: dm1 port map(F=>temp3,S0=>B0,S1=>C0,A=>Q0,B=>Q1,C=>Q2,D=>Q3);
end Behavioral;
 SIMULACION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux2_tb is
-- Port ( );
end demux_tb;

architecture Behavioral of demux2_tb is

component demux2 is
Port ( A0 : in STD_LOGIC;
B0 : in STD_LOGIC;
C0 : in STD_LOGIC;
Q0 : out STD_LOGIC;
Q1 : out STD_LOGIC;
Q2 : out STD_LOGIC;
Q3 : out STD_LOGIC);
end component demux2;
signal A0: std_logic:='0';
signal B0: std_logic:='0';
signal C0: std_logic:='0';
signal Q0: std_logic:='0';
signal Q1: std_logic:='0';
signal Q2: std_logic:='0';
signal Q3: std_logic:='0';
begin
uut:demux1 port map (A0=>A0,B0=>B0,C0=>C0,Q0=>Q0,Q1=>Q1,Q2=>Q2,Q3=>Q3);
STIMULUS_ROCESS:process
begin
A0<='0';
B0<='0';
C0<='0';
wait for 10ns;
A0<='0';
B0<='0';
C0<='1';
wait for 10ns;
A0<='0';
B0<='1';
C0<='0';
wait for 10ns;
A0<='0';
B0<='1';
C0<='1';
wait for 10ns;
A0<='1';
B0<='0';
C0<='0';
wait for 10ns;
A0<='1';
B0<='0';
C0<='1';
wait for 10ns;
A0<='0';
B0<='0';
C0<='0';
wait for 10ns;
A0<='1';
B0<='1';
C0<='1';
wait for 10ns;

end process
end Behavioral;
5.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sum is
port (
sVect : out std_logic_vector (3 downto 0);
mainCarryOut : out std_logic;
aVect : in std_logic_vector (3 downto 0);
bVect : in std_logic_vector (3 downto 0);
mainCarryIn : in std_logic
);
end sum;

architecture Behavioral of sumador4bts is

component oneBitFullAdder is
port (
sum, carryOut : out std_logic;
a, b, carryIn : in std_logic
);
end component;

signal auxCarry : std_logic_vector (4 downto 0);

begin
auxCarry(0) <= mainCarryIn;

bit_s0: oneBitFullAdder port map (

sum => sVect(0),
carryOut => auxCarry(1),
a => aVect(0),
b => bVect(0),
carryIn => auxCarry(0)
);

bit_s1: oneBitFullAdder port map (

sum => sVect(1),
carryOut => auxCarry(2),
a => aVect(1),
b => bVect(1),
carryIn => auxCarry(1)
);

bit_s2: oneBitFullAdder port map (

sum => sVect(2),
carryOut => auxCarry(3),
a => aVect(2),
 b => bVect(2),
carryIn => auxCarry(2)
);

bit_s3: oneBitFullAdder port map (

sum => sVect(3),
carryOut => auxCarry(4),
a => aVect(3),
b => bVect(3),
carryIn => auxCarry(3)
);

mainCarryOut <= auxCarry(4);

end Behavioral;

SIMULACION

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sumador4bts_tb is
-- Port ( );
end sumador4bts_tb;

architecture Behavioral of sumador4bts_tb is

component fourBitsFullAdder is
port (
sVect : out std_logic_vector (3 downto 0);
mainCarryOut : out std_logic;
aVect : in std_logic_vector (3 downto 0);
bVect : in std_logic_vector (3 downto 0);
mainCarryIn : in std_logic
);
end component;
signal testFourBitsA, testFourBitsB, testFourBitsSum : std_logic_vector (3 downto 0);
signal testCarryIn, testCarryOut : std_logic;
begin
unit_under_test : fourBitsFullAdder port map (
sVect => testFourBitsSum,
mainCarryOut => testCarryOut,

aVect => testFourBitsA,

bVect => testFourBitsB,
mainCarryIn => testCarryIn
);
generate_signals : process
begin
testCarryIn <= '0'; testFourBitsA <= "0000"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0001"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0010"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0011"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0100"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0101"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0110"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "0111"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1000"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1001"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1010"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1011"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1100"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1101"; testFourBitsB <= "0001"; wait for 10 ns;
 testCarryIn <= '0'; testFourBitsA <= "1110"; testFourBitsB <= "0001"; wait for 10 ns;
testCarryIn <= '0'; testFourBitsA <= "1111"; testFourBitsB <= "0001"; wait for 10 ns;
wait;
end process;

end Behavioral;