Microcontroller

Communication-Interrupt-Timer
Contoh Komunikasi Parallel
• 11 pin digunakan untuk komunikasi Arduino
dengan LCD
• Praktis
• Boros Pin
I2C
 What is I2C?
◼ Shorthand for an “Inter-integrated circuit” bus
◼ Developed by Philips Semiconductor for TV sets in the
1980’s
◼ I2C devices include EEPROMs, thermal sensors, and real-
time clocks
◼ Used as a control interface to signal processing devices
that have separate data interfaces, e.g. RF tuners, video
decoders and encoders, and audio processors.
◼ I2C bus has three speeds:
◼ Slow (under 100 Kbps)

◼ Fast (400 Kbps)

◼ High-speed (3.4 Mbps) – I C v.2.0

2

◼ Limited to about 10 feet for moderate speeds

Sample I2C Device
 Internal structure I2C
Master Core
Addr
Clock
000 Prescale
Addr Generator
001 Register
Addr
011 Command
WISHBOR Register SDA
N Addr
Bit & Byte
100 Status Controller
Interface
Register
SCL
Transmit
Addr
101

Register Data IO
Addr
110 Receiver Shift Register
Register
External connection
 Register List
Name Address Width Access Description
PRERlo 000 8 RW Clock Prescale Register
Lo-byte
PRERhi 001 8 RW Clock Prescale Register
Hi-byte

CTR Null 8 RW Control Register

TXR 101 8 W Transmit Register
RXR 110 8 R Receive Register
CR 011 8 W Command Register
SR 100 8 R Status Register
Control register
Transmit Register

Receive Register
Command Register
Status Register
I2C Bus Configuration

◼ 2-wire serial bus – Serial data (SDA) and Serial clock

(SCL)
◼ Half-duplex, synchronous, multi-master bus
◼ No chip select or arbitration logic required
◼ Lines pulled high via resistors, pulled down via
open-drain drivers (wired-AND)
I2C Protocol

1. Master sends start condition (S) and controls the

clock signal
2. Master sends a unique 7-bit slave device address
3. Master sends read/write bit (R/W) – 0 - slave
receive, 1 - slave transmit
4. Slave with matching 7-bit device address always
sends acknowledge bit (ACK)
5. Transmitter (slave or master) transmits 1 byte of
data
I2C Protocol (cont.)

6. Receiver issues an ACK bit for the byte received

7. Repeat 5 and 6 if more bytes need to be
transmitted
8. Master always sends stop condition (P)
a. For write transaction (master transmitting),
master issues stop condition (P) after last byte of
data.
b. For read transaction (master receiving), master
does not acknowledge final byte, just issues stop
condition (P) to tell the slave the transmission is
 I2C Signals

◼ Start – high-to-low transition of the SDA line while SCL line is

high
◼ Stop – low-to-high transition of the SDA line while SCL line is high
◼ Ack – While transmitter allows SDA to float, the receiver pulls
SDA low throughout the entire next clock pulse on SCL.
◼ Data – transition takes place while SCL is low and is valid while
SCL is high
Bit Command Controller
I
I2C Signals
A B C D I
Write 1 byte of data
to a slave

▪ Generate start command

▪ Write slave address+write bit
▪ Receive acknowledge from slave
▪ Write data
▪ Receive acknowledge from slave
▪ Generate stop command
Read 1 byte of data
to a slave

▪ Generate start command

▪ Write slave address+write bit
▪ Receive acknowledge from slave
▪ Write data
▪ Receive acknowledge from slave
▪ Generate stop command
• Receive acknowledge from slave
• Generate repeated start signal
• Write slave address + read bit
• Receive acknowledge from slave
• Read byte from slave
• Write no acknowledge to
slave,indicationg end of transfer
• Generate stop signal
I2C Features
◼ “Clock stretching” – when the receiver needs more
time to process a bit, it can pull SCL low to keep it
from going high a bit longer. This technique is called
clock stretching . On SDL low, the transmitter can
send its next data value, but this value will not be
interpreted as a valid data symbol by the receiver
until after the slave is ready to release SCL to go
high.
◼ “General call” broadcast – addresses every device on
the bus
◼ 10-bit extended addressing for new designs. 7-bit
addresses all exhausted
 Clock Synchronization
Start counting Start counting
low period high period
wait
state

SCL1 Master1 SCL

SCL2 Master2 SCL

SCL wired-AND SCL

◼ If two or more masters simultaneously try to control

the bus, a clock synchronization procedure
determines the bus clock.
◼ Because of the wired-AND connection of the I2C
signals a high to low transition affects all devices
connected to the bus.
Multiple Devices

➢ Master :- Initiate a message

➢ Slave :- Response to message
Multi-Master Support

➢ Master detect arbitration loss

Advantages Of I2C

➢ Reduce IC Pins, Cost and Area

➢ Reduce PCB Size And Cost
 Internal structure I2C
Master Core
Addr
Clock
000 Prescale
Addr Generator
001 Register
Addr
011 Command
WISHBOR Register SDA
N Addr
Bit & Byte
100 Status Controller
Interface
Register
SCL
Transmit
Addr
101

Register Data IO
Addr
110 Receiver Shift Register
Register
2 Arduino I2C Communication
Master
Slave
SPI
Serial Peripheral Interface (SPI)
In the early days of microcontrollers, both National Semiconductors and Motorola started
introducing simple serial communication, based on the previous Figure. Each formulated
a set of rules which governed how their microcontrollers worked, and allowed others to
develop devices which could interface correctly. These became de facto standards.
Motorola called its standard Serial Peripheral Interface (SPI), and National
Semiconductors called theirs Microwire. They’re very similar to each other.
An SPI network with one Master and multiple slaves can be constructed as shown.
SPI on the mbed: Master
The mbed has two SPI ports, each can be configured
as Master or Slave.

The application programming interface (API)

summary for SPI Master is shown.

On the mbed, as with many SPI devices, the same

pin is used for SDI if in Master mode, or SDO if Slave.

Hence this pin gets to be called MISO, Master in,

Slave out. Its partner pin is MOSI.

Functions Usage
SPI Create a SPI master connected to the specified pins
format Configure the data transmission mode and data length
frequency Set the SPI bus clock frequency
write Write to the SPI Slave and return the response
SPI on the mbed: Mode Mode
0
Polarity
0
Phase
0
1 0 1
2 1 0
3 1 1

The mode is a feature

of SPI that allows
choice of which clock
edge is used to clock
data into the shift
register (indicated as
“Data strobe” in the
diagram), and whether
the clock idles high or
low.

For most applications

the default mode, i.e.
Mode 0, is acceptable.
 Mode Polarity Phase

Clock Polarity and Phase 0

1
0
0
0
1
2 1 0
The SPI protocol uses 4 signals clock (SCLK) 3 1 1

http://dlnware.com/theory/SPI-Transfer-Modes
Clock

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Serial data
• Data is synchronised to the clock
• When there is no data being sent, there is no signal on the clock line
• Every time the clock pulses, one bit is output by the transmitter and should be
read by the receiver
• The receiver synchronises its reading of the data with an edge of the clock.
Parallel Parallel
Read/write Read/write
SDO SDI
SDO – serial data out
SDI – serial data in
Shift Shift SCLK – serial clock
Register SDI SDO Register
msb lsb msb lsb
SCLK SCLK
Clock
Master Slave
SPI on the mbed: Slave
• The Slave program (next slide) uses the mbed functions shown in the
Table.
• It is almost the mirror image of the Master program, with small but key
differences.
• It also declares variables switch_word and recd_val.
• The Slave program configures its switch_word just like the Master.
• While the Master initiates a transmission when it wishes, the Slave must wait.
The mbed library does this with the receive( ) function. This returns 1 if data
has been received, and 0 otherwise.
• If data has been received from the Master, then data has also been sent from
Slave to Master.
Functions Usage
SPISlave Create a SPI slave connected to the specified pins
format Configure the data transmission format
frequency Set the SPI bus clock frequency
receive Polls the SPI to see if data has been received
read Retrieve data from receive buffer as slave
reply Fill the transmission buffer with the value to be written out as
slave on the next received message from the master.
Evaluating SPI
The SPI standard is extremely effective. The electronic hardware is simple and therefore
cheap, and data can be transferred rapidly.
There are disadvantages.
• There is no acknowledgement from the receiver, so in a simple system the Master
cannot be sure that data has been received.
• There is no addressing. In a system where there are multiple slaves, a separate |SS line
must be run to each Slave, as seen earlier. Therefore we begin to lose the advantage that
serial communications should give us, i.e. a limited number of interconnect lines.
• There is no error-checking. Suppose some electromagnetic interference was
experienced in a long data link, data or clock would be corrupted, but the system would
have no way of detecting this, or correcting for it.
Overall SPI could be graded as: simple, convenient and low-cost, but not appropriate for
complex or high reliability systems.
 Parallel Parallel
Read/write Read/write
SDO SDI
SDO – serial data out
SDI – serial data in
Shift Shift SCLK – serial clock
Register SDI SDO Register
msb lsb msb lsb
SCLK SCLK
Clock
Master Slave

Assume the shift registers in the Master and Slave are 8-bit – each has 8 D-type
flip-flops
Each register is loaded with a new word via the parallel I/O lines
The Master then produces 8 clock pulses.
For each clock pulse, data is output from the msb of each register (SDO)
Each SDO is connected to the lsb of the other shift register (SDI)
As each bit is clocked out of one register, it is clocked into the other.
After 8 clock cycles, the word that was in the master shift register as been
transferred to the slave shift register, and vice versa.
SPI: Master-Slave Configuration
• Configuration
• master data output/slave data input (MOSI)
• master data input/slave data output (MISO)
• slave chip select (CS) – usually active low
• When multiple slave devices exist, the master must output a unique CS signal
for each slave, but data lines can be shared. The programmer must
know how data is timed between peripherals when shared.
SPI
• The master device starts an SPI data transfer by
doing the following :
• Configures to SPI clock (SCLK) to be a frequency that the
recipient slave device can handle (max is 70 MHz)
• Sets the chip select line (CS) of the intended recipient to
0V
• Starts the clock pulses on SCLK to indicate that that
data is to be transferred
• Simultaneously sends data as consecutive bits on MOSI
•Number of bits in each data frame can be configured, but is usually
between 4 and 16 bits.
•The slave returns data in the same manner on MISO.
CLK

DATA

1 0 1 0 0 0 0 1

A 1
 Disadvantages of Synchronous
Serial Data Communication
• Synchronous serial communication protocols are
extremely useful ways of moving data around. But
taking a clock signal to every node does have these
disadvantages:
• An extra (clock) line needs to go to every data node.
• The bandwidth needed for the clock is always twice the
bandwidth needed for the data; therefore, it is the
demands of the clock which limit the overall data rate.
• Over long distances, clock and data themselves could lose
synchronisation.
2 Arduino SPI
RS-485
Different signals with RS485
Longer distance and higher bit rates
CAN BUS
Interrupt
What is an Interrupt?
• An interrupt is a signal that tells the processor to
immediately stop what it is doing and handle some
high priority processing. That high priority
processing is called an Interrupt Handler.
• An interrupt handler is like any other void function.
If you write one and attach it to an interrupt, it will
get called whenever that interrupt signal is
triggered. When you return from the interrupt
handler, the processor goes back to continue what
it was doing before.
Interrupt source
• Timer interrupts from one of the
Arduino timers.
• External Interrupts from a change in
state of one of the external interrupt
pins.
• Pin-change interrupts from a change in
state of any one of a group of pins.
What are they good for?
• Using interrupts, you don’t need to write loop code
to continuously check for the high priority interrupt
condition. You don't have to worry about sluggish
response or missed button presses due to long-
running subroutines.
• The processor will automagically stop whatever it is
doing when the interrupt occurs and call your
interrupt handler. You just need to write code to
respond to the interrupt whenever it happens.
Timer Interrupts
• Timers and timer interrupts let us do exactly that.
We can set up a timer to interrupt us once per
millisecond. The timer will actually call us to let us
know it is time to check the clock!
Arduino Timers
• The Arduino has 3 timers: Timer 0, Timer 1 and
Timer 2. Timer 0 is already set up to generate a
millisecond interrupt to update the millisecond
counter reported by millis().
Frequency and Counts
• Timers are simple counters that count at some
frequency derived from the 16MHz system clock. You
can configure the clock divisor to alter the frequency
and various different counting modes. You can also
configure them to generate interrupts when the timer
reaches a specific count.
• Timer0 is an 8-bit that counts from 0 to 255 and
generates an interrupt whenever it overflows. It uses a
clock divisor of 64 by default to give us an interrupt rate
of 976.5625 Hz (close enough to a 1 KHz for our
purposes). We won't mess with the freqency of Timer0,
because that would break millis()!
Comparison Register
• Arduino timers have a number of configuration
registers. These can be read or written to using special
symbols defined in the Arduino IDE. For comprehensive
description of all these registers and their functions,
see the links in "For further reading" below.
• We'll set up a up a comparison register for Timer 0 (this
register is known as OCR0A) to generate another
interrupt somewhere in the middle of that count. On
every tick, the timer counter is compared with the
comparison register and when they are equal an
interrupt will be generated.
• The code below will generate a 'TIMER0_COMPA'
interrupt whenever the counter value passes 0xAF.