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EEM 486 Computer Architecture Homework VI 1. Consider The Following Code Sequence

This document contains two homework problems about computer architecture and pipelining. Problem 1 asks about executing a code sequence with and without forwarding hardware, and reordering instructions to minimize cycles. Problem 2 describes a register-memory architecture pipeline and asks about determining the number of adders and read/write ports needed, and identifying any data forwarding between ALU stages to avoid stalls.

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Halim Koroglu
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39 views

EEM 486 Computer Architecture Homework VI 1. Consider The Following Code Sequence

This document contains two homework problems about computer architecture and pipelining. Problem 1 asks about executing a code sequence with and without forwarding hardware, and reordering instructions to minimize cycles. Problem 2 describes a register-memory architecture pipeline and asks about determining the number of adders and read/write ports needed, and identifying any data forwarding between ALU stages to avoid stalls.

Uploaded by

Halim Koroglu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EEM 486 Computer Architecture

Homework VI

1. Consider the following code sequence.

lw $3, 0($5)
lw $4, 4($5)
add $7, $7, $3
add $8, $8, $4
add $10, $7, $8
sw $6, 0($5)

Assume that a register read and register write in the same clock cycle is possible.

a. Without any forwarding hardware in the pipelined datapath, how many cycles does
this code sequence take to execute?

b. With forwarding hardware in the pipelined datapath, how many cycles does it take to
execute?

c. With forwarding hardware in the pipelined datapath, reorder the instruction so that it
takes the minimum number of clock cycles.

2. A register-memory architecture has two instruction formats: a register-register format and


a register-memory format. There is a single-memory addressing mode (offset + base
register).

There is a set of ALU operations with format:

ALUop Rdest, Rsrc1, Rsrc2

or

ALUop Rdest, Rsrc1, MEM

where the ALUop is one of the following: Add, Subtract, And, Or, Load (Rsrc1 ignored),
Store. Rsrc or Rdest are registers. MEM is a base register and offset pair.

Branches use a full compare of two registers and are PC-relative. Assume that this
machine is pipelined so that a new instruction is started every clock cycle. The following
pipeline structure is
The first ALU stage is used for effective address calculation for memory references and
branches. The second ALU cycle is used for operations and branch comparison. RF is
both a decode and register-fetch cycle. Assume that when a register read and a register
write of the same register occur in the same clock the write data is forwarded.

a. Find the number of adders needed, counting any adder or incrementer; show a
combination of instructions and pipe stages that justify this answer. You need only
give one combination that maximizes the adder count.
b. Find the number of register read and write ports and memory read and write ports
required. Show that your answer is correct by showing a combination of instructions
and pipeline stage indicating the instruction and the number of read ports and write
ports required for that instruction.
c. Determine any data forwarding for any ALUs that will be needed. Assume that there
are separate ALUs for the ALU1 and ALU2 pipe stages. Put in all forwarding among
ALUs needed to avoid or reduce stalls. Show the relationship between the two
instructions involved in forwarding using a similar format to the following table.

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