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 INTEGRATED CIRCUITS

SA571
Compandor

Product specification 1997 Aug 14

IC17 Data Handbook


 
 
Philips Semiconductors Product specification

Compandor SA571

DESCRIPTION PIN CONFIGURATION

The SA571 is a versatile low cost dual gain control circuit in which
D, and N Packages1
either channel may be used as a dynamic range compressor or
expandor. Each channel has a full-wave rectifier to detect the RECT CAP 1 1 16 RECT CAP 2
average value of the signal, a linerarized temperature-compensated
RECT IN 1 2 15 RECT IN 2
variable gain cell, and an operational amplifier.
AG CELL IN 1 3 14 AG CELL IN 2
The SA571 is well suited for use in cellular radio and radio
GND 4 13 VCC
communications systems, modems, telephone, and satellite
broadcast/receive audio systems. INV. IN 1 5 12 INV. IN 2

RES. R3 1 6 11 RES. R3 2
FEATURES
• Complete compressor and expandor in one IChip
OUTPUT 1 7 10 OUTPUT 2

THD TRIM 1 8 9 THD TRIM 2

• Temperature compensated
• Greater than 110dB dynamic range
TOP VIEW
NOTE:
1. SOL - Released in Large SO Package Only. SR00675
• Operates down to 6VDC Figure 1. Pin Configuration
• System levels adjustable with external components
• Distortion may be trimmed out
• Dynamic noise reduction systems APPLICATIONS
• Voltage-controlled amplifier • Cellular radio
• High level limiter
• Low level expandor—noise gate
• Dynamic filters
• CD Player

ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
16-Pin Plastic Small Outline Large (SOL) -40 to +85°C SA571D SOT162-1
16-Pin Plastic Dual In-Line Package (DIP) -40 to +85°C SA571N SOT38-4

BLOCK DIAGRAM
THD TRIM R3 INVERTER IN

R2 20k R3 20k
∆G IN VARIABLE –
GAIN
OUTPUT
VREF
+
R4 30k 1.8V
RECT IN R1 10k
RECTIFIER

RECT CAP SR00676

Figure 2. Block Diagram

1997 Aug 14 2 853-0812 18285

Philips Semiconductors Product specification

Compandor SA571

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNITS
Maximum operating voltage
VCC VDC
571 18
Operating ambient temperature range
TA °C
SA -40 to +85
PD Power dissipation 400 mW

AC ELECTRICAL CHARACTERISTICS
VCC = +6V, TA = 25°C; unless otherwise stated.
LIMITS
SYMBOL PARAMETER TEST CONDITIONS SA5715 UNITS
MIN TYP MAX
VCC Supply voltage 6 18 V
ICC Supply current No signal 3.2 4.8 mA
IOUT Output current capability ±20 mA
SR Output slew rate ±.5 V/µs
Untrimmed 0.5
Gain cell distortion2 2.0 %
Trimmed 0.1
Resistor tolerance ±5 ±15 %
Internal reference voltage 1.65 1.8 1.95 V
Output DC shift3 Untrimmed ±30 ±150 mV
Expandor output noise No signal, 15Hz-20kHz1 20 60 µV
Unity gain level6 1kHz -1.5 0 +1.5 dBm
Gain change2, 4 ±0.1 dB
Reference drift4 +2, -25 +20, -50 mV
Resistor drift4 +8, -0 %
Rectifier input,
Tracking error (measured relative to
V2 = +6dBm, V1 = 0dB +0.2
value at unity gain) equals [VO - VO
dB
(unity gain)] dB - V2dBm
V2 = -30dBm, V1 = 0dB +0.2 -1, +1.5
Channel separation 60 dB
NOTES:
1. Input to V1 and V2 grounded.
2. Measured at 0dBm, 1kHz.
3. Expandor AC input change from no signal to 0dBm.
4. Relative to value at TA = 25°C.
5. Electrical characteristics for the SA571 only are specified over -40 to +85°C temperature range.
6. 0dBm = 775mVRMS.

1997 Aug 14 3
Philips Semiconductors Product specification

Compandor SA571

CIRCUIT DESCRIPTION bias current for the ∆G cell. The low tempco of this type of reference
The SA571 compandor building blocks, as shown in the block provides very stable biasing over a wide temperature range.
diagram, are a full-wave rectifier, a variable gain cell, an operational The typical performance characteristics illustration shows the basic
amplifier and a bias system. The arrangement of these blocks in the input-output transfer curve for basic compressor or expander
IC result in a circuit which can perform well with few external circuits.
components, yet can be adapted to many diverse applications.

COMPRESSOR INPUT LEVEL OR EXPANDOR OUTPUT LEVEL (dBm)

+20
The full-wave rectifier rectifies the input current which flows from the
rectifier input, to an internal summing node which is biased at VREF. +10
The rectified current is averaged on an external filter capacitor tied
to the CRECT terminal, and the average value of the input current 0
controls the gain of the variable gain cell. The gain will thus be
proportional to the average value of the input signal for –10
capacitively-coupled voltage inputs as shown in the following
–20
equation. Note that for capacitively-coupled inputs there is no offset
voltage capable of producing a gain error. The only error will come
–30
from the bias current of the rectifier (supplied internally) which is
less than 0.1µA. –40

|V IN  V REF | avg –50

G
R1
–60
or
| V IN | avg –70
G
R1
–80
The speed with which gain changes to follow changes in input signal
–40 –30 –20 –10 0 +10
levels is determined by the rectifier filter capacitor. A small capacitor
COMPRESSOR OUTPUT LEVEL
will yield rapid response but will not fully filter low frequency signals. OR
Any ripple on the gain control signal will modulate the signal passing EXPANDOR INPUT LEVEL (dBm)
SR00677
through the variable gain cell. In an expander or compressor
Figure 3. Basic Input-Output Transfer Curve
application, this would lead to third harmonic distortion, so there is a
trade-off to be made between fast attack and decay times and TYPICAL TEST CIRCUIT
distortion. For step changes in amplitude, the change in gain with
time is shown by this equation. VCC = 15V

G(t)  (G initial  G final) e  t
0.1µF 10µF

G final ;
 10k x C RECT
13
The variable gain cell is a current-in, current-out device with the ratio 6.11
IOUT/IIN controlled by the rectifier. IIN is the current which flows from 20k
the ∆G input to an internal summing node biased at VREF. The 2.2µF
following equation applies for capacitively-coupled inputs. The 20k
∆G
V1
output current, IOUT, is fed to the summing node of the op amp. 7.10 VO
3.14
V IN  V REF V IN
I IN  
R2 R2
VREF
A compensation scheme built into the ∆G cell compensates for 2.2 10k
temperature and cancels out odd harmonic distortion. The only V2
30k
distortion which remains is even harmonics, and they exist only 2.15
because of internal offset voltages. The THD trim terminal provides
a means for nulling the internal offsets for low distortion operation. 4 1.16 5.12 8.9

The operational amplifier (which is internally compensated) has the 8.2k 200pF
non-inverting input tied to VREF, and the inverting input connected to 2.2

the ∆G cell output as well as brought out externally. A resistor, R3, is

SR00678
brought out from the summing node and allows compressor or
expander gain to be determined only by internal components. Figure 4. Typical Test Circuit

The output stage is capable of ±20mA output current. This allows a

+13dBm (3.5VRMS) output into a 300Ω load which, with a series INTRODUCTION
resistor and proper transformer, can result in +13dBm with a 600Ω
Much interest has been expressed in high performance electronic
output impedance.
gain control circuits. For non-critical applications, an integrated
A bandgap reference provides the reference voltage for all summing circuit operational transconductance amplifier can be used, but
nodes, a regulated supply voltage for the rectifier and ∆G cell, and a when high-performance is required, one has to resort to complex
discrete circuitry with many expensive, well-matched components.

1997 Aug 14 4
Philips Semiconductors Product specification

Compandor SA571

This paper describes an inexpensive integrated circuit, the SA571 rectifier and ∆G cell (located at the right of R1 and R2) have the
Compandor, which offers a pair of high performance gain control same potential. The THD trim pin is also at the VREF potential.
circuits featuring low distortion (<0.1%), high signal-to-noise ratio
Figure 7 shows how the circuit is hooked up to realize an expandor.
(90dB), and wide dynamic range (110dB).
The input signal, VIN, is applied to the inputs of both the rectifier and
CIRCUIT BACKGROUND the ∆G cell. When the input signal drops by 6dB, the gain control
The SA571 Compandor was originally designed to satisfy the current will drop by a factor of 2, and so the gain will drop 6dB. The
requirements of the telephone system. When several telephone output level at VOUT will thus drop 12dB, giving us the desired 2-to-1
channels are multiplexed onto a common line, the resulting expansion.
signal-to-noise ratio is poor and companding is used to allow a wider Figure 8 shows the hook-up for a compressor. This is essentially an
dynamic range to be passed through the channel. Figure 5 expandor placed in the feedback loop of the op amp. The ∆G cell is
graphically shows what a compandor can do for the signal-to-noise setup to provide AC feedback only, so a separate DC feedback loop
ratio of a restricted dynamic range channel. The input level range of is provided by the two RDC and CDC. The values of RDC will
+20 to -80dB is shown undergoing a 2-to-1 compression where a determine the DC bias at the output of the op amp. The output will
2dB input level change is compressed into a 1dB output level bias to:
change by the compressor. The original 100dB of dynamic range is R DC1
R DC2
thus compressed to a 50dB range for transmission through a V OUT DC  1

R4
restricted dynamic range channel. A complementary expansion on
the receiving end restores the original signal levels and reduces the
THD TRIM R3 INVIN
channel noise by as much as 45dB.
8,9 6,11 5,12
The significant circuits in a compressor or expander are the rectifier R2 R3
GIN 20k 20k
and the gain control element. The phone system requires a simple ∆G OUTPUT
full-wave averaging rectifier with good accuracy, since the rectifier 3,14 VREF
IG R4 7,10
accuracy determines the (input) output level tracking accuracy. The RECTIN 30k 1.8V
gain cell determines the distortion and noise characteristics, and the 2,15 R1
1,16 VCC PIN 13
phone system specifications here are very loose. These specs could 10k
GND PIN 4
have been met with a simple operational transconductance CRECT
SR00680
multiplier, or OTA, but the gain of an OTA is proportional to
temperature and this is very undesirable. Therefore, a linearized Figure 6. Chip Block Diagram (1 of 2 Channels)
transconductance multiplier was designed which is insensitive to
temperature and offers low noise and low distortion performance. R3
These features make the circuit useful in audio and data systems as
well as in telecommunications systems.
*CIN1
R2
BASIC CIRCUIT HOOK-UP AND OPERATION ∆G –
Figure 6 shows the block diagram of one half of the chip, (there are + VOUT
two identical channels on the IC). The full-wave averaging rectifier VIN
R4
provides a gain control current, IG, for the variable gain (∆G) cell.
VREF
The output of the ∆G cell is a current which is fed to the summing *CIN2 R1
node of the operational amplifier. Resistors are provided to establish
circuit gain and set the output DC bias.
COMPRESSION

NOTE:
2 R 3 V IN (avg)
EXPANSION

*CRECT
GAIN 
R1 R2 IB
IB = 140µA
INPUT OUTPUT
LEVEL LEVEL *EXTERNAL COMPONENTS SR00681
+20 –20
Figure 7. Basic Expander
0dB 0dB

–40 –40
V REF   1

R DCTOT
30k
 1.8V
NOISE
The output of the expander will bias up to:
–80 –80 R3
SR00679
V OUT DC  1
V
R 4 REF
Figure 5. Restricted Dynamic Range Channel

The circuit is intended for use in single power supply systems, so V REF  1
20k
30k
 1.8V  3.0V
the internal summing nodes must be biased at some voltage above
ground. An internal band gap voltage reference provides a very The output will bias to 3.0V when the internal resistors are used.
stable, low noise 1.8V reference denoted VREF. The non-inverting External resistors may be placed in series with R3, (which will affect
input of the op amp is tied to VREF, and the summing nodes of the the gain), or in parallel with R4 to raise the DC bias to any desired
value.

1997 Aug 14 5
Philips Semiconductors Product specification

Compandor SA571

have typical NPN βs of 200 and PNP βs of 40. The a’s of 0.995 and
R2
∆G
0.975 will produce errors of 0.5% on negative swings and 2.5% on
positive swings. The 1.5% average of these errors yields a mere
0.13dB gain error.
R1
At very low input signal levels the bias current of Q2, (typically
CRECT* * 50nA), will become significant as it must be supplied by Q5. Another
CF
*
RDC R * DC
low level error can be caused by DC coupling into the rectifier. If an
offset voltage exists between the VIN input pin and the base of Q2,
CIN CDC * an error current of VOS/R1 will be generated. A mere 1mV of offset
R3
VOUT will cause an input current of 100nA which will produce twice the
VIN
error of the input bias current. For highest accuracy, the rectifier
R4 VREF should be coupled into capacitively. At high input levels the β of the

 
NOTES: 1 PNP Q6 will begin to suffer, and there will be an increasing error until
R1 R2 IB 2
GAIN
the circuit saturates. Saturation can be avoided by limiting the
2R 3 V INavg
current into the rectifier input to 250µA. If necessary, an external
IB = 140µA resistor may be placed in series with R1 to limit the current to this
External components SR00682 value. Figure 11 shows the rectifier accuracy vs input level at a
frequency of 1kHz.
Figure 8. Basic Compressor
V+
I = VIN / R1 V+

Q3 Q7

R1 Q4

VIN Q5
R1
D1 10k
RS
Q1 Q2 VIN
10k
CR IG RS
10k
Q6
Q8
I1 I2 Q9

CR

SR00684 V–

Figure 9. Rectifier Concept NOTE:

V IN avg
IG
2
R 1 SR00683
CIRCUIT DETAILS—RECTIFIER
Figure 10. Simplified Rectifier Schematic
Figure 9 shows the concept behind the full-wave averaging rectifier.
The input current to the summing node of the op amp, VINR1, is At very high frequencies, the response of the rectifier will fall off. The
supplied by the output of the op amp. If we can mirror the op amp roll-off will be more pronounced at lower input levels due to the
output current into a unipolar current, we will have an ideal rectifier. increasing amount of gain required to switch between Q5 or Q6
The output current is averaged by R5, CR, which set the averaging conducting. The rectifier frequency response for input levels of
time constant, and then mirrored with a gain of 2 to become IG, the 0dBm, -20dBm, and -40dBm is shown in Figure 12. The response at
gain control current. all three levels is flat to well above the audio range.
Figure 10 shows the rectifier circuit in more detail. The op amp is a +1
one-stage op amp, biased so that only one output device is on at a
time. The non-inverting input, (the base of Q1), which is shown
ERROR GAIN dB

grounded, is actually tied to the internal 1.8V VREF. The inverting

input is tied to the op amp output, (the emitters of Q5 and Q6), and
0
the input summing resistor R1. The single diode between the bases
of Q5 and Q6 assures that only one device is on at a time. To detect
the output current of the op amp, we simply use the collector
currents of the output devices Q5 and Q6. Q6 will conduct when the
–1
input swings positive and Q5 conducts when the input swings –40 –20 0
negative. The collector currents will be in error by the a of Q5 or Q6 RECTIFIER INPUT dBm SR00685
on negative or positive signal swings, respectively. ICs such as this
Figure 11. Rectifier Accuracy

1997 Aug 14 6
Philips Semiconductors Product specification

Compandor SA571

I C1 I C4 I 1
I IN
 
I C2 I C3 I 1  I IN

INPUT = 0dBm plus the relationships IG=IC3+IC4 and IOUT=IC4-IC3 will yield the
GAIN ERROR (dB)

–20dBm
multiplier transfer function,
0
IG V IN I G
I OUT  I IN 
3 –40dBm I1 R2 I1

This equation is linear and temperature-insensitive, but it assumes

ideal transistors.

4
10k 1MEG VOS = 5mV
FREQUENCY (Hz) SR00686
3
Figure 12. Rectifier Frequency Response vs Input Level 4mV

% THD
2 3mV
VARIABLE GAIN CELL
Figure 13 is a diagram of the variable gain cell. This is a linearized 2mV
two-quadrant transconductance multiplier. Q1, Q2 and the op amp 1
1mV
provide a predistorted drive signal for the gain control pair, Q3 and .34
Q4. The gain is controlled by IG and a current mirror provides the
output current. –6 0 +6
INPUT LEVEL (dBm)
SR00688
The op amp maintains the base and collector of Q1 at ground
potential (VREF) by controlling the base of Q2. The input current IIN Figure 14. ∆G Cell Distortion vs Offset Voltage
(=VIN/R2) is thus forced to flow through Q1 along with the current I1,
If the transistors are not perfectly matched, a parabolic, non-linearity
so IC1=I1+IIN. Since I2 has been set at twice the value of I1, the
is generated, which results in second harmonic distortion. Figure 14
current through Q2 is:
gives an indication of the magnitude of the distortion caused by a
I2-(I1+IIN)=I1-IIN=IC2. given input level and offset voltage. The distortion is linearly
proportional to the magnitude of the offset and the input level.
The op amp has thus forced a linear current swing between Q1 and
Saturation of the gain cell occurs at a +8dBm level. At a nominal
Q2 by providing the proper drive to the base of Q2. This drive signal
operating level of 0dBm, a 1mV offset will yield 0.34% of second
will be linear for small signals, but very non-linear for large signals,
harmonic distortion. Most circuits are somewhat better than this,
since it is compensating for the non-linearity of the differential pair,
which means our overall offsets are typically about mV. The
Q1 and Q2, under large signal conditions.
distortion is not affected by the magnitude of the gain control
current, and it does not increase as the gain is changed. This
V+ second harmonic distortion could be eliminated by making perfect
transistors, but since that would be difficult, we have had to resort to
I1 other methods. A trim pin has been provided to allow trimming of the
140µA
internal offsets to zero, which effectively eliminated
second harmonic distortion. Figure 15 shows the simple trim
network required.
Figure 16 shows the noise performance of the ∆G cell. The
maximum output level before clipping occurs in the gain cell is
R2
plotted along with the output noise in a 20kHz bandwidth. Note that
20k
Q1 Q2 Q3 Q4 the noise drops as the gain is reduced for the first 20dB of gain
VIN IIN
reduction. At high gains, the signal to noise ratio is 90dB, and the
total dynamic range from maximum signal to minimum noise is
110dB.

I2 (= 2I1) IG VCC
280µA

NOTE: V–
I I V IN R
G G
I  I 
OUT I 1 IN I2 R2
SR00687
3.6V
Figure 13. Simplified ∆G Cell Schematic 6.2k
20k

The key to the circuit is that this same predistorted drive signal is To THD Trim
applied to the gain control pair, Q3 and Q4. When two differential ≈200pF
pairs of transistors have the same signal applied, their collector
current ratios will be identical regardless of the magnitude of the SR00689
currents. This gives us:
Figure 15. THD Trim Network

1997 Aug 14 7
Philips Semiconductors Product specification

Compandor SA571

+20
RESISTORS
Inspection of the gain equations in Figures 7 and 8 will show that the
basic compressor and expander circuit gains may be set entirely by
0
resistor ratios and the internal voltage reference. Thus, any form of
MAXIMUM resistors that match well would suffice for these simple hook-ups,
–20 SIGNAL LEVEL and absolute accuracy and temperature coefficient would be of no
OUTPUT (dBm)

90dB importance. However, as one starts to modify the gain equation with
110dB external resistors, the internal resistor accuracy and tempco become
–40
very significant. Figure 19 shows the effects of temperature on the
diffused resistors which are normally used in integrated circuits, and
–60
the ion-implanted resistors which are used in this circuit. Over the
critical 0°C to +70°C temperature range, there is a 10-to-1 improve-
–80 ment in drift from a 5% change for the diffused resistors, to a 0.5%
NOISE IN
20kHz BW
change for the implemented resistors. The implanted resistors have
–100 another advantage in that they can be made the size of the diffused
–40 –20 0 resistors due to the higher resistivity. This saves a significant
VCA GAIN (0dB) SR00690 amount of chip area.
Figure 16. Dynamic Range 140Ω /
1.15
Control signal feedthrough is generated in the gain cell by imperfect

NORMALIZED RESISTANCE
DIFFUSED
RESISTOR
device matching and mismatches in the current sources, I1 and I2.
1.10
When no input signal is present, changing IG will cause a small
1kΩ /
output signal. The distortion trim is effective in nulling out any control
LOW TC

ÇÇÇÇÇÇ
signal feedthrough, but in general, the null for minimum feedthrough 1.05 IMPLANTED
will be different than the null in distortion. The control signal RESISTOR

feedthrough can be trimmed independently of distortion by tying a 1.00

1% ERROR
current source to the ∆G input pin. This effectively trims I1. Figure 17 BAND
shows such a trim network.
.95
–40 0 40 80 120
VCC
TEMPERATURE SR00693

Figure 19. Resistance vs Temperature

R-SELECT FOR

3.6V
470k
100k TO PIN 3 OR 14

SR00691

Figure 17. Control Signal Feedthrough

OPERATIONAL AMPLIFIER
The main op amp shown in the chip block diagram is equivalent to a
741 with a 1MHz bandwidth. Figure 18 shows the basic circuit. Split
collectors are used in the input pair to reduce gM, so that a small
compensation capacitor of just 10pF may be used. The output
stage, although capable of output currents in excess of 20mA, is
biased for a low quiescent current to conserve power. When driving
heavy loads, this leads to a small amount of crossover distortion.

I1 I2
Q6

Q1 Q2 D1
–IN +IN OUT
D2
CC

Q2

Q3 Q4

SR00692

Figure 18. Operational Amplifier

1997 Aug 14 8
Philips Semiconductors Product specification

Compandor SA571

SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

1997 Aug 14 9
Philips Semiconductors Product specification

Compandor SA571

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

1997 Aug 14 10
Philips Semiconductors Product specification

Compandor SA571

DEFINITIONS
Data Sheet Identification Product Status Definition

This data sheet contains the design target or goal specifications for product development. Specifications
Objective Specification Formative or in Design
may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
Product Specification Full Production
at any time without notice, in order to improve design and supply the best possible product.

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICATIONS

Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors  Copyright Philips Electronics North America Corporation 1997

811 East Arques Avenue All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381


 
 
1997 Aug 14 11