2424 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.

11, NOVEMBER 2006

Bandwidth Extension Techniques

for CMOS Amplifiers
Sudip Shekhar, Student Member, IEEE, Jeffrey S. Walling, Student Member, IEEE, and David J. Allstot, Fellow, IEEE

Abstract—Inductive-peaking-based bandwidth extension tech- [6], [7]. Because conventional methods provide limited band-
niques for CMOS amplifiers in wireless and wireline applications width extension to meet the critical requirements of high-speed
are presented. To overcome the conventional limits on bandwidth applications, there is a need for techniques that achieve larger
extension ratios, these techniques augment inductive peaking
using capacitive splitting and magnetic coupling. It is shown that bandwidths without increased power consumption and design
a critical design constraint for optimum bandwidth extension is complexity.
the ratio of the drain capacitance of the driver transistor to the Consider the common-source amplifier shown in Fig. 2 where
load capacitance. This, in turn, recommends the use of different is the load resistance, and and represent the drain par-
techniques for different capacitance ratios. Prototype wideband asitic and load capacitance, respectively; it is used extensively
amplifiers in 0.18- m CMOS are presented that achieve a mea-
sured bandwidth extension ratio up to 4.1 and simultaneously in differential amplifiers in wireline applications with several
maintain high gain ( 12 dB) in a single stage. Even higher stages cascaded to achieve high gain. Thus, includes the gate
enhancement ratios are shown through the introduction of a capacitance of the next stage. Depending on the scaling of ad-
modified series-peaking technique combined with staggering tech- jacent stages, the ratio typically
niques. Ultra-wideband low-noise amplifiers in 0.18- m CMOS varies from 0.2–0.5.1 Note that is a design constraint be-
are presented that exhibit bandwidth extension ratios up to 4.9.
cause the desired gain, voltage swing, and bias current set the
Index Terms—Bandwidth extension, low-noise amplifier, transistor sizes in each stage. This observation leads to two im-
low-power, peaking, staggering, T-coil, transformer, ultra-wide-
band (UWB), wireless, wireline.
portant conclusions: 1) A given bandwidth extension technique
may not be optimum for all values, and 2) a multi-stage am-
plifier may achieve superior performance using different band-
I. INTRODUCTION width extension techniques in different stages.
In wireless applications, a common-source LNA with an
C OMMUNICATION trends foretell future CMOS solutions
that transmit and receive data at high speeds with low error
rates, low cost and low power. Wireline devices that operate at
input matching network (e.g., a source-degenerated UWB LNA
[8]) achieves a bandpass response. includes the gate capac-
10–40 Gb/s such as MUX/DEMUX circuits for Ethernet appli- itance of the buffer or mixer following the LNA, and typical
cations demand the design of broadband amplifiers [1], [2], and values of again range from 0.2–0.5 because the transistor
40 Gb/s optical transceivers [Fig. 1(a)] require broadband am- sizing depends on gain, bias current, noise figure (NF), etc.
plification in constituent preamplifiers, drivers, transimpedance In contrast, transistor sizes in a common-gate LNA are often
amplifiers, etc. [3]. Ultra-wideband (UWB) wireless receivers smaller so can be less than 0.2.
[Fig. 1(b)] that function in the 3.1–10.6 GHz spectrum also ben- This paper describes broadband design approaches that
efit from bandwidth extension techniques in low-noise amplifier achieve substantially larger bandwidth extension ratios
(LNA) designs [4], [5]. (BWERs) than previously demonstrated, with an underlying
Although CMOS is viable for system-on-chip solutions, its theme that different drive/load conditions and different
applications (low-pass for wireline and bandpass for wireless)
parasitics limit the performance of broadband amplifiers and
demand different techniques for best performance. In each
motivate the use of bandwidth extension techniques such as dis-
of Sections II through IV, a conventional bandwidth exten-
tributed amplification. However, distributed amplifiers consume
sion technique based on passive filtering is first presented,
large area and high power and are difficult to design owing to
and an improved approach with a larger BWER is then intro-
delay line losses that necessitate extensive modeling and elec-
duced. Sections V and VI describe the design of high-speed
tromagnetic simulation.
wideband amplifiers for wireline applications and give mea-
Passive filtering (e.g., shunt and series peaking) has been used
sured results, respectively. A series-peaking technique with
since the 1930s to extend amplifier bandwidth; it uses inductors
large gain-peaking for low- applications is proposed in
to trade off bandwidth versus peaking in the magnitude response
Section VII. Next, stagger-tuning, a technique common in
distributed amplifiers, is used in Section VIII to compensate
Manuscript received January 12, 2006; revised July 15, 2006. This work was
supported by the National Science Foundation under Contracts CCR-0086032
the peaked response of the proposed series-peaking technique
and CCR-0120255, and by the Semiconductor Research Corporation under in the design of a single-stage UWB LNA [9]. Measured
Contracts 2001-HJ-926 and 2003-TJ-1093. results of the LNA follow in Section IX. Conclusions are given
The authors are with the Department of Electrical Engineering, University
of Washington, Seattle, WA 98195 USA (e-mail: [email protected]; 1k can be greater than 0.5 in some applications such as when a large photo-
[email protected]; [email protected]). diode junction capacitance (C ) is followed by a smaller capacitive load (C )
Digital Object Identifier 10.1109/JSSC.2006.883336 looking into the transimpedance amplifier (TIA) of Fig. 1(b).

0018-9200/$20.00 © 2006 IEEE

SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2425

Fig. 1. (a) A typical optical communication transceiver [3]. (b) One implementation of a UWB receiver front-end [5].

Fig. 2. A common-source amplifier.

Fig. 3. A common-source amplifier with shunt peaking.
in Section X, and the design flow of asymmetric T-coils is
highlighted in the Appendix.

II. BRIDGED-SHUNT PEAKING

Shunt peaking is a bandwidth extension technique in which
an inductor connected in series with the load resistor shunts
the output capacitor (Fig. 3) [6], [7]. Treating
the transistor as a small-signal dependent current source,
, the gain is simply the product of the transimpedance
and the transconductance . As is approximately Fig. 4. A common-source amplifier with bridged-shunt peaking.
constant, only transimpedance is considered hereafter. For the
shunt-peaked network: Substituting the 3 dB bandwidth of the reference common-
source amplifier, , and the variable
(1) into (1) and normalizing to the impedance at DC gives

The inductor introduces a zero in that increases the

impedance with frequency, compensates the decreasing (2)
impedance of , and thus extends the 3 dB bandwidth. An
equivalent explanation for increased bandwidth is reduced rise- For shunt peaking, gives the maximum BWER of 1.84
time. That is, the inductor delays current flow to the resistive [6], [7], [10]. This extension comes with 1.5 dB of peaking. A
branch so that more current initially charges which reduces maximally flat gain is achieved for but BWER is
risetime [7]. reduced to 1.72.
2426 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 5. Ideal bandwidth improvement with bridged-shunt peaking versus k =C =C .

Although the increased impedance of the inductor accounts

for the bandwidth improvement, it also leads to peaking in
the response. Hence, techniques to eliminate peaking with
maximum BWER are desired. One remedy is to add in shunt
with the inductor a capacitor that should be large enough to
negate peaking but small enough to not significantly alter the
gain response. A common-source amplifier incorporating such
a bridged-shunt network [11], [12] is shown in Fig. 4 where
Fig. 6. A common-source amplifier with series peaking and drain parasitic
capacitance.
(3)
TABLE I
SERIES PEAKING SUMMARY
and , , and . Compared
to (2), introduces another pole and zero in . For
, a BWER of 1.83 is achieved with a flat gain re-
sponse, in contrast to the shunt-peaked design with a nearly
identical BWER of 1.84 but 1.5 dB of peaking. Fig. 5 shows
magnitude responses for the bridged-shunt-peaked circuit for
several practical values of along with the shunt-peaked
and uncompensated (Fig. 2) cases. A subtle advan-
tage of bridged-shunt peaking over shunt peaking is that the
maximum bandwidth is achieved for a larger value of , which
translates to a smaller inductance with smaller die area, higher inductor is inserted to separate the total load capacitance into
self-resonant frequency, etc. two constituent components. To understand this effect, con-
An inductor implemented in silicon has significant shunt par- sider the series-peaked amplifier (Fig. 6) whose normalized
asitic capacitances. By connecting to the supply (Fig. 4), its transimpedance with is
parasitic contributes to (note: there are no pure shunt-peaked
designs in silicon because in practice ). In a differential (4)
implementation, it also enables the use of symmetrical induc-
tors to save area. On the other hand, connecting to the drain
adds a parasitic to and reduces the bandwidth. As expected, the separation of from creates another pole,
which affects BWER versus as shown in Table I. As the par-
III. BRIDGED-SHUNT-SERIES PEAKING asitic capacitance ratio increases, BWER increases to a max-
In designs where the drain parasitic (Fig. 2) is signifi- imum of 2.52 for . If the passband peaking that occurs
cant, better BWER is achieved using capacitive splitting—an for higher values of is acceptable, an even larger BWER is
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2427

Fig. 7. Ideal bandwidth improvement with series peaking versus k = C =C .

achievable. Fig. 7 shows 3 dB bandwidth improvements for

practical values. Series-peaked designs with (i.e.,
) have been reported [13], [14].
Additional insight into the increased bandwidth achieved by
capacitive splitting is gained by considering the step response of
the amplifier. Without , the transistor charges ,
but with only is charged initially because delays current
flow to the rest of the network. This reduces risetime at the drain
and increases bandwidth [7].
Combining capacitive splitting of the series-peaked circuit
Fig. 8. A common-source amplifier with bridged-shunt-series peaking and
and inductive peaking of the bridged-shunt approach results in drain parasitic capacitance.
the bridged-shunt-series-peaked network of Fig. 8. It uses two
inductors but provides larger BWER values than its shunt-se-
TABLE II
ries-peaked counterpart. BRIDGED-SHUNT-SERIES PEAKING SUMMARY
Substituting , , and , ,
and , as defined before, the normalized transimpedance func-
tion of the bridged-shunt-series-peaked network is as shown in
(5) at the bottom of the page. Table II shows results for a range
of and passband ripple values; for , a BWER of 4
is possible. Fig. 9 shows bandwidth improvements for several
values of . A response with no gain-peaking is achieved for an ideal BWER of 3.5 with 1.8 dB peaking is a special case of
and , which affords pole–zero cancellation. bridged-shunt-series peaking with and ; it
However, such cancellations require precise component values is sub-optimum in applications where the load capacitance is
that are difficult to realize due to distributed parasitic effects and large [2]. In contrast, in a bridged-shunt-series-
process, voltage, and temperature (PVT) variations. Note that peaked design adds a degree of freedom to control a zero that
the shunt-series design reported by Galal et al. [3] that gives mitigates the effects of parasitics and leads to a larger BWER.

(5)
2428 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 9. Ideal bandwidth improvements with bridged-shunt-series peaking versus k = C =C .

For , for example, a simple shunt-series-peaked design

gives BWER values of 3.51 and 3.78 for 0 dB and 2 dB peaking,
respectively, which is inferior to the bridged-shunt-series design
exemplified in Table II.
IV. ASYMMETRIC T-COIL PEAKING
Bridged-shunt-series peaking gives a large BWER for
. However, as the load capacitance increases , the
capacitive-splitting action of and the bridging action of
become ineffective in achieving a large BWER. To overcome
this drawback, the magnetic coupling action of a transformer
is used. In an asymmetric T-coil-peaked ampli-
fier [12] [Fig. 10(a)], the coils are wound to achieve a negative
mutual inductance. As in bridged-shunt-series peaking, the sec-
ondary inductor facilitates capacitive splitting so that the ini- Fig. 10. (a) A common-source amplifier with asymmetric T-coil peaking and
tial charging current flows only to . Next, the current begins drain parasitic capacitance, and (b) an equivalent T-coil peaking network with
to flow in , which causes a proportional amount of current to a T-model of the transformer.
flow to . The negative magnetic coupling allows for an initial
boost in the current flow to the load capacitance , because
the capacitor is effectively connected in series with the nega- , , and , the normalized transimpedance is as shown
tive mutual inductance element of the T-coil. This allows in (6) at the bottom of the page. Table III shows the improve-
for an improvement in rise time and thus BWER. In Fig. 10(b), ment in bandwidth versus and passband ripple. Although
the equivalent small-signal network incorporates a T-model of the non-peaked cases show large BWER, the required pole–zero
the transformer. The coupling constant is related to the mu- cancellation is again difficult to implement for the reasons men-
tual inductance as . Substituting , , tioned earlier. For 2 dB peaking, a BWER of 5.59 is obtained

(6)
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2429

Fig. 11. Ideal bandwidth improvements with asymmetric T-coil peaking versus k = C =C .

TABLE III by designing each stage for relatively low gain and wide band-
ASYMMETRIC T-COIL PEAKING SUMMARY width, and then cascading several stages to provide the desired
overall gain. This approach suffers bandwidth shrinkage with
increased die area and power consumption.
The techniques presented herein provide large BWER in a
single stage and span a wide range of values. Hence, they
provide leeway to sacrifice some bandwidth to increase the gain
per stage so that the overall gain and bandwidth goals are met
in the minimum number of stages.
To demonstrate this concept, three single-stage amplifiers
with different values are designed for gains greater than
12 dB and bandwidths of about 10 GHz. Two bridged-shunt-se-
for . Fig. 11 plots bandwidth improvements for var- ries amplifiers [Fig. 12(a)] with and 0.5, and one
ious values of . asymmetric T-coil amplifier [Fig. 12(b)] with are
Employing an asymmetric T-coil and properly utilizing the designed, along with an uncompensated reference amplifier
drain capacitance leads to pole–zero locations that are op- for comparison. The bridged-shunt-series amplifiers utilize
timized for a larger BWER—much larger, in fact, than with the standard library inductor values whereas the asymmetric T-coil
classical bridged T-coil network with . The latter can- amplifier requires the design of a custom T-coil. After choosing
cels a pole-pair with a zero-pair [7] by using a symmetric T-coil the inductor values using the results given earlier, the initial
and neglecting the drain capacitance, but a BWER of only 2.83 is amplifier designs are optimized to maximize bandwidth, gain
achieved. For an asymmetric T-coil, positive magnetic coupling and gain-flatness; it is observed that the higher order parasitics
[1] is suboptimal. It provides a BWER of only 3.23 because it of the coils and the and of the transistors substantially
does not fully exploit the magnetic coupling action of the trans- affect pole–zero placements, and thus the component values
former to improve rise time. for optimal performance. To insure first-pass success, para-
sitic-aware optimization [16] is performed to determine the
V. DESIGN OF HIGH-SPEED WIDEBAND final component values. Like the GBW product, it is observed
DIFFERENTIAL AMPLIFIERS that BWER also depends on the gain of the amplifier; i.e., as
gain is increased, the effect of and increases and BWER
A. High-Gain High-Bandwidth Design decreases from its theoretical value. If the gain is decreased,
In conventional single-stage wideband amplifier design, BWER approaches, but never reaches, the ideal value.2 So,
a tradeoff is made between bandwidth and gain due to the the two bridged-shunt-series amplifiers designed for 14 dB
fixed gain–bandwidth (GBW) product. However, for fine-line gain, exhibit a larger deviation from the calculated (4, 3.5) to
CMOS technologies, the GBW product actually decreases 2Similarly, the deviation from the theoretical component values is small for
with increased gain because of higher order parasitic effects amplifiers with smaller gain (smaller W=L transistors). For amplifiers with
[15]—mostly because becomes increasingly significant as large gain, the higher order effects significantly change the inductor values and
the transistor is increased. Thus, a compromise is made a parasitic-aware optimization is employed for a robust design.
2430 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 12. (a) A bridged-shunt-series peaked amplifier, and (b) an asymmetric T-coil peaked amplifier.

Fig. 13. T-coil winding structure used in the asymmetric T-coil peaked
amplifier.

simulated BWER values (3.3, 3.2) than the asymmetric T-coil Fig. 14. Electromagnetic simulation results for the T-coil design.
amplifier, which is designed for a smaller gain of 12 dB. It
has simulated and calculated BWER values of 4.2 and 4.6, re-
spectively. Nevertheless, the single-stage amplifiers of Fig. 12 secondary, with 3.24 m trace width and 3 m spacing. Fig. 14
achieve the largest combined gain and BWER values reported shows the simulated winding inductances. To facilitate accurate
to date, and the total current consumption in each differential simulations, a wideband compact circuit model is implemented
amplifier is only 15 mA. (Fig. 15) which incorporates elements that estimate bulk eddy
current losses as well as skin and proximity effects [19]. The
B. Design of Asymmetric T-Coils T-coil has a simulated self-resonance frequency of 19.2 GHz
Designing the asymmetric T-coil involves several factors. and a of 9.
Most notably, the required magnetic coupling ratio is
relatively low, in the range of 0.3–0.7, which typically excludes VI. MEASUREMENT RESULTS OF HIGH-SPEED WIDEBAND
interleaved T-coil structures [17]. Furthermore, the complexity DIFFERENTIAL AMPLIFIERS
associated with the design of a symmetric coil is avoided owing A typical application of these circuits does not include
to the required non-unity turns ratio. Finally, structures that driving a real impedance load, so they are not designed to
minimize parasitic effects between windings are desirable. For drive such loads. This creates a dilemma in measurements as
these reasons, the asymmetric concentric winding structure or standard high-frequency equipment typically has a real port
tapped inductor depicted in Fig. 13 is chosen [18]. impedance of 50 , which leaves limited options for making
The T-coil used in the asymmetric T-coil-peaked amplifier is measurements.
designed using the procedure outlined in the Appendix. It con- Although input matching is easily achieved by connecting a
sists of four windings of the primary and three windings of the 50- resistor in shunt with the input at the expense of noise
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2431

Fig. 15. Wideband compact circuit model for the asymmetric T-coil.

performance, this matching option is not viable at the output due

to its negative impact on gain. Buffering the amplifiers using
matched unity-gain amplifiers is another option. However, the
design of the buffer is challenging, as it must have frequency Fig. 16. Chip microphotographs of (a) reference amplifier with k = 0:4,
performance similar to that of the wideband amplifier under test. (b) reference amplifier with k = 0:3, (c) bridged-shunt-series peaked ampli-
fier with k = 0:4, and (d) asymmetric T-coil peaked amplifier with k = 0:3.
Finally, the use of passive matching techniques is difficult owing [The k = 0:5 case is not shown but the amplifier design is similar to (c)].
to the relatively poor quality on-chip passives that contribute
loss and thermal noise.
Another choice is to design the amplifier without matching VII. SERIES PEAKING TECHNIQUE
networks, and use familiar measurement techniques to ob- FOR LOW VALUES
tain its -parameters, which are then used to calculate gain
through simple manipulations. The -parameter matrix ob- The peaking techniques described above use passive filter
tained from measurement is transformed to a mixed-mode networks to shape the gain response above the original 3 dB
-parameter matrix that gives parameters for both differential- frequency. However, if the network is designed to introduce a
and common-mode performance [20]: larger peaking above the 3 dB frequency, and this peaking is
then compensated, a larger BWER is achievable.
In the conventional series-peaked network of Fig. 6, the load
resistor shunts the drain node. Rewriting (4) with , its
transimpedance is

(8)
(7)
To determine the differential-mode voltage gain, the upper left
quadrant -parameter sub-matrix is converted into a -param- In the proposed modified version (Fig. 18) where shunts
eter sub-matrix using a reference impedance of 50 [21]. The , is
voltage gain is then simply the ratio of to .
The bridged-shunt-series and asymmetric T-coil amplifiers (9)
along with the unpeaked reference amplifier are designed and
fabricated in a six-metal 0.18- m CMOS process with a top Equation (9) for is similar to that of conventional se-
metal thickness of 2 m. The chip microphotographs are shown ries peaking (8) except that by moving the position of the load
in Fig. 16. The circuits are measured using a Cascade probe impedance, the third denominator term now contains instead
station and an Agilent PNA network analyzer. The differential of . In the earlier sections, we described techniques that give
circuits draw 15 mA from a 2-V supply. The bridged-shunt-se- larger BWER values for . The peaking tech-
ries amplifiers show 14.1 dB gain and 8 GHz bandwidth, and nique of (9) is proposed for ; i.e., where
the asymmetric T-coil design gives 12 dB gain with 10.4 GHz is
bandwidth. Fig. 17 shows measured frequency responses of the
peaked amplifiers relative to the reference amplifier. The mea-
sured BWER factors achieved from the bridged-shunt-series and
asymmetric T-coil amplifiers are 3.0 and 4.1, respectively; the
asymmetric T-coil design yields the largest measured BWER re-
ported so far for a low-pass peaking response. A comparison of (10)
bandwidth extension results is presented in Table IV.
2432 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 17. Measured frequency responses. (a) Bridged-shunt-series (BSS) peaked amplifier with k = 0 4. (b) Bridged-shunt-series (BSS) peaked amplifier with
:
k = 0:5. (c) Asymmetric T-coil (ATC) peaked amplifier with k = 0:3.

TABLE IV
COMPARISON OF BANDWIDTH EXTENSION TECHNIQUES

impedance of rises and the overall gain increases. At , the

ideal inductor resonates with and gives a sharp
peak. Beyond the network is capacitive and a steep roll-off
in gain is observed.
By modifying , the peak frequency is moved relative
to for a given load and ( 0.1). Two possibili-
ties exist to decrease the peaking in the gain response: 1) the
Fig. 18. Proposed series peaking technique with k < 0:1. overall quality factor of the network is decreased, and 2) the
input current source itself is designed for a gain response with
an inverse relationship to the transimpedance of the network.
For , , and with , the The second method is inspired by pre-emphasis techniques that
gain response is shown in Fig. 19. At low frequencies, gain is are used in wireline transceivers for equalization; the technique
constant where the normalized transimpedance is unity. As fre- described above, however, more resembles de-emphasis. Both
quency is increased, the pole created by that sets causes techniques are combined in this work to shape the bandpass re-
the amplitude to roll off. As the frequency approaches , the sponse of a UWB LNA.
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2433

Fig. 19. Simulated normalized responses of proposed series peaking with L ideal, and L including typical parasitic affects in a CMOS implementation
( -model).

VIII. STAGGER-COMPENSATED SERIES PEAKING

FOR A UWB LNA

A. Low- Series-Peaked Network

Utilizing a low- monolithic inductor for decreases the
overall of the network (Fig. 18), which reduces peaking and
broadens the magnitude response. Fig. 19 also shows an ex-
ample of the response when the ideal inductor is
replaced with its parasitic-laden -model . In the final
implementations, a small series resistor is added to
to further reduce its .

B. Stagger-Compensation in a Common-Gate UWB LNA Fig. 20. Proposed series peaking in a common-gate low-noise amplifier with
stagger compensation.
When several narrowband amplifiers with different resonant
frequencies are cascaded, the resulting multi-stage amplifier can
have an overall response that is broadband with adequate gain tire bandwidth. For input matching, the common-source-based
flatness. This is the stagger-tuning technique that has been used UWB LNA has employed bandpass filters with multiple induc-
extensively in distributed amplifiers [22], [23]. Simulation re- tors [8], [24]. Compared to a common-source LNA, a common-
sults have been reported for a two-stage common-source-based gate LNA offers design simplicity, low power, good linearity,
UWB LNA that also employed stagger-tuning [24]. Here, an ap- and a frequency-independent noise factor of
proach is presented wherein stagger-tuning within a single stage (neglecting induced gate noise) where and are empirical
is used to flatten the overall gain response associated with the process- and bias-dependent parameters [25]. The low power
series-peaked -network described above. consumption and negligible frequency-dependence of sug-
An LNA is a critical component in the front-end of a UWB gest that a common-gate topology is amenable to broadband
receiver. It should have low return loss, low noise figure, high applications.
gain across the entire 7.5 GHz UWB band (3.1–10.6 GHz), In a common-gate LNA, the input match condition
and minimum power and die area. For narrowband amplifiers, keeps the size of the transistor small so that the gate-
the source-degenerated common-source LNA is currently more source and gate-drain capacitances also remain small. Thus,
popular than the common-gate LNA because of superior gain is usually smaller than 0.2. The gain of the common-gate LNA
and noise performance at the expense of higher power. Previous depends on the ratio of load to source impedances, . As
implementations of 3.1–10.6 GHz UWB amplifiers have been the value of is fixed (50 ), is necessarily large for high
based on the common-source configuration [8], [24]. To obtain gain. Because a high , together with the total load capaci-
a wideband response, shunt peaking has been used at the load. tance, sets a bandwidth constraint, a technique for bandwidth
By adopting the techniques described in Sections II–IV, a larger extension is needed which has a large BWER for .
BWER is possible which allows an increase in the load resistance Thus, the low- series-peaked network is utilized at the output
and larger gain. as shown in Fig. 20 for a broadband response.
To obtain broadband input matching, the input impedance of As stated before, the input matching is achieved by making
the amplifier should be resistive and equal to 50 over the en- the effective input resistance equal to (50 ); the
2434 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 21. Simulated normalized responses for the LNA of Fig. 20.

Fig. 22. (a) A general g -boosting common-gate LNA, and (b) its capacitor cross-coupled implementation.

total source capacitance is tuned out by a source inductor proper staggering of and . Consider the input network of
at the resonant frequency . and form a shunt par- the common-gate amplifier shown in Fig. 20. It can be shown
allel resonant network with [25]. A low that the normalized input transconductance is
for the input shunt network suggests a possible broadband
impedance match.
For the UWB LNA, dB is needed from (11)
3.1–10.6 GHz. By properly sizing the source inductor
and the input transistor , is optimized to meet this
specification over the entire band. The requirement for a single
inductor for the input match in the common-gate UWB LNA Fig. 21 shows the normalized plots of transconductance re-
gives it an advantage over its common-source counterparts. sponse of the input network, the transimpedance response of the
Because of the low- shunt network, the input match is best low- series-peaked output network, and the overall stagger-
at the resonant frequency and degrades on either side. Note compensated response of the amplifier.
that for a tuned output load, as in a narrowband LNA, this is de-
sirable because the gain is maximum at the desired operating C. Design Considerations for a -Boosted
frequency, and lower at other frequencies, thus giving a highly Stagger-Compensated UWB LNA
selective response. However, for a broadband response where
the load is resistive, there is a significant roll-off in the transcon- For a common-gate LNA, significant improvement in is
ductance gain after . We utilize this roll-off for canceling the achieved through the use of -boosting [26]. Fig. 22(a) shows
peaking at in the transimpedance gain at the output, as well as a -boosted common-gate LNA, where an inverting gain of
to flatten the overall gain of the amplifier. This is done through between the source and the gate terminals reduces the power
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2435

Fig. 23. A UWB LNA employing stagger-compensated series peaking (DC biasing not shown).

consumption by a factor , and simultaneously improves larger than the resonant frequency of the input-matching net-
to work . As the input match deviates from the
input source impedance beyond , the effective gate-source
voltage decreases so that peaking at is suppressed and an ef-
(12) fective compensation is achieved in a single-stage configuration.
To facilitate testing, a buffer is needed to drive the off-chip
for and input matching condition 50- load. A unity-gain common-source stage is chosen for the
. An inverting gain of unity is easily realized in a buffer. Its initial bandwidth (about 7.5 GHz) falls short of the
differential configuration by capacitor cross-coupling the two core LNA bandwidth, but shunt peaking using a slab inductor
branches [Fig. 22(b)] [27]. The inverting gain is approximately is sufficient to extend it. A slab inductor is used because the
, where and are the coupling and required inductance is small and substantial area is saved. In
gate-source capacitances, respectively. By making , the actual implementation of a complete receiver front-end, this
, and induced gate noise is negligible. buffer is not needed. Care is taken to ensure a gain of near unity
A schematic of the -boosted stagger-compensated UWB over its maximum bandwidth for accurate gain-flatness charac-
LNA is shown in Fig. 23. The input match condition sets terization of the LNA. The value of coupling capacitor in
of , and linearity determines its overdrive voltage Fig. 23 is also carefully chosen. A large value of adds to the
. With knowledge of and the overdrive voltage, overall parasitic capacitance at the output node, affecting the
of is determined. Minimum channel length (0.18 m) overall bandwidth. A small value, on the other hand, has signif-
is chosen for all devices due to noise and considerations. icant ac impedance that leads to reduced gain.
With the transistor size and overdrive known, the supply current After choosing the component values from the above design
and the gate capacitance are easily calculated. Next, total source flow, the design is then optimized to maximize bandwidth, gain,
capacitance is determined from and the pad capaci- gain-flatness and input matching; a clear trade-off is observed
tance . (Another advantage of a common-gate topology is between bandwidth and gain-flatness. is maintained better
that it is easy to absorb into the total source capacitance than 13 dB over the UWB band (3.1–10.6 GHz). and
). The resonant frequency of the input tank is chosen are of equal sizes to trade off gain and optimal for NF and
next, and an estimate of is obtained. The desired gain dic- the parasitic capacitance at the drain of . A small series re-
tates the value of ; as also sets the dominant pole fre- sistor ( , not shown in Fig. 23) is added to to trade
quency, it cannot be arbitrarily high. A cascode transistor is off gain-flatness for a slight degradation in gain and NF. Finally,
added to improve reverse isolation. The size of determines a shunt peaking inductor is added at the output (Fig. 23) to
the drain parasitic capacitance . If the width of equals reduce the roll-off in the gain response between and , for
that of , their source and drain nodes can be merged which which simulations show an improvement of 0.3–0.8 dB in the
reduces parasitic capacitance. This avoids the deterioration of roll-off. This improvement is traded off against silicon area, and
bandwidth and noise figure. On the other hand, sizing dif- is expendable if area is the major concern. Finally (not imple-
ferently from gives another degree of freedom to optimize mented in this work), the use of symmetric center-tapped in-
gain and . With the knowledge of , , and load capaci- ductors is suggested for and , as well as the use of 3-D
tance , is determined. Next, the series-peaked network is inductors for and for area savings.
added to the load (Fig. 23). To introduce staggering to flatten In a narrowband -boosted common-gate LNA [26], [27],
the overall gain response and achieve a large BWER, is kept the input and output are matched to the same resonant frequency,
2436 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 24. Measured S -parameters of LNA #1. Fig. 26. Measured noise figures of the two versions of the UWB LNA.

Fig. 25. Measured S -parameters of LNA #2. Fig. 27. Measured IIP3 of the two versions of the UWB LNA.

and the main contribution to the overall NF comes from

(Fig. 22). In the proposed UWB LNA (Fig. 23), the input and
output resonances are staggered. Although (12) is valid at the
resonance frequency of the input shunt network where
, the input match is kept better than 10 dB
throughout the UWB band so that the in-band deviation in the
NF is maintained at a low value. Although is still the dom-
inant source of noise, the load resistor , cascode device ,
peaking inductor , and its series resistance , source-inductor
, and the unity-gain buffer all contribute to the overall NF.

IX. MEASUREMENT RESULTS OF UWB LNA Fig. 28. Chip microphotographs. (a) LNA #1. (b) LNA #2.
Two versions of the UWB LNA are fabricated in a six-metal
0.18- m RF CMOS process. Figs. 24 and 25 show typical mea-
sured -parameter responses. Before extension, the BW of LNA (5.5 dB) at 3.1 GHz (12.25 GHz), and the average over the
#1 as determined by simulations using layout-extracted load re- corresponding 3 dB BW is 4.75 dB (4.98 dB).
sistance (190 ) and node capacitance (320 fF) values is Fig. 27 shows the two-tone IIP3 values across the 3 dB
GHz; for LNA #2, GHz. (Experience with sim- bandwidths; the minimum and maximum values are 7.4 dBm
ilar amplifiers shows agreement within 5% between such sim- (7.6 dBm) and 8.3 dBm (9.1 dBm), respectively. Power con-
ulated and measured values.) To move the second peak sumption in the differential cores is only 4.5 mW. Thus, trade-
to a higher frequency in LNA #2, is reduced and and offs among BW, gain flatness, and NF are illustrated in the two
are optimized. The measured upper 3 dB BW of LNA #1 versions.
(#2) is 10.7 GHz (12.26 GHz) corresponding to a BWER of 4.1 The UWB LNA using the stagger-compensated series-
(4.9). peaks at 8.5 dB (8.2 dB) with 2.4 dB (3.0 dB) in-band peaking technique achieves a measured BWER of 4.9. More gen-
gain variation; is better than 10 dB between 2.8–10.8 GHz erally, the new topology also exhibits superior figure-of-merit
(2.7–11 GHz), and is better than 10 dB up to 10.3 GHz (FOM) performance (Table V):
(11 GHz).
NF performance is plotted in Fig. 26; the minimum is 4.4 dB
(13)
(4.6 dB) at 6.25 GHz (6.25 GHz), the maximum is 5.3 dB
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2437

TABLE V
WIDEBAND LNA PERFORMANCE COMPARISON

Note: LNA #1, LNA #2, and [31] are differential LNAs; hence, their differential power, area, and FOMs are given.

Further improvements in this design are expected though the use TABLE VI
of aggressive optimization methods [16]. Fig. 28 shows a chip COMPARISON OF DC INDUCTANCES FROM GROVER CALCULATIONS
area including pads of 1 mm for each version. The layouts are VERSUS ELECTROMAGNETIC SIMULATIONS
similar, with the main difference being the sizes of the active
and passive devices.

X. CONCLUSION
CMOS implementations of the bridged-shunt-series and
asymmetric T-coil-peaked amplifiers demonstrate a trade off
between delay and gain flatness to achieve measured BWER
each loop, using standard Grover calculations [29] yielding an
values up to 4.1. Wide bandwidth is achieved simultaneously
inductance matrix:
with high gain, which means fewer stages with concomi-
tant power and area advantages. Another important result
is that different approaches achieve maximum BWER for
different values: specifically, bridged-shunt-series is best
for and the asymmetric T-coil is best for (14)
.
A fully integrated common-gate UWB LNA employs a
stagger-compensated series-peaking technique in a single
stage, applicable for , to extend bandwidth, and a Here, is the total number of complete windings with the diag-
capacitor cross-coupled -boosting technique to reduce NF onal elements representing and all others representing .
and power. A simple input-matching scheme obviates the use With the knowledge of the structure (i.e., which rings belong to
of multiple inductors and complex filters. Two versions in the secondary, which belong to the primary, etc.), summation of
0.18- m CMOS show BWER factors of 4.1 and 4.9 and the the elements of , along with the elements of of the pri-
highest reported FOMs. mary loops, yields . is calculated similarly. To estimate
, the sum of the mutual inductive elements that consist of a
APPENDIX loop of the primary to a loop of the secondary is computed:
Electromagnetic simulations are necessary because accu-
rate characterization of the inductor is critical, not only for
estimation of the winding inductances, (primary) and
(secondary), but also for estimation of and associated ca-
pacitive and resistive parasitics. To decrease the relatively long (15)
simulation times associated with complex electromagnetic field The calculations can be made quickly based upon the physical
solvers, a two-step design cycle is adopted to insure accurate dimensions of the spiral structure, along with quick estimates for
characterization of the inductors and maintain a shorter design parasitic resistive and capacitive elements. With these estimates,
cycle. In the first step, the inductance is estimated using a the second step is electromagnetic simulation albeit with fewer
concentric windings approximation [28], by breaking down the iterations. A comparison of these inductance values to the DC
inductors into concentric rings. The partial self-inductances estimates in Table VI shows that errors in the inductance values
and mutual-inductances are then calculated for at DC are less than 10%.
2438 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

ACKNOWLEDGMENT [21] D. M. Pozar, Microwave Engineering, 2nd ed. New York: Wiley,
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Radio Frequency Integrated Circuits Symp., Jun. 2006, pp. 63–66. (Hons.) in electronics and communications engi-
[10] S. S. Mohan, M. D. M. Hershenson, S. P. Boyd, and T. H. Lee, “Band- neering from the Indian Institute of Technology,
width extension in CMOS with optimized on-chip inductors,” IEEE J. Kharagpur, in 2003. He received the M.S. degree
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Washington, Seattle, in 2005, where he is currently
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intern with Intel Corporation, Hillsboro, OR, where
IRE, pp. 1271–1276, Aug. 1954. he worked on the modeling and design of serial
[13] B. Analui and A. Hajimiri, “Bandwidth enhancement for trans- links. His current research interests include RF
impedance amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. transceivers, frequency synthesizers and mixed-signal circuits for high-speed
1263–1270, Aug. 2004. I/O interfaces.
[14] C.-H. Wu, C.-H. Lee, and S.-I. Liu, “CMOS wideband amplifiers using Mr. Shekhar is a recipient of the Intel Foundation Ph.D. Fellowship for
multiple inductive-series peaking technique,” IEEE J. Solid-State Cir- 2006–2007.
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CMOS RF Circuits. Norwell, MA: Kluwer Academic, 2003. Jeffrey S. Walling (S’03) received the B.S. degree
from the University of South Florida, Tampa, in
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2000, and the M.S. degree from the University of
CMOS technology,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.
Washington, Seattle, in 2005, both in electrical
2334–2340, Dec. 2003.
engineering. He is currently working toward the
[18] S. S. Mohan, C. P. Yue, M. D. M. Hershenson, S. S. Wong, and T. Ph.D. degree at the University of Washington.
H. Lee, “Modeling and characterization of on-chip transformers,” in Prior to starting his graduate education, he was
IEDM Tech. Dig., Dec. 1998, pp. 531–534. with Motorola, Plantation, FL, working in cellular
[19] A. C. Watson, D. Melendy, P. Francis, K. Hwang, and A. Weisshaar, “A handset development. He interned for Intel, Hills-
comprehensive compact-modeling methodology for spiral inductors in boro, OR, in the summer of 2006, where he worked
silicon-based RFICs,” IEEE Trans. Microw. Theory Tech., vol. 52, no. on highly digital transmitter architectures. He is
3, pp. 849–857, Mar. 2004. currently with the University of Washington, where his research interests
[20] D. E. Bockelman and W. R. Eisenstadt, “Combined differential and include high-efficiency transmitter architectures and power amplifier design.
common-mode scattering parameters: Theory and simulation,” IEEE Mr. Walling was a recipient of the Analog Devices Outstanding Student De-
Trans. Microw. Theory Tech., vol. 43, no. 7, pp. 1530–1539, Jul. 1995. signer Award in 2006.
SHEKHAR et al.: BANDWIDTH EXTENSION TECHNIQUES FOR CMOS AMPLIFIERS 2439

David J. Allstot (S’72–M’72–SM’83–F’92) re- CAS-S, and the 2005 Aristotle Award of the Semiconductor Research Corpo-
ceived the B.S. degree from the University of ration. He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS
Portland, Portland, OR, the M.S. degree from AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING from 1990 to
Oregon State University, Corvallis, and Ph.D. degree 1993 and its Editor from 1993 to 1995. He was on the Technical Program Com-
from the University of California, Berkeley. mittee, IEEE Custom Integrated Circuits Conference, from 1990–1993, Edu-
He has held several industrial and academic cation Award Committee, IEEE CAS-S, from 1990 to 1993, Board of Gover-
positions and has been the Boeing-Egtvedt Chair nors, IEEE CAS-S, from 1992 to 1995, Technical Program Committee, IEEE
Professor of Engineering at the University of International Symposium on Low-Power Electronics and Design, from 1994
Washington, Seattle, since 1999. He is currently to 1997, Mac Van Valkenberg Award Committee, IEEE CAS-S, from 1994 to
the Chair of Electrical Engineering. He has advised 1996, and Technical Program Committee, IEEE ISSCC, from 1994 to 2004.
approximately 80 M.S. and Ph.D. graduates and He was the 1995 Special Sessions Chair, IEEE International Symposium on
published about 225 papers. CAS (ISCAS), an Executive Committee Member and the Short Course Chair,
Dr. Allstot is a Member of Eta Kappa Nu and Sigma Xi. He has received ISSCC, from 1996–2000, Co-Chair, IEEE Solid-State Circuits (SSC) and Tech-
several outstanding teaching and advising awards. Other awards include the nology Committee, from 1996 to 1998, Distinguished Lecturer, IEEE CAS-S,
1978 IEEE W.R.G. Baker Prize Paper Award, 1995 IEEE Circuits and Sys- from 2000–2001, Distinguished Lecturer, IEEE SSC Society, from 2006–2007,
tems Society (CAS-S) Darlington Best Paper Award, 1998 IEEE International and the Co-General Chair, IEEE ISCAS in 2002.
Solid-State Circuits Conference (ISSCC) Beatrice Winner Award, 1999 IEEE
CAS-S Golden Jubilee Medal, 2004 Technical Achievement Award of the IEEE