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PRELIMINARY CY28447
Clock Generator for Intel® Calistoga Chipset

Features • 33 MHz PCI clocks

• Buffered Reference Clock 14.318MHz
• Compliant to Intel® CK410M
• Low-voltage frequency select inputs
• Selectable CPU frequencies
• I2C support with readback capabilities
• Differential CPU clock pairs
• Ideal Lexmark Spread Spectrum profile for maximum
• 100 MHz differential SRC clocks electromagnetic interference (EMI) reduction
• 96 MHz differential dot clock • 3.3V power supply
• 27 MHz Spread and Non-spread video clock • 72-pin QFN package
• 48 MHz USB clock
CPU SRC PCI REF DOT96 USB_48M LCD 27M
• SRC clocks independently stoppable through
CLKREQ#[1:9] x2 / x3 x9/11 x5 x2 x1 x1 x1 x2

• 96/100 MHz spreadable differential video clock

Block Diagram Pin Configuration

CLKREQ9#
CLKREQ8#

CLKREQ6#

CLKREQ4#
VDD_SRC
VDD

VSS_SRC
XIN 14.318MHz

SRCC_8

SRCC_7

SRCC_6

SCRC_5

SCRC_4

SRCC_3
SRCT_8

SRCT_7

SRCT_6

SRCT_5

SRCT_4

SRCT_3
Crystal REF[1:0]
XOUT PLL Reference
IREF
SEL_CLKREQ VDD
PCI_STP# CPU CPUT[0:1] 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

CPU_STP# PLL Divider CPUC[0:1] VDD_SRC 1 54 VDD_SRC

VDD SRCC_9 2 53 SRCC_2
CLKREQ[1:9]#
CPUT2_ITP/SRCT10 SRCT_9 3 52 SRCT_2
ITP_SEL CPUC2_ITP/SRCC10 VSS_SRC 4 51 SRCC_1
VDD CPUC2_ITP / SRCC_10 5 50 SRCT_1
FS[C:A]
SRCT(1:9]) CPUT2_ITP / SRCT_10 6 49 VDD_SRC
SRCC(1:9]) VDDA 7 48 SRCC_0 / LCD100MC
VSSA 8 47 SRCT_0 / LCD100MT
VDD
IREF 9 CY28447 46 CLKREQ1#
PCI[1:4]
CPUC1 10 45 FSB/TEST_MODE
VDD_PCI CPUT1 11 44 DOT96C / 27M_SS
PCIF0 VDD_CPU 12 43 DOT96T / 27M_NSS
VDD CPUC0 13 42 VSS_48
LVDS SRCT0/100MT_SST CPUT0 14 41 48M / FSA
Divider SRCC0/100MC_SST VSS_CPU 15 40 VDD_48
PLL
VDD48 SCLK 16 39 VTT_PWRGD# / PD
27MSpread SDATA 17 38 CLKREQ7#
FCTSEL1
VDD_REF 18 37 PCIF0/ITP_SEL
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VDD48
Fixed DOT96T
XIN
XOUT

VSS_REF
REF1

CLKREQ2#
PCI1
CLKREQ3#
CLKREQ5#
VDD_PCI
VSS_PCI
PCI2
PCI3

VSS_PCI
VDD_PCI
CPU_STP#
PCI_STP#

PCI4 / FCTSEL1
REF0 / FSC_TEST_SEL

PLL
Divider
DOT96C
VDD48
48M
27M
PLL
Divider VDD48
VTT_PWRGD#/PD 27MNon-spread

SDATA I2C
SCLK Logic

Rev 1.0, November 20, 2006 Page 1 of 21

2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com
 CY28447

Pin Description
Pin No. Name Type Description
1, 49, 54, 65 VDD_SRC PWR 3.3V power supply for outputs.
2, 3, 50, 51, SRCT/C[1:9] O, DIF 100 MHz Differential serial reference clocks.
52, 53, 55,
56, 58, 59,
60, 61, 63,
64, 66, 67,
69, 70
4, 68 VSS_SRC GND Ground for outputs.
5, 6 CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC10 ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
7 VDDA PWR 3.3V power supply for PLL.
8 VSSA GND Ground for PLL.
9 IREF I A precision resistor is attached to this pin which is connected to the internal
current reference.
10, 11, 13, 14 CPUT/C[0:1] O, DIF Differential CPU clock outputs.
12 VDD_CPU PWR 3.3V power supply for outputs.
15 VSS_CPU GND Ground for outputs.
16 SCLK I SMBus-compatible SCLOCK.
17 SDATA I/O, OD SMBus-compatible SDATA.
18 VDD_REF PWR 3.3V power supply for outputs.
19 XOUT O, SE 14.318 MHz crystal output.
20 XIN I 14.318 MHz crystal input.
21 VSS_REF GND Ground for outputs.
22 REF1 O Fixed 14.318 MHz clock output.
23 REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is
asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active LOW.
25 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active LOW.
26, 28, 29, CLKREQ[1:9]# I, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW).
38, 46, 57,
62, 71, 72
27, 32, 33 PCI[1:3] O, SE 33 MHz clock outputs
30, 36 VDD_PCI PWR 3.3V power supply for outputs.
31, 35 VSS_PCI GND Ground for outputs.
34 PCI4/FCTSEL1 I/O, PD 33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).

FCTS E L1 P in 43 P in 44 P in 47 P in 48
0 DOT96T DOT96C 96/100M_T 96/100M_C
1 27M_NSS 27M_SS SRCT0 SRCC0

37 ITP_SEL/PCIF0 I/O, PD, 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
SE (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10

Rev 1.0, November 20, 2006 Page 2 of 21

 CY28447

Pin Description (continued)

Pin No. Name Type Description
39 VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FSA, FSB,
FSC, FCTSEL1, and ITP_SEL. After VTT_PWRGD# (active LOW) assertion, this
pin becomes a real-time input for asserting power down (active HIGH).
40 VDD_48 PWR 3.3V power supply for outputs.
41 48M/FSA I/O Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
42 VSS_48 GND Ground for outputs.
43, 44 DOT96T/ 27M_NSS O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output
DOT96C/ 27M_SS Selected via FCTSEL1 at VTTPWRGD# assertion.
45 FSB/TEST_MODE I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48 SRC[T/C]0/ O,DIF 100 MHz differential serial reference clock output / Differential 96/100-MHz
LCD100M[T/C] SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD# assertion.

Frequency Select Pins (FSA, FSB, and FSC) initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
Host clock frequency selection is achieved by applying the are normally made upon system initialization, if any are
appropriate logic levels to FSA, FSB, FSC inputs prior to required. The interface cannot be used during system
VTT_PWRGD# assertion (as seen by the clock synthesizer). operation for power management functions.
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip Data Protocol
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a The clock driver serial protocol accepts byte write, byte read,
one-shot functionality in that once a valid LOW on block write, and block read operations from the controller. For
VTT_PWRGD# has been sampled, all further VTT_PWRGD#, block write/read operation, the bytes must be accessed in
FSA, FSB, and FSC transitions will be ignored, except in test sequential order from lowest to highest byte (most significant
mode. bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
Serial Data Interface system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
To enhance the flexibility and function of the clock synthesizer, as described in Table 2.
a two-signal serial interface is provided. Through the Serial The block write and block read protocol is outlined in Table 3
Data Interface, various device functions, such as individual while Table 4 outlines the corresponding byte write and byte
clock output buffers, can be individually enabled or disabled. read protocol. The slave receiver address is 11010010 (D2h)
The registers associated with the Serial Data Interface
Table 1. Frequency Select Table FSA, FSB, and FSC[1]
FSC FSB FSA CPU SRC PCIF/PCI 27MHz REF0 DOT96 USB
1 0 1 100 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz
0 0 1 133 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz
0 1 1 166 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz
0 1 0 200 MHz 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz
.

Table 2. Command Code Definition

Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Note:
1. 27-MHz and 96-MHz can not be output at the same time.

Rev 1.0, November 20, 2006 Page 3 of 21

 CY28447

Table 3. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count – 8 bits 20 Repeat start
(Skip this step if I2C_EN bit set)
28 Acknowledge from slave 27:21 Slave address – 7 bits
36:29 Data byte 1 – 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2 – 8 bits 37:30 Byte Count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte/Slave Acknowledges 46:39 Data byte 1 from slave – 8 bits
.... Data Byte N – 8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave – 8 bits
.... NOT Acknowledge
.... Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1 Start 1 Start
8:2 Slave address – 7 bits 8:2 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code – 8 bits 18:11 Command Code – 8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte – 8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address – 7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave – 8 bits
38 NOT Acknowledge
39 Stop

Rev 1.0, November 20, 2006 Page 4 of 21

 CY28447

Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 1 SRC[T/C]7 SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
6 1 SRC[T/C]6 SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
5 1 SRC[T/C]5 SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
4 1 SRC[T/C]4 SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
3 1 SRC[T/C]3 SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
2 1 SRC[T/C]2 SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
1 1 SRC[T/C]1 SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
0 1 SRC[T/C]0 SRC[T/C]0 / LCD_96_100M[T/C] Output Enable
/LCD_96_100M[T/C] 0 = Disable (Hi-Z), 1 = Enable

Byte 1: Control Register 1

Bit @Pup Name Description
7 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6 1 27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
5 1 USB_48MHz USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
4 1 REF0 REF0 Output Enable
0 = Disabled, 1 = Enabled
3 1 REF1 REF1 Output Enable
0 = Disabled, 1 = Enabled
2 1 CPU[T/C]1 CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
1 1 CPU[T/C]0 CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
0 0 CPU, SRC, PCI, PCIF PLL1 (CPU PLL) Spread Spectrum Enable
Spread Enable 0 = Spread off, 1 = Spread on

Byte 2: Control Register 2

Bit @Pup Name Description
7 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
6 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
5 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
3 1 Reserved Reserved, Set = 1
2 1 Reserved Reserved, Set = 1
1 1 CPU[T/C]2 CPU[T/C]2 Output Enable
0 = Disabled (Hi-Z), 1 = Enabled
0 1 Reserved Reserved, Set = 1

Rev 1.0, November 20, 2006 Page 5 of 21

 CY28447

Byte 3: Control Register 3

Bit @Pup Name Description
7 0 SRC7 Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6 0 SRC6 Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5 0 SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4 0 SRC4 Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3 0 SRC3 Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2 0 SRC2 Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1 0 SRC1 Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0 0 SRC0 Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 LCD_96_100M[T/C] LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6 0 DOT96[T/C] DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5 0 RESERVED RESERVED, Set = 0
4 0 RESERVED RESERVED, Set = 0
3 0 PCIF0 Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2 1 CPU[T/C]2 Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1 1 CPU[T/C]1 Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0 1 CPU[T/C]0 Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 SRC[T/C] SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
3 0 SRC[T/C][9:1] SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted

Rev 1.0, November 20, 2006 Page 6 of 21

 CY28447

Byte 5: Control Register 5 (continued)

Bit @Pup Name Description
1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 TEST_SEL REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6 0 TEST_MODE Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
5 1 REF1 REF1 Output Drive Strength
0 = Low, 1 = High
4 1 REF0 REF0 Output Drive Strength
0 = Low, 1 = High
3 1 PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert
to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2 HW FSC FSC Reflects the value of the FSC pin sampled on power up
0 = FSC was low during VTT_PWRGD# assertion
1 HW FSB FSB Reflects the value of the FSB pin sampled on power up
0 = FSB was low during VTT_PWRGD# assertion
0 HW FSA FSA Reflects the value of the FSA pin sampled on power up
0 = FSA was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Revision Code Bit 3 Revision Code Bit 3
6 0 Revision Code Bit 2 Revision Code Bit 2
5 0 Revision Code Bit 1 Revision Code Bit 1
4 1 Revision Code Bit 0 Revision Code Bit 0
3 1 Vendor ID Bit 3 Vendor ID Bit 3
2 0 Vendor ID Bit 2 Vendor ID Bit 2
1 0 Vendor ID Bit 1 Vendor ID Bit 1
0 0 Vendor ID Bit 0 Vendor ID Bit 0
Byte 8: Control Register 8
Bit @Pup Name Description
7 0 RESERVED RESERVED, Set = 0
6 0 RESERVED RESERVED, Set = 0
5 0 RESERVED RESERVED, Set = 0
4 0 RESERVED RESERVED, Set = 0
3 0 RESERVED RESERVED, Set = 0
2 1 USB_48M USB_48MHz Output Drive Strength
0= Low, 1= High
1 1 RESERVED RESERVED, Set = 1
0 1 PCIF0 PCIF0 Output Drive Strength
0 = Low, 1 = High

Rev 1.0, November 20, 2006 Page 7 of 21

 CY28447

Byte 9: Control Register 9

Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
27M_SS / LCD 96_100M SS Spread Spectrum Selection table:
5 0 S1 S[1:0] SS%
4 0 S0 ‘00’ = –0.5%(Default value)
‘01’ = –1.0%
‘10’ = –1.5%
‘11’ = –2.0%
3 1 RESERVED RESERVED, Set = 1
2 1 27M_SS 27M Spread Output Enable
0 = Disable (Tri-state), 1 = Enabled
1 1 27M_SS Spread Enable 27M_SS Spread spectrum enable.
0 = Disable, 1 = Enable.
0 0 RESERVED RESERVED set = 0

Byte 10: Control Register 10

Bit @Pup Name Description
7 1 RESERVED RESERVED, Set = 1
6 1 RESERVED RESERVED, Set = 1
5 1 SRC[T/C]9 SRC[T/C]9 Output Enable
0 = Disable (Hi-Z), 1 = Enable
4 1 SRC[T/C]8 SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
3 0 RESERVED RESERVED, Set = 0
2 0 SRC[T/C]10 Allow control of SRC[T/C]10 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1 0 SRC[T/C]9 Allow control of SRC[T/C]9 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0 0 SRC[T/C]8 Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 11: Control Register 11
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 HW RESERVED RESERVED
5 HW RESERVED RESERVED
4 HW RESERVED RESERVED
3 0 27M_SS / 27M_NSS 27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED Set = 0
0 HW RESERVED RESERVED

Rev 1.0, November 20, 2006 Page 8 of 21

 CY28447

Byte 12: Control Register 12

Bit @Pup Name Description
7 0 CLKREQ#9 CLKREQ#9 Input Enable
0 = Disable 1 = Enable
6 0 CLKREQ#8 CLKREQ#8 Input Enable
0 = Disable 1 = Enable
5 0 CLKREQ#7 CLKREQ#7 Input Enable
0 = Disable 1 = Enable
4 0 CLKREQ#6 CLKREQ#6 Input Enable
0 = Disable 1 = Enable
3 0 CLKREQ#5 CLKREQ#5 Input Enable
0 = Disable 1 = Enable
2 0 CLKREQ#4 CLKREQ#4 Input Enable
0 = Disable 1 = Enable
1 0 CLKREQ#3 CLKREQ#3 Input Enable
0 = Disable 1 = Enable
0 0 CLKREQ#2 CLKREQ#2 Input Enable
0 = Disable 1 = Enable
Byte 13: Control Register 13
Bit @Pup Name Description
7 0 CLKREQ#1 CLKREQ#1 Input Enable
0 = Disable 1 = Enable
6 1 LCD 96_100M Clock LCD 96_100M Clock Speed
Speed 0 = 96 MHz 1 = 100 MHz
5 1 RESERVED RESERVED, Set = 1
4 1 RESERVED RESERVED, Set = 1
3 1 PCI4 PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
2 1 PCI3 PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
1 1 PCI2 PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
0 1 PCI1 PCI1 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High

Table 5. Crystal Recommendations

Frequency Drive Shunt Cap Motional Tolerance Stability Aging
(Fund) Cut Loading Load Cap (max.) (max.) (max.) (max.) (max.) (max.)
14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm

The CY28447 requires a Parallel Resonance Crystal. Substi- the crystal will see must be considered to calculate the appro-
tuting a series resonance crystal will cause the CY28447 to priate capacitive loading (CL).
operate at the wrong frequency and violate the ppm specifi- Figure 1 shows a typical crystal configuration using the two
cation. For most applications there is a 300-ppm frequency trim capacitors. An important clarification for the following
shift between series and parallel crystals due to incorrect discussion is that the trim capacitors are in series with the
loading. crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
Crystal Loading approximately equal to the load capacitance of the crystal.
Crystal loading plays a critical role in achieving low ppm perfor- This is not true.
mance. To realize low ppm performance, the total capacitance

Rev 1.0, November 20, 2006 Page 9 of 21

 CY28447

(Ce1,Ce2) should be calculated to provide equal capacitance

loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)

Total Capacitance (as seen by the crystal)

Figure 1. Crystal Capacitive Clarification 1
CLe = 1 1
( Ce1 + Cs1 + Ci1 + Ce2 + Cs2 + Ci2
)
Calculating Load Capacitors
CL....................................................Crystal load capacitance
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to CLe......................................... Actual loading seen by crystal
correctly calculate crystal loading. As mentioned previously, using standard value trim capacitors
the capacitance on each side of the crystal is in series with the Ce..................................................... External trim capacitors
crystal. This means the total capacitance on each side of the Cs .............................................. Stray capacitance (terraced)
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in Ci ...........................................................Internal capacitance
series with the crystal, trim capacitors (Ce1,Ce2) should be (lead frame, bond wires etc.)
calculated to provide equal capacitive loading on both sides.
CLK_REQ# Description
Clock Chip The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
Ci1 Ci2 register byte 8. The CLKREQ# signal is a de-bounced signal
Pin in that it’s state must remain unchanged during two consec-
3 to 6p utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
X1 X2 CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
Cs1 Cs2
All differential outputs that were stopped are to resume normal
Trace operation in a glitch-free manner. The maximum latency from
2.8 pF
XTAL
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven HIGH
Ce1 Ce2 Trim within 10 ns of CLKREQ# deassertion to a voltage greater than
33 pF 200 mV.
Figure 2. Crystal Loading Example CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)

As mentioned previously, the capacitance on each side of the The impact of deasserting the CLKREQ# pins is that all SRC
crystal is in series with the crystal. This means the total capac- outputs that are set in the control registers to stoppable via
itance on each side of the crystal must be twice the specified deassertion of CLKREQ# are to be stopped after their next
load capacitance (CL). While the capacitance on each side of transition. The final state of all stopped DIF signals is LOW,
the crystal is in series with the crystal, trim capacitors both SRCT clock and SRCC clock outputs will not be driven.

CLKREQ#X

SRCT(free running)

SRCC(free running)

SRCT(stoppable)

SRCT(stoppable)

Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform

Rev 1.0, November 20, 2006 Page 10 of 21

 CY28447

PD (Power-down) Clarification bit corresponding to the output of interest is programmed to

The VTT_PWRGD# /PD pin is a dual-function pin. During “1”, then both the “Diff clock” and the “Diff clock#” are tri-state.
initial power-up, the pin functions as VTT_PWRGD#. Once Note that Figure 4 shows CPUT = 133 MHz and PD drive
VTT_PWRGD# has been sampled LOW by the clock chip, the mode = ‘1’ for all differential outputs. This diagram and
pin assumes PD functionality. The PD pin is an asynchronous description is applicable to valid CPU frequencies 100, 133,
active HIGH input used to shut off all clocks cleanly prior to 166, and 200 MHz. In the event that PD mode is desired as
shutting off power to the device. This signal is synchronized the initial power-on state, PD must be asserted HIGH in less
internal to the device prior to powering down the clock synthe- than 10 μs after asserting Vtt_PwrGd#. It should be noted that
sizer. PD is also an asynchronous input for powering up the 96_100_SSC will follow the DOT waveform is selected for
system. When PD is asserted HIGH, all clocks need to be 96 MHz and the SRC waveform when in 100-MHz mode.
driven to a LOW value and held prior to turning off the VCOs PD Deassertion
and the crystal oscillator.
The power-up latency is less than 1.8 ms. This is the time from
PD (Power-down) Assertion the deassertion of the PD pin or the ramping of the power
When PD is sampled HIGH by two consecutive rising edges supply until the time that stable clocks are output from the
of CPUC, all single-ended outputs will be held LOW on their clock chip. All differential outputs stopped in a three-state
next HIGH-to-LOW transition and differential clocks must be condition resulting from power down will be driven high in less
held HIGH or tri-stated (depending on the state of the control than 300 μs of PD deassertion to a voltage greater than
register drive mode bit) on the next diff clock# HIGH-to-LOW 200 mV. After the clock chip’s internal PLL is powered up and
transition within 4 clock periods. When the SMBus PD drive locked, all outputs will be enabled within a few clock cycles of
mode bit corresponding to the differential (CPU, SRC, and each other. Figure 5 is an example showing the relationship of
DOT) clock output of interest is programmed to ‘0’, the clock clocks coming up. It should be noted that 96_100_SSC will
outputs are held with “Diff clock” pin driven HIGH at 2 x Iref, follow the DOT waveform is selected for 96 MHz and the SRC
and “Diff clock#” tri-state. If the control register PD drive mode waveform when in 100-MHz mode.

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 4. Power-down Assertion Timing Waveform

Tstable
<1.8 ms
PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33MHz
Tdrive_PWRDN#
REF <300 μs, >200 mV

Figure 5. Power-down Deassertion Timing Waveform

Rev 1.0, November 20, 2006 Page 11 of 21

 CY28447

CPU_STP# Assertion CPUT is driven HIGH with a current value equal to 6 x (Iref),
The CPU_STP# signal is an active LOW input used for and the CPUC signal will be tri-stated.
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function. CPU_STP# Deassertion
When the CPU_STP# pin is asserted, all CPU outputs that are The deassertion of the CPU_STP# signal will cause all CPU
set with the SMBus configuration to be stoppable via assertion outputs that were stopped to resume normal operation in a
of CPU_STP# will be stopped within two–six CPU clock synchronous manner, synchronous manner meaning that no
periods after being sampled by two rising edges of the internal short or stretched clock pulses will be produce when the clock
CPUC clock. The final states of the stopped CPU signals are resumes. The maximum latency from the deassertion to active
CPUT = HIGH and CPUC = LOW. There is no change to the outputs is no more than two CPU clock cycles.
output drive current values during the stopped state. The

CPU_STP#

CPUT

CPUC

Figure 6. CPU_STP# Assertion Waveform

CPU_STP#

CPUT

CPUC

CPUT Internal

CPUC Internal

Tdrive_CPU_STP#,10 ns>200 mV

Figure 7. CPU_STP# Deassertion Waveform

1.8 ms

CPU_STOP#

PD

CPUT(Free Running

CPUC(Free Running

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven

Rev 1.0, November 20, 2006 Page 12 of 21

 CY28447

1.8mS

CPU_STOP#

PD

CPUT(Free Running)

CPUC(Free Running)

CPUT(Stoppable)

CPUC(Stoppable)

DOT96T

DOT96C

Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state

PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running.

Tsu
PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 10. PCI_STP# Assertion Waveform

Rev 1.0, November 20, 2006 Page 13 of 21

 CY28447

PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
Tsu Tdrive_SRC

PCI_STP#

PCI_F

PCI

SRC 100MHz

Figure 11. PCI_STP# Deassertion Waveform

FS_A, FS_B,FS_C

VTT_PW RGD#

PW RGD_VRM

0.2-0.3mS W ait for Sample Sels Device is not affected,

VDD Clock Gen
Delay VTT_PW RGD# VTT_PW RGD# is ignored

Clock State State 0 State 1 State 2 State 3

Off On
Clock Outputs

Off On
Clock VCO

Figure 12. VTT_PWRGD# Timing Diagram

S1 S2

Delay VTT_PWRGD# = Low Sample

>0.25mS Inputs straps

VDD_A = 2.0V

Wait for <1.8ms

S0 S3
VDD_A = off Normal Enable Outputs
Power Off Operation

VTT_PWRGD# = toggle

Figure 13. Single-ended Load Configuration

Rev 1.0, November 20, 2006 Page 14 of 21

 CY28447

Absolute Maximum Conditions

Parameter Description Condition Min. Max. Unit
VDD Core Supply Voltage –0.5 4.6 V
VDD_A Analog Supply Voltage –0.5 4.6 V
VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC
TS Temperature, Storage Non-functional –65 150 °C
TA Temperature, Operating Ambient Functional 0 85 °C
TJ Temperature, Junction Functional – 150 °C
ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/W
ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W
ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V
UL-94 Flammability Rating At 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
All VDDs 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
VILI2C Input Low Voltage SDATA, SCLK – 1.0 V
VIHI2C Input High Voltage SDATA, SCLK 2.2 – V
VIL_FS FS_[A,B] Input Low Voltage VSS – 0.3 0.35 V
VIH_FS FS_[A,B] Input High Voltage 0.7 VDD + 0.5 V
VILFS_C FS_C Input Low Voltage VSS – 0.3 0.35 V
VIMFS_C FS_C Input Middle Voltage 0.7 1.7 V
VIHFS_C FS_C Input High Voltage 1.8 VDD + 0.5 V
VIL 3.3V Input Low Voltage VSS – 0.3 0.8 V
VIH 3.3V Input High Voltage 2.0 VDD + 0.3 V
IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 5 μA
IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 μA
VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V
VOH 3.3V Output High Voltage IOH = –1 mA 2.4 – V
IOZ High-impedance Output
–10 10 μA
Current
CIN Input Pin Capacitance 3 5 pF
COUT Output Pin Capacitance 3 6 pF
LIN Pin Inductance – 7 nH
VXIH Xin High Voltage 0.7VDD VDD V
VXIL Xin Low Voltage 0 0.3VDD V
IDD3.3V Dynamic Supply Current At max. load in low drive mode per Figure 15 and – 300 mA
Figure 17 @133 MHz
IPD3.3V Power-down Supply Current PD asserted, Outputs Driven – 70 mA
IPD3.3V Power-down Supply Current PD asserted, Outputs Tri-state – 5 mA

Rev 1.0, November 20, 2006 Page 15 of 21

 CY28447

AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
TDC XIN Duty Cycle The device will operate reliably with input 47.5 52.5 %
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD XIN Period When XIN is driven from an external 69.841 71.0 ns
clock source
T R / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns
TCCJ XIN Cycle to Cycle Jitter As an average over 1-μs duration – 500 ps
LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm
CPU at 0.7V
TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.997001 10.00300 ns
TPERIOD 133-MHz CPUT and CPUC Period Measured at crossing point VOX 7.497751 7.502251 ns
TPERIOD 166-MHz CPUT and CPUC Period Measured at crossing point VOX 5.998201 6.001801 ns
TPERIOD 200-MHz CPUT and CPUC Period Measured at crossing point VOX 4.998500 5.001500 ns
TPERIODSS 100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns
TPERIODSS 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 7.497751 7.539950 ns
TPERIODSS 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 5.998201 6.031960 ns
TPERIODSS 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 4.998500 5.026634 ns
TPERIODAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX 9.912001 10.08800 ns
period
TPERIODAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX 7.412751 7.587251 ns
period
TPERIODAbs 166-MHz CPUT and CPUC Absolute Measured at crossing point VOX 5.913201 6.086801 ns
period
TPERIODAbs 200-MHz CPUT and CPUC Absolute Measured at crossing point VOX 4.913500 5.086500 ns
period
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX 9.912001 10.13827 ns
period, SSC
TPERIODSSAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX 7.412751 7.624950 ns
period, SSC
TPERIODSSAbs 166-MHz CPUT and CPUC Absolute Measured at crossing point VOX 5.913201 6.116960 ns
period, SSC
TPERIODSSAbs 200-MHz CPUT and CPUC Absolute Measured at crossing point VOX 4.913500 5.111634 ns
period, SSC
TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 85[2] ps
TCCJ2 CPU2_ITP Cycle to Cycle Jitter Measured at crossing point VOX – 125[2] ps
LACC Long-term Accuracy Measured at crossing point VOX – 300 ppm
TSKEW CPU1 to CPU0 Clock Skew Measured at crossing point VOX – 100 ps
TSKEW2 CPU2_ITP to CPU0 Clock Skew Measured at crossing point VOX – 150 ps
T R / TF CPUT and CPUC Rise and Fall Time Measured from VOL = 0.175 to 175 700 ps
VOH = 0.525V
TRFM Rise/Fall Matching Determined as a fraction of – 20 %
2*(TR – TF)/(TR + TF)
ΔTR Rise Time Variation – 125 ps
ΔTF Fall Time Variation – 125 ps
Note:
2. Measured with one REF on.

Rev 1.0, November 20, 2006 Page 16 of 21

 CY28447

AC Electrical Specifications (continued)

Parameter Description Condition Min. Max. Unit
VHIGH Voltage High Math averages Figure 17 660 850 mV
VLOW Voltage Low Math averages Figure 17 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + V
0.3
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 17. Measure SE – 0.2 V
SRC at 0.7V
TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz SRCT and SRCC Period Measured at crossing point VOX 9.997001 10.00300 ns
TPERIODSS 100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns
TPERIODAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX 9.872001 10.12800 ns
Period
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX 9.872001 10.17827 ns
Period, SSC
TSKEW Any SRCT/C to SRCT/C Clock Skew Measured at crossing point VOX – 250 ps
TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125[2] ps
LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm
T R / TF SRCT and SRCC Rise and Fall Time Measured from VOL = 0.175 to 175 800 ps
VOH = 0.525V
TRFM Rise/Fall Matching Determined as a fraction of – 20 %
2*(TR – TF)/(TR + TF)
ΔTR Rise TimeVariation – 125 ps
ΔTF Fall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 17 660 850 mV
VLOW Voltage Low Math averages Figure 17 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 180 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + V
0.3
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 17. Measure SE – 0.2 V
LCD 96_100M_SSC at 0.7V
TDC SSCT and SSCC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz SSCT and SSCC Period Measured at crossing point VOX 9.997001 10.00300 ns
TPERIODSS 100-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX 9.997001 10.05327 ns
TPERIODAbs 100-MHz SSCT and SSCC Absolute Measured at crossing point VOX 9.872001 10.12800 ns
Period
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX 9.872001 10.17827 ns
Period, SSC
TPERIOD 96-MHz SSCT and SSCC Period Measured at crossing point VOX 10.41354 10.41979 ns
TPERIODSS 96-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX 10.41354 10.47215 ns
TPERIODAbs 96-MHz SSCT and SSCC Absolute Measured at crossing point VOX 10.16354 10.66979 ns
Period
TPERIODSSAbs 96-MHz SRCT and SRCC Absolute Measured at crossing point VOX 10.16354 10.72266 ns
Period, SSC
TCCJ SSCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps
LACC SSCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm

Rev 1.0, November 20, 2006 Page 17 of 21

 CY28447

AC Electrical Specifications (continued)

Parameter Description Condition Min. Max. Unit
T R / TF SSCT and SSCC Rise and Fall Time Measured from VOL = 0.175 to 175 700 ps
VOH = 0.525V
TRFM Rise/Fall Matching Determined as a fraction of – 20 %
2*(TR – TF)/(TR + TF)
ΔTR Rise TimeVariation – 125 ps
ΔTF Fall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 17 660 850 mV
VLOW Voltage Low Math averages Figure 17 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + V
0.3
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 17. Measure SE – 0.2 V
PCI/PCIF at 3.3V
TDC PCI Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.99100 30.00900 ns
TPERIODSS Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.9910 30.15980 ns
TPERIODAbs Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.49100 30.50900 ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V 29.49100 30.65980 ns
THIGH PCIF and PCI high time Measurement at 2.4V 12.0 – ns
TLOW PCIF and PCI low time Measurement at 0.4V 12.0 – ns
T R / TF PCIF/PCI rising and falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps
TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 500 ps
LACC PCIF/PCI Long Term Accuracy Measured at crossing point VOX – 300 ppm
DOT96 at 0.7V
TDC DOT96T and DOT96C Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD DOT96T and DOT96C Period Measured at crossing point VOX 10.41354 10.41979 ns
TPERIODAbs DOT96T and DOT96C Absolute Period Measured at crossing point VOX 10.16354 10.66979 ns
TCCJ DOT96T/C Cycle to Cycle Jitter Measured at crossing point VOX – 250 ps
LACC DOT96T/C Long Term Accuracy Measured at crossing point VOX – 300 ppm
T R / TF DOT96T and DOT96C Rise and Fall Measured from VOL = 0.175 to 175 900 ps
Time VOH = 0.525V
TRFM Rise/Fall Matching Determined as a fraction of – 20 %
2*(TR – TF)/(TR + TF)
ΔTR Rise Time Variation – 125 ps
ΔTF Fall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 17 660 850 mV
VLOW Voltage Low Math averages Figure 17 –150 – mV
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + V
0.3
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 17. Measure SE – 0.2 V
48_M at 3.3V
TDC Duty Cycle Measurement at 1.5V 45 55 %

Rev 1.0, November 20, 2006 Page 18 of 21

 CY28447

AC Electrical Specifications (continued)

Parameter Description Condition Min. Max. Unit
TPERIOD Period Measurement at 1.5V 20.83125 20.83542 ns
TPERIODAbs Absolute Period Measurement at 1.5V 20.48125 21.18542 ns
THIGH 48_M High time Measurement at 2.4V 8.094 11.100 ns
TLOW 48_M Low time Measurement at 0.4V 7.694 11.100 ns
T R / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 2.0 V/ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps
LACC 48M Long Term Accuracy Measured at crossing point VOX – 100 ppm
27_M at 3.3V
TDC Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread Disabled 27M Period Measurement at 1.5V 27.000 27.0547 ns
Spread Enabled 27M Period Measurement at 1.5V 27.000 27.0547
THIGH 27_M High time Measurement at 2.0V 10.5 – ns
TLOW 27_M Low time Measurement at 0.8V 10.5 – ns
T R / TF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 500 ps
LACC 27_M Long Term Accuracy Measured at crossing point VOX – 0 ppm
REF at 3.3V
TDC REF Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD REF Period Measurement at 1.5V 69.8203 69.8622 ns
TPERIODAbs REF Absolute Period Measurement at 1.5V 68.82033 70.86224 ns
T R / TF REF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
TSKEW REF Clock to REF Clock Measurement at 1.5V – 500 ps
TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps
LACC Long Term Accuracy Measurement at 1.5V – 300 ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up – 1.8 ms
TSS Stopclock Set-up Time 10.0 – ns
TSH Stopclock Hold Time 0 – ns

Rev 1.0, November 20, 2006 Page 19 of 21

 CY28447

Test and Measurement Set-up

For Single-ended Signals and Reference
The following diagram shows test load configurations for the
single-ended PCI, USB, and REF output signals.

33Ω Measurement
PCI/
Point
USB 60Ω 5pF

12Ω Measurement
Point
60Ω 5pF
REF 12Ω Measurement
Point
60Ω 5pF

Figure 15.Single-ended Load Configuration Low Drive Option

12Ω M easurem ent

P oint
60Ω 5pF
12Ω M easurem ent
P C I/
P oint
USB 60Ω 5pF

12Ω M easurem ent

P oint
60Ω 5pF

12Ω M easurem ent

REF
P oint
60Ω 5pF
12Ω M easurem ent
P oint
60Ω 5pF

Figure 16. Single-ended Load Configuration High Drive Option

The following diagram shows the test load configuration for the
differential CPU and SRC outputs.

33Ω M e a s u re m e n t
CPUT
SRCT P o in t
D O T96T 4 9 .9 Ω 2pF
96_100_SSC T 1 0 0 Ω D if f e r e n t ia l
M e a s u re m e n t
CPUC 33Ω
SRCC P o in t
D O T96C 4 9 .9 Ω 2pF
96_100_SSC C
IR E F
475Ω

Figure 17. 0.7V Differential Load Configuration

Rev 1.0, November 20, 2006 Page 20 of 21

 CY28447

3 .3 V s ig n a l s
T DC
- -

3 .3 V

2 .4 V

1 .5 V

0 .4 V
0V

TR TF

Figure 18. Single-ended Output Signals (for AC Parameters Measurement)

Ordering Information
Part Number Package Type Product Flow
Lead-free
CY28447LFXC 72-pin QFN Commercial, 0° to 85°C
CY28447LFXCT 72-pin QFN – Tape and Reel Commercial, 0° to 85°C

Package Diagram

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72-Lead QFN 10 x 10 mm (Punch Version) LF72A
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While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.

Rev 1.0, November 20, 2006 Page 21 of 21