Transactions on Industrial Electronics

A Boost-Cuk-Based High Step-up DC-AC Inverter for Grid-

tied AC Micro-grid Applications with Lossless Passive
Snubber

Journal: Transactions on Industrial Electronics

Manuscript ID 21-TIE-0286

Manuscript Type: Regular paper

Manuscript Subject: Renewable Energy Systems

DC-AC power conversion, DC-DC power conversion, Solar power

Keywords:
generation

Are any of authors IEEE

Yes
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Are any of authors IES

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Page 1 of 8 Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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2
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4 A Boost-Cuk-Based High Step-up DC-AC
5
6 Inverter for Grid-tied AC Micro-grid
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9
Applications with Lossless Passive Snubber
10
11 Reza Heidari, student member, IEEE, and Ehsan Adib
12
13
14  problem. This topology comprises an individual PV module
15 Abstract—In this study, a novel two-stage grid-tied high with an inverter [7]. Elimination of low-frequency power
16 step-up inverter is proposed. The first stage (DC-DC) is a transformers, which are costly and bulky, creation of very
17 combination of boost and cuk converters. The second compact design, improvement of flexibility and modularity,
18 stage (DC-AC) comprises a conventional half-bridge
eradication of the mismatch losses between PV modules, and
19 inverter. The ground leakage current is eliminated in the
proposed topology by simultaneous grounding of the PV reduction of installation cost are the main advantages of
20
module and the grid. A lossless passive snubber with the microinverters [8], [9].
21
minimum elements is also proposed and analyzed to Recently, various studies have been conducted to present a
22 provide the soft-switching conditions. In this snubber more reliable, efficient, small-sized, and cost-effective HSU
23 circuit, the snubber capacitance discharges to the output converter. As previously mentioned, an appropriate DC voltage
24 DC-link to decrease the converter circulation losses. The
level is required to connect the PV module with the inverter.
25 main attributes of the proposed DC-DC converter with
lossless passive snubber are the simple structure of the Therefore, designing a perfect HSU converter is important to
26
DC-DC converter and snubber circuit, simple control remove all concerns and frailties.
27
scheme, and high efficiency. Various operation modes of In this regard, both isolated and non-isolated converters have
28 the proposed topology are theoretically analyzed and been studied in previous literature. Nonetheless, utilizing non-
29 investigated. The experimental results substantiate the isolated HSU converters is more desirable on account of the low
30 effectiveness and performance of the proposed boost-cuk-
efficiency and high cost of transformers. It is important to
31 based high step-up inverter with the lossless snubber.
mention that the trouble with the ground leakage current in the
32
Index Terms—Boost converter, cuk converter, grid-tied, PV panel must be considered in the converter design to achieve
33
high step-up inverter, lossless passive snubber, two-stage. a highly efficient HSU converter [10]. This problem is due to a
34
common-mode voltage across the parasitic capacitors between
35
I. INTRODUCTION the panel surface and the ground. To suppress the ground
36
leakage current, some solutions are investigated in [11]. In this
37
38 H IGH step-up (HSU) DC to DC converter plays a significant
role in renewable energy systems such as fuel cell, regard, the common-mode source at switching frequency must
be eliminated, which can be attained by specific converter
39 photovoltaic (PV) panel, and thermoelectric module to achieve
structures and modulation methods [11]. Elimination of ground
40 a proper level of DC voltage for AC and DC loads [1]-[2].
leakage currents in non-isolated PV systems is accomplished by
41 The grid-tied AC microgrid system is categorized into a
negative grounding of PV modules [12]. By combining a DC-
42 centralized inverter, string inverter, and microinverter [3]-[4].
DC converter with a half-bridge inverter and grounding of the
43 The centralized inverter has some major drawbacks such as
44 high-voltage DC cables between the inverter and the modules, PV module and grid, the ground leakage current is removed.
45 power losses owing to a centralized maximum power point Using a half-bridge or full-bridge inverter needs a DC-link
46 tracking (MPPT), mismatch between the modules and string voltage higher than the output DC voltage of PV modules.
47 diodes, large size and complex installation, and interrupted Therefore, the HSU converter is necessary. In this regard,
48 energy transmissions due to inverter failure [3]. String inverter various topologies are introduced to attain a high efficient HSU
49 is an improved version of a centralized inverter. To resolve converter [13]-[18].
50 some problems of the centralized inverter, the PV modules are Combined boost, forward and flyback [10], combined cuk
51 connected in series in string inverter to achieve a higher output and sepic [13], combined boost and flyback [14], and combined
52 voltage. However, the attainment of MPPT for each PV module boost with buck-boost [15] are some prominent examples of
53 is impossible similar to the centralized inverter [5]-[6]. The combining converters in order to achieve the HSU converter.
54 microinverter system is finally developed to remove the MPPT To illustrate, as cuk and sepic converter have the same input, an
55 inductor and one switch are used at the input of the converter,
56
Reza Heidari is with the Electrical Engineering Department, Ehsan Adib is with the Electrical and Computer Engineering
57 Shahrekord University, Shahrekord, Iran (e-mail: Department, Isfahan University of Technology, Isfahan, Iran (phone: +98
58 [email protected]). 31 3391 5465; fax: +98 31 3391 2451; e-mail: [email protected]).
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 Transactions on Industrial Electronics Page 2 of 8
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

1
2 in [13]. Also, the gain of these converters is the same with the control algorithm of the input converter and half-bridge
3 inverse polarity; hence, the combination of these converters is inverter. Next, the performance of the proposed topology is
4 suitable for microinverters since the ground leakage current is investigated by various categories of experiments in section IV.
5 removed, and the upper and lower DC link voltage, are Finally, Section V describes the contributions of this paper
6 balanced. It is significant to be mentioned that, this converter is briefly as a conclusion.
7 hard-switched [13].
8 Some researchers endeavor to improve the boost-based II. ANALYSIS OF THE PROPOSED TOPOLOGY
9 converters by utilizing some techniques such as coupled Fig. 1 illustrates the proposed two-stage grid-tied high step-
10 inductor [16], switched inductor [17], and voltage doubler [18]. up DC-AC inverter with lossless passive snubber. As revealed,
11 These types of topologies have usually numerous the DC-DC section, which is identified by black lines and
12 semiconductor devices and energy storage elements, which elements, comprises a boost and a cuk converter. These
13 makes the converter bulky and costly. converters have common input including input voltage, input
14 Employing snubber circuits are unavoidable to provide the inductor, and switch Q, while the outputs are connected in
15 soft-switching conditions in [19]-[22]. The snubber circuits series. The output inductor of the cuk converter is substituted
16 play a significant role to reduce the switching losses and by a coupled inductor. The magnetizing inductance of the
17 electromagnetic interference (EMI) and create a safe operating coupled inductor is utilized as output cuk inductance. Thus, this
18 area (SOA) [19]. Among snubber circuits, the lossless passive magnetizing inductance is modeled on the primary side.
19 snubber is more preferable for simplicity and robustness [19]. The lossless passive snubber is identified by red lines and
20 A lossless snubber is proposed in [19] for boost converter and elements and includes a secondary leakage inductance 𝐿𝑙𝑘−𝑠𝑒𝑐 ,
21 can be applied to almost all types of converters. This lossless a capacitor 𝐶𝑠 , and two diodes 𝐷𝑠1 and 𝐷𝑠2 . The secondary
22 snubber includes four diodes, three inductors, and a capacitor. voltage of the coupled inductor 𝑉𝑠𝑒𝑐 must be slightly higher than
23 The stored energy in this snubber circuit discharges to the 𝑉𝑜1 , otherwise the snubber circuit does not perform precisely.
24 output voltage, which decreases the converter circulation Moreover, the snubber capacitance must be completely charged
25 losses. A load-independent lossless snubber, which contributes while the switch is on.
26 to a wide range variation of duty cycle, is investigated in [20]. The half-bridge inverter (green lines and elements) is
27 In this snubber circuit, all semiconductor elements are under connected to the DC-link voltages. The unwanted ground
28 soft-switching conditions, and the converter is fully soft leakage current also is eliminated in the proposed topology due
29 switched. Another lossless snubber is presented for a to the simultaneous grounding of the PV module and grid.
30 bidirectional buck-boost converter (BBBC) in [21]. The authors
31 try to minimize the number of elements in the lossless snubber A. Operation Modes
32 circuit [21]-[22]. To reach a simple analysis of the proposed topology, all
33 In this paper, a high step-up DC-AC inverter is proposed for semiconductor elements are considered ideal. The coupled
34 AC microgrid applications. The proposed topology consists of inductor is modeled by two primary and secondary leakage
35 a DC-DC stage connected to a conventional half-bridge. The inductances (𝐿𝑙𝑘−𝑝 and 𝐿𝑙𝑘−𝑠𝑒𝑐 ) and a magnetizing inductance
36 DC-DC stage is established by a boost converter and a cuk (𝐿𝑚 ) as output cuk-inductance. The turn ratio is defined as
37 converter with common input and series output voltage. By
38 negative grounding of the PV module and grid, the ground 𝑛 = 𝑁𝑠𝑒𝑐 ⁄𝑁𝑝 (1)
39 leakage current is eliminated. A lossless passive snubber is also
40 designed to achieve soft-switching conditions as well as high where 𝑁𝑝 and 𝑁𝑠𝑒𝑐 are the primary and secondary winding
41 efficiency. This snubber circuit can discharge the snubber turns, respectively.
42 capacitor to the output voltage. The proposed DC-DC stage Fig. 2 depicts the key waveforms of the fundamental
43 comprises a main switch, an input inductor, a boost diode, a cuk elements in the proposed topology. As seen, eleven operation
44 diode, two snubber diodes, a cuk capacitor, a snubber capacitor, modes establish a complete period as shown in Fig. 3.
45 a coupled inductor, and two output capacitors. Mode 1 (𝑡0 − 𝑡1 ): In this mode, the switch voltage is reached
46 In general, the most significant attributes of the proposed zero at the beginning of this period, and the switch current is
47 topology are as follows: increased from zero. The primary leakage current 𝐼𝑙𝑘−𝑝 is
48 - ZVS turn-off and ZCS turn-on of the main switch
linearly changed from the negative value equal to input current
49 - ZVZCS turn-off and turn-on of the boost diode
𝐼𝑖𝑛 to zero, and the current is transmitted to the switch Q. All
50 - ZVZCS turn-off of the cuk diode
diodes are off, and the voltage of the first snubber diode 𝑉𝐷𝑠1 ,
51 - ZVZCS turn-off and turn-on of the snubber diodes
unlike other diodes, is zero since the voltage of the switch 𝑉𝑠𝑤 ,
52 - Simple structure of the DC-DC stage, simple control scheme,
the snubber capacitance 𝑉𝐶𝑠 , secondary leakage inductance
53 and simple snubber circuit with the minimum elements
voltage 𝑉𝑙𝑘−𝑠𝑒𝑐 , and coupled inductor 𝑉𝐿𝑚 are zero. It must be
54 - Low circulation losses due to discharging snubber capacitance
mentioned that the input inductance 𝐿𝑖𝑛 is linearly charged by
55 to the output voltage
56 The paper organization is as follows. Section II explains the the input voltage 𝑉𝑖𝑛 , and this trend will continue as long as the
57 operation modes of the proposed DC-DC stage as well as the switch Q is on (end of sixth mode). In general, the following
58 main relations of this converter. Then, Section III presents the relations are established in this mode:
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Page 3 of 8 Transactions on Industrial Electronics
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2 𝐼𝑠𝑤 = 𝐼𝑖𝑛 + 𝐿𝑙𝑘−𝑝 (2) Mode 7 (𝑡6 − 𝑡7 ): Snubber capacitor 𝐶𝑠 is discharged through
3 𝑉𝑖𝑛 the second snubber diode 𝐷𝑠2 , and the snubber capacitor voltage
𝐼𝑖𝑛 = 𝐼𝑖𝑛0 + 𝑡 (3)
4 𝐿𝑖𝑛 𝑉𝐶𝑠 and second snubber diode current 𝐼𝐷𝑆2 decrease to zero.
5 Thus, the first DC-link voltage 𝑉𝑜1 increases during this mode.
6 Mode 2 (𝑡1 − 𝑡2 ): Snubber capacitor 𝐶𝑠 is resonantly charged Furthermore, the switch voltage reaches to the first DC-link
7 through the first snubber diode 𝐷𝑠1 and secondary leakage voltage 𝑉𝑜1 . Besides, the cuk diode 𝐷2 turns on to pass the input
8 inductance 𝐿𝑙𝑘−𝑠𝑒𝑐 . Therefore, its voltage reaches near the first current 𝐼𝑖𝑛 as well as the primary leakage inductance current
9 DC-link voltage 𝑉𝑜1 at the end of this mode. Therefore, 𝐼𝑙𝑘−𝑝 . Moreover, the first snubber diode 𝐷𝑠1 turns off under
10 ZVZCS condition, and the voltage of boost and cuk diodes
11 𝑡 reduces to zero.
𝑉𝐶𝑠 = 𝑉𝑜1 ∗ sin⁡( ) (4)
12 √𝐿𝑙𝑘−𝑠𝑒𝑐 × 𝐶𝑠 Mode 8 (𝑡7 − 𝑡8 ): The cuk diode current 𝐼𝐷2 decreases during
13 𝐶𝑠 ∗ 𝑉𝑜1 𝑡 this mode since both input and primary leakage currents (𝐼𝑖𝑛 and
14 𝐼𝐶𝑠 = ∗ cos⁡( ) (5)
√𝐿𝑙𝑘−𝑠𝑒𝑐 × 𝐶𝑠 √𝐿𝑙𝑘−𝑠𝑒𝑐 × 𝐶𝑠 𝐼𝑙𝑘−𝑝 ) have a reducing trend. Before reaching the end of this
15 𝐼𝑝 = 𝑛 ∗ 𝐼𝑠𝑒𝑐 = 𝑛 ∗ 𝐼𝐶𝑠 mode, the boost diode 𝐷1 turns on under ZVZCS condition, and
(6)
16 the input current is transferred to the boost diode 𝐷1 . Therefore,
17 the input current 𝐼𝑖𝑛 passes only the boost diode 𝐷1 at the end
The first snubber diode 𝐷𝑠1 turns on under ZVZCS condition,
18 of this mode. Consequently, the primary leakage inductance
and the second snubber diode voltage 𝑉𝐷𝑠2 is decreased to zero
19 and cuk currents (𝐼𝑙𝑘−𝑝 and 𝐼𝐷2 ) reduces to zero at the end of
during this mode. Besides, “n” times of the first snubber diode
20
current 𝐼𝐷𝑠1 passes through the primary leakage inductance this mode.
21
𝐿𝑙𝑘−𝑝 , and “n +1” times through the switch Q. The magnetizing Mode 9 (𝑡8 − 𝑡9 ): The boost diode current 𝐼𝐷1 decreases to
22
inductance 𝐿𝑚 is linearly charged, and this trend will continue zero, and the input current is transferred to the second DC-link
23
voltage through the cuk capacitance 𝐶1 and primary leakage
24 as long as the switch Q is on (end of sixth mode).
inductance 𝐿𝑙𝑘−𝑝 .
25
26 𝑉𝐿𝑚 Mode 10 (𝑡9 − 𝑡10): At the beginning of this mode, the cuk,
𝐼𝐿𝑚 = 𝐼𝑙𝑚0 + 𝑡 (7) boost, and second snubber diodes turn off under ZVZCS
27 𝐿𝑚
28 𝐼𝑙𝑘−𝑝 = 𝐼𝑙𝑚 + 𝐼𝑝 (8) condition. Besides, the switch voltage 𝑉𝑠𝑤 decreases to the input
29 voltage since the voltage of input inductance reduces to zero.
30 Mode 3 (𝑡2 − 𝑡3 ): the second snubber diode 𝐷𝑆2 conducts Furthermore, the input current 𝐼𝑖𝑛 and the primary leakage
31 under ZVZCS condition, and the snubber capacitance current inductance current 𝐼𝑙𝑘−𝑝 are equal but in an adverse direction
32 𝐼𝐶𝑠 reduces to zero. Also, the switch current 𝐼𝑠𝑤 and primary during this mode. Moreover, all semiconductor elements are off
33 leakage current 𝐼𝑙𝑘−𝑝 are linearly decreased. during this mode.
34 Mode 4 (𝑡3 − 𝑡4 ): Both snubber diodes conduct during this Mode 11 (𝑡10 − 𝑡0 ): In this mode, the switch Q turns on under
35 mode. The negative voltage of the secondary leakage low voltage and zero current (ZCS turn-on). Besides, the first
36 inductance 𝐿𝑙𝑘−𝑠𝑒𝑐 results in its current reduction, and this snubber diode voltage 𝑉𝐷𝑠1 is
37 current reaches zero at the end of this mode. When this current
38 reduces to zero, the voltage of secondary leakage inductance 𝑉𝐷𝑠1 = 𝑉𝐶𝑠 + 𝑉𝑠𝑤 − 𝑛 ∗ 𝑉𝐿𝑚 + 𝑉𝑙𝑘−𝑠𝑒𝑐 (10)
39 𝑉𝑙𝑘−𝑠𝑒𝑐 changes from a negative value to zero, which leads to a
40 small decline in the magnetizing inductance voltage 𝑉𝐿𝑚 . In this Since the 𝑉𝐶𝑠 , 𝑉𝐿𝑚 , 𝑉𝑙𝑘−𝑠𝑒𝑐 are zero, 𝑉𝐷𝑠1 is equal to the
41 mode, 𝐶1 is discharging while 𝐶𝑜1 and 𝐶𝑜2 are charging. switch voltage 𝑉𝑠𝑤 . Thus, 𝑉𝐷𝑠1 reduces to zero similar to 𝑉𝑠𝑤 .
42 Mode 5 (𝑡4 − 𝑡5 ): By voltage decline of 𝑉𝐿𝑚 , the primary B. Formula Derivation
43 leakage inductance voltage 𝑉𝑙𝑘−𝑝 increases since
44 In this section, the gain ratio of the output DC-link voltages
45 to the input voltage are mathematically analyzed and calculated.
𝑉𝑙𝑘−𝑝 = 𝑉𝑐1 − 𝑉𝑜2 − 𝑉𝐿𝑚 (9) For simplicity, the coupling coefficient is supposed unity, and
46
47 the first and second output DC-link voltage are named 𝑉𝑜1 and
This voltage increment results in an increment in the primary 𝑉𝑜2 , respectively.
48
leakage and switch currents (𝐼𝑙𝑘−𝑝 and 𝐼𝑠𝑤 ) until the end of this The voltage per second law for inductance is the solution for
49
50 mode. The energy stored in 𝐶1 is also transferred to 𝐶𝑜2 . achieving the voltage gain ratio. The input inductance voltage
51 Mode 6 (𝑡5 − 𝑡6 ): The switch is turned off at the beginning during different modes is
52 of this period. Hence. The switch current 𝐼𝑠𝑤 decreases to zero
53 during this mode. The second snubber diode 𝐷𝑠2 conducts while (𝑉𝐿𝑖𝑛 )𝐷𝑇 = 𝑉𝑖𝑛 = 𝑉𝑚𝑝 ⁡⁡⁡⁡𝑡0 < 𝐷𝑇 < 𝑡6 (11)
54 the voltage remains at zero from previous modes (ZVZCS turn- (𝑉𝐿𝑖𝑛 )𝐷1𝑇 = 𝑉𝑖𝑛 − 𝑉𝑜1 ⁡⁡⁡⁡𝑡6 < 𝐷1 𝑇 < 𝑡9 (12)
55 on). Since 𝑉𝑜1 − 𝑉𝐶𝑠 is zero, and due to conduction of 𝐷𝑠2 , ZVS
56 turn-off of the switch is also provided. Moreover, the primary where 𝑉𝑚𝑝 is the input voltage, attained from the PV module by
57 leakage inductance current 𝐼𝑙𝑘−𝑝 decreases linearly, and this the maximum power point tracking (MPPT) method.
58 trend will continue until the end of the ninth mode.
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 Transactions on Industrial Electronics Page 4 of 8
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1 Iin Lin ID1 D1 Lin D1 Lin D1

2 PV
Module
+ VLin -
Isw - VD1 +
Q
+
Q
+

3 + + Vin VO1 Vin VO1

ICs - VCs + IDs2 Ds2 S1
Cs
Ds1
Ds2 - Cs
Ds1
Ds2 -
Cin Vsw Q VO1
+ Lg Ig
4 - Cs - Vs2 + -
VDs1 Ds1 + Llk-sec Llk-sec
+ +

5
- Vinv Vg D2 VO2 D2 VO2
Isec=IDs1 n
-
n
-
- - :
1
:
1

6 +
Llk-sec V
lk-sec + C1 Llk-p C1 Llk-p
VD2 D2 - Vsec + n +
7 VO2 Lm=Lcuk Lm=Lcuk
S2 Mode 1 Mode 2
- : - Lin D1 Lin D1

8
ID2 1
IC1 + VC1 - + +
Ip - Vlk-p + Vin Q VO1 Vin Q VO1

9 C1 ILm -VLm+ Llk-p Ilk-p

Cs
Ds1
Ds2 - Cs
Ds1
Ds2 -

Lm=Lcuk
10 Fig. 1. Proposed grid-tied boost-cuk-based high step-up DC-AC Llk-sec
+
Llk-sec
+

11
D2 n
VO2 D2 n
VO2
inverter with lossless passive snubber. :
1
- :
1
-

12 C1
Lm=Lcuk
Llk-p C1
Lm=Lcuk
Llk-p

13
DT D1T Mode 3 Mode 4
Lin D1 Lin D1

14 VGS
Vin Q
+
VO1 Vin Q
+
VO1

15
Cs Ds2 - Cs Ds2 -
Ds1 Ds1
Iin
16 VLin
D2
Llk-sec
+
VO2 D2
Llk-sec
+
VO2

17
n n
: - : -
1 1

18 C1
Lm=Lcuk
Llk-p C1
Lm=Lcuk
Llk-p

Isw
19
Mode 5 Mode 6
Lin D1 Lin D1
Vsw
20 Vin Q
Cs Ds2
+
VO1
-
Vin Q
Cs Ds2
+
VO1
-
21 Ilk-p Ds1 Ds1

22 D2
Llk-sec
+
VO2 D2
Llk-sec
+
VO2

23
n n
ICs : - : -
1 1
VCs
24 C1
Mode 7
Lm=Lcuk
Llk-p C1
Mode 8
Lm=Lcuk
Llk-p

25 ID1
Lin D1 Lin D1

26 VD1 + +
Vin Q VO1 Vin Q VO1
Cs Ds2 - Cs Ds2 -

27
Ds1 Ds1
ID2
VD2
28
Llk-sec Llk-sec
+ +
D2 n
VO2 D2 n
VO2

29
: - : -
1 1

IDs1
30 C1 Llk-p C1 Llk-p
VDs1 Mode 9
Lm=Lcuk Lm=Lcuk
Mode 10

31
Lin D1

32 IDs2
VDs2
Vin Q
Cs
Ds1
Ds2
VO1
-

33 Llk-sec
34
+
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t0 D2 VO2
n
-
Fig. 2. Key waveforms of the lossless snubber dc-dc stage. :

35 1

Llk-p
36
C1
Lm=Lcuk
Mode 11
The magnetizing inductance voltage in different modes is
37 Fig. 3. The circuit of various operation modes of the proposed
38 method.
(𝑉𝐿𝑚 )𝐷𝑇 = 𝑉𝑐1 − 𝑉𝑜2 ⁡⁡⁡⁡𝑡0 < 𝐷𝑇 < 𝑡6 (13)
39
(𝑉𝐿𝑚 )𝐷1𝑇 = −𝑉𝑜2 ⁡⁡⁡⁡𝑡6 < 𝐷1 𝑇 < 𝑡9 (14) 𝑉𝐶1 𝐷 + 𝐷1
40 𝑉𝐶1 = 𝑉𝑜1 ⁡⁡ ⇒ ⁡ = (17)
41 𝑉𝑖𝑛 𝐷1
42 It must be mentioned that both 𝑉𝐿𝑖𝑛 and 𝑉𝐿𝑚 are zero for other
43 periods (𝑡9 < (1 − 𝐷 − 𝐷1 )𝑇 < 𝑡0 ). And therefore, based on (16) and (17)
44 According to (11) and (12), the gain ratio of 𝑉𝑜1 to the input
45 voltage 𝑉𝑖𝑛 is calculated by (15). 𝑉𝑜2 𝐷
= (18)
46 𝑉𝑖𝑛 𝐷1
47 𝑉𝑜1 𝐷 + 𝐷1
= (15)
48 𝑉𝑖𝑛 𝐷1 Equations (15) and (18) show that 𝑉𝑜1 and 𝑉𝑜2 are not equal.
49 The time duration for 𝐷1 𝑇 depends on the magnetizing
50 Moreover, the gain ratio of 𝑉𝑜2 to the cuk capacitance- inductance value. Designing a small magnetizing inductance
51 voltage 𝑉𝐶1 is estimated by (13) and (14) compared to the input inductance can reduce the time duration
52 of 𝐷1 𝑇. Therefore,
53 𝑉𝑜2 𝐷
= (16)
54 𝑉𝐶1 𝐷 + 𝐷1 𝑖𝑓⁡⁡𝐷 ≫ 𝐷1 ⁡⁡ ⇒ ⁡ 𝑉𝑜1 ≈ 𝑉𝑜2 ⁡ (19)
55
56 As obvious the gain ratio between 𝑉𝐶1 and 𝑉𝑖𝑛 is computed It must be mentioned that the magnetizing inductance value
57 by the voltage per second law for input inductance. should not be too small, since the switch cannot turn on under
58 ZCS condition. Furthermore, the minimum value of 𝑉𝑜1 and 𝑉𝑜2
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1 VO1 VO*
2 for grid-tied applications must be 311(V) for conventional H- PV High step_up V
Min(VO1, VO2) O LPF +-
Module Inverter and Grid VO2
3 bridge inverter. Therefore, according to (18) and considering Q S1 S2

4 the solar panel voltage about 50(V): Vmp Imp Ig

Vg
Duty PWM Ig*
MPPT Comparator PI
5 Generator
𝑉𝑜2 𝐷 311 Fig. 4. Control algorithm of the proposed topology.
6 = = = 6.22 ≈ 7 (20)
7 𝑉𝑖𝑛 𝐷1 50
8
9 since 𝐷 ≈ 7𝐷1 , the difference between 𝑉𝑜1 and 𝑉𝑜2 is small.
10
11 III. CONTROL BLOCK
12 In the previous section, the operation modes of the DC-DC
Fig. 5. Picture of the implemented 150-W prototype of the proposed
13 stage and the voltage gain ratio for both DC-link output
high step-up DC–AC inverter.
14 voltages are discussed.
15 The control scheme of the proposed DC-AC inverter is TABLE I
16 explored in this section. Fig. 4 illustrates the control algorithm PEAK VOLTAGE AND CURRENT OF ALL SEMICONDUCTORS
17 of the proposed topology. A peak current mode control is Elements Peak voltage Peak current
18 adopted for the control of the conventional H-bridge inverter to Switch Q 𝑉𝑜1 △ 𝐼𝐿𝑚 − 𝐼𝐿𝑖𝑛
Diode 𝐷1 𝑉𝑜1 𝐼𝐿𝑖𝑛
19 inject a high-quality sinusoidal current with the unity power Diode 𝐷2 𝑉𝑜1 △ 𝐼𝐿𝑚
20 factor. This technique provides a pure AC current without DC Diode 𝐷𝑠1 𝑉𝑜1 + 𝑛𝑉𝑜2 𝐼𝐶𝑠−𝑚𝑎𝑥 ∝ 𝐶𝑠
21 offset value, caused by voltage difference between two output Diode 𝐷𝑠2 𝑉𝑜1 𝐼𝐶𝑠−𝑚𝑎𝑥 ∝ 𝐶𝑠
22 DC-link voltages. It must be noted that minimum DC-link
23 voltage must be higher than 311 volts for grid-tied applications Based on (17), the following equation is derived
24 to prevent distortion in output current. Thus, the minimum
25 value of 𝑉𝑜1 and 𝑉𝑜2 is used in each control period. A low pass 𝐷1
𝑉𝑖𝑛 = (2𝑉𝑜1 ) (22)
26 filter must also be used to eliminate the low frequency of DC- 𝐷 + 𝐷1
27 link voltage and have a precise control scheme on the AC side.
28 The maximum power must be extracted from the PV module Hence, according to (22) and (20), the input inductance is
29 by the MPPT method. Implementing the MPPT method is easy obtained by (23)
30 in the proposed topology since there is just a main switch [10].
31 In general, two separate control loops are employed for the 𝐷𝑇𝑉𝑜1
𝐿𝑖𝑛 = (23)
32 input DC side and output AC side. The former is responsible 4 △ 𝐼𝐿𝑖𝑛
33 for extracting maximum power (MP) from the PV module,
34 while the latter must inject the extracted power from the PV Moreover, the magnetizing (cuk) inductance is calculated by
35 module to the grid.
36 𝐷𝑇𝑉𝑜2
𝐿𝑚 = 𝐿𝑐𝑢𝑘 = (24)
37 IV. EXPERIMENTAL RESULTS 7 △ 𝐼𝐿𝑚
38
The proposed topology prototype is designed and
39 Based on (23) and (24), if it is assumed that 𝑉𝑜1 = 𝑉𝑜2 ; thus,
implemented in the laboratory (Fig. 5). The proposed topology
40
is also investigated by three categories of experimental results
41 7𝐿𝑚 △ 𝐼𝐿𝑚 = 4𝐿𝑖𝑛 △ 𝐼𝐿𝑖𝑛 (25)
including the performance of all semiconductor elements
42
during a complete period (Fig. 6), soft-switching of
43 The cuk capacitance is responsible to charge the magnetizing
semiconductor elements during the moment of turning on and
44 inductance, second DC-link voltage, as well as first DC-link
off (Fig. 7), efficiency confirmation of the DC-DC stage (Fig.
45 voltage as long as the switch is on. The value of this capacitance
8), and grid-tied performance (Fig. 9).
46 is attained as
The input DC side and output AC side controllers of the
47
proposed high step-up DC–AC inverter are performed by a 𝐼𝐿𝑖𝑛 (1 − 𝐷)𝑇
48 𝐶1 = 𝐶𝑐𝑢𝑘 = (26)
LaunchPad XL TMS320F28379D, a floating-point discrete
49 △ 𝑉𝑐1
signal processor board. The controllers of the proposed
50
topology are coded through Simulink/MATLAB. To select proper semiconductor elements, the peak voltage
51
52 A. Soft-switching performance analysis and currents of all elements are tabulated in TABLE I. The
53 voltage and current stresses of these elements are based on the
The input inductance and input voltage must charge 𝐶𝑜1 and
54 theoretical analysis discussed in sections II and III.
𝐶1 . Therefore, according to (15) The proposed snubber circuit is designed to obtain soft-
55
56 switching conditions. In this regard, the snubber capacitor must
𝐷1
57 𝑉𝑖𝑛 = (𝑉 + 𝑉𝑐1 ) (21) be charged as long as the switch is on until its voltage reaches
𝐷 + 𝐷1 𝑜1 the first output DC-link voltage. Hence, two issues must be
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1
2 considered to perform the soft-switching well.
3 First, the turn ratio of the coupled inductor must choose an
4 appropriate value. As obvious, the secondary side voltage of
5 coupled inductor 𝑉𝑠𝑒𝑐 , the secondary leakage inductance
6 𝐿𝑙𝑘−𝑠𝑒𝑐 , and snubber capacitor 𝐶𝑠 form a second-order circuit
7 with zero initial values (𝐼𝐿𝑙𝑘−𝑠𝑒𝑐0 = 𝑉𝐶𝑠0 = 0). Therefore,
8 (a) (b)
9 𝑉𝐶𝑠−𝑚𝑎𝑥 = 2 × 𝑉𝑠𝑒𝑐 = 2 × 𝑛𝑚𝑖𝑛 × 𝑉𝐿𝑚 (27)
10
11 where 𝑛𝑚𝑖𝑛 is the minimum value of turn ratio to attain a proper
12 soft-switching circuit and satisfy the condition 𝑉𝐶𝑠−𝑚𝑎𝑥 = 𝑉𝑜1 .
13
14 𝑛𝑚𝑖𝑛 = 𝑉𝑜1 ⁄(2 × 𝑉𝐿𝑚 ) (28)
15
16 According to (15) and (18) and assuming minimum 311(V) (c) (d)
17 for DC-link voltages, 𝑉𝑜1 must be higher than 311(V) in (28). Fig. 6. Experimental results of the proposed topology during a
As the voltage of the magnetizing inductance is about input complete period (for all current figures 1V/div=3A), (a) input
18 inductance voltage (blue) and current (red), (b) switch voltage (blue)
19 voltage (based on (17) and (18)) while the switch is on, the and current (red), (c) boost-diode voltage (blue) and current (red), (d)
20 appropriate n is calculated by (28) to charge the snubber cuk-diode voltage (blue) and current (red).
21 capacitor to the first output voltage level.
22 Second, there are some limitations in choosing proper
23 snubber capacitors. This capacitor must charge completely as
24 long as the switch is on. Hence, half of the resonance period of
25 the secondary leakage inductance and snubber capacitance must
26 be less than 𝑡𝑜𝑛 = 𝐷𝑇.
27
28 𝜋√𝐿𝑙𝑘−𝑠𝑒𝑐 𝐶𝑠 ≤ 𝐷𝑇 (29) (a) (b)
29
30 The snubber capacitor provides ZVS turn-off for the DC-DC
31 converter switch and its value is calculated based on the current
32 fall time (𝑡𝑓 ) of the switch as following
33
34 𝐶𝑠 = 𝑖𝐶𝑠 ∗ 𝑡𝑓 ⁄∆𝑉 (30)
35
36 By considering ∆𝑉 = 0.1 ∗ 𝑉𝑜1 and 𝐼𝐶𝑠 equal to the average (c) (d)
37 of switch current, the snubber capacitance is obtained by (30).
Fig. 7. Soft switching conditions: (a) ZVS turn-off of switch, (b) ZCS
turn-on of switch, (c) ZVZCS turn-off and ZVZCS turn-on of boost
38 diode, (d) ZVZCS turn-off of cuk diode.
39 TABLE II
ELEMENTS USED IN THE PROPOSED METHOD
40 Another consideration in designing the system is that the cuk
Symbols Parameter Value
41 PV Solar Module NA-E130G diode 𝐷2 must be a fast diode with voltage stress equal to the
42 𝑉𝑚𝑝 Voltage at MPP 45.4v first output DC-link voltage 𝑉𝑜1 . TABLE II illustrates the
43 𝐼𝑚𝑝 Current at MPP 3.3A element's value and model used in the proposed topology.
44 𝑉𝑔 Grid voltage 220 Vrms
Fig. 6 substantiates the eleven operation modes and
45 𝐿𝑔 Grid inductance 4mH
𝑓𝑠𝑤 Switching frequency 50KHz theoretical analysis discussed in Section II-A. Fig. 6a verifies
46 𝐿𝑚 Magnetizing inductance 17uH the volt per second law for input inductance analyzed in section
47 𝐿𝑙𝑘−𝑝 Primary leakage inductance 1uH II-B. Moreover, it shows 𝐷𝑇 ≈ 7𝐷1 𝑇.
48 𝐿𝑙𝑘−𝑠𝑒𝑐 Secondary leakage inductance 14uH Fig. 6b illustrates the voltage of switch after turning off, first
49 k Coupling coefficient 0.96
increased to the first DC-link voltage, and then it decreases to
n Turn ratio 6
50 𝐶𝑜1 &𝐶𝑜2 Output capacitor 66uF input voltage which is about one-sixth of output voltage. Thus,
51 Q Main switch SiHG70N60AEF the switch turns on under low voltage and zero current.
52 𝐷1 Boost diode MUR860
The voltage of the boost diode 𝐷1 and cuk diode 𝐷2 have
𝐷2 Cuk diode MUR860
53 𝐶1 Cuk capacitance 5.6uF almost the same voltage (Figs. 6c and 6d).
54 𝐶𝑠 Snubber capacitance 6nF Fig. 7 approves the soft-switching condition analyzed in
55 𝐷𝑠1 First snubber diode UF5408
section II-A. The switch turns off under ZVS condition (Fig.
56 𝐷𝑠2 Second snubber diode MUR860
7a) and turns on under low voltage and zero current (Fig. 7b).
𝑆1 & 𝑆2 H-bridge switch FGL40n120
57 Figs. 7c and 7d reveal both boost and cuk diodes turn off under
58
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1
2 ZVZCS condition. Besides, the boost diode turns on under
3 ZVZCS condition resulting in a high-efficiency DC-DC
4 converter.
5 B. Efficiency analysis
6 To approve the performance of the proposed HSU converter,
7 the DC-DC stage is independently experienced under various
8 loads. Fig. 8 depicts the efficiency of the proposed DC-DC (a) (b)
9 stage with lossless passive snubber (blue curve). As exposed, Fig. 9. Grid-tied results, (a) reference grid current (blue) and
10 the efficiency at full load is 97.13%, and the maximum measured grid current (red), (b) DC-link voltages.
11 efficiency is 97.46%. The total system efficiency is also
12 depicted in this figure (red curve). TABLE III
13 TABLE III illustrates that the proposed topology has a higher
COMPARISON OF THE CONVERTERS
14 efficiency compared to other topologies introduced in the other No. of
No. of Hard VS.
Efficiency of
Ref. passive soft-
15 studies. The control of the presented converters with only one
semiconductors
elements switching
DC-DC stage
16 Full load:
switch is easier than other topologies to extract maximum 1 switch 5 capacitors Soft-
17 [10]
5 diodes 3 inductors switching
94.6%
power from the PV panel. Among introduced single-switch Max.: 96.2%
18
converters, the proposed topology has the minimum passive Full load:
19 [12]
4 switches 3 capacitors Hard-
95.31%
elements as well. The proposed method has also lower diodes 2 diodes 1 inductor switching
20 Max.: 96.68%
compared to [10]. It is noted that 2 diodes of the proposed
21 1 switch 4 capacitors Hard-
Half of full
method are utilized for soft-switching conditions. As obvious, [13] load:
22 2 diodes 3 inductors switching
92.3%
the soft-switching conditions can increase the efficiency;
23 Full load:
however, it can be improved by other techniques like increasing 2 switches 4 capacitors Soft-
24 [14]
3 diodes 1 inductor switching
95.45%
the number of switches even under hard-switching conditions Max.: 96.77%
25 2 switches 2 capacitors Hard-
[12] and using the transformer to reduce the duration of switch [15] -
26 2 diodes 2 inductors switching
conduction [18]. In general, the implementation of the proposed
27 2 switches 3 capacitors Hard-
Full load:
method is most cost-effective due to using a simple soft- [17] 92%
28 3 diodes 4 inductors switching
Max.: 92.5%
switching circuit with the minimum elements.
29 Full load:
2 switches 5 capacitors Soft-
30 C. Grid-tied performance analysis [18]
2 diodes 2 inductors switching
97.1%
Max.: 97.3%
31 Fig. 9a depicts the measured grid current follows its Full load:
32 reference value precisely. It must be mentioned that these
Proposed 1 switch 4 capacitors Soft-
97.13%
method 4 diodes 2 inductors switching
33 currents are depicted through the DAC pin of the mentioned Max.: 97.46%
34 DSP board. The DAC pin gets a signal between 0-4095 and
35 converts that signal to a voltage between 0-3V. As revealed V. CONCLUSION
36 from Fig. 9a, the middle of an AC current is a value equal to A two-stage high step-up DC-AC inverter with the lossless
37 2048, is equivalent to 1.5V. passive snubber is the major contribution of this paper. In this
38 Besides, this figure substantiates the peak current mode regard, the principal operation modes of the DC-DC stage are
39 control scheme utilized for controlling the output AC side. As theoretically explored. Then, the voltage gain ratio of this
40 mentioned, this technique can eliminate injecting a current with topology is analyzed. The ground leakage current is eliminated
41 a DC offset value to the grid. Two output DC-link voltages are by employing a half-bridge inverter and connecting the ground
42 also illustrated in Fig. 9b. These voltages have low-frequency of the solar module to the grid. As the DC-DC stage consists of
43 oscillation that makes it necessary to use an LPF for output AC the conventional boost and cuk converters, the structure is
44 side control. simple. Besides, a simple control scheme of input converter and
45 half-bridge inverter is adopted due to employing the lower
46 number of semiconductor switches. Moreover, the soft-
47 switching condition, caused by the proposed lossless snubber
48 circuit with the minimum elements, provides a high-efficiency
49 converter. Besides, the converter circulation losses are
50 eliminated, since the snubber capacitor discharges to the output
51 DC-link capacitor. Finally, the experiments validate the
52 efficacy and performance of the proposed topology.
53
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