AVR ARCHITECTURE

Features
• Advanced RISC Architecture
• 131 Instructions
• 32 × 8 General Purpose Working Registers
• 32Kbytes of In-System Self-programmable Flash program memory
• 1024Bytes EEPROM
• 2Kbytes Internal SRAM
• Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
• One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
• Real Time Counter with Separate Oscillator
• Four PWM Channels
• 8-channel, 10-bit ADC
• Byte-oriented Two-wire Serial Interface

AVR CPU Core

ALU (Arithmetic-Logic-Unit)
This is where arithmetic operations between general purpose registers or between a register
and an immediate are executed
Status-Register
It contains information about the result of the most recently executed arithmetic instruction.
Stack Pointer
It is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls.
General Purpose Register File
It is optimized for the AVR Enhanced RISC instruction set by supporting various
input/output schemes

MEMORY ARCHITECTURE
  AVR architecture is based on Harvard Architecture and has two main memory spaces:
o Data Memory
o Program Memory
 Also features EEPROM Memory for data storage
 All memory spaces are linear and regular.
In-System Reprogrammable Flash Program Memory
 32Kbytes for program storage.
 Organized as 16K x 16 .
 Memory space divided into two sections(Security) –
o Boot Loader
o Application Program
 write/erase cycles >10,000
 14 bits wide Program Counter (PC) (addressing -16K-program-memory-locations).
SRAM Data Memory

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
2K
bytes of internal data SRAM(with Extended I/O space from 0x60- 0xFF) are accessible
through the following addressing modes.
• Direct
–reaches the entire data space.
• Indirect with Displacement
–reaches 63 address locations from the base address given by the Y- or -Z-register.
• Indirect
– In Register File, registers R26 to R31 feature the indirect addressing pointer registers.
• Indirect with Pre-decrement
– Address registers X, Y, and Z are decremented.
• Indirect with Post-increment
– The address registers X, Y, and Z are incremented.
Data Memory Access Times: performed in two clkCPU cycles

EEPROM Data Memory

ATmega328/P contains 1K bytes of data EEPROM memory.
Organized as a separate data space, in which single bytes can be read and written.
Write/erase cycles>100,000.
Access between EEPROM and CPU is by specifying the EEPROM Address Registers, the
EEPROM Data Register, and the EEPROM Control Register.
 I/O PORTS

 ATmega328P has 23-I/O Pins assigned to three General Purpose Input Output
Ports(GPIO) (8-bit Ports B, D and 7-bit Port-C) some of which have alternate
functions.

 Each port is controlled by 3 8-bit registers. Each pin consist of three register bits
which are:
o The DDRx(n)-bit in DDRx-Register selects pin direction. Writing 1 to DDx(n)
configures pin as input while 0 configures pin as output.
o The PORTx(n)-bit in PORTx-Register.
 Writing 1 to PORTx(n)(bit) when DDRx(n)=1(input), pin is driven
high and pull-up resistor is activated.
 Writing 0 to PORTx(n)(bit) when DDRx(n)=0(output), pin is driven
low. To switch the pull-up resistor off, PORTx(n) has to be written to
'0' or the pin has to be configured as an output pin
o PINx(n)(bit) in PINx register.
 Writing a '1' to PINx(n)(bit) toggles value of PORTx(n)(bit),
independent on the value of DDRx(n).
I/O-port-pin-as-an-input
I/O-port-pin-as-an-output

Synchronization-Timing
Note: Takes a clock cycle for data output to be reflected on the input
 INTERRUPTS
Allow program to respond to events when they occur or to ignore events until the occur
There are external and internal events as follows:
 External events e.g.UART ready with/for next character. Signal change on pin.
 Internal events e.g. Power failure, Arithmetic exception, Timer “tick”.
Interrupts
Interrupt model
When an interrupt event occurs. Processor does an automatic procedure call which is
automatically done to address for that interrupt.Each event has its own interrupt address
The global interrupt enable bit (in SREG) is automatically cleared i.e. nested interrupts are
disabled. SREG bit can be set to enable nested interrupts if desired.
Interrupt procedure does whatever it needs to, then returns via RETI. The global interrupt
enable bit is automatically set on RETI. One program instruction is always executed after
RETI
Interrupt-types
Type 1 – Event remembered when interrupt is disabled.If interrupt disabled, flag is set.When
interrupt is enabled again, interrupt takes place, and flag reset
Type 2 – Event not remembered when interrupt is disabled. Signal level causes interrupt.If
level occurs when interrupt is enabled, interrupt takes place. If interrupt is not enabled, and
level goes away before the interrupt is enabled, nothing happens
Interrupt handler is invisible to program, except through side-effects, e. g. via flags or
variables
Interrupt-Vectors
Table in memory containing the first instruction of each interrupt handler
Typically at program address 0
External Interrupts
Monitors changes in signals on pins
Event can be configured by setting control registers appropriately

External Interrupt Pins:

INT0-PORT-D[2] and INT1-PORT-D[3]–provide range of event options,
PCINT[23:0]–provide any signal change (toggle),
PCINT[7:0]–PORT-B-[7:0], PCINT[14:8]–PORT-C[6:0], PCINT[23:16]–PORT D [7:0]

INT0 and INT1

External-Interrupt-Control-Register

Sense-Control(INT0 is the same)

External-Interrupt-Mask-Register

If INT# bit is set (and the SREG I-bit is set), interrupts are enabled on pin INT#
External-Interrupt-Flag-Register

Interrupt flag bit is set when a change triggers an interrupt request

Flag is cleared automatically when interrupt routine is executed

PCINT[23:0]
Pin-Change-Interrupt-Control-Register

PCIE2 enables interrupts for PCINT[23:16]

PCIE1 enables interrupts for PCINT[14:8]
PCIE0 enables interrupts for PCINT[7:0]

Pin-Change-Interrupt-Flag-Register

PCIF# set if corresponding pins generate an interrupt request

Cleared automatically when interrupt routine is executed

PCINT[23:0]
Pin-Change-Mask-Register-2

Each bit controls whether interrupts are enabled for the corresponding pin
Change on any enabled pin causes an interrupt
(Mask registers 1 and 0 are similar)
 TIMERS
ATMega328P has three timers:
8-bit-Timer/Counter 0(TC0)
TC0 is a general purpose module which allows accurate program execution timing and wave
generation.

It can be clocked internally, via the prescaler, or by an external clock source on the T0 pin
Registers:

 TCNT0–Timer/Counter-Register(8-bit)

 Output Compare Registers (OCR0A&OCR0B)-compared with the timer/counter

value at all times and result used by waveform generator to generate a PWM on
Output Compare pins (OC0A&OC0B).

 TCCR0A/B – Timer/Counter-Control Registers

 TIMSK0 – Timer/Counter Interrupt Mask Register: Individually masks all interrupts

 TIFR0 – Timer/Counter Interrupt Flag Register: makes all interrupt requests visible.
COUNTER-UNIT
Programmable bi-directional counter unit.

 Depending on mode of operation, counter is cleared, incremented, or decremented at

each timer clock(clkT0). clkT0 generated from a clock source, selected by the Clock
Select bits (CS0[2:0]). When no clock source is selected (CS0=0x0) the timer is
stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides all counter clear or count
operations.
 Counting sequence is determined by setting WGM01 and WGM00 bits located in
TCCR0A and WGM02 bit located in the TCCR0B.

Modes of Operation
This determines the behaviour of the Timer/Counter and the Output Compare pins. It is
defined by the combination of the TCCR0A and WGM0[2:0] bits in the
TCCR0A.COM0x[1:0]
Normal-Mode
 Timer increments.
 Wraps around at TOP = 0xFF.
 Starts again at 0.
 TOV0 interrupt flag set when TCNT0 reset to 0.
 Useful for generating interrupts every N time units.
 Set TCNT0 to an initial value (255 – N).
CTC(Clear-Timer-on-Compare) Mode
 Timer increments
 Wraps around at OCR0A
 OCR0A defines top value of counter
 Starts again at 0
 OCF0A interrupt flag set when TCNT0 reset to 0
 Pin OC0A can be made to toggle when counter resets
  Generate output waveform

Fast-PWM-Mode (3/7)
 Timer increments
 Wraps around at 0xFF (3) or OCR0A (7)
 Start again at 0
 Pin OC0x generates waveform
 Set (reset) when timer=0
 Reset (set) when timer=OCR0x

TC1 - 16-bit-Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing, wave
generation, and signal timing measurement.
Same Timer/clock sources as TCO
Registers:
 TCNT1, OCR0A/B and Input Capture Register(ICR1) are all 16-Bit-registers and
special procedures are followed when accessing them.
 TCCR1A/B/C are 8-bit registers
 TIFR1
 TIMSK1
 The functions of the registers are similar to those of Timer/Counter one except some
are 16-bit processes and for the ICR1.
Counter Unit
16-bit bi-directional counter unit but similar sequence as TC0.
Input Capture Unit

 Event on input causes:

 Counter value (TCNT1) to be written to ICR1(Time-stamp)
 Interrupt flag ICF1 to be set(Causing an interrupt, if enabled)
 Pin ICP1 – Port B [0]
 Noise Canceller(Pulses less than 4 clock cycles long are filtered)
 Useful for measuring frequency and duty cycle(PWM inputs)

Output-Compare-Units
16-bit-Comparator

Modes of Operation
The modes are similar to those of TC0 except with additional modes like Phase-Correct-
PWM Mode and Phase-and-Frequency-Correct PWM Mode

TC2 - 8-bit-Timer/Counter2
Timer/Counter2 (TC2) is a general purpose, channel, 8-bit Timer/Counter module.

Registers
 TCNT2 ,OCR2A and OCR2B are 8-bit registers.
 TIFR2.
 TIMSK2.
 Asynchronous Status Register (ASSR) controls asynchronous operation of clock
source.
Timer/Counter Clock Sources:
TC2 can be clocked by internal synchronous or external asynchronous clock source: When
the Asynchronous TC2 bit in the ASSR.AS2 is written to '1', the clock source is taken from
the Timer/Counter Oscillator connected to TOSC1 and TOSC2.
TC2 has similar counter unit and output compare unit to TC0
POWER MODES(SLEEP-MODES)
 Enables application to shut down unused modules in the MCU, thereby saving power.

 To enter any sleep mode, the Sleep Enable bit in the Sleep Mode Control
 Register(SMCR.SE)must be written to '1' and a SLEEP instruction must be executed.
 Sleep Mode Select bits(SM[2:0]) select which sleep mode.

Idle-Mode
Writing ‘000’ to SM[2:0] bits, SLEEP instruction makes MCU enter Idle mode, stopping
CPU but allowing SPI, USART, Analog-Comparator, 2-wire Serial Interface, Timer/
Counters, Watchdog, and interrupt system to continue operating. This mode basically halts
clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external and some internal interrupts.
ADC-Noise-Reduction-Mode
Writing ‘001' to SM[2:0] bits, the SLEEP instruction makes the MCU enter ADC-Noise-
Reduction mode, stopping CPU but allowing ADC, external interrupts, 2-wire Serial
Interface address watch, Timer/Counter2(1), and Watchdog to continue operating. It basically
halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
Except ADC Conversion Complete interrupt only these events wake MCU from this mode:
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• 2-wire Serial Interface address match
Power-Down Mode
When the SM[2:0] bits are written to '010', the SLEEP instruction makes the MCU enter
Power-Down mode. In this mode, external Oscillator is stopped, while external interrupts, 2-
wire Serial Interface, address watch, and the Watchdog continue operating.
Only one of these events can wake up the MCU:
• External Reset
• Watchdog System Reset
• Watchdog Interrupt
• Brown-out Reset
• 2-wire Serial Interface address match
• External level interrupt on INT
• Pin change interrupt
This mode basically halts all generated clocks, allowing operation of asynchronous modules
only.
Power-save Mode
When the SM[2:0] bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode.
This mode is identical to Power-down, with one exception:
If TC2 is enabled, it will keep running during sleep. The device can wake up from either
Timer Overflow or Output Compare event from TC2 if the corresponding Timer/Counter2
interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.
Standby Mode
When the SM[2:0] bits are written to '110' and an external crystal/resonator clock option is
selected, SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-Down with the exception that the Oscillator is kept running. From Standby mode, the
device wakes up in six clock cycles.

Extended Standby Mode

When the SM[2:0] bits are written to '111' and an external crystal/resonator clock option
selected, the SLEEP instruction makes the MCU enter this mode. It is identical to Power-
Save mode with exception that Oscillator is kept running.
ADC - Analog to Digital Converter
ATmega328P features a 10-bit successive approximation ADC which is connected to an 8-
channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from
the pins of Port A.
Sample and Hold circuit ensures input voltage to the ADC is held at constant level during
conversion.
Reference is selectable, either an external reference can be used or the internal 2.56V
reference can be brought into action.  There external reference can be connected to the AREF
pin.

The analog input channel is selected by writing to the MUX bits in the ADC Multiplexer
Selection register ADMUX.MUX[3:0]. Any of the ADC input pins, plus GND and fixed
bandgap voltage reference, can be selected as single ended inputs to ADC.
ADC is enabled by writing ‘1' to the ADC Enable bit in the ADC Control and Status Register
A (ADCSRA.ADEN).
Voltage reference and input channel selections don’t take effect until ADEN is set.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL.
To ensure that the content of the Data Registers belongs to the same conversion: On reading
ADCL, ADC access to Data Registers is blocked. On reading ADCH, ADC access to the
ADCH and ADCL Registers is re-enabled.
ADC has interrupt to be triggered when a conversion completes.

COMMUNICATION MODES
SPI

Master initiates communication, pulling low the Slave-Select(SS) pin of the desired Slave.
Both prepare the data to be sent in their respective shift Registers, and Master generates the
required clock pulses on SCK line (writing a byte to the SPI Data Register(SPDR) starts the
SPI clock generator) to interchange data. Data is always shifted from Master to Slave on the
Master-Out – Slave-In(MOSI), line, and from Slave to Master on the Master-In – Slave Out,
MISO, line. After shifting one byte, clock generator stops, setting end of Transmission Flag
(SPIF). If SPI Interrupt Enable bit (SPIE) in SPCR Register is set, interrupt is requested.
Master may continue to shift next byte by writing it into SPDR, or signal end of packet by
pulling high the SS line. The last incoming byte will be kept in the Buffer Register for later
use
For Slave, SPI interface will remain sleeping with MISO tri-stated as long as SS pin high. In
this state, software may update the contents of SPDR, but data will not be shifted out by
incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been
completely shifted, SPIF is set. If SPIE bit in SPCR is set, interrupt is requested. Slave may
continue to place new data to be sent into SPDR before reading incoming data. The last
incoming byte will be kept in Buffer Register for later use.
SPI Control Register 0

Data Modes(SPI-Modes)
Four combinations exist of SCK phase and polarity with respect to serial data determined by
CPHA and CPOL(from-SPCR).

USART(Universal-Synchronous-Asynchronous-Receiver-Transceiver)
USART is a highly flexible serial communication device that supports Multi-processor and
Double-Speed-Asynchronous-Communication Modes.
Multi-Processor Communication Mode
If Receiver is set up to receive frames containing 5 to 8 data bits, then the first stop bit
indicates if t frame contains data/address information. If Receiver is set up for frames with 9
data bits, then the ninth bit (RXB8) is used for identifying address/data frames. When frame
type bit (the-first-stop/the-ninth-bit) is '1', frame contains an address. When the frame type bit
is '0', it is a data frame.
Multi-Processor-Communication-mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which slave-MCU
has been addressed. If a particular slave-MCU has been addressed, it will receive the
following data frames as normal, while the other slave MCUs will ignore the received frames
until another address frame is received.
NOTE: The USART can be set to a master SPI compliant mode of operation(USARTSPI)

TWI - 2-wire-Serial-Interface
TWI is ideally suited for typical microcontroller applications.
TWI protocol allows the systems designer to interconnect up to 128 different devices using
only two bidirectional bus lines: one for clock (SCL) and one for data (SDA).
TW1 Transmission Modes
The TWI can operate in one of four major modes:
• Master Transmitter (MT)
A number of data bytes are transmitted to a Slave Receiver
• Master Receiver (MR)
a number of data bytes are received from a Slave Transmitter
• Slave Transmitter (ST)
a number of data bytes are transmitted to a Master Receiver
• Slave Receiver (SR)
a number of data bytes are received from a Master Transmitter

CLOCK SYSTEM
Clock-Control-Unit-Outputs
CPU-Clock(clkCPU)
Routed to parts of the system concerned with AVR-Core operation..
I/O-Clock(clkI/O)
Used by most I/O modules also the External Interrupt module
Flash-Clock(clkFLASH)
Controls Flash-Memory-interface operation and is responsible for memory read write.
Asynchronous-Timer-Clock (clkASY)
Allows the Asynchronous Timer/Counter to be clocked directly from an external clock. ADC
ADC-Clock(clkADC)
Allows halting the CPU and I/O clocks while ADC conversion in order to reduce noise
generated by digital circuitry.
Clock Sources
The device has the following clock sources, selectable by Flash Fuse bits
Clock from the selected source is input to the AVR clock generator and routed to the
appropriate modules.

Low Power Crystal Oscillator

This has reduced voltage swing on XTAL2 output.
If crystal frequency exceeds specification of the device (depends on VCC), the
CKDIV8(Fuse) can be programmed in order to divide the internal frequency by 8 to meet
specification of device(Same for full-swing-crystal-oscillator).

It can operate in three different modes, each optimized for specific frequency range and
selected by the fuses CKSEL3…1.

Full Swing Crystal Oscillator

It has rail-to-rail swing on the XTAL2 output. It will only operate for VCC
= 2.7 – 5.5 volts.
C1&C2 should always be equal for both crystals and resonators with optimal value of the
capacitors depending crystal or resonator in use, amount of stray capacitance, and
electromagnetic noise of the environment.

Low Frequency Crystal Oscillator

It is optimized for use with a 32.768kHz watch crystal.
Calibrated Internal RC Oscillator
By-default, it provides approximate 8.0MHz clock.
Though voltage and temperature dependent, it can be very accurately calibrated by the user.
It may be selected as the system clock by programming the CKSEL Fuses.
If selected, it operates with no external components.

128kHz Internal Oscillator

It is a low power Oscillator providing a 128kHz clock, nominal at 3V and 25 oC.
It can be selected as the system-clock by programming the CKSEL Fuses to “11”.

External Clock
To drive the device from an external clock source the XTAL1 pin is connected to the clock
source and the XTAL2 pin can be used as GPIO PB7