MC34262, MC33262

Power Factor Controllers

The MC34262/MC33262 are active power factor controllers
specifically designed for use as a preconverter in electronic ballast
and in off−line power converter applications. These integrated
circuits feature an internal startup timer for stand−alone applications,
a one quadrant multiplier for near unity power factor, zero current
detector to ensure critical conduction operation, transconductance http://onsemi.com
error amplifier, quickstart circuit for enhanced startup, trimmed
internal bandgap reference, current sensing comparator, and a totem
pole output ideally suited for driving a power MOSFET. POWER FACTOR
Also included are protective features consisting of an overvoltage
comparator to eliminate runaway output voltage due to load removal, CONTROLLERS
input undervoltage lockout with hysteresis, cycle−by−cycle current
limiting, multiplier output clamp that limits maximum peak switch MARKING
current, an RS latch for single pulse metering, and a drive output high
DIAGRAMS
state clamp for MOSFET gate protection. These devices are
available in dual−in−line and surface mount plastic packages.
8
Features
PDIP−8 MC3x262P
• Overvoltage Comparator Eliminates Runaway Output Voltage P SUFFIX AWL
• Internal Startup Timer CASE 626 YYWWG
8
• One Quadrant Multiplier
1
1
• Zero Current Detector
• Trimmed 2% Internal Bandgap Reference
• Totem Pole Output with High State Clamp 8
3x262
• Undervoltage Lockout with 6.0 V of Hysteresis SOIC−8
ALYW
D SUFFIX
• Low Startup and Operating Current 8
1 CASE 751
G
• Supersedes Functionality of SG3561 and TDA4817 1
• These are Pb−Free and Halide−Free Devices
x = 3 or 4
A = Assembly Location
Zero Current Detector Zero Current WL, L = Wafer Lot
Detect Input
5 YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
2.5V Undervoltage G = Pb−Free Package
VCC
Reference Lockout
8

PIN CONNECTIONS

Voltage Feedback
Drive Output 1 8 VCC
Input
Multiplier, 7 Compensation 2 7 Drive Output
Latch, Multiplier Input 3 6 GND
PWM, Current Sense
Input Current Sense 4 5 Zero Current
Timer, 4
Overvoltage Input Detect Input
&
Comparator (Top View)
Logic
+
1.08 Vref
ORDERING INFORMATION
Error Amp + See detailed ordering and shipping information in the package
Multiplier Vref
Multiplier Voltage dimensions section on page 17 of this data sheet.
Input 3
Feedback
1 Input
Quickstart

GND 6 Compensation 2
Figure 1. Simplified Block Diagram

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

August, 2013 − Rev. 14 MC34262/D
 MC34262, MC33262

MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) IO 500 mA
Current Sense, Multiplier, and Voltage Feedback Inputs Vin −1.0 to +10 V
Zero Current Detect Input Iin mA
High State Forward Current 50
Low State Reverse Current −10
Power Dissipation and Thermal Characteristics
P Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 70°C PD 800 mW
Thermal Resistance, Junction−to−Air RqJA 100 °C/W
D Suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C PD 450 mW
Thermal Resistance, Junction−to−Air RqJA 178 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature (Note 4) TA °C
MC34262 0 to + 85
MC33262 − 40 to +105
Storage Temperature Tstg − 65 to +150 °C
ESD Protection (Note 2)
Human Body Model ESD HBM 2000 V
Machine Model ESD MM 200 V
Charged Device Model ESD CDM 2000 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum package power dissipation limits must be observed.
2. ESD protection per JEDEC JESD22−A114−F for HBM, per JEDEC JESD22−A115−A for MM, and per JEDEC JESD22−C101D for CDM.
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (VCC = 12 V (Note 3), for typical values TA = 25°C, for min/max values TA is the operating
ambient temperature range that applies (Note 4), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ERROR AMPLIFIER
Voltage Feedback Input Threshold VFB V
TA = 25°C 2.465 2.5 2.535
TA = Tlow to Thigh (VCC = 12 V to 28 V) 2.44 − 2.54
Line Regulation (VCC = 12 V to 28 V, TA = 25°C) Regline − 1.0 10 mV
Input Bias Current (VFB = 0 V) IIB − − 0.1 − 0.5 mA
Transconductance (TA = 25°C) gm 80 100 130 mmho
Output Current IO mA
Source (VFB = 2.3 V) − 10 −
Sink (VFB = 2.7 V) − 10 −
Output Voltage Swing V
High State (VFB = 2.3 V) VOH(ea) 5.8 6.4 −
Low State (VFB = 2.7 V) VOL(ea) − 1.7 2.4

OVERVOLTAGE COMPARATOR
Voltage Feedback Input Threshold VFB(OV) 1.065 VFB 1.08 VFB 1.095 VFB V
MULTIPLIER
Input Bias Current, Pin 3 (VFB = 0 V) IIB − − 0.1 − 0.5 mA
Input Threshold, Pin 2 Vth(M) 1.05 VOL(EA) 1.2 VOL(EA) − V
3. Adjust VCC above the startup threshold before setting to 12 V.
4. Tlow = 0°C for MC34262 Thigh = +85°C for MC34262
= −40°C for MC33262 = +105°C for MC33262.

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 MC34262, MC33262

ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V (Note 6), for typical values TA = 25°C, for min/max values TA is the
operating ambient temperature range that applies (Note 7), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
MULTIPLIER
Dynamic Input Voltage Range V
Multiplier Input (Pin 3) VPin 3 0 to 2.5 0 to 3.5 −
Compensation (Pin 2) VPin 2 Vth(M) to Vth(M) to −
(Vth(M) + 1.0) (Vth(M) + 1.5)
Multiplier Gain (VPin 3 = 0.5 V, VPin 2 = Vth(M) + 1.0 V) (Note 8) K 0.43 0.65 0.87 1/V
ZERO CURRENT DETECTOR
Input Threshold Voltage (Vin Increasing) Vth 1.33 1.6 1.87 V
Hysteresis (Vin Decreasing) VH 100 200 300 mV
Input Clamp Voltage V
High State (IDET = + 3.0 mA) VIH 6.1 6.7 −
Low State (IDET = − 3.0 mA) VIL 0.3 0.7 1.0
CURRENT SENSE COMPARATOR
Input Bias Current (VPin 4 = 0 V) IIB − − 0.15 −1.0 mA
Input Offset Voltage (VPin 2 = 1.1 V, VPin 3 = 0 V) VIO − 9.0 25 mV
Maximum Current Sense Input Threshold (Note 9) Vth(max) 1.3 1.5 1.8 V
Delay to Output tPHL(in/out) − 200 400 ns
DRIVE OUTPUT
Output Voltage (VCC = 12 V) V
Low State (ISink = 20 mA) VOL − 0.3 0.8
Low State (ISink = 200 mA) − 2.4 3.3
High State (ISource = 20 mA) VOH 9.8 10.3 −
High State (ISource = 200 mA) 7.8 8.4 −
Output Voltage (VCC = 30 V) VO(max) V
High State (ISource = 20 mA, CL = 15 pF) 14 16 18
Output Voltage Rise Time (CL = 1.0 nF) tr − 50 120 ns
Output Voltage Fall Time (CL = 1.0 nF) tf − 50 120 ns
Output Voltage with UVLO Activated VO(UVLO) − 0.1 0.5 V
(VCC = 7.0 V, ISink = 1.0 mA)
RESTART TIMER
Restart Time Delay tDLY 200 620 − ms
UNDERVOLTAGE LOCKOUT
Startup Threshold (VCC Increasing) Vth(on) 11.5 13 14.5 V
Minimum Operating Voltage After Turn−On (VCC Decreasing) VShutdown 7.0 8.0 9.0 V
Hysteresis VH 3.8 5.0 6.2 V
TOTAL DEVICE
Power Supply Current ICC mA
Startup (VCC = 7.0 V) − 0.25 0.4
Operating − 6.5 12
Dynamic Operating (50 kHz, CL = 1.0 nF) − 9.0 20
Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − V
5. Maximum package power dissipation limits must be observed.
6. Adjust VCC above the startup threshold before setting to 12 V.
7. Tlow = 0°C for MC34262 Thigh = +85°C for MC34262
= −40°C for MC33262 = +105°C for MC33262.
Pin 4 Threshold
8. K +
VPin 3 (VPin2 * Vth(M))
9. This parameter is measured with VFB = 0 V, and VPin 3 = 3.0 V.

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 MC34262, MC33262

VCS, CURRENT SENSE PIN 4 THRESHOLD (V)

VCS, CURRENT SENSE PIN 4 THRESHOLD (V) 1.6 0.08
VCC = 12 V VPin 2 = 3.75 V
1.4 TA = 25°C 0.07 VPin 2 = 3.5 V
VPin 2 = 3.25 V VCC = 12 V
1.2 VPin 2 = 3.75 V 0.06 VPin 2 = 3.0 V TA = 25°C
VPin 2 = 2.75 V
VPin 2 = 3.5 V
1.0 0.05 VPin 2 = 2.75 V VPin 2 = 2.5 V
VPin 2 = 3.25 V
0.8 VPin 2 = 2.5 V 0.04
VPin 2 = 3.0 V VPin 2 = 2.25 V
0.6 VPin 2 = 2.25 V 0.03
0.4 0.02
VPin 2 = 2.0 V
0.2 0.01
VPin 2 = 2.0 V
0 0
-0.2 0.6 1.4 2.2 3.0 3.8 -0.12 -0.06 0 0.06 0.12 0.18 0.24
VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V) VM, MULTIPLIER PIN 3 INPUT VOLTAGE (V)

Figure 2. Current Sense Input Threshold Figure 3. Current Sense Input Threshold
versus Multiplier Input versus Multiplier Input, Expanded View
DVFB, VOLTAGE FEEDBACK THRESHOLD CHANGE (mV)

DVFB(OV), OVERVOLTAGE INPUT THRESHOLD (%VFB)

4.0 110
VCC = 12 V VCC = 12 V
Pins 1 to 2
0
109

-4.0
108
-8.0

107
-12

-16 106
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 4. Voltage Feedback Input Threshold Figure 5. Overvoltage Comparator Input

Change versus Temperature Threshold versus Temperature

120 0
Phase VCC = 12 V 4.00 V VCC = 12 V
gm, TRANSCONDUCTANCE (mmho)

100 VO = 2.5 V to 3.5 V 30 RL = 100 k

q, EXCESS PHASE (DEGREES)

Transconductance RL = 100 k to 3.0 V CL = 2.0 pF

CL = 2.0 pF TA = 25°C
80 TA = 25°C 60 V/DIV
3.25 V
60 90
0

40 120

20 150 2.50 V

0 180
3.0 k 10 k 30 k 100 k 300 k 1.0 M 3.0 M 5.0 ms/DIV
f, FREQUENCY (Hz)

Figure 6. Error Amp Transconductance and Figure 7. Error Amp Transient Response
Phase versus Frequency

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 MC34262, MC33262

1.80 900 800

Ichg, QUICKSTART CHARGE CURRENT (mA)

Vchg, QUICKSTART CHARGE VOLTAGE (V)

VCC = 12 V VCC = 12 V

tDLY, RESTART TIME DELAY (ms)

1.76 800 700

1.72 700 600

Voltage Current
1.68 600 500

1.64 500 400

-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 8. Quickstart Charge Current Figure 9. Restart Timer Delay

versus Temperature versus Temperature

1.7 0
VCC VCC = 12 V
Vsat, OUTPUT SATURATION VOLTAGE (V)
VCC = 12 V
Upper Threshold 80 ms Pulsed Load
Vth, THRESHOLD VOLTAGE (V)

(Vin, Increasing) -2.0 120 Hz Rate

1.6
Source Saturation
-4.0 (Load to Ground)

1.5
-6.0
4.0
Sink Saturation
1.4 (Load to VCC)
2.0
Lower Threshold
(Vin, Decreasing) GND
1.3 0
-55 -25 0 25 50 75 100 125 0 80 160 240 320
TA, AMBIENT TEMPERATURE (°C) IO, OUTPUT LOAD CURRENT (mA)

Figure 10. Zero Current Detector Input Figure 11. Output Saturation Voltage
Threshold Voltage versus Temperature versus Load Current
VO , OUTPUT VOLTAGE

VCC = 12 V VCC = 12 V
90%
CL = 1.0 nF CL = 15 pF 5.0 V/DIV
TA = 25°C TA = 25°C
I CC , SUPPLY CURRENT

100 mA/DIV

10%

100 ns/DIV 100 ns/DIV

Figure 12. Drive Output Waveform Figure 13. Drive Output Cross Conduction

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 MC34262, MC33262

16 14

13
I CC , SUPPLY CURRENT (mA)

VCC , SUPPLY VOLTAGE (V)

Startup Threshold
12 (VCC Increasing)
12

11
8.0
VFB = 0 V 10
Current Sense = 0 V
Multiplier = 0 V 9.0 Minimum Operating Threshold
4.0
CL = 1.0 nF (VCC Decreasing)
f = 50 kHz 8.0
TA = 25°C
0 7.0
0 10 20 30 40 -55 -25 0 25 50 75 100 125
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

Figure 14. Supply Current Figure 15. Undervoltage Lockout Thresholds

versus Supply Voltage versus Temperature

FUNCTIONAL DESCRIPTION
Introduction frequency switching converter for the power processing,
With the goal of exceeding the requirements of with the boost converter being the most popular topology,
legislation on line−current harmonic content, there is an Figure 18. Since active input circuits operate at a frequency
ever increasing demand for an economical method of much higher than that of the ac line, they are smaller,
obtaining a unity power factor. This data sheet describes a lighter in weight, and more efficient than a passive circuit
monolithic control IC that was specifically designed for that yields similar results. With proper control of the
power factor control with minimal external components. It preconverter, almost any complex load can be made to
offers the designer a simple, cost−effective solution to appear resistive to the ac line, thus significantly reducing
obtain the benefits of active power factor correction. the harmonic current content.
Most electronic ballasts and switching power supplies
use a bridge rectifier and a bulk storage capacitor to derive Vpk
raw dc voltage from the utility ac line, Figure 16.
Rectified
Rectifiers Converter
DC
AC
Line 0
Line Sag
+ Bulk
Storage Load
Capacitor
AC Line
Voltage

Figure 16. Uncorrected Power Factor Circuit 0

This simple rectifying circuit draws power from the line AC Line
Current
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and results
in a high charge current spike, Figure 17. Since power is
only taken near the line voltage peaks, the resulting spikes Figure 17. Uncorrected Power Factor
of current are extremely nonsinusoidal with a high content Input Waveforms
of harmonics. This results in a poor power factor condition
where the apparent input power is much higher than the real The MC34262, MC33262 are high performance, critical
power. Power factor ratios of 0.5 to 0.7 are common. conduction, current−mode power factor controllers
Power factor correction can be achieved with the use of specifically designed for use in off−line active
either a passive or an active input circuit. Passive circuits preconverters. These devices provide the necessary
usually contain a combination of large capacitors, features required to significantly enhance poor power
inductors, and rectifiers that operate at the ac line factor loads by keeping the ac line current sinusoidal and
frequency. Active circuits incorporate some form of a high in phase with the line voltage.

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 MC34262, MC33262

Operating Description UC3842 series. Referring to the block diagrams in

The MC34262, MC33262 contain many of the building Figures 20, 21, and 22 note that a multiplier has been added
blocks and protection features that are employed in modern to the current sense loop and that this device does not
high performance current mode power supply controllers. contain an oscillator. The reasons for these differences will
There are, however, two areas where there is a major become apparent in the following discussion. A description
difference when compared to popular devices such as the of each of the functional blocks is given below.

Rectifiers PFC Preconverter Converter

AC
Line High
+ + Bulk
Frequency Load
Storage
Bypass MC34362 Capacitor
Capacitor

Figure 18. Active Power Factor Correction Preconverter

Error Amplifier can occur during initial startup, sudden load removal, or
An Error Amplifier with access to the inverting input and during output arcing and is the result of the low bandwidth
output is provided. The amplifier is a transconductance that must be used in the Error Amplifier control loop. The
type, meaning that it has high output impedance with Overvoltage Comparator monitors the peak output voltage
controlled voltage−to−current gain. The amplifier features of the converter, and when exceeded, immediately
a typical gm of 100 mmhos (Figure 6). The noninverting terminates MOSFET switching. The comparator threshold
input is internally biased at 2.5 V ± 2.0% and is not pinned is internally set to 1.08 Vref. In order to prevent false
out. The output voltage of the power factor converter is tripping during normal operation, the value of the output
typically divided down and monitored by the inverting filter capacitor C3 must be large enough to keep the
input. The maximum input bias current is − 0.5 mA, which peak−to−peak ripple less than 16% of the average dc
can cause an output voltage error that is equal to the product output. The Overvoltage Comparator input to Drive Output
of the input bias current and the value of the upper divider turn−off propagation delay is typically 400 ns. A
resistor R2. The Error Amp output is internally connected comparison of startup overshoot without and with the
to the Multiplier and is pinned out (Pin 2) for external loop Overvoltage Comparator circuit is shown in Figure 24.
compensation. Typically, the bandwidth is set below 20 Hz,
Multiplier
so that the amplifier’s output voltage is relatively constant
A single quadrant, two input multiplier is the critical
over a given ac line cycle. In effect, the error amp monitors
element that enables this device to control power factor.
the average output voltage of the converter over several
The ac full wave rectified haversines are monitored at Pin 3
line cycles. The Error Amp output stage was designed to
with respect to ground while the Error Amp output at Pin 2
have a relatively constant transconductance over
is monitored with respect to the Voltage Feedback Input
temperature. This allows the designer to define the
threshold. The Multiplier is designed to have an extremely
compensated bandwidth over the intended operating
linear transfer curve over a wide dynamic range, 0 V to
temperature range. The output stage can sink and source
3.2 V for Pin 3, and 2.0 V to 3.75 V for Pin 2, Figures 2 and
10 mA of current and is capable of swinging from 1.7 V to
3. The Multiplier output controls the Current Sense
6.4 V, assuring that the Multiplier can be driven over its
Comparator threshold as the ac voltage traverses
entire dynamic range.
sinusoidally from zero to peak line, Figure 18. This has the
A key feature to using a transconductance type amplifier,
effect of forcing the MOSFET on−time to track the input
is that the input is allowed to move independently with
line voltage, resulting in a fixed Drive Output on−time, thus
respect to the output, since the compensation capacitor is
making the preconverter load appear to be resistive to the
connected to ground. This allows dual usage of of the
ac line. An approximation of the Current Sense
Voltage Feedback Input pin by the Error Amplifier and by
Comparator threshold can be calculated from the following
the Overvoltage Comparator.
equation. This equation is accurate only under the given
Overvoltage Comparator test condition stated in the electrical table.
An Overvoltage Comparator is incorporated to eliminate VCS, Pin 4 Threshold ≈ 0.65 (VPin 2 − Vth(M)) VPin 3
the possibility of runaway output voltage. This condition

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 MC34262, MC33262

A significant reduction in line current distortion can be Current Sense Comparator and RS Latch
attained by forcing the preconverter to switch as the ac line The Current Sense Comparator RS Latch configuration
voltage crosses through zero. The forced switching is used ensures that only a single pulse appears at the Drive
achieved by adding a controlled amount of offset to the Output during a given cycle. The inductor current is
Multiplier and Current Sense Comparator circuits. The converted to a voltage by inserting a ground−referenced
equation shown below accounts for the built−in offsets and sense resistor R7 in series with the source of output switch
is accurate to within ten percent. Let Vth(M) = 1.991 V Q1. This voltage is monitored by the Current Sense Input
and compared to a level derived from the Multiplier output.
VCS, Pin 4 Threshold = 0.544 (VPin 2 − Vth(M)) VPin 3
The peak inductor current under normal operating
+ 0.0417 (VPin 2 − Vth(M))
conditions is controlled by the threshold voltage of Pin 4
Zero Current Detector where:
The MC34262 operates as a critical conduction current Pin 4 Threshold
IL(pk ) =
mode controller, whereby output switch conduction is R7
initiated by the Zero Current Detector and terminated when
Abnormal operating conditions occur during
the peak inductor current reaches the threshold level preconverter startup at extremely high line or if output
established by the Multiplier output. The Zero Current voltage sensing is lost. Under these conditions, the
Detector initiates the next on−time by setting the RS Latch Multiplier output and Current Sense threshold will be
at the instant the inductor current reaches zero. This critical internally clamped to 1.5 V. Therefore, the maximum peak
conduction mode of operation has two significant benefits. switch current is limited to:
First, since the MOSFET cannot turn−on until the inductor 1.5 V
current reaches zero, the output rectifier reverse recovery Ipk(max) =
R7
time becomes less critical, allowing the use of an
inexpensive rectifier. Second, since there are no deadtime An internal RC filter has been included to attenuate any
gaps between cycles, the ac line current is continuous, thus high frequency noise that may be present on the current
limiting the peak switch to twice the average input current. waveform. This filter helps reduce the ac line current
distortion especially near the zero crossings. With the
The Zero Current Detector indirectly senses the inductor
component values shown in Figure 21, the Current Sense
current by monitoring when the auxiliary winding voltage
Comparator threshold, at the peak of the haversine varies
falls below 1.4 V. To prevent false tripping, 200 mV of
from 1.1 V at 90 Vac to 100 mV at 268 Vac. The Current
hysteresis is provided. Figure 10 shows that the thresholds Sense Input to Drive Output turn−off propagation delay is
are well−defined over temperature. The Zero Current typically less than 200 ns.
Detector input is internally protected by two clamps. The
upper 6.7 V clamp prevents input overvoltage breakdown Timer
while the lower 0.7 V clamp prevents substrate injection. A watchdog timer function was added to the IC to
Current limit protection of the lower clamp transistor is eliminate the need for an external oscillator when used in
provided in the event that the input pin is accidentally stand−alone applications. The Timer provides a means to
shorted to ground. The Zero Current Detector input to automatically start or restart the preconverter if the Drive
Drive Output turn−on propagation delay is typically 320 ns. Output has been off for more than 620 ms after the inductor
current reaches zero. The restart time delay versus
Peak temperature is shown in Figure 9.
Undervoltage Lockout and Quickstart
An Undervoltage Lockout comparator has been
Average
Inductor Current incorporated to guarantee that the IC is fully functional
before enabling the output stage. The positive power
supply terminal (VCC) is monitored by the UVLO
comparator with the upper threshold set at 13 V and the
lower threshold at 8.0 V. In the stand−by mode, with VCC
at 7.0 V, the required supply current is less than 0.4 mA.
This large hysteresis and low startup current allow the
0 implementation of efficient bootstrap startup techniques,
making these devices ideally suited for wide input range
off−line preconverter applications. An internal 36 V
On
clamp has been added from VCC to ground to protect the IC
MOSFET and capacitor C4 from an overvoltage condition. This
Q1
Off feature is desirable if external circuitry is used to delay the
startup of the preconverter. The supply current, startup, and
Figure 19. Inductor Current and MOSFET
operating voltage characteristics are shown in Figures 14
Gate Voltage Waveforms
and 15.

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A Quickstart circuit has been incorporated to optimize MOSFETs. The Drive Output is capable of up to ±500 mA
converter startup. During initial startup, compensation peak current with a typical rise and fall time of 50 ns with
capacitor C1 will be discharged, holding the error amp a 1.0 nF load. Additional internal circuitry has been added
output below the Multiplier threshold. This will prevent to keep the Drive Output in a sinking mode whenever the
Drive Output switching and delay bootstrapping of Undervoltage Lockout is active. This characteristic
capacitor C4 by diode D6. If Pin 2 does not reach the eliminates the need for an external gate pulldown resistor.
multiplier threshold before C4 discharges below the lower The totem−pole output has been optimized to minimize
UVLO threshold, the converter will “hiccup” and cross−conduction current during high speed operation. The
experience a significant startup delay. The Quickstart addition of two 10 W resistors, one in series with the source
circuit is designed to precharge C1 to 1.7 V, Figure 8. This output transistor and one in series with the sink output
level is slightly below the Pin 2 Multiplier threshold, transistor, helps to reduce the cross−conduction current and
allowing immediate Drive Output switching and bootstrap radiated noise by limiting the output rise and fall time. A
operation when C4 crosses the upper UVLO threshold. 16 V clamp has been incorporated into the output stage to
limit the high state VOH. This prevents rupture of the
Drive Output
MOSFET gate when VCC exceeds 20 V.
The MC34262/MC33262 contain a single totem−pole
output stage specifically designed for direct drive of power

APPLICATIONS INFORMATION
The application circuits shown in Figures 20, 21 and 22 0.998 at nominal line. Figures 21 and 22 are universal input
reveal that few external components are required for a preconverter examples that operate over a continuous input
complete power factor preconverter. Each circuit is a peak voltage range of 90 Vac to 268 Vac. Figure 21 provides an
detecting current−mode boost converter that operates in output power of 175 W (400 V at 440 mA) while Figure 22
critical conduction mode with a fixed on−time and variable provides 450 W (400 V at 1.125 A). Both circuits have an
off−time. A major benefit of critical conduction operation observed worst−case power factor of approximately 0.989.
is that the current loop is inherently stable, thus eliminating The input current and voltage waveforms of Figure 21 are
the need for ramp compensation. The application in shown in Figure 23 with operation at 115 Vac and 230 Vac.
Figure 20 operates over an input voltage range of 90 Vac to The data for each of the applications was generated with the
138 Vac and provides an output power of 80 W (230 V at test set−up shown in Figure 25.
350 mA) with an associated power factor of approximately

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Table 1. Design Equations

Notes Calculation Formula
Calculate the maximum required output power. Required Converter Output Power PO = VO IO
Calculated at the minimum required ac line voltage 2 2 PO
for output regulation. Let the efficiency h = 0.92 for Peak Inductor Current IL(pk) =
hVac(LL)
low line operation.
Let the switching cycle t = 40 ms for universal input
(85 to 265 Vac) operation and 20 ms for fixed input
Inductance
t ǒ VO
2
− Vac(LL) Ǔ h Vac(LL)2
(92 to 138 Vac, or 184 to 276 Vac) operation. LP =
2 VO PO
In theory the on−time ton is constant. In practice ton
tends to increase at the ac line zero crossings due 2 PO LP
Switch On−Time ton =
to the charge on capacitor C5. Let Vac = Vac(LL) for initial h Vac2
ton and toff calculations.
The off−time toff is greatest at the peak of the ac line ton
voltage and approaches zero at the ac line zero toff =
Switch Off−Time VO
crossings. Theta (q) represents the angle of the ac −1
line voltage. 2 Vac ⎪Sin q⎜

The minimum switching frequency occurs at the peak

of the ac line voltage. As the ac line voltage traverses 1
Switching Frequency f=
from peak to zero, toff approaches zero producing an ton + toff
increase in switching frequency.
Set the current sense threshold VCS to 1.0 V for
universal input (85 Vac to 265 Vac) operation and VCS
to 0.5 V for fixed input (92 Vac to 138 Vac, or Peak Switch Current R7 =
184 Vac to 276 Vac) operation. Note that VCS must IL(pk)
be <1.4 V.
Set the multiplier input voltage VM to 3.0 V at high Vac 2
line. Empirically adjust VM for the lowest distortion VM =
over the ac line voltage range while guaranteeing
startup at minimum line.
Multiplier Input Voltage
ǒ R5
R3
+1 Ǔ
The IIB R1 error term can be minimized with a divider
current in excess of 50 mA. Converter Output Voltage VO = Vref ǒ R2
R1
+1 Ǔ − IIB R2

The calculated peak−to−peak ripple must be less than

ǒ Ǔ
16% of the average dc output voltage to prevent false Converter Output 2
1
tripping of the Overvoltage Comparator. Refer to the Peak to Peak DVO(pp) = IO + ESR2
Overvoltage Comparator text. ESR is the equivalent Ripple Voltage 2pfac C3
series resistance of C3.
The bandwidth is typically set to 20 Hz. When operating gm
at high ac line, the value of C1 may need to be Error Amplifier Bandwidth BW =
2 p C1
increased. (See Figure 26)
The following converter characteristics must be chosen:
VO − Desired output voltage Vac − AC RMS line voltage
IO − Desired output current Vac (LL) − AC RMS low line voltage
DVO − Converter output peak−to−peak ripple voltage

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10
 MC34262, MC33262

1 C5 100k
R6 1N4934
D2 D4 8 D6
+
+ 36V 100
92 to RFI Zero Current 1.2V C4
138 Vac Filter D1 D3 Detector
+ 6.7V 5 22k
1.6V/ R4 T
1.4V
UVLO
2.5V
Reference + 13V/
8.0V MUR130
D5 VO
230V/
16V + 0.35A
Timer R 220
10 MTP
7 C3
Drive 8N50E
Delay Output Q1
RS 10
Latch

2.2M 1.0M
R5 20k 4 R2
Current Sense
Comparator 10pF 0.1
Overvoltage R7
1.5V
Comparator
+
1.08 Vref
Error Amp
10mA +
Multiplier Vref 1
0.01 7.5k 3
C2 R3 11k
Quickstart R1

6 2
0.68
C1

Figure 20. 80 W Power Factor Controller

Power Factor Controller Test Data

AC Line Input DC Output
Current Harmonic Distortion (% Ifund)
Vrms Pin PF Ifund THD 2 3 5 7 VO(pp) VO IO PO h(%)
90 85.9 0.999 0.93 2.6 0.08 1.6 0.84 0.95 4.0 230.7 0.350 80.8 94.0
100 85.3 0.999 0.85 2.3 0.13 1.0 1.2 0.73 4.0 230.7 0.350 80.8 94.7
110 85.1 0.998 0.77 2.2 0.10 0.58 1.5 0.59 4.0 230.7 0.350 80.8 94.9
120 84.7 0.998 0.71 3.0 0.09 0.73 1.9 0.58 4.1 230.7 0.350 80.8 95.3
130 84.4 0.997 0.65 3.9 0.12 1.7 2.2 0.61 4.1 230.7 0.350 80.8 95.7
138 84.1 0.996 0.62 4.6 0.16 2.4 2.3 0.60 4.1 230.7 0.350 80.8 96.0
This data was taken with the test set−up shown in Figure 25.
T = Coilcraft N2881−A
Primary: 62 turns of # 22 AWG
Secondary: 5 turns of # 22 AWG
Core: Coilcraft PT2510, EE 25
Gap: 0.072″ total for a primary inductance (LP) of 320 mH
Heatsink = AAVID Engineering Inc. 590302B03600, or 593002B03400

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11
 MC34262, MC33262

1 C5 100k
R6 1N4934
D2 D4 8 D6
+
+ 36V 100
90 to RFI Zero Current 1.2V C4
268 Vac Filter D1 D3 Detector
+ 6.7V 5 22k
1.6V/ R4 T
1.4V
UVLO
2.5V
Reference + 13V/
8.0V MUR460
D5 VO
+ 400V/
Timer R 16V 330 0.44A
10 MTP
7 C3
Drive 14N50E
Delay Output Q1
RS 10
Latch

1.3M 1.6M
R5 20k 4 R2
Current Sense
Comparator 10pF 0.1
Overvoltage R7
1.5V
Comparator
+
1.08 Vref
Error Amp
10mA +
Multiplier Vref 1
0.01 12k 3
C2 R3 10k
Quickstart R1

6 2
0.68
C1

Figure 21. 175 W Universal Input Power Factor Controller

Power Factor Controller Test Data

AC Line Input DC Output
Current Harmonic Distortion (% Ifund)
Vrms Pin PF Ifund THD 2 3 5 7 VO(pp) VO IO PO h(%)
90 193.3 0.991 2.15 2.8 0.18 2.6 0.55 1.0 3.3 402.1 0.44 176.9 91.5
120 190.1 0.998 1.59 1.6 0.10 1.4 0.23 0.72 3.3 402.1 0.44 176.9 93.1
138 188.2 0.999 1.36 1.2 0.12 1.3 0.65 0.80 3.3 402.1 0.44 176.9 94.0
180 184.9 0.998 1.03 2.0 0.10 0.49 1.2 0.82 3.4 402.1 0.44 176.9 95.7
240 182.0 0.993 0.76 4.4 0.09 1.6 2.3 0.51 3.4 402.1 0.44 176.9 97.2
268 180.9 0.989 0.69 5.9 0.10 2.3 2.9 0.46 3.4 402.1 0.44 176.9 97.8
This data was taken with the test set−up shown in Figure 25.
T = Coilcraft N2880−A
Primary: 78 turns of # 16 AWG
Secondary: 6 turns of # 18 AWG
Core: Coilcraft PT4215, EE 42−15
Gap: 0.104″ total for a primary inductance (LP) of 870 mH
Heatsink = AAVID Engineering Inc. 590302B03600

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12
 MC34262, MC33262

2 C5 100k
R6 1N4934
D2 D4 8 D6
+
+ 36V 100
Zero Current 1.2V C4
90 to RFI
D1 D3 Detector
268 Vac Filter
+ 6.7V 5 22k
1.6V/ R4 T
1.4V
UVLO
2.5V
Reference + 13V/
8.0V MUR460
D5 VO
400V/
16V + 1.125A
Timer R 330
10 MTW
7 C3
Drive 20N50E
Delay Output Q1
RS 10
Latch

1.3M 1.6M
R5 20k 4 330 R2
Current Sense
Comparator 10pF 0.001 0.05
Overvoltage R7
1.5V
Comparator
+
1.08 Vref
Error Amp
10mA +
Multiplier Vref
0.01 12k 1
3
C2 R3 10k
Quickstart R1

6 2
0.68
C1

Figure 22. 450 W Universal Input Power Factor Controller

Power Factor Controller Test Data

AC Line Input DC Output
Current Harmonic Distortion (% Ifund)
Vrms Pin PF Ifund THD 2 3 5 7 VO(pp) VO IO PO h(%)
90 489.5 0.990 5.53 2.2 0.10 1.5 0.25 0.83 8.8 395.5 1.14 450.9 92.1
120 475.1 0.998 3.94 2.5 0.12 0.29 0.62 0.52 8.8 395.5 1.14 450.9 94.9
138 470.6 0.998 3.38 2.1 0.06 0.70 1.1 0.41 8.8 395.5 1.14 450.9 95.8
180 463.4 0.998 2.57 4.1 0.21 2.0 1.6 0.71 8.9 395.5 1.14 450.9 97.3
240 460.1 0.996 1.91 4.8 0.14 4.3 2.2 0.63 8.9 395.5 1.14 450.9 98.0
268 459.1 0.995 1.72 5.8 0.10 5.0 2.5 0.61 8.9 395.5 1.14 450.9 98.2
This data was taken with the test set−up shown in Figure 25.
T = Coilcraft P3657−A
Primary: 38 turns Litz wire, 1300 strands of #48 AWG, Kerrigan−Lewis, Chicago, IL
Secondary: 3 turns of # 20 AWG
Core: Coilcraft PT4220, EE 42−20
Gap: 0.180″ total for a primary inductance (LP) of 190 mH
Heatsink = AAVID Engineering Inc. 604953B04000 Extrusion

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13
 MC34262, MC33262

Input = 115 VAC, Output = 175 W Input = 230 VAC, Output = 175 W
Voltage = 100 V/DIV

Voltage = 100 V/DIV

Current = 1.0 A/DIV

Current = 1.0 A/DIV

2.0 ms/DIV 2.0 ms/DIV

Figure 23. Power Factor Corrected Input Waveforms

(Figure 21 Circuit)

Without Overvoltage Comparator With Overvoltage Comparator

500 V 8%
26% 432 V
400 V 400 V
80 V/DIV

80 V/DIV
0V 0V
200 ms/DIV 200 ms/DIV

Figure 24. Output Voltage Startup Overshoot

(Figure 21 Circuit)

2X Step-Up
Isolation RFI Test Filter
Line Transformer HI HI
AC POWER ANALYZER T
PM 1000
0.005 0 to 270 Vac
115 Vac W VA PF Vrms Arms Output to Power
Input
A V 0.1 1.0
Factor
Autoformer 0 1 2 3 5 0.005 Controller Circuit
I O Vcf Acf Ainst FREQ HARM
Neutral LO LO
7 9 11 13 Voltech

Earth

Figure 25. Power Factor Test Set−Up

An RFI filter is required for best performance when connecting the preconverter directly to the ac line. The filter attenuates
the level of high frequency switching that appears on the ac line current waveform. Figures 20 and 21 work well with
commercially available two stage filters such as the Delta Electronics 03DPCG5. Shown above is a single stage test filter
that can easily be constructed with four ac line rated capacitors and a common−mode transformer. Coilcraft CMT3−28−2
was used to test Figures 20 and 21. It has a minimum inductance of 28 mH and a maximum current rating of 2.0 A. Coilcraft
CMT4−17−9 was used to test Figure 22. It has a minimum inductance of 17 mH and a maximum current rating of 9.0 A. Circuit
conversion efficiency h (%) was calculated without the power loss of the RFI filter.

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14
 MC34262, MC33262

Error Amp R2
10mA +
1

R1

6 2

C1

Figure 26. Error Amp Compensation

The Error Amp output is a high impedance node and is susceptible to noise pickup. To minimize pickup, compensation
capacitor C1 must be connected as close to Pin 2 as possible with a short, heavy ground returning directly to Pin 6. When
operating at high ac line, the voltage at Pin 2 may approach the lower threshold of the Multiplier, ≈ 2.0 V. If there is
excessive ripple on Pin 2, the Multiplier will be driven into cut−off causing circuit instability, high distortion and poor power
factor. This problem can be eliminated by increasing the value of C1.

7 7

22k 4 R 22k 4

10pF C 10pF D1 R7
R7
Current Current
Sense Sense
Comparator Comparator

Figure 27. Current Waveform Spike Suppression Figure 28. Negative Current Waveform
Spike Suppression
A narrow turn−on spike is usually present on the leading edge of A negative turn−off spike can be observed on the trailing edge of
the current waveform and can cause circuit instability. The the current waveform. This spike is due to the parasitic
MC34262 provides an internal RC filter with a time constant of inductance of resistor R7, and if it is excessive, it can cause
220 ns. An additional external RC filter may be required in circuit instability. The addition of Schottky diode D1 can
universal input applications that are above 200 W. It is effectively clamp the negative spike. The addition of the external
suggested that the external filter be placed directly at the Current RC filter shown in Figure 27 may provide sufficient spike
Sense Input and have a time constant that approximates the attenuation.
spike duration.

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15
 MC34262, MC33262

(Top View)

3.0″

4.5″
(Bottom View)

NOTE: Use 2 oz. copper laminate for optimum circuit performance.

Figure 29. Printed Circuit Board and Component Layout

(Circuits of Figures 20 and 21)

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16
 MC34262, MC33262

DEVICE ORDERING INFORMATION

Device Operating Temperature Range Package Shipping†
MC34262DG SOIC−8 98 Units / Rail
(Pb−Free)

MC34262DR2G SOIC−8 2500 / Tape & Reel

TA = 0°C to +85°C (Pb−Free)

MC34262PG PDIP−8 50 Units / Rail

(Pb−Free)

MC33262DG SOIC−8 98 Units / Rail

(Pb−Free)

MC33262DR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)
TA = −40°C to +105°C
MC33262PG PDIP−8 50 Units / Rail
(Pb−Free)

MC33262CDR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
NOTES:
D A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
E 2. CONTROLLING DIMENSION: INCHES.
H 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
8 5
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
E1 NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
1 4
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
NOTE 8 LEADS UNCONSTRAINED.
c 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
b2 B END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
NOTE 5
INCHES MILLIMETERS
A2 DIM MIN MAX MIN MAX
e/2 A −−−− 0.210 −−− 5.33
A NOTE 3 A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
L b 0.014 0.022 0.35 0.56
b2 0.060 TYP 1.52 TYP
C 0.008 0.014 0.20 0.36
D 0.355 0.400 9.02 10.16
SEATING
PLANE D1 0.005 −−−− 0.13 −−−
A1 E 0.300 0.325 7.62 8.26
C M E1 0.240 0.280 6.10 7.11
D1 e 0.100 BSC 2.54 BSC
eB −−−− 0.430 −−− 10.92
e eB L 0.115 0.150 2.92 3.81
8X b END VIEW M −−−− 10 ° −−− 10 °
0.010 M C A M B M NOTE 6
SIDE VIEW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN XXXXXXXXX
3. DC − IN AWL
4. AC IN
5. GROUND YYWWG
6. OUTPUT
7. AUXILIARY
8. VCC
XXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42420B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−8 PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011

NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
G = Pb−Free Package

0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
STYLE 5: STYLE 6: STYLE 7: STYLE 8:
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
STYLE 9: STYLE 10: STYLE 11: STYLE 12:
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
STYLE 21: STYLE 22: STYLE 23: STYLE 24:
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

STYLE 25: STYLE 26: STYLE 27: STYLE 28:

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2
7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 2 OF 2

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