LAB MANUAL

Computer
Architecturean
d
Organization
B. TECH 20-24
SEM - 3

KHURSHID ALAM
IILMU/UG/2020/T104
 IILM UNIVERSITY, GURUGRAM

EXPERIMENT:- 01
VERIFICATION AND INTERPRETATION OF TRUTH TABLE FOR AND,
OR, NOT, NAND, NOR, EX-OR, EX-NOR GATES.

AIM
To verify and interpret the logic and truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates
using RTL (Resistor Transistor Logic), DTL (Diode Transistor Logic) and TTL (Transistor Transistor Logic)
logics in simulator 1 and verify the truth table for AND, OR, NOT, NAND, NOR, Ex-OR, Ex-NOR gates in
simulator 2.
THEORY
Introduction
Logic gates are the basic building blocks of any digital system. Logic gates are electronic
circuits having one or more than one input and only one output. The relationship between the
input and the output is based on a certain logic. Based on this, logic gates are named as

1) AND gate
2) OR gate
3) NOT gate
4) NAND gate
5) NOR gate
6) Ex-OR gate
7) Ex-NOR gate
1) AND gate
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B or can be written as AB

Y= A.B

Figure-1:Logic Symbol of AND Gate

Figure-2:Truth Table of AND Gate

A simple 2-input logic AND gate can be constructed using RTL (Resistor-Transistor-Logic)
switches connected together as shown below with the inputs connected directly to the
transistor bases. Both transistors must be saturated “ON” for an output at Q.

Figure-3:AND Gate through RTL logic

2) OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

Y= A+B
Figure-4:Logic Symbol of OR Gate

Figure-5: Truth Table of OR Gate

OR gate can be realized by DRL (Diode-Resistance-Logic) or by TTL (Transistor-Transistor-

Logic). Presently, we will learn how to implement the OR gate using DRL (Diode-Resistance-
Logic). To realize OR gate, we will use a diode at every input of the OR gate. The anode part of
diode is connected with input while the cathode part is joined together and a resistor,
connected with the cathode is grounded. In this case, we have taken two inputs which can be
seen in the circuit below.
When both the inputs are at logic 0 or low state then the diodes D1 and D2 become reverse
biased. Since the anode terminal of diode is at lower voltage level than the cathode terminal, so
diode will act as open circuit so there is no voltage across resistor and hence output voltage is
same as ground. When either of the diodes is at logic 1 or high state then the diode
corresponding to that input is forward bias. Since this time anode is at high voltage than
cathode therefore current will flow through forward biased diode and this current then appears
on resistor causing high voltage at output terminal also. Hence at output we get high or logic 1
or +5V. So, if any or both inputs are high, the output will be high or “1”.
Figure-6:OR Gate through DRL logic

3) NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known
as NOT A. This is also shown as A' or A with a bar over the top, as shown at the outputs.

Y= A'

Figure-7:Logic Symbol of NOT Gate

Figure-8:Truth Table of NOT Gate

NOT gate can be realized through transistor.The input is connected through resistor R2 to the
transistor’s base. When no voltage is present on the input, the transistor turns off. When the
transistor is off, no current flows through the collector-emitter path. Thus, current from the
supply voltage (Vcc) flows through resistor R1 to the output. In this way, the circuit’s output is
high when its input is low.
When voltage is present at the input, the transistor turns on, allowing current to flow through
the collector-emitter circuit directly to ground. This ground path creates a shortcut that
bypasses the output, which causes the output to go low.
In this way, the output is high when the input is low and low when the input is high.

Figure-9:NOT Gate through Transistor

4) NAND gate
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.

Y= AB
Figure-10:Logic Symbol of NAND Gate

Figure-11:Truth Table of NAND Gate

A simple 2-input logic NAND gate can be constructed using RTL (Resistor-transistor-logic)
switches connected together as shown below with the inputs connected directly to the
transistor bases. Either transistor must be cut-off or “OFF” for an output at Q.

Figure-12: NAND gate through RTL Logic.

5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all
NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.

Y= A+B

Figure-13: Logic Symbol of NOR gate

Figure-14: Truth Table of NOR gate

A simple 2-input logic NOR gate can be constructed using RTL (Resistor-transistor-logic)
switches connected together as shown below with the inputs connected directly to the
transistor bases. Both transistors must be cut-off or “OFF” for an output at Q.

Figure-15: NOR gate through RTL Logic.

6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its
two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

Y= A⊕B

Figure-16: Logic Symbol of Ex-OR gate

Figure-17:Truth Table of Ex-OR gate

Ex-OR gate is created from AND, NAND and OR gates.The output is high only when both the
inputs are different.

Figure-18:Ex-OR gate through RTL Logic.

7) Ex-NOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output
if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small
circle on the output. The small circle represents inversion.

Y= A⊕B

Figure-19:Logic Symbol of Ex-NOR gate

Figure-20:Truth Table of Ex-NOR gate
Ex-NOR gate is created from AND, NOT and OR gates.The output is high only when both the
inputs are same.

Figure-21:Ex-NOR gate through RTL Logic.

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT: - 02

AIM
Construction of half/ full adder using XOR
and NAND gates and verification of its
operation
To verify the truth table of half adder and full adder by using XOR and
NAND gates respectively and analyze the working of half adder and full
adder circuit with the help of LEDs in simulator 1 and verify the truth table
only of half adder and full adder in simulator 2.

THEORY
Introduction
Adders are digital circuits that carry out addition of numbers. Adders are a
key component of arithmetic logic unit. Adders can be constructed for most
of the numerical representations like Binary Coded Decimal (BCD), Excess – 3,
Gray code, Binary etc. out of these, binary addition is the most frequently
performed task by most common adders. Apart from addition, adders are
also used in certain digital applications like table index calculation, address
decoding etc.

Binary addition is similar to that of decimal addition. Some basic

binary additions are shown below.

Figure 1. Schematic representation of half adder

1)Half Adder
Half adder is a combinational circuit that performs simple addition of two
binary numbers. If we assume A and B as the two bits whose addition is to
be performed, the block diagram and a truth table for half adder with A,
B as inputs and Sum, carry as outputs can be tabulated as follows.
Figure 2. Block diagram and truth table of half adder

The sum output of the binary addition carried out above is similar to
that of an Ex-OR operation while the carry output is similar to that of an
AND operation. The same can be verified with help of Karnaugh Map.
The truth table and K Map simplification and logic diagram for sum output is
shown below.

Figure 3. Truth table, K Map simplification and Logic diagram for sum output
of half adder\

Sum = A B' + A' B

The truth table and K Map simplification and logic diagram for carry is
shown below.

Figure 4. Truth table, K Map simplification and Logic diagram for sum output
of half adder

Carry = AB
If A and B are binary inputs to the half adder, then the logic function to
calculate sum S is Ex – OR of A and B and logic function to calculate carry C
is AND of A and B. Combining these two, the logical circuit to implement
the combinational circuit of half adder is shown below.
Figure 5. Half Adder Logic Diagram

As we know that NAND and NOR are called universal gates as any logic
system can be implemented using these two, the half adder circuit can
also be implemented using them. We know that a half adder circuit has
one Ex – OR gate and one AND gate.

1.1) Half Adder using NAND gates

Five NAND gates are required in order to design a half adder. The circuit to
realize half adder using NAND gates is shown below.

Figure 6. Realization of half adder using NAND gates

### 1.2)Half Adder using NOR gates

Five NOR gates are required in order to design a half adder. The circuit to
realize half adder using NOR gates is shown below.
Figure 7. Realization of half adder using NOR Gates

2) Full Adder

Full adder is a digital circuit used to calculate the sum of three binary bits.
Full adders are complex and difficult to implement when compared to half
adders. Two of the three bits are same as before which are A, the augend
bit and B, the addend bit. The additional third bit is carried bit from the
previous stage and is called 'Carry' – in generally represented by CIN. It
calculates the sum of three bits along with the carry. The output carry is
called Carry – out and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S,
Carry OUT as outputs is shown below.
Figure 8. Full Adder Block Diagram and Truth Table

Figure 9. Full Adder Logic Diagram

Based on the truth table, the Boolean functions for Sum (S) and
Carry – out (COUT) can be derived using K – Map.
Figure 10. The K-Map simplified equation for sum is S = A'B'Cin + A'BCin' +
ABCin

Figure 11. The K-Map simplified equation for COUT is COUT = AB + ACIN + BCIN

In order to implement a combinational circuit for full adder, it is clear

from the equations derived above, that we need four 3-input AND gates
and one 4- input OR gates for Sum and three 2-input AND gates and one 3-
input OR gate for Carry – out.

2.1) Full Adder using NAND gates

As mentioned earlier, a NAND gate is one of the universal gates and can be
used to implement any logic design. The circuit of full adder using only
NAND
gates is shown below.

Figure 12. Full Adder using NAND gates

2.2) Full Adder using NOR gates

As mentioned earlier, a NOR gate is one of the universal gates and can be
used to implement any logic design. The circuit of full adder using only NOR
gates is shown below.

Figure 13. Full Adder using NOR gates

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT: -03

AIM
To verify the truth table of half subtractor by using the ICs of XOR, NOT and
AND gates and of full subtractor by using the ICs of XOR, AND, NOT and OR
gates respectively and analyse the working of half subtractor and full
subtractor circuit with the help of LEDs in simulator 1 and verify the truth
table only of half subtractor and full subtractor in simulator 2.

THEORY: -

Introduction
Subtractor circuits take two binary numbers as input and subtract one binary
number input from the other binary number input. Similar to adders, it gives
out two outputs, difference and borrow (carry-in the case of Adder). There are
two types of subtractors.

Half Subtractor
Full Subtractor
1) Half Subtractor
The half-subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend) and
two outputs Difference and Borrow. The logic symbol and truth table are
shown below.

Figure-1:Logic Symbol of Half subtractor

Figure-2:Truth Table of Half subtractor

Figure-3:Circuit Diagram of Half subtractor

From the above truth table we can find the boolean expression.

Difference = A ⊕ B
Borrow = A' B
From the equation we can draw the half-subtractor circuit as shown in the
figure 3.
RESULT :- 01
 FULL- SUBTRACTOR
AIM
To verify the truth table of half subtractor by using the ICs of XOR, NOT and
AND gates and of full subtractor by using the ICs of XOR, AND, NOT and OR
gates respectively and analyse the working of half subtractor and full
subtractor circuit with the help of LEDs in simulator 1 and verify the truth
table only of half subtractor and full subtractor in simulator 2.

THEORY
Introduction
Subtractor circuits take two binary numbers as input and subtract one binary
number input from the other binary number input. Similar to adders, it gives
out two outputs, difference and borrow (carry-in the case of Adder). There are
two types of subtractors.

Half Subtractor
Full Subtractor
A full subtractor is a combinational circuit that performs subtraction involving
three bits, namely A (minuend), B (subtrahend), and Bin (borrow-in) . It
accepts three inputs: A (minuend), B (subtrahend) and a Bin (borrow bit) and
it produces two outputs: D (difference) and Bout (borrow out). The logic
symbol and truth table are shown below.
Figure-4:Logic Symbol of Full subtractor

Figure-5:Truth Table of Full subtractor

From the above truth table we can find the boolean expression.
D = A ⊕ B ⊕ Bin
Bout = A' Bin + A' B + B Bin
From the equation we can draw the Full-subtractor circuit as shown in the

figure 6.

Figure-6:Circuit Diagram of Full subtractor

RESULT:02
EXPERIMENT:- 04

Realization of logic functions with the help of universal

gates NAND and NOR Gate

AIM
To implement the logic functions i.e. AND, OR, NOT, Ex-OR, Ex- NOR and a
logical expression with the help of NAND and NOR universal gates
respectively.

THEORY
Introduction
Logic gates are electronic circuits which perform logical functions on one or
more inputs to produce one output. There are seven logic gates. When all
the input combinations of a logic gate are written in a series and their
corrresponding outputs written along them, then this input/ output
combination is called Truth Table.

1) Nand gate as Universal gate

NAND gate is actually a combination of two logic gates i.e. AND gate
followed by NOT gate. So its output is complement of the output of an AND
gate.This gate can have minimum two inputs. By using only NAND gates,
we can realize all logic functions: AND, OR, NOT, Ex-OR, Ex-NOR, NOR. So
this gate is also called as universal gate.
1.1) NAND gates as OR gate
From DeMorgan’s theorems:
(A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
Figure-1:NAND gates as OR gate

Figure-2:Truth table of OR

1.2) NAND gates as AND gate

A NAND produces complement of AND gate. So, if the output of a NAND
gate is inverted, overall output will be that of an AND gate.
Y = ((A.B)’)’
Y = (A.B)

Figure-3:NAND gates as AND gate

Figure-4:Truth table of AND

1.3) NAND gates as Ex-OR gate

The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be
achieved with the logic diagram shown in the left side.

Figure-5:NAND gate as Ex-OR gate

Figure-6:Truth table of Ex-OR

1.4)NAND gates as Ex-NOR gate
Ex-NOR gate is actually Ex-OR gate followed by NOT gate. So give the output
of Ex-OR gate to a NOT gate, overall output is that of an Ex-NOR gate.
Y = AB+ A’B’

Figure-7:NAND gates as Ex-NOR gate

Figure-8:Truth table of Ex-NOR

1.5) Implementing the simplified function with NAND gates only
We can now start constructing the circuit. First note that the
entire
expression is inverted and we have three terms ANDed. This means that
we must use a 3-input NAND gate. Each of the three terms is, itself, a
NAND expression. Finally, negated single terms can be generates with a
2-input NAND gate acting as an inverted. The expression illustrates a
circuit using NAND gates only.

F=((C'.B.A)'(D'.C.A)'(C.B'.A)')'

The stepwise simplication of this expression is done on the basis of this

logic diagram in Figure 9:
Figure-9:Implementing the simplified function with NAND gates only

2) Nor gate as Universal Gate

NOR gate is actually a combination of two logic gates: OR gate followed by
NOT gate. So its output is complement of the output of an OR gate.This gate
can have minimum two inputs, output is always one. By using only NOR
gates, we can realize all logic functions: AND, OR, NOT, Ex-OR, Ex-NOR,
NAND. So this gate is also called universal gate.

2.1)NOR gates as OR gate

A NOR produces complement of OR gate. So, if the output of a NOR gate is
inverted, overall output will be that of an OR gate.
Y = ((A+B)’)’
Y = (A+B)

Figure-10:NOR gates as OR gate

Figure-11:Truth table of
OR 2.2)NOR gates as AND
gate From DeMorgan’s
theorems:
(A+B)’ = A’B’
(A’+B’)’ = A’’B’’ =
AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.

Figure-12:NOR gates as AND gate

Figure-13:Truth table of
AND 2.3)NOR gates as Ex-OR
gate
Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So give the output
of Ex-NOR gate to a NOT gate, overall output is that of an Ex-OR gate.
Y = A’B+ AB’
Figure-14:NOR gates as Ex-OR gate

Figure-15:Truth table of Ex-OR

2.4) NOR gates as Ex-NOR gate

The output of a two input Ex-NOR gate is shown by: Y = AB + A’B’. This can be
achieved with the logic diagram shown in the left side.
Figure-16:NOR gates as Ex-NOR gate

Figure-17:Truth table of Ex-NOR

2.5) Constructing a circuit with NOR gates only
Designing a circuit with NOR gates only uses the same basic techniques as
designing a circuit with NAND gates; that is, the application of deMorgan’s
theorem. The only difference between NOR gate design and NAND gate
design is that the former must eliminate product terms and the later must
eliminate sum terms.
F=(((C.B'.A)+(D.C'.A)+(C.B'.A))')'

Figure-18:Implementing the simplified function with NOR gates only

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT:- 05

Construction of NOR gate latch and verification of

its operation
AIM
To verify the truth table and timing diagram of NOR gate latch using NOR
gate IC and analyse the circuit of NOR gate latch with the help of LEDs
display.

THEORY
Introduction
Latches are basic storage elements that operate with signal levels (rather
than signal transitions). Latches controlled by a clock transition are flip-
flops. Latches are edge-sensitive devices. Latches are useful for the design
of the asynchronous sequential circuit.

SR (Set-Reset) Latch – SR Latch is a circuit with:

(i)2 cross-coupled NOR gates or 2 cross-coupled NAND gates.

(ii)2 inputs S for SET and R for RESET.
(iii)2 outputs Q, Q.

The SR Latch using NOR gate is shown below with its truth table:

Figure-1:Logic Symbol of NOR gate latch

Figure-2:Truth Table of NOR gate latch

While the R and S inputs are both low, feedback maintains the Q
and Q outputs in a constant state, with Q the complement of Q. If S (Set) is
pulsed high while R (Reset) is held low, then the Q output is forced high,
and stays high when S returns to low; similarly, if R is pulsed high while S
is held low, then the Q output is forced low, and stays low when R returns
to low.The R = S = 1 combination is called a restricted combination or a
forbidden state because, as both NOR gates then output zeros, it breaks
the logical equation Q = Q. The combination is also inappropriate in
circuits where both inputs may go low simultaneously (i.e. a transition
from restricted to keep). The output would lock at either 1 or 0 depending
on the propagation time relations between the gates (a race condition).

Figure-3:Timing Diagram of NOR gate latch

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED
EXPERIMENT:-06

Design and verify the 4-Bit Serial In - Parallel Out

Shift Registers.

AIM
To analyze the circuit and truth table of 4-bit SIPO (serial input
parallel output) shift register by using IC 7474 (D flip flop).

THEORY
Introduction
In Serial In Parallel Out (SIPO) shift registers, the data is stored into the
register serially while it is retrieved from it in parallel-fashion. Figure 1
shows an n-bit synchronous SIPO shift register sensitive to positive edge of
the clock pulse. Here the data word which is to be stored (Data in) is fed
serially at the input of the first flip-flop (D1 of FF1). It is also seen that the
inputs of all other flip-flops (except the first flip-flop FF1) are driven by
the outputs of the preceding ones like the input of FF2 is driven by the
output of FF1. In this kind of shift register, the data stored within the
register is obtained as a parallel- output data word (Data out) at the
individual output pins of the flip-flops (Q1 to Qn).

In general, the register contents are cleared by applying high on the

clear pins of all the flip-flops at the initial stage. After this, the first bit,
B1 of the input data word is fed at the D1 pin of FF1.This bit (B1) will
enter into FF1, get
stored and thereby appears at its output Q1 on the appearance of first
leading edge of the clock. Further at the second clock pulse, the bit B1
right- shifts and gets stored into FF2 while appearing at its output pin Q2
while a new bit, B2 enters into FF1. Similarly at each clock pulse the data
within the register moves towards right by a single bit while a new bit of
the input word enters into the register. Meanwhile one can extract the
bits stored within the register in parallel-fashion at the individual flip-flop
outputs.

Analyzing on the same grounds, one can note that the n-bit input data word
is

obtained as an n-bit output data word from the shift register at the
rising edge of the nth clock pulse. This working of the shift-register
can be summarized as in Table I and the corresponding waveforms are
given by figure 2.
In the right-shift SIPO shift-register, data bits shift from left to right for each
clock pulse. However if the data bits are made to shift from right to left in the
same design, one gets a left-shift SIPO shift-register as shown by figure 3.
Nevertheless the basic working principle remains the same except the fact
that now Bn down to B1 is stored in Qn down to Q1 i.e. Q1 = B1, Q2 = B2 …
Qn = Bn at the nth clock pulse.

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT:-07

Implementation and verification of decoder/de-

multiplexer and encoder using logic gates.

AIM
To analyse the truth table of 4 * 2 decoder/de-multiplexer using NOT (7404)
and AND (7408) logic gate ICs and 2 * 4 encoder using OR (7432) logic gate IC
and to understand the working of 4 * 2 decoder and 2 * 4 encoder circuit
with the help of LEDs display.

THEORY
Introduction
Binary code of N digits can be used to store 2N distinct elements of coded
information. This is what encoders and decoders are used for. Encoders
convert 2N lines of input into a code of N bits and Decoders decode the N bits
into 2N lines.

1) 2x4 Decoder / De-multiplexer

The name “Decoder” means to translate or decode coded information
from one format into another, so a digital decoder transforms a set of
digital input signals into an equivalent decimal code at its output
A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of m=2^n unique output lines.

Figure 1. Logic Diagram of Decoder

1.1) 2-to-4 Binary Decoder

Figure 2. Circuit Diagram of 2-to-4 Decoder

The 2-to-4 line binary decoder depicted above consists of an array of four
AND gates. The 2 binary inputs labelled A and B are decoded into one of 4
outputs, hence the description of 2-to-4 binary decoder. Each output
represents one of the minterms of the 2 input variables, (each output = a
minterm).
Figure 3. Logic Diagram and Truth table of 2-to-4 Decoder

The binary inputs A and B determine which output line from Q0 to Q3 is

“HIGH” at logic level “1” while the remaining outputs are held “LOW” at logic
“0” so only one output can be active (HIGH) at any one time.

Therefore, whichever output line is “HIGH” identifies the binary code present
at the input, in other words it “decodes” the binary input. Some binary
decoders have an additional input pin labelled “Enable” that controls the
outputs from the device.

This extra input allows the decoders outputs to be turned “ON” or

“OFF” as required. Output is only generated when the Enable input has
value 1; otherwise, all outputs are 0. Only a small change in the
implementation is required: the Enable input is fed into the AND gates
which produce the outputs.
If enable is 0, all AND gates are supplied with one of the inputs as 0 and
hence no output is produced. When enable is 1, the AND gates get one of
the
inputs as 1, and now the output depends upon the remaining inputs. Hence
the output of the decoder is dependent on whether the Enable is high or low.
2) Encoder
An Encoder is a combinational circuit that performs the reverse
operation of Decoder. It has maximum of 2n input lines and ‘n’ output
lines, hence it encodes the information from 2n inputs into an n-bit code.
It will produce a binary code equivalent to the input, which is active
High. Therefore, the encoder encodes 2n input lines with ‘n’ bits.

Figure 4. Logic Diagram of ENCODER

2.1 )4 : 2 Encoder
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two outputs A1
& A0. At any time, only one of these 4 inputs can be ‘1’ in order to get the
respective binary code at the output.

Figure 5. Logic symbol and truth table of 4 to 2 encoder

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT :- 08

Implementation of 4x1 multiplexer and 1x4

demultiplexer using logic gates.
AIM
To analyze the truth table and working of 1x4 De-Multiplexer by using 3-
input NAND and 1-input NOT logic gate ICs and 4x1 Multiplexer by using 3-
input AND, 3-input OR, and 1-input NOT logic gate ICs
.
THEORY

Introduction
The function of a multiplexer is to select the input of any ‘n’ input lines
and feed that to one output line. The function of a de-multiplexer is to
inverse the function of the multiplexer and the shortcut forms of the
multiplexer. The de- multiplexers are mux and demux. Some multiplexers
perform both multiplexing and de-multiplexing operations.

Figure-1: Block diagram of Multiplexer and De-multiplexer

1)Multiplexer is a device that has multiple inputs and a single line output.
The select lines determine which input is connected to the output, and
also to increase the amount of data that can be sent over a network
within certain time. It is also called a data selector.

Multiplexers are classified into four types:

a) 2-1 multiplexer (1 select line)
b) 4-1 multiplexer (2 select lines)
c) 8-1 multiplexer (3 select lines)
d) 16-1 multiplexer (4 select
lines) 1.1) 4x1 Multiplexer
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0
& S1 and one output Y. The block diagram of 4x1 Multiplexer is shown in
the following figure. One of these 4 inputs will be connected to the output
based on the combination of inputs present at these two selection lines.
Truth table of 4x1 Multiplexer is shown below.

Figure-2: Block diagram of 4x1 Multiplexer

Figure-3:Truth table of 4x1 Multiplexer

2) De-multiplexer is also a device with one input and multiple output lines.
It is used to send a signal to one of the many devices. The main difference
between a multiplexer and a de-multiplexer is that a multiplexer takes two
or more signals and encodes them on a wire, whereas a de-multiplexer
does
reverse to what the multiplexer does.

De-multiplexer is classified into four types:

a) 1-2 demultiplexer (1 select line)
b)1-4 demultiplexer (2 select lines)
c)1-8 demultiplexer (3 select lines)
d)1-16 demultiplexer (4 select

lines) 2.2) 1x4 De-multiplexer

1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and
four outputs Y0, Y1, Y2 & Y3. The block diagram of 1x4 De-Multiplexer is
shown in the following figure.

Figure-4: Block diagram of 1x4 De-Multiplexer

Figure-5: Truth table of 1x4 De-Multiplexer

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
EXPERIMENT:-09

Verify Binary to Gray and Gray to Binary conversion

using NAND gates only.

AIM
To analyze the truth table of binary to gray and gray to binary converter
using combination of NAND gates and to understand the working of binary
to gray and gray to binary converter with the help of LEDs display

THEORY

Introduction
Binary Numbers is default way to store numbers, but in many applications
binary numbers are difficult to use and a variation of binary numbers is
needed. Gray code is an ordering of the binary numeral system such that
two successive values differ in only one bit (binary digit). Gray codes are
very useful in the normal sequence of binary numbers generated by the
hardware that may cause an error or ambiguity during the transition from
one number to the next. So, the gray code can eliminate this problem
easily since only one bit changes its value during any transition between
two numbers.

Gray code has property that two successive numbers differ in only one bit
because of this property gray code does the cycling through various states
with minimal effort and used in K-maps, error correction, communication
etc.

In computer science many a times we need to convert binary code to gray

code and vice versa. This conversion can be done by applying following
rules: 1) Binary to Gray conversion:
The Most Significant Bit (MSB) of the gray code is always equal to the MSB of
the given binary code.
Other bits of the output gray code can be obtained by Ex-ORing binary code
bit at that index and previous index.
There are four inputs and four outputs. The input variable is defined as B 3, B2,
B1, B0 and the output variables are defined as G3, G2, G1, G0. From the
truth table, combinational circuit is designed. The logical expressions are
defined as:

B3 = G3
B2 ⊕ B3 = G2
B1 ⊕ B2 = G1
B0 ⊕ B1 = G0

Figure-1: Binary to Gray Code Converter Circuit

Figure-2: Binary to Gray Code Converter Truth Table

2) Gray to binary conversion:
1. The Most Significant Bit (MSB) of the binary code is always equal to the
MSB of the given binary number.
2.Other bits of the output binary code can be obtained by checking gray
code bit at that index. If current gray code bit is 0, then copy previous
binary code bit, else copy invert of previous binary code bit.

There are four inputs and four outputs. The input variable are defined as G 3,
G2, G1, G0 and the output variables are defined as B3, B2, B1, B0. From the
truth table, combinational circuit is designed. The logical expressions are
defined as :

G0 ⊕ G1 ⊕ G2 ⊕ G3 = B 0
G1 ⊕ G2 ⊕ G3 = B1
G2 ⊕ G3 = B2
G3 = B3

Figure-3: Gray to Binary Code Converter Circuit

Figure-4: Gray to Binary Code Converter Truth Table

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
SIMULATION

1) Binary to Gray conversion:

2) Gray to binary conversion
EXPERIMENT: -10

Verify the truth table of one bit and two-bit comparator using
logic gates.

AIM
To analyze the truth table of 1-bit comparator by using NOT, AND and NOR logic
gate ICs and 2-bit comparator by using 1-input NOT, 3-input AND, 2-input AND,
3-input OR and 2-input Ex-NOR logic gate ICs and to understand the working of
1-bit comparator and 2- bit comparator with the help of LEDs display.

THEORY
Introduction
A magnitude digital comparator is a combinational circuit that compares two
digital or binary numbers in order to find out whether one binary number is
equal, less than or greater than the other binary number. We logically design a
circuit for which we will have two inputs one for A and other for B and have three
output terminals, one for A > B condition, one for A = B condition and one for A
< B condition.

Figure-1: Block Diagram of Comparator

1) 1-Bit Magnitude Comparator:

A comparator used to compare two bits is called a single bit comparator. It
consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers. The
truth table for a 1-bit comparator is given below:

Figure-2: Truth Table of 1-Bit Comparator

From the above truth table logical expressions for each output can be
expressed as follows:
A>B:
AB' A <
B : A'B
A = B : A'B' + AB

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below :

Figure-3: Logic Circuit of 1-Bit Comparator

2) 2-Bit Magnitude Comparator:
A comparator used to compare two binary numbers each of two bits is called a
2- bit magnitude comparator. It consists of four inputs and three outputs to
generate less than, equal to and greater than between two binary numbers.
The truth table for a 2-bit comparator is given below:

Figure-4: Truth Table of 2-Bit Comparator

From the above truth table logical expressions for each output can be
expressed as follows:
A > B : A1B1’ + A0B1’B0’ + A1A0B0’
A = B : A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below :
Figure-5: Logic Circuit of 2-Bit Comparator

Applications of Comparators:
 Comparators are used in central processing units (CPUs)
and microcontrollers (MCUs).
 These are used in control applications in which the binary numbers
representing physical variables such as temperature, position, etc. are
compared with a reference value.
 Comparators are also used as process controllers and for Servo motor
control.
 Used in password verification and biometric applications.

CONCLUSION
ALL THE TRUTH TABLES ARE CHECKED AND VERIFIED.
SIMULATION

1- Bit Magnitude Comparator

2- Bit Magnitude Comparator

******END*******
SUBMITED BY : KHURSHID ALAM T104