Low power VLSI Design

Static power Dissipation

Leakage Power Dissipation

Nanometer Transistors

Emerging devices in the sub-100 nm regime

post challenges to low-power design
– Leakage
– Variability
– Reliability

Log (Id ) versus V at two different drain voltages for

0.35um CMOS process
Scaling trends and power consumption

ITRS projections for transistor scaling

trends and power consumption: (a)
physical
dimensions and supply voltage and (b)
device power consumption
TRANSISTOR LEAKAGE MECHANISMS

Summary of leakage current mechanisms of

deep-submicrometer transistors.

I1 is the reverse-bias pn junction leakage;

I2 is the subthreshold leakage;
I3is the oxide tunneling current;
I4 is the gate current due to hot-carrier injection;
I5 is the GIDL; and
I6 is the channel punchthrough current.
Currents I2, I5 and I6 are off-state leakage mechanisms,
While I1 And I3 occur in both ON and OFF states.
I4 can occur in the off state, but more typically occurs during the
transistor bias states in transition.
Reverse diode leakage current:

The reverse diode leakage occurs

when the pn-junction between the
drain and the bulk of
the transistor is reversely biased
Band-to-Band Tunneling Current
The tunneling current density is given
by

the electric field at the junction is given by

High electric field

BTBT in reverse-biased pn junction 10 V/cm across the reverse-biased pn junction causes
significant current to flow through the junction due to tunneling
of electrons from the valence band of the p region to
the conduction band of the n region
Subthreshold leakage current

which is due to carrier diffusion between the

source and the drain region of the transistor in
weak inversion.

An MOS transistor in the subthreshold

operating region behaves similar to a bipolar
device and the subthreshold current exhibits an
exponential dependence on
the gate voltage.
Cont..

Variation of minority carrier concentration in the channel

of a MOSFET biased in the weak inversion

Subthreshold leakage in a negative-channel

metal–oxide–semiconductor (NMOS) transistor
 DIBL

nchannel ID vs. VG showing DIBL, GIDL, weak

inversion, and pn junction reverse-bias leakage components

Lateral energy-band diagram at the surface versus distance

(normalized to the channel length L) from the source to the
drain for: (a) long-channel MOSFET; (b) a short-channel
MOSFET; (c) a short-channel MOSFET at high drain bias. The
gate voltage is same for all three cases [17].
 Body Effect:

n channel log(ID ) versus VG for six substrate biases on a

0.35um logic process technology (VD = 2.7 V)
the substrate sensitivity is higher for higher bulk
doping concentration, and the substrate sensitivity decreases
as the substrate reverse bias increases. At , Vbs =0 the substrate
Fig. 9 is that as vth increases, sensitivity is Cdm/Cox or m (4). Therefore, m is
because of applied reverse substrate bias and a shift in the also called body effect coefficient
I-V– curve, decreases.
Narrow-Width Effect:
The decrease in gate width modulates the threshold voltage of a transistor, and thereby modulates
the subthreshold leakage.

Three types of device structures and associated inversion–

depletion layer. (a) Large-geometry MOSFET. (b) LOCOS gate
MOSFET. (c) Trench isolated MOSFET.

This narrow-width effect can be modeled as

an increase in Vth by the amount VNCE given by
 Variation of threshold voltage with
gate width for uniform doping

Variation of threshold voltage with gate

width in the case of trench isolated
buried channel P-MOSFET showing the
anomalous behavior
Threshold voltage roll-off

Threshold voltage roll-off with change in

channel length; V reduction is more
severe at higher drain bias.

Schematic diagram for charge-sharing model explaining

the reduction of Vth due to the source/drain depletion regions.
The bulk charge that needs to be inverted is proportional to the
area under the trapezoidal region given by Qb α Wdm (L + L’ )=2,
which is less than the total depletion charge in the long-channel
case, which is Qb α Wdm(L)
Effect of Temperature

Temperature dependence of the subthreshold

leakage current is important, since digital
very large scale integration (VLSI) circuits
usually operate at elevated temperatures due to
the power dissipation (heat generation) of the
circuit.
 Tunneling into and Through Gate Oxide
The mechanism of tunneling between substrate
and gate polysilicon can be primarily divided
into two parts, namely:

(1) Fowler–Nordheim (FN) tunneling; and

(2) (2) direct tunneling.

Tunneling of electrons through an MOS capacitor. (a) Energy-band diagram at

flat-band condition. (b) Energy-band diagram with positive gate bias showing
tunneling of electron from substrate to gate. (c) Energy-band diagram at negative
gate bias showing tunneling of electron from gate to substrate
(1) Fowler–Nordheim (FN) tunneling;
In the case of FN tunneling, electrons tunnel through a The FN current equation represents the tunneling
triangular potential barrier through the triangular potential barrier and is
valid for

Since
short-channel devices mostly operate at

2) Direct Tunneling
in the case of direct tunneling, electrons tunnel through a
trapezoidal potential barrier.

Direct tunneling current is significant for

lowoxide thicknesses.
Simulated direct tunneling current density in thin-oxide
polysilicon gate MOS devices.

Three mechanisms for gate leakage

Components of tunneling current

Injection of Hot Carriers from Substrate to Gate Oxide

Injection of hot electrons from substrate to oxide

Gate-Induced Drain Leakage

Condition of the depletion region near the drain-gate overlap region of an MOS transistor when (a) surface is
accumulated with low negative gate bias; and (b) n+ region is depleted or inverted with high negative gate bias

Very high and abrupt drain doping is

Thinner oxide thickness and higher (higher potential preferred for minimizing GIDL, as it provides
between gate and drain) enhance the electric field and lower series resistance required nfor high
therefore increase GIDL transistor drive currents
Punch-through
An increase in the reverse bias across the junctions
(with increase in ) also pushes the junctions nearer to
each other. When the combination of channel length and
reverse bias leads to the merging of the depletion regions,
punchthrough is said to have occurred

In submicrometer MOSFETs, a adjust implant is

used to have a higher doping at the surface than
that in the bulk. This causes a
greater expansion of the depletion region below
the surface
(due to smaller doping there) as compared to the
surface