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Visvesvaraya National Institute of Technology Nagpur: Vlsi Design MTECH 2021-23 VHDL Lab

The document contains VHDL code and test benches for several basic digital logic circuits including an 4x2 encoder, 2x4 decoder, 2x1 multiplexer, 1x2 demultiplexer, 1-bit comparator, 3-input majority gate, full adder, and full subtractor. The code uses dataflow modeling to describe the logic functions and outputs of each circuit. Test benches are provided to simulate and test the behavior of each circuit by applying test inputs and observing the outputs.

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Rutvik Patel
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37 views24 pages

Visvesvaraya National Institute of Technology Nagpur: Vlsi Design MTECH 2021-23 VHDL Lab

The document contains VHDL code and test benches for several basic digital logic circuits including an 4x2 encoder, 2x4 decoder, 2x1 multiplexer, 1x2 demultiplexer, 1-bit comparator, 3-input majority gate, full adder, and full subtractor. The code uses dataflow modeling to describe the logic functions and outputs of each circuit. Test benches are provided to simulate and test the behavior of each circuit by applying test inputs and observing the outputs.

Uploaded by

Rutvik Patel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VISVESVARAYA NATIONAL INSTITUTE

OF TECHNOLOGY NAGPUR

VLSI DESIGN
MTECH 2021-23
VHDL LAB

ASSIGNMENT 1
Submitted by

Rutvik Patel
MT21MVD022
1. Write program, simulate and synthesize the 4×2 Encoder
using Data-flow modelling.

 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ENCODER is
Port ( D0 : IN STD_LOGIC;
D1 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
D3 : IN STD_LOGIC;
a : OUT STD_LOGIC;
b : OUT STD_LOGIC );
end ENCODER;
architecture Behavioral of ENCODER is
begin

A <= D2 OR D3;
B <= D1 OR D3;

end Behavioral;

 Test_Bench:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_ENCODER IS
END tb_ENCODER;
ARCHITECTURE behavior OF tb_ENCODER IS
COMPONENT ENCODER
PORT(
D0 : IN std_logic;
D1 : IN std_logic;
D2 : IN std_logic;
D3 : IN std_logic;
a : OUT std_logic;
b : OUT std_logic );
END COMPONENT;

signal D0 : std_logic := '0';


signal D1 : std_logic := '0';
signal D2 : std_logic := '0';
signal D3 : std_logic := '0';
signal a : std_logic;
signal b : std_logic;

BEGIN

uut: ENCODER PORT MAP (


D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
a => a,
b => b);
stim_proc: process
begin

wait for 100 ns;


D0 <= '1'; D1 <= '0'; D2 <= '0'; D3 <= '0';
wait for 100 ns;
D0 <= '0'; D1 <= '1'; D2 <= '0'; D3 <= '0';
wait for 100 ns;
D0 <= '0'; D1 <= '0'; D2 <= '1'; D3 <= '0';
wait for 100 ns;
D0 <= '0'; D1 <= '0'; D2 <= '0'; D3 <= '1';
end process;
END;

 Output:-

2. Write program, simulate and synthesize the 2×4


Decoder using Data-flow modelling.

 Code:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DECODER is
Port ( D0 : out STD_LOGIC;
D1 : out STD_LOGIC;
D2 : out STD_LOGIC;
D3 : out STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC );
end DECODER;

architecture Behavioral of DECODER is

begin

D0 <= not a and not b ;


D1 <= not a and b ;
D2 <= a and not b ;
D3 <= a and b ;

end Behavioral;

 Test_Bench:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_DECODER IS
END tb_DECODER;

ARCHITECTURE behavior OF tb_DECODER IS

COMPONENT DECODER
PORT(
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic;
a : IN std_logic;
b : IN std_logic );
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal D0 : std_logic;
signal D1 : std_logic;
signal D2 : std_logic;
signal D3 : std_logic;
BEGIN
uut: DECODER PORT MAP (
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
a => a,
b => b);

stim_proc: process
begin
wait for 100 ns;
a <= '0'; b <= '0';
wait for 100 ns;
a <= '1'; b <= '0';
wait for 100 ns;
a <= '0'; b <= '1';
wait for 100 ns;
a <= '1'; b <= '1';
end process;
END;

 Output :-
3. Write program, simulate and synthesize the 2×1
multiplexer using Data-flow modelling.

 Code :-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX is
Port ( D0 : in STD_LOGIC;
D1 : in STD_LOGIC;
a : in STD_LOGIC;
Y : out STD_LOGIC);
end MUX;

architecture Behavioral of MUX is

begin

Y <= ( not a and D0 ) or ( a and D1 );

end Behavioral;

 Test_bench :-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_mux IS
END tb_mux;
ARCHITECTURE behavior OF tb_mux IS

COMPONENT MUX
PORT(
D0 : IN std_logic;
D1 : IN std_logic;
A : IN std_logic;
Y : OUT std_logic );
END COMPONENT;
signal D0 : std_logic := '0';
signal D1 : std_logic := '0';
signal A : std_logic := '0';
signal Y : std_logic;

BEGIN
uut: MUX PORT MAP (
D0 => D0,
D1 => D1,
A => A,
Y => Y );
stim_proc: process
begin
wait for 100 ns;
D0 <= '1';
D1 <= '0';

A <= '0';
wait for 100 ns;
A <= '1';
wait for 100 ns;

D0 <= '0';
D1 <= '1';

A <= '0';
wait for 100 ns;
A <= '1';
end process;
END;
 Output:-
4. Write program, simulate and synthesize the 1×2
demultiplexer using Data-flow modelling.

 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DEMUX is
Port ( D0 : out STD_LOGIC;
D1 : out STD_LOGIC;
a : in STD_LOGIC;
Y : in STD_LOGIC);
end DEMUX;
architecture Behavioral of DEMUX is
begin

D0 <= not a and Y;


D1 <= a and Y;

end Behavioral;

 Test_bench:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_demux IS
END tb_demux;

ARCHITECTURE behavior OF tb_demux IS

COMPONENT DEMUX
PORT(
D0 : out std_logic;
D1 : out std_logic;
a : IN std_logic;
Y : IN std_logi);
END COMPONENT;
signal Y : std_logic := '0';
signal a : std_logic := '0';
signal D0 : std_logic;
signal D1 : std_logic;

BEGIN

uut: DEMUX PORT MAP (


D0 => D0,
D1 => D1,
a => a,
Y => Y);

stim_proc: process
begin

wait for 100 ns;

Y <= '1';
a <= '0';
wait for 100 ns;
a <= '1';
end process;

END;

 Output:-
5. Write program, simulate and synthesize the 1bit
comparator using Data-flow modelling.

 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator is
Port ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
AGB : OUT STD_LOGIC; --A greather than B
AEB : OUT STD_LOGIC; --A equals to B
ALB : OUT STD_LOGIC ); -- A less than B
end comparator;
architecture Behavioral of comparator is
begin

AGB <= A and not B;


AEB <= A xnor B;
ALB <= not A and B;

end Behavioral;

 Test_Bench:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Comperator IS
END tb_Comperator;
ARCHITECTURE behavior OF tb_Comperator IS
COMPONENT comparator
PORT(
A : IN std_logic;
B : IN std_logic;
AGB : OUT std_logic;
ALB : OUT std_logic;
AEB : OUT std_logic );
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal AGB : std_logic;
signal ALB : std_logic;
signal AEB : std_logic;

BEGIN
uut: comparator PORT MAP (
A => A,
B => B,
AGB => AGB,
ALB => ALB,
AEB => AEB);
stim_proc: process
begin
wait for 100 ns;
A <= '0'; B <= '0';
wait for 100 ns;
A <= '0'; B <= '1';
wait for 100 ns;
A <= '1'; B <= '0';
wait for 100 ns;
A <= '1'; B <= '1';
end process;

 Test_Output:-

6. Write program, simulate and synthesize the 3 input


majority gate using Data- flow modelling.

 Truth_Table and Function:-

 Function: - BC + AC + AB:-
 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IPMAJORITY is
Port ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Y : OUT STD_LOGIC);

end IPMAJORITY;

architecture Behavioral of IPMAJORITY is

begin

Y <= (A and B) or (B and C) or (C and A);

end Behavioral;

 Test_Bench:-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Majority IS
END tb_Majority;

ARCHITECTURE behavior OF tb_Majority IS


COMPONENT IPMAJORITY
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
Y : OUT std_logic);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal Y : std_logic;

BEGIN
uut: IPMAJORITY PORT MAP (
A => A,
B => B,
C => C,
Y => Y);

stim_proc: process
begin

wait for 50 ns;


A <= '0'; B <= '0'; C <= '0';
wait for 100 ns;
A <= '0'; B <= '0'; C <= '1';
wait for 100 ns;
A <= '0'; B <= '1'; C <= '0';
wait for 100 ns;
A <= '0'; B <= '1'; C <= '1';
wait for 100 ns;
A <= '1'; B <= '0'; C <= '0';
wait for 100 ns;
A <= '1'; B <= '0'; C <= '1';
wait for 100 ns;
A <= '1'; B <= '1'; C <= '0';
wait for 100 ns;
A <= '1'; B <= '1'; C <= '1';
end process;

END;

 Output:-
7. Write program, simulate and synthesize the Full
adder and Full substractor using Data-flow modelling.

 Full Adder:-
 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end FA;
architecture Behavioral of FA is
begin

sum<= A xor B xor C;


carry <= (A and B) or (B and C) or (C and A);

end Behavioral;

 Test_Bench:-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity full_adder_tb is
end full_adder_tb;

architecture behave of full_adder_tb is


signal r_BIT1 : std_logic := '0';
signal r_BIT2 : std_logic := '0';
signal r_BIT3 : std_logic := '0';
signal w_SUM : std_logic;
signal w_CARRY : std_logic;
begin

UUT : entity work.FA


port map (
A => r_BIT1,
B => r_BIT2,
C => r_BIT3,
sum => w_SUM,
carry => w_CARRY
);

process is
begin
r_BIT1 <= '0';
r_BIT2 <= '0';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '0';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '1';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '1';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '0';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '0';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '1';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '1';
r_BIT3 <= '1';
wait for 50 ns;
end process;
end behave;
 Output:-

 Full Subtractor:-
 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FS is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
difference : out STD_LOGIC;
borrow : out STD_LOGIC);
end FS;
architecture Behavioral of FS is
begin

sum<= A xor B xor C;


carry <= (not A and B) or (B and C) or (C and not A);

end Behavioral;

 Test_Bench:-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity full_subtractor_tb is
end full_subtractor_tb;

architecture behave of full_subtractor_tb is


signal r_BIT1 : std_logic := '0';
signal r_BIT2 : std_logic := '0';
signal r_BIT3 : std_logic := '0';
signal w_DIFFERENCE : std_logic;
signal w_BORROW : std_logic;
begin

UUT : entity work.FS


port map (
A => r_BIT1,
B => r_BIT2,
C => r_BIT3,
difference => w_DIFFERENCE,
carry => w_BORROW
);

process is
begin
r_BIT1 <= '0';
r_BIT2 <= '0';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '0';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '1';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '0';
r_BIT2 <= '1';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '0';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '0';
r_BIT3 <= '1';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '1';
r_BIT3 <= '0';
wait for 50 ns;
r_BIT1 <= '1';
r_BIT2 <= '1';
r_BIT3 <= '1';
wait for 50 ns;
end process;
end behave;
 Output:-

8. In system the 4-bit binary data is output. We need to


display the data on 7 segment LED display. Design the
module accordingly.

D0 (a) = ~B~D + C + BD + A

D1 (b) = ~B + ~C~D + CD

D2 (c) = ~C + D + B

D3 (d) = ~B~D + ~BC + B~CD + C~D + A

D4 (e) = ~B~D + C~D

D5 (f) = ~C~D + B~C + B~D + A

D6 (g) = ~BC + B~C + A + B~D

*Included every don’t care condition in this function.


 Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
D0 : out STD_LOGIC;
D1 : out STD_LOGIC;
D2 : out STD_LOGIC;
D3 : out STD_LOGIC;
D4 : out STD_LOGIC;
D5 : out STD_LOGIC;
D6 : out STD_LOGIC);
end BCD;
architecture Behavioral of BCD is

begin

D0 <= (not B and not D) or C or ( B and D ) or A;


D1 <= ( not B ) or (not C and not D ) or (c and d);
D2 <= ( not C ) or D or B;
D3 <= (not B and not D ) or ( not B and C ) or ( B and not C
and D ) or ( C and not D ) or A;
D4 <= (not B and not D ) or ( C and not D );
D5 <= (not C and not D ) or ( B and not C) or ( B and not D);

D6 <= ( not B and C) or ( B and not C ) or A or ( B and not


D);

end Behavioral;
 Test_BENCH:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Majority IS
END tb_Majority;

ARCHITECTURE behavior OF tb_Majority IS


COMPONENT BCD
PORT(
A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
D0 : out STD_LOGIC;
D1 : out STD_LOGIC;
D2 : out STD_LOGIC;
D3 : out STD_LOGIC;
D4 : out STD_LOGIC;
D5 : out STD_LOGIC;
D6 : out STD_LOGIC);
END COMPONENT;
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal D0 : std_logic;
signal D1 : std_logic;
signal D2 : std_logic;
signal D3 : std_logic;
signal D4 : std_logic;
signal D5 : std_logic;
signal D6 : std_logic;

BEGIN
uut: BCD PORT MAP (
A => A,
B => B,
C => C,
D => D,
D0 => D0,
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6);

stim_proc: process
begin

wait for 50 ns;

A <= '0'; B <= '0'; C <= '0'; D <= '0';


wait for 50 ns;
A <= '0'; B <= '0'; C <= '0'; D <= '1';
wait for 50 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '0';
wait for 50 ns;
A <= '0'; B <= '0'; C <= '1'; D <= '1';
wait for 50 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '0';
wait for 50 ns;
A <= '0'; B <= '1'; C <= '0'; D <= '1';
wait for 50 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '0';
wait for 50 ns;
A <= '0'; B <= '1'; C <= '1'; D <= '1';
wait for 50 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '0';
wait for 50 ns;
A <= '1'; B <= '0'; C <= '0'; D <= '1';
wait for 50 ns;
A <= '1'; B <= '0'; C <= '1'; D <= '0';
end process;

END;

 Output:-
 Conclusion:-
Hence the given combinational circuits 4*2 encoder, 2*4
decode, 2*1 MUX, 1*2 DEMUX, 1 bit comparator, 3 input
majority gate, full adder, full subtractor and 7 segment
display codes are simulated and observed the outputs as per
their corresponding truthtables.

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