B.Tech – CSE – Sem.

3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4- Session-1
Introduction to Sequential circuits, Latch and Flip-Flops
 Sequential Circuits

Every digital system is likely to have combinational circuits,

most systems encountered in practice also include storage
elements, which require that the system be described in term
of sequential logic.

2
Synchronous Clocked Sequential Circuit

A sequential circuit may use many flip-flops to store as many

bits as necessary. The outputs can come either from the
combinational circuit or from the flip-flops or both.

3
 Latches --SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or
two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.

4
SR Latch with NAND Gates

5
 SR Latch with Control Input

The operation of the basic SR latch can be modified by

providing an additional control input that determines when
the state of the latch can be changed. In Fig. 5-5, it consists
of the basic SR latch and two additional NAND gates.

6
 D Latch

One way to eliminate the undesirable condition of the

indeterminate state in SR latch is to ensure that inputs S
and R are never equal to 1 at the same time in Fig 5-5. This
is done in the D latch.

7
Graphic Symbols for latches
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.

8
 Flip-Flops

The state of a latch or flip-flop is switched by a change in

the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.

9
Clock Response in Latch

In Fig (a) a positive level response in the control input

allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.

10
Clock Response in Flip-Flop

11
S-R Flip Flop

• The SET-RESET flip flop is designed with the help of two NOR gates and
also two NAND gates. These flip flops are also called S-R Latch.
• S-R Flip Flop using NOR Gate The design of such a flip flop includes two
inputs, called the SET [S] and RESET [R].
• There are also two outputs, Q and Q’.
• From the diagram it is evident that the flip flop has mainly four
states. They are S=1, R=0—Q=1, Q’=0 This state is also called the SET
state.
• S=0, R=1—Q=0, Q’=1 This state is known as the RESET state. In both
the states you can see that the outputs are just compliments of each
other and that the value of Q follows the value of S.
• S=0, R=0—Q & Q’ = Remember If both the values of S and R are
switched to 0, then the circuit remembers the value of S and R in
their previous state.
• S=1, R=1—Q=0, Q’=0 [Invalid] This is an invalid state because the
values of both Q and Q’ are 0. They are supposed to be compliments
of each other. Normally, this state must be avoided.
S-R Flip Flop using NAND Gate
• Like the NOR Gate S-R flip flop, this one also has four states. They are S=1,
R=0—Q=0, Q’=1 This state is also called the SET state.
• S=0, R=1—Q=1, Q’=0 This state is known as the RESET state. In both the
states you can see that the outputs are just compliments of each other
and that the value of Q follows the compliment value of S.
• S=0, R=0—Q=1, & Q’ =1 [Invalid] If both the values of S and R are switched
to 0 it is an invalid state because the values of both Q and Q’ are 1. They
are supposed to be compliments of each other. Normally, this state must
be avoided.
• S=1, R=1—Q & Q’= Remember If both the values of S and R are switched
to 1, then the circuit remembers the value of S and R in their previous
state.
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4
Session-2 ( Gated SR Flip Flops, Edge Triggered RS Fip-flop)
Session-3(Edge Triggered D Fip-flops, Edge Triggered T Fip-flops)
Gated SR Latch
• The basic latch changes its state when the input signals
change

• It is hard to control when these input signals will

change and thus it is hard to know when the latch may
change its state.

• We want to have something like an Enable input

• In this case it is called the “Clock” input because it is

desirable for the state changes to be synchronized
Circuit Diagram for the Gated SR Flip-Flop

[ Figure 5.5a from the textbook ]

Circuit Diagram for the Gated SR Flip-Flop

This is the “gate”

of the gated latch
Circuit Diagram for the Gated SR Flip-Flop

Notice that these

are
complements of
each other
Circuit Diagram and Characteristic Table
for the Gated SR Flip-Flop

[ Figure 5.5a-b from the textbook ]

Circuit Diagram and Graphical Symbol
for the Gated SR Flip-Flop

[ Figure 5.5a,c from the textbook ]

Timing Diagram for the Gated SR Flip-Flop

[ Figure 5.5c from the textbook ]

Gated SR Flip-Flop with NAND gates

S
Q

Clk

Q
R

[ Figure 5.6 from the textbook ]

Gated SR Flip-Flop with NAND gates

S
Q

Clk

Q
R

In this case the “gate” is

constructed using
NAND gates! Not AND
 Edge-Triggered Flip-Flops
• In basic master-slave flip-flops, master is enabled during the entire period the
control input is 1.
– This can result in 0’s and 1’s catching.
– To avoid this, signals on information lines are restricted from changing during the time the
master is enabled.
– Also a delay in the output since master’s state is established during the positive edge and
transferred to the slave on the negative edge of clock.
• Edge-triggered flip-flops use just one of the edges of the clock signal.
– This is referred to as the triggering edge.
• Response to triggering edge at the output of the flip-flop is almost immediate
(depends only on propagation delay times).
• Once triggering occurs, flip-flop is unresponsive to information input changes until
the next triggering edge.
Edge-Triggered SR Flip-Flops
1. C = 0. Regardless of input at D,
outputs of gates 2,3 are 1. So
𝑆 = 𝑅 = 1. State of latch is held.
2. Assume D = 0: Output of gate 4 is 1,
output of gate 1 is 0. When C goes
to 1: all inputs to gate 3 are 1,
output changes to 0. Output of gate
2 remains at 1 since output of gate 1
is 0. So 𝑆 = 1, 𝑅 = 0. Output of
gate 3 (0) is fed to input of gate 4.
Output of gate 4, gate 1 not affected
by changes to D.
3. Assume C = 0, D = 1. Outputs of
gates 2,3, are 1. Output of gate 4 is
𝑆 𝑅 Latch 0, output of gate 1 is 1. When C goes
to 1: output of gate 2 is 0, output of
gate 3 remains at 1. So 𝑆 = 0, 𝑅 =
1. Output from gate 2 is input to
gates 1, 3 so their outputs remain at
1. Changes in D have no affect on
state of flip-flop while C = 1.
Edge-Triggered SR Flip-Flops
 Timing Diagram

During setup and hold times 𝑡𝑠𝑢 , 𝑡ℎ with respect to the

triggering edge of the clock, D input must not change.
 Negative-Edge Triggered D Flip-Flop
• A falling edge (high to low transition) of control signal is used to
sample the D input line.
• Simply place inverter at the control input of the flip-flop.
Positive-Edge Triggered T-Flip-Flop
 Characteristic Equations
• Next state table: Shows the value of the next state of the flip-
flop for each combination of values to the present state of the
flip-flops and their information lines.
• The algebraic description of the next-state table of a flip-flop is
called the characteristic equation of the flip-flop.
• Obtained by constructing the K-map for 𝑄 + in terms of the
present state and information input variables.
Next State Tables
Characteristic Equations
T Flip Flop

• This is a much simpler version of the J-K flip flop. Both the J and K inputs
are connected together and thus are also called a single input J-K flip flop.
• When clock pulse is given to the flip flop, the output begins to toggle.
Here also the restriction on the pulse width can be eliminated with a
masterslave or edge-triggered construction.
 Flip-Flop Solution

• Use edge-triggering instead of master-slave

• An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
• Edge-triggered flip-flops can be built directly
at the electronic circuit level, or
• A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.
 Edge-Triggered D Flip-Flop
D D Q S Q
Q
• The edge-triggered
C
D flip-flop is the
same as the master- C C Q R Q Q
slave D flip-flop
• It can be formed by:
– Replacing the first clocked S-R latch with a clocked D latch or
– Adding a D input and inverter to a master-slave S-R flip-flop
• The delay of the S-R master-slave flip-flop can be avoided since
the 1s-catching behavior is not present with D replacing S and R
inputs
• The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
• It is called a negative-edge triggered flip-flop
 Positive-Edge Triggered D Flip-Flop
D D Q S Q Q
C
C C Q R Q Q

• Formed by
adding inverter
to clock input

• Q changes to the value on D applied at the positive clock edge within timing constraints to be
specified
• Our choice as the standard flip-flop for most sequential circuits

25
Edge-Triggered FF Operation

26
Edge-Triggered FF Operation

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Edge-Triggered FF Operation

28
Edge-Triggered FF Operation

29
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL ELECTRONICS
(Regulations 2018)

UNIT 4
Session-6(Edge Triggered J-K Fip-flop, Edge
Triggered Master Slave Fip-flop)
 J-K FLIP-FLOP

• A J-K flip-flop has very similar characteristics to an S-R

flip-flop. The only difference is that the undefined
• condition for an S-R flip-flop, i.e., Sn = Rn = 1 condition,
is also included in this case. Inputs J and K behave
• like inputs S and R to set and reset the flip-flop
respectively. When J = K = 1, the flip-flop is said to be in
a
• toggle state, which means the output switches to its
complementary state every time a clock passes.
• The data inputs are J and K, which are ANDed with Q'
and Q respectively to obtain the inputs for S and R
An S-R flip-flop converted into a J-K flip-
flop
A J-K flip-flop using NAND gates
Logic symbol of a J-K flip-flop
The TRUTH table for JK flip-flop
Case 1. When the clock is applied and J = 0, whatever the value of Q'n (0 or 1), the output of
NAND gate 1 is 1.
Similarly, when K = 0, whatever the value of Qn (0 or 1), the output of gate 2 is also 1.
Therefore, when J = 0 and K = 0, the inputs to the basic flip-flop are S = 1 and R = 1. This
condition forces the flip-flop to remain in the same state.
Case 2. When the clock is applied and J = 0 and K = 1 & the previous state of the flip-flop is
reset (i.e., Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flip-flop
does not alter the state and remains in the reset state. But if the flip-flop is in set condition
(i.e., Qn = 1 & Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop
changes its state and resets.
• Case 3. When the clock is applied and J = 1 and K = 0 and the previous
state of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R
= 1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes
to the set state. But if the flip-flop is already in set condition (i.e., Qn =
1 and Q'n = 0), then S = 1 and R = 1. Since S = 1 and R = 1, the basic
flip-flop does not alter its state and remains in the set state.

• Case 4. When the clock is applied and J = 1 and K = 1 and the previous
state of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R
= 1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes
to the set state. But if the flip-flop is already in set condition (i.e., Qn =
1 and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic
flip-flop changes its state and goes to the reset state. So we find that for
J = 1 and K = 1, the flip-flop toggles its state from set to reset and vice
versa. Toggle means to switch to the opposite state.
 Master-Slave Flip-Flops
(Pulse Triggered Flip-Flops)
• Aside from latches, two categories of flip-flops.
– Master-slave flip-flops (pulse-triggered flip-flops)
– Edge-triggered flip-flops
• Latches have immediate output response (known as
transparency)
• May be undesirable:
– May be necessary to sense the current state of a flip-flop
while allowing new state information to be entered.
 Master-Slave SR Flip-Flop
• Two sections, each capable of storing a binary symbol.
• First section is referred to as the master and the second
section as the slave.
• Information is entered into the master on one edge or level of
a control signal and is transferred to the slave on the next
edge or level of the control signal.
• Each section is a latch.
 Master-Slave SR Flip-Flop

• C = 0:
– Master is disabled. Any changes to S,R ignored.
– Slave is enabled. Is in the same state as the master.
• C = 1:
– Slave is disabled (retains state of master)
– Master is enabled, responds to inputs. Changes in state of master are not reflected in disabled
slave.
• C = 0:
– Master is disabled.
– Slave is enabled and takes on new state of the master.
• Important: For short periods during rising and falling edges, both master and slave are
disabled.
 Master-Slave SR Flip-Flop

Slave only takes on state

Pulse
of the master at 𝑡4 .
symbol
indicates
master Postponed output
enabled indicator: output
when C = 1 change postponed until
and state end of pulse
of master
transferred If S, R = 1 when control
to slave at signal goes from high to
the end of low we are in an
the pulse unpredicable state. Can
period. cause metastable state.
 Timing Diagram for
Master-Slave SR flip-flop
 Master-Slave JK Flip-Flop
• The output state of a master-slave SR flip-flop
is undefined upon returning the control input
to 0 when S = R = 1.
– Necessary to avoid this condition.
• Master-slave JK flip-flop allows its two
information input lines to be simultaneously 1.
– Results in toggling the output of the flip flop.
 Master-Slave JK Flip-Flop

• Assume in 1-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 0, output of K-gate is 1.
– If clock is changed to C = 1 then master is reset.
• Assume in 0-state, C = 0, J = K = 1.
– Due to feedback, the output of the J-gate is 1, output of K-gate is 0.
– If clock is changed to C = 1 then master is set.
• 1 on J input line, 0 on K input line sets the flip-flop.
– If in 1-state, unchanged b/c S,R set to 0.
– If in 0-state, S set to 1, R set to 0.
• 0 on J input, 1 on K input line resets the flip-flop. Why?
Master-Slave JK Flip-Flop
 Timing Diagram for
Master-Slave JK Flip-Flop
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4
Session-7( Analysis of synchronous sequential circuits: State Equation,
State Table, State Diagram)
 Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of obtaining a

table or a diagram for the time sequence of inputs, outputs,
and internal states. It is also possible to write Boolean
expressions that describe the behavior of the sequential
circuit. These expressions must include the necessary time
sequence, either directly or indirectly.

2
 State Equations

The behavior of a clocked sequential circuit can be

described algebraically by means of state equations. A state
equation specifies the next state as a function of the
present state and inputs. Consider the sequential circuit. It
consists of two D flip-flops A and B, an input x and an
output y.

3
Fig.5-15 Example of Sequential Circuit

4
 State Equation
A(t+1) = A(t) x(t) + B(t) x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that specifies

the condition for a flip-flop state transition. The left side of
the equation with (t+1) denotes the next state of the flip-
flop one clock edge later. The right side of the equation is
Boolean expression that specifies the present state and
input conditions that make the next state equal to 1.

Y(t) = (A(t) + B(t)) x(t)`

5
 State Table

The time sequence of inputs, outputs, and flip-flop states

can be enumerated in a state table (sometimes called
transition table).

6
 State Diagram

The information available in a state table can be

represented graphically in the form of a state diagram. In
this type of diagram, a state is represented by a circle, and
the transitions between states are indicated by directed
lines connecting the circles.

1/0 : means input =1

output=0

7
 Flip-Flop Input Equations
The part of the combinational circuit that generates
external outputs is descirbed algebraically by a set of
Boolean functions called output equations. The part of the
circuit that generates the inputs to flip-flops is described
algebraically by a set of Boolean functions called flip-flop
input equations. The sequential circuit of consists of two D
flip-flops A and B, an input x, and an output y. The logic
diagram of the circuit can be expressed algebraically with
two flip-flop input equations and an output equation:

DA = Ax + Bx
DB = A`x
y = (A + B)x`
8
 Analysis with D Flip-Flop

The circuit we want to analyze is described by the input

equation DA = A x y
The DA symbol implies a D flip-flop with output A. The x and
y variables are the inputs to the circuit. No output equations
are given, so the output is implied to come from the output
of the flip-flop.

9
 Analysis with D Flip-Flop
The binary numbers under Axy are listed from 000 through
111 as shown in Fig. 5-17(b). The next state values are
obtained from the state equation A(t+1) = A x y

The state diagram consists of two circles-one for each state

as shown in Fig. 5-17(c)

10
Analysis with JK Flip-Flops

11
 Analysis with JK Flip-Flop

The circuit can be specified by the flip-flop input equations

JA = B KA = Bx`
JB = x` KB = A`x + Ax` = A x

12
 Analysis with JK Flip-Flops
A(t + 1) = JA` + K`A
B(t + 1) = JB` + K`B
Substituting the values of JA and KA from the input
equations, we obtain the state equation for A:

A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax

The state equation provides the bit values for the column
under next state of A in the state table. Similarly, the state
equation for flip-flop B can be derived from the characteristic
equation by substituting the values of JB and KB:

B(t + 1) = x`B` + (A x)`B = B`x` + ABx + A`Bx`

13
 Analysis with JK Flip-Flops

The state diagram of the sequential circuit is shown in Fig.

5-19.

14
 Analysis With T Flip-Flops
Characteristic equation
Q(t + 1) = T Q = T`Q + TQ`

00/0 : means
state is 00
output is 0

15
 Analysis With T Flip-Flops
Consider the sequential circuit shown in Fig. 5-20. It has
two flip-flops A and B, one input x, and one output y. It
can be described algebraically by two input equations and
an output equation: Use present state
as inputs

TA = Bx
TB = x
y = AB

A(t+1)=(Bx)’A+(Bx)A’
=AB’+Ax’+A’Bx

B(t+1)=xB

16
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4
Session-8 ( Synthesis of Sequential Circuits, Problem Session)
 Synthesis Sequential Circuits:
Design Procedure

The procedure for designing synchronous sequential

circuits can be summarized by a list of recommended steps.

1. From the word description and specifications of the desired

operation, derive a state diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output
equations.
7. Draw the logic diagram.
2
Example D Flip-Flop
Design Procedure

3
Synthesis Using D Flip-Flops
A(t + 1) = DA(A, B, x) = ∑ (3, 5, 7)
B(t + 1) = DB(A, B, x) = ∑ (1, 5, 7)
y(A, B, x) = ∑ (6, 7)

4
Synthesis Using D Flip-Flops
DA = Ax +Bx
DB = Ax + B`x
y = AB

5
Synthesis Using D Flip-Flops

6
Synthesis Using JK Flip-Flops

Different from Table 5-11 !!

Ref. Table 5-1

7
Synthesis Using JK Flip-Flops

8
Synthesis Using JK Flip-Flops

9
Synthesis Using T Flip-Flops
The synthesis using T flip-flops will be demonstrated by
designing a binary counter. An n-bit binary counter consists
of n flip-flops that can count in binary from 0 to 2n-1. The
state diagram of a 3-bit counter is shown in Fig. 5-29.

Ref. Table 5-1

10
Synthesis Using T Flip-Flops

11
Synthesis Using T Flip-Flops

12
Synthesis Using T Flip-Flops

13
State Reduction and Assignment
State Reduction and Assignment (Contd.)
State Reduction and Assignment (Contd.)
State Reduction and Assignment (Contd.)
State Reduction and Assignment
(Contd.)

State Assignment

State Binary Gray CodeOne-Hot

a 000 000 00001
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000
State Reduction and Assignment
(Contd.)
Reduced State Table:
Binary State Assignment
Next State Output
State x=0 x=1 x=0 x=1
000 001 0 0
001
010 010 011 0 0

011 000 011 0 0

100 100 011 0 1

101 000 011 0 1

State Reduction and Assignment
(Contd.)
Reduced State Table:
Binary State Assignment
Next State Output
State
x=0 x=1 x=0 x=1
001
000 001 0 0
010
010 011 0 0
011
000 011 0 0
100
100 011 0 1
101
000 011 0 1
Design Procedure

• Develop State Diagram From Specs

• Reduce States
• Assign Binary values to States
• Write Binary-coded State Table
• Choose Flip-Flops
• Derive Input and Output Equations
• Draw the Logic Diagram
Develop State Diagram:
Sequence Detector

• Detect 3 or more 1s in sequence (a Moore Model)

D Flip-Flop Input Equations

State Input Next State Output

A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1

Input equations come

A(t+1) = DA(A,B,x) = S(3,5,7)
directly from the next = D (A,B,x) = S(1,5,7)
B(t+1) B
state in D Flip-Flop y(A,B,x) = S(6,7)
design
Simplified Boolean Equations
Sequence Detector: D Flip-Flops
 Using JK or T Flip-Flops

1. Develop Excitation Table Using Excitation Tables

JK Flip-Flop T Flip-Flop

Q(t) Q(t+1) J K Q(t) Q(t+1) T

0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 1
1 1 X 0 1 1 0
State Table: JK Flip-Flop Inputs

Present Next
State Input State Flip-Flop Inputs
A B x A B JA KA JB KB
0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0
0 1 0 0 1 0 1 0 1
1 0 1 1 0 1 0 1 0
1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
Maps for J and K Input Equations
JK Flip-Flop Sequence Detector
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4
Session-11( Asynchronous Sequential Circuits, Transition Table)
Session-12( State Table, Flow Table)
Definitions:

State Table:
The relationship that exists among the inputs, outputs, present states and next states can be
specified by either the state table or the state diagram

Transition Table:
Transition table is table of states and transition, useful to analyze an asynchronous circuit from the
circuit diagram

Flow Table:
In a flow table the states are named by letter symbols
 B.Tech – CSE – Sem. 3
18CSS201J – ANALOG AND DIGITAL
ELECTRONICS
(Regulations 2018)
UNIT 4
Session-13( Asynchronous Sequential Circuits Analysis and Problem
Solving Session)
Asynchronous Sequential Circuits
Asynchronous sequential circuits basics
✓No clock signal is required
✓Internal states can change at any instant of time when there is
a change in the input variables
✓Have better performance but hard to design due to timing
problems
Why Asynchronous Circuits?
✓Accelerate the speed of the machine (no need to wait for the
next clock pulse).
✓Simplify the circuit in the small independent gates.
✓Necessary when having multi circuits each having its own
clock.
Analysis Procedure
✓The analysis consists of obtaining a table or a diagram that
describes the sequence of internal states and outputs as a
function of changes in the input variables.
Example Circuit
✓ Construction of Asynchronous
Circuits:
• using only gates
• with feedback paths
✓ Analysis:
• Lump all of the delay associated
with each feedback path into a
“delay” box
• Associate a state variable with
each delay output
• Construct the flow table
✓ Network equations
Q1+ = X1X2’+ X1’X2Q2+X2Q1Q2’
Q2+ = X1’X2Q1’+ X1Q2+ X2Q2
Z = X1⊕Q1⊕Q2
 Example Circuit: Output Table
✓ 1.Starting in total state X X Q Q =0000
1 2 1 2

✓ 2.Input changes to 01
• Internal state changes to 01 and then
to 11.
✓ 3.Input changes to 11.
• Go to unstable total state 1111 and
then to 1101.
✓ 4.Input changes to 10.
• Go to unstable total state 1001 and
then to 1011.
✓ The output sequence:
0 (0) (1) 0 (1) 0 (0) 1

• Condensed to the form

0 (1) 0 (1) 0 1.
• Two transient 1 outputs can be
eliminated by proper design.
 Transition Table
✓ Transition table is useful to analyze an asynchronous
circuit from the circuit diagram. Procedure to obtain
transition table:
1. Determine all feedback loops in the circuits
2. Mark the input (yi) and output (Yi) of each feedback
loop
3. Derive the Boolean functions of all Y’s
4. Plot each Y function in a map and combine all maps
into one table (flow table)
5. Circle those values of Y in each square that are equal
to the value of y in the same row
Asynchronous Sequential Circuit
✓ The excitation variables: Y1 and Y2
• Y1 = xy1+ xy2
• Y2 = xy1 + xy2
CUT

CUT
Transition Table
✓ Combine the internal state with input
variables
• Stable total states:
y1y2x = 000, 011, 110 and 101
 Transition Table
✓ In an asynchronous sequential circuit, the
internal state can change immediately after
a change in the input.
✓ It is sometimes convenient to combine the
internal state with input value together and
call it the Total State of the circuit.
(Total state = Internal state + Inputs)
✓ In the example , the circuit has
• 4 stable total states: (y1y2x=
000, 011, 110, and 101)
• 4 unstable total states: (y1y2x=
001, 010, 111, and 100)
 Transition Table
✓ If y=00 and x=0 Y=00 (Stable state)
✓ If x changes from 0 to 1 while y=00,
the circuit changes Y to 01 which is
temporary unstable condition (Yy)
✓ As soon as the signal propagates to
make Y=01, the feedback path
causes a change in y to 01.
(transition form the first row to the
second row)
✓ If the input alternates between 0
and 1, the circuit will repeat the
sequence of states
 Flow Table
✓ A flow table is similar to a transition table except that the internal
state are symbolized with letters rather than binary numbers.
✓ It also includes the output values of the circuit for each stable
state.
 Flow Table

✓ In order to obtain the

circuit described by a
flow table, it is
necessary to convert
the flow table into a
transition table from
which we can derive
the logic diagram.
✓ This can be done
through the assignment
of a distinct binary
value to each state.
 Race condition
✓ Two or more binary state variables will change value when one input variable changes.
✓ Cannot predict state sequence if unequal delay is encountered.
✓ Non-critical race: The final stable state does not depend on the change order of state
variables
✓ Critical race: The change order of state variables will result in different stable states.
Must be avoided !!
 Race Solution
✓ It can be solved by making a proper binary assignment to the state
variables.
✓ The state variables must be assigned binary numbers in such a way
that only one state variable can change at any one time when a state
transition occurs in the flow table.
 Stability Check
✓ Asynchronous sequential circuits may oscillate between
unstable states due to the feedback
• Must check for stability to ensure proper operations
✓ Can be easily checked from the transition table
• Any column has no stable states unstable
Ex: when x1x2=11 in (b), Y and y are never the same
Y=x2(x1y)’=x’1x2+x2y’