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Assignment 1.3 CHAPTER 1

This document discusses computer architecture and organization. It addresses several topics: 1) The categories of functions specified by computer instructions are processor-memory, processor-I/O, data processing, and control. 2) The states that define instruction execution are instruction address calculation, instruction fetch, instruction operation decoding, operand address calculation, operand fetch, data operation, and operand store. 3) Approaches to dealing with multiple interrupts are disabling interrupts so they remain pending, and interrupt service routines which assign priorities.

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113 views

Assignment 1.3 CHAPTER 1

This document discusses computer architecture and organization. It addresses several topics: 1) The categories of functions specified by computer instructions are processor-memory, processor-I/O, data processing, and control. 2) The states that define instruction execution are instruction address calculation, instruction fetch, instruction operation decoding, operand address calculation, operand fetch, data operation, and operand store. 3) Approaches to dealing with multiple interrupts are disabling interrupts so they remain pending, and interrupt service routines which assign priorities.

Uploaded by

Scholar Macay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment 1.

3 CPE 310 - Computer Architecture and Organization

3.1 What general categories of functions are specified by computer


instructions?

- The categories are processor-memory, processor-I/O, data processing, and


control.

3.2 List and briefly define the possible states that define an instruction
execution.

 Instruction Address Calculation (IAC) - Determine the address of the next


instruction to be executed.

 Instruction Fetch (IF) -Read instruction from its memory location into the
processor.

 Instruction Operation Decoding - Analyze instruction to determine type of


operation to be performed and operands to be used.

 Operand Address Calculation (OAC) - If the operation involves reference to an


operand in memory or available via I/O, then determine the address of the
operand.

 Operand Fetch (OF) -Fetch the operand from memory or read it in from I/O.

 Data Operation- Perform the operation indicated in the instruction.

 Operand Store (OS) - Write the result into memory or out to I/O.
Assignment 1.3 CPE 310 - Computer Architecture and Organization

3.3 List and briefly define two approaches to dealing with multiple
interrupts.

- Disabling Interrupts- processor has the ability to and will ignore the specific
interrupts. Those interrupts remain pending and will be checked after the
processor has enabled interrupts.

- Interrupt Service Routine (ISR) - priorities assigned to the different types of


interrupts. Interrupt service routines with higher priorities can interrupt ones
with lower priority, in which case the ISR with the lower priority is put on the
stack until that ISR is completed.

3.4 What types of transfers must a computer's interconnection structure


(e.g., bus) support?

- Memory to processor, processor to memory, I/O to processor, processor to I/O,


and I/O to or from memory.

3.5 What is the benefit of using a multiple-bus architecture compared to a


single-bus architecture?

- It is efficient, since if only one bus is for everything, only one device can then
communicate at a time, since if more than one device were to try and send data
on the single bus, transmission would be garbled.
Assignment 1.3 CPE 310 - Computer Architecture and Organization

3.6 List and briefly define the QPI protocol layers.

 Physical - consists of the actual wires carrying the signals, as well as circuitry and
logic to support ancillary features required in the transmission and receipt of the
1s and 0s.
 Link - responsible for reliable transmission and flow control.
 Routing - provides the framework for directing packets through the fabric.
 Protocol -the high-level set of rules for exchanging packets of data between
devices.
Assignment 1.3 CPE 310 - Computer Architecture and Organization

3.7 List and briefly define the PCIe protocol layers.

 Physical layer -consists of the actual wires carrying the signals, as well as circuitry
and logic to support ancillary features required in the transmission and receipt of
the 1s and 0s.
 Data Link layer - responsible for reliable transmission and flow control.
 Transaction layer - generates and consumes data packets sued to implement
load/store data transfer mechanisms and also manages the flow control of those
packets between the two components on a link.

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