Scribd
Upload
53 views

Lecture 9 - Universal Synchronous Asynchronous Synchronous Asynchronous Receiver Transmitter (Usart)

The document discusses the Universal Synchronous Asynchronous Receiver Transmitter (USART) module and Analog to Digital (A/D) converter module. The USART can operate asynchronously or synchronously and is used for serial communication. The A/D converter converts analog signals to digital values. Key steps are outlined for configuring and performing conversions with both modules.

Uploaded by

sudhir
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
53 views

Lecture 9 - Universal Synchronous Asynchronous Synchronous Asynchronous Receiver Transmitter (Usart)

The document discusses the Universal Synchronous Asynchronous Receiver Transmitter (USART) module and Analog to Digital (A/D) converter module. The USART can operate asynchronously or synchronously and is used for serial communication. The A/D converter converts analog signals to digital values. Key steps are outlined for configuring and performing conversions with both modules.

Uploaded by

sudhir
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 29

LECTURE 9 –

UNIVERSAL
SYNCHRONOUS ASYNCHRONOUS
RECEIVER TRANSMITTER (USART)
USART – Basics
• USART is also known as a Serial Communications
Interface or SCI.)

• The USART can be configured as a full duplex


asynchronous system that can communicate with
peripheral devices such as CRT terminals and personal
computers, or

• it can be configured as a half duplex synchronous


system that can communicate with peripheral devices
such as A/D or D/A integrated circuits, serial EEPROMs
etc.
Continued…
• The USART can be configured in the following modes:
– Asynchronous (full duplex)
– Synchronous - Master (half duplex)
– Synchronous - Slave (half duplex)

• Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set


in order to configure pins RC6/TX/CK and RC7/RX/DT as
the Universal Synchronous Asynchronous Receiver
Transmitter.

• The USART module also has a multi-processor


communication capability using 9-bit address
detection.
Registers Associated with USART
• TXSTA
– Transmit Status and Control Register.

• RCSTA
– Receive Status and Control Register
Baud Rate Generation (BRG)
• The BRG supports both the Asynchronous and
Synchronous modes of the USART.

• It is a dedicated 8-bit baud rate generator. The


SPBRG register controls the period of a free running
8-bit timer.

• In Asynchronous mode, bit BRGH (TXSTA<2>) also


controls the baud rate.
Continued…
• The formula for computation of the baud rate
for different USART modes which only apply in
Master mode (internal clock).

• Given the desired baud rate and FOSC, the


nearest integer value for the SPBRG register
can be calculated using the formula
USART – Asynchronous Mode
• Asynchronous mode is selected by clearing bit
SYNC (TXSTA<4>).

• The USART Asynchronous module consists of


the following important elements:
– Baud Rate Generator
– Sampling Circuit
– Asynchronous Transmitter
– Asynchronous Receiver
Continued…
• The TXREG register is loaded with data in software.

• The TXREG register is empty and flag bit TXIF


(PIR1<4>) is set.

• The actual transmission will not occur until the


TXREG register has been loaded with data and the
baud rate generator (BRG) has produced a shift
clock.
Steps for using USART - Asynchronous
mode
• When setting up an Asynchronous Transmission, follow these
steps:

1. Initialize the SPBRG register for the appropriate baud rate. If a


high speed baud rate is desired, set bit BRGH.

2. Enable the asynchronous serial port by clearing bit SYNC and


setting bit SPEN.

3. If interrupts are desired, then set enable bit TXIE.

4. If 9-bit transmission is desired, then set transmit bit TX9.


Continued…
5. Enable the transmission by setting bit TXEN, which
will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit should


be loaded in bit TX9D.

7. Load data to the TXREG register (starts transmission).

8. If using interrupts, ensure that GIE and PEIE (bits 7


and 6) of the INTCON register are set.
Block Diagram of Asynchronous
Transmission
Block Diagram of Asynchronous
Reception
Various Steps for Asynchronous
Reception are:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired, set
bit BRGH.

2. Enable the asynchronous serial port by clearing bit


SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit RCIE.

4. If 9-bit reception is desired, then set bit RX9.


Continued…
5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is complete and an


interrupt will be generated if enable bit RCIE is set.

7. Read the RCSTA register to get the ninth bit (if enabled) and
determine if any error occurred during reception.

8. Read the 8-bit received data by reading the RCREG register.

9. If any error occurred, clear the error by clearing enable bit


CREN.

10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of
the INTCON register are set.
USART – Synchronous Mode
• In Synchronous mode, the data is transmitted in a half-
duplex manner (i.e., transmission and reception do not
occur at the same time).

• When transmitting data, the reception is inhibited and


vice versa.

• Synchronous mode is entered by setting bit SYNC


(TXSTA<4>).

• In addition, enable bit SPEN (RCSTA<7>) is set in order


to configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (clock) and DT (data) lines, respectively.
Various Steps:
• Steps to follow when setting up a Synchronous
Transmission:

1. Initialize the SPBRG register for the appropriate


baud rate.

2. Enable the synchronous master serial port by


setting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.


Continued…
4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit should be


loaded in bit TX9D.

7. Start transmission by loading data to the TXREG


register.

8. If using interrupts, ensure that GIE and PEIE (bits 7 and


6) of the INTCON register are set.
A/D Converter Module
• The Analog-to-Digital (A/D) Converter module has five
inputs for the 28-pin devices and eight for the other
devices.

• The analog input charges a sample and hold capacitor.

• The output of the sample and hold capacitor is the


input into the converter.

• The converter then generates a digital result of this


analog level via successive approximation.
Continued…
• The A/D conversion of the analog input signal results in
a corresponding 10-bit digital number.

• The A/D module has high and low voltage reference


input that is software selectable to some combination
of VDD, VSS, RA2, or RA3.

• The A/D converter has a unique feature of being able to


operate while the device is in SLEEP mode.

• To operate in SLEEP, the A/D clock must be derived


from the A/D’s internal RC oscillator.
Continued…
• The A/D module has four registers. These registers
are:

– A/D Result High Register (ADRESH)


– A/D Result Low Register (ADRESL)
– A/D Control Register0 (ADCON0)
– A/D Control Register1 (ADCON1)
Continued…
• The ADCON0 register, controls the operation of the
A/D module.

• The ADCON1 register, configures the functions of


the port pins.

• The port pins can be configured as analog inputs


(RA3 can also be the voltage reference), or as
digital I/O.
Registers Associated with A/D Module

ADCON0 Register

ADCON1 Register
Various steps for doing the A/D
Conversion
• These steps should be followed for doing an
A/D Conversion:

1. Configure the A/D module:


– Configure analog pins/voltage reference and
digital I/O (ADCON1)
– Select A/D input channel (ADCON0)
– Select A/D conversion clock (ADCON0)
– Turn on A/D module (ADCON0)
CONTINUED…
2. Configure A/D interrupt (if desired):
– Clear ADIF bit
– Set ADIE bit
– Set PEIE bit
– Set GIE bit

3. Wait the required acquisition time.

4. Start conversion: Set GO/DONE bit (ADCON0)


Continued…
5. Wait for A/D conversion to complete, by either:
– Polling for the GO/DONE bit to be cleared.
– With interrupts enabled, waiting for the A/D interrupt.

6. Read A/D result register pair (ADRESH:ADRESL), clear bit


ADIF if required.

7. For the next conversion, go to step 1 or step 2, as required.

** The A/D conversion time per bit is defined as TAD. A


minimum wait of 2TAD is required before the next
acquisition starts.

You might also like