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Exercises On Memory Management

This document contains 7 questions about memory management concepts like contiguous memory allocation strategies, page table translation, and two-level page tables. It asks the reader to determine physical addresses from logical addresses using a sample page table, calculate memory access times with and without a translation lookaside buffer (TLB), and identify frame numbers and page table entry bit sizes for different memory management configurations.

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123 views

Exercises On Memory Management

This document contains 7 questions about memory management concepts like contiguous memory allocation strategies, page table translation, and two-level page tables. It asks the reader to determine physical addresses from logical addresses using a sample page table, calculate memory access times with and without a translation lookaside buffer (TLB), and identify frame numbers and page table entry bit sizes for different memory management configurations.

Uploaded by

Lộc Sẹo
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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April 29 2021

IT3072E Operating Systems: Exercises on memory management

1. Assume the base and limit registers contain the same value, 16,384.
Is this just an accident, or are they always the same? It is just an
accident, why are they the same in this case?

2. Assume contiguous memory allocation is used to allocate memory space


to processes and we have the current memory hole sizes of 10 MB, 4
MB, 20 MB, 18 MB, 7 MB, 9 MB, 12 MB, and 15 MB. The existence of
these holes are kept in a list in the same order. Which hole are taken
for successive processes of size 1) 12 MB; 2) 10 MB; 3) 9 MB given
the decision to allocate a hole is based on one of the following strategy
(each strategy seek a hole in the order of the list):

(a) First fit


(b) Worst fit
(c) Best fit

3. Using the page table on slide 31 in the class notes, what are the physical
addresses of the logical addresses

(a) 4,096
(b) 2,062
(c) 8,949
(d) 11,266

4. A system implements a paged virtual address space for each process


using a one-level page table. The maximum size of an address space
is 16 megabytes. The page table for the running process includes the
following entries:

0 4
1 8
2 16
3 17
4 9

The page size is 4KB and the maximum physical memory size of the
machine is 2 megabytes.

(a) How many bits are required for each page table entry?
(b) What is the maximum number of entries in a page table?
(c) How many bits are there in a virtual address?
(d) To which physical address will the virtual address 1524 translate
to?
(e) Assuming that frame 0 starts at the physical address 0, that con-
secutive frame numbers have consecutive physical addresses (the
first address of frame i + 1 follows immediately the last address
of frame i), then, which virtual address will translate to physical
address 65536?

5. Consider a paging system with the page table stored in memory.

(a) If a memory reference takes 400ns, how long does it takes to fetch
data through the page table?
(b) If we add a TLB, and 85% of all page-table references are found
in the TLB (i.e. hit rate is 85%), what is the effective memory
reference time? (Assume that finding a page-table entry in the
associative registers takes zero time, if the entry is there.)

6. Consider a paging system with the page table stored in memory. As-
sume the overhead to read an entry in the page table is 5ns (access to
the page table is 5 ns). To reduce this overhead, a TLB is installed,
where a look up in the TLB cost 1ns. What hit rate is needed to reduce
the average overhead to access the page table to 2ns?

7. A system implements a paged virtual address space using a two-level


page table. The maximum size of a process address space is 2 megabytes
(221 bytes). The page table for the running process includes the follow-
ing entries:

The page size is 2KB (211 ) and the maximum physical memory size of
the machine is 1 megabyte (220 bytes).

(a) How many bits are required for each page table entry?
(b) What is the maximum number of entries in a page table?
(c) How many bits there is in virtual addresses generated by the CPU?
(d) To which physical address will the virtual address 9812 translate
to?
(e) Assuming that frame 0 starts at the physical address 0, that con-
secutive frame numbers have consecutive physical addresses (the
first address of frame i + 1 follows immediately the last address
of frame i), then, which virtual address will translate to physical
address 33768?

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