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17ec53 - Verilog HDL - Combined

This document provides information about a lecture on Verilog HDL, including the course code, objectives, outcomes, and syllabus. The lecture notes were prepared by faculty in the Electronics and Communication Engineering department at Maharaja Institute of Technology Mysore. The syllabus covers 5 modules on Verilog HDL, including an introduction to VHDL. The objectives are to learn Verilog and VHDL constructs and different abstraction levels to effectively model digital circuits. The outcomes include understanding Verilog processes, applying concepts in stimulus/design blocks, and analyzing modeling procedures.

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0% found this document useful (0 votes)

241 views124 pages

17ec53 - Verilog HDL - Combined

Uploaded by

rachitha s

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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Maharaja Education Trust (R), Mysuru

Maharaja Institute of Technology Mysore

Belawadi, SrirangaPattana Taluk, Mandya – 571 477

Approved by AICTE, New Delhi,

Affiliated to VTU, Belagavi & Recognized by Government of Karnataka

Lecture Notes on
Verilog hdl(17EC53)

Prepared by

Department of
Electronics and Communication Engineering
Maharaja Education Trust (R), Mysuru
Maharaja Institute of Technology Mysore
Belawadi, SrirangaPattana Taluk, Mandya – 571 477

Vision/ ಆಶಯ
“To be recognized as a premier technical and management institution promoting extensive
education fostering research, innovation and entrepreneurial attitude"
ಸಂಶೋಧನೆ,
ಆವಿಷ್ಕಾ ರಹಾಗೂಉದ್ಯ ಮಶೋಲತೆಯನ್ನು ಉತೆತ ೋಜಿಸುವಅಗ್ರ ಮಾನ್ಯ ತಾಂತ್ರರ ಕಮತ್ತತ ಆಡಳಿತವಿಜ್ಞಾ ನ್ಶಕ್ಷಣಕಾಂ

ದ್ರ ವಾಗಿಗುರುತ್ರಸಿಕೊಳ್ಳು ವುದು.

Mission/ ಧ್ಯ ೇಯ
 To empower students with indispensable knowledge through dedicated teaching and
collaborative learning.
ಸಮರ್ಪಣಾಮನೋಭಾವದ್ಬೋಧನೆಹಾಗೂಸಹಭಾಗಿತವ ದ್ಕಲಿಕಾಕರ ಮಗ್ಳಿಾಂದ್ವಿದ್ಯಯ ರ್ಥಪಗ್ಳನ್ನು ಅತಯ ತಾ ೃ
ಷ್ಟ ಜ್ಞಾ ನ್ಸಂರ್ನ್ು ರಾಗಿಸುವುದು.
 To advance extensive research in science, engineering and management disciplines.
ವೈಜ್ಞಾ ನಿಕ,

ತಾಂತ್ರರ ಕಹಾಗೂಆಡಳಿತವಿಜ್ಞಾ ನ್ವಿಭಾಗ್ಗ್ಳಲಿಿ ವಿಸತ ೃತಸಂಶೋಧನೆಗ್ಳೊಡನೆಬೆಳವಣಿಗೆಹಾಂದುವುದು.

 To facilitate entrepreneurial skills through effective institute - industry collaboration and

interaction with alumni.
ಉದ್ಯ ಮಕ್ಷ ೋತಗ್ಳೊಡನೆಸಹಯೋಗ್,
ಸಂಸ್ಥೆ ಯಹಿರಿಯವಿದ್ಯಯ ರ್ಥಪಗ್ಳೊಾಂದಿಗೆ ನಿರಂತರಸಂವಹನ್ಗ್ಳಿಾಂದ್ವಿದ್ಯಯ ರ್ಥಪಗ್ಳಿಗೆಉದ್ಯ ಮಶೋಲತೆಯಕೌಶ
ಲಯ ರ್ಡೆಯಲುನೆರವಾಗುವುದು.

 To instill the need to uphold ethics in every aspect.

ಜಿೋವನ್ದ್ಲಿಿ ನೈತ್ರಕಮೌಲಯ ಗ್ಳನ್ನು ಅಳವಡಿಸಿಕೊಳ್ಳು ವುದ್ರಮಹತವ ದ್ಕುರಿತ್ತಅರಿವುಮೂಡಿಸುವುದು.
 To mould holistic individuals capable of contributing to the advancement of the society.
ಸಮಾಜದ್ಬೆಳವಣಿಗೆಗೆಗ್ಣನಿೋಯಕೊಡುಗೆನಿೋಡಬಲಿ ರ್ರಿಪೂಣಪವಯ ಕ್ತತ ತವ ವುಳು ಸಮರ್ಪನಾಗ್ರಿೋಕರನ್ನು ರೂಪಿ
ಸುವುದು.

ii
Maharaja Institute of Technology Mysore
Department of Electronics and Communication Engineering

VISION OF THE DEPARTMENT

“To be recognized by the society at large as offering value based quality education to groom the
next generation entrepreneurs, leaders and researchers in the field of electronics and
communication to meet the challenges at global level”.

MISSION OF THE DEPARTMENT

1. To groom the students with strong foundations of Electronics and Communication
Engineering and to facilitate them to pursue higher education and research.
2. To educate and prepare the students to be competent to face the challenges of the
industry/society and /or to become successful entrepreneurs.
3. To provide ethical and value-based education by promoting activities addressing the societal
needs.
4. Enable students to develop skills to solve complex technological problems of current times
and also provide a framework for promoting collaborative and multidisciplinary activities.

PROGRAM SPECIFIC OUTCOMES

Students graduating in Electronics and Communication Engineering will also be able to
1. Apply the basic concepts of engineering science into various areas of Electronics and
Communication Engineering to develop solutions as per specifications.
2. Solve complex Electronics and Communication Engineering problems, using state of the art
hardware and software tools, along with analytical skills to arrive at cost effective and
efficient solutions.

iii
Maharaja Institute of Technology Mysore
Department of Electronics and Communication Engineering
Program Outcomes

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

iv
Maharaja Institute of Technology Mysore
Department of Electronics and Communication Engineering
Course Overview

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for

describing a digital system like a network switch or a microprocessor or a memory or a
flip−flop. It means, by using a HDL we can describe any digital hardware at any level.
Designs, which are described in HDL are independent of technology, very easy for designing
and debugging, and are normally more useful than schematics, particularly for large circuits..

The goal, for students of this course, will be to learn the fundamentals of the verilog hardware
description language from the ground up. And then Starting to write the codes for the digital
systems in three styles i.e, Behavioral description Data- flow description and Structural
description.

This course will enable students to design practical systems using Xilinix tool for various
applications such as elevator, hex keypadetc .course content is divided into5 modules with 4
modules mainly verilog HDL and module 5 an introduction to VHDL
Course Objectives
Course objectives: This course will enable students to:
 Differentiate between Verilog and VHDL descriptions.
 Learn different Verilog HDL and VHDL constructs.
 Familiarize the different levels of abstraction in Verilog.
 Understand Verilog Tasks and Directives.
 Understand timing and delay Simulation.
 Learn VHDL at design levels of data flow, behavioral and structural for effective modelling
of digital circuits
Course Outcomes

CO’s DESCRIPTION OF THE OUTCOMES

Understand the process, importance in Verilog HDL and Apply the same in
17EC53.1 stimulus block and design block.
Apply the concepts of digital electronics to understand the basics of HDL and
17EC53.2 hierarchical modeling concepts.
Apply gate level modeling and data flow modeling procedures to develop the
17EC53.3 software modules for digital systems.
Analyze the behavior of structural, dataflow and behavior modeling procedures written
17EC53.4 in Verilog and VHDL language

Sandesh NG Manasa MG Rajesh N Rajesh N

Faculties Course Coordinator

Facilitator NBA Coordinator HOD

v
Maharaja Institute of Technology Mysore
Department of Electronics and Communication Engineering
Syllabus
Subject Name: VERILOG HDL Subject Code: 17EC53
Module -1
Overview of Digital Design with Verilog HDL:
Evolution of CAD, emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in HDLs. (Text1) L1,
Hierarchical Modeling Concepts: L2
Top-down and bottom-up design methodology, differences between modules and module instances, parts
of a
simulation, design block, stimulus block. (Text1)
Module -2
Basic Concepts:
L1,
Lexical conventions, data types, system tasks, compiler directives. (Text1)
L2,
Modules and Ports:
Module definition, port declaration, connecting ports, hierarchical name referencing. (Text1) L3
Module -3
Gate-Level Modeling:
Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and L1,
turn- off delays, min, max, and typical delays. (Text1) L2,
Dataflow Modeling: L3
Continuous assignments, delay specification, expressions, operators, operands, operator types. (Text1)
Module -4
Behavioral Modeling: L1,
Structured procedures, initial and always, blocking and non-blocking statements, delay control, generate L2,
statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks. L3
Module -5
Introduction to VHDL:
Introduction: Why use VHDL?, Shortcomings, Using VHDL for Design Synthesis, Design tool flow, L1,
Font conventions. L2,
Entities and Architectures: Introduction, A simple design, Design entities, Identifiers, Data objects, L3
Data types, and Attributes. (Text 2)
Text Books:
1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and
Synthesis”, Pearson Education, Second Edition.
2. Kevin Skahill, “VHDL for Programmable Logic”, PHI/Pearson education, 2006.
Reference Books:
1. Donald E. Thomas, Philip R. Moor by, “The Verilog Hardware Description Language”, Springer
Science+Business Media, LLC, Fifth edition.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson(Prentice Hall), Second edition.
3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier.

vi
Maharaja Institute of Technology Mysore
Department of Electronics and Communication Engineering
Index
Subject Name:VERILOG HDL Subject Code: 17EC53

Sl. No. Particulars Page No.

1. Vision and Mission of the Institute ii

2. Vision, Mission and PSOs of the Department iii

3. Program Outcomes iv

4. Course Overview v

5. Syllabus vi

6. Module - 1: Overview of Digital Design with Verilog HDL, 1-16

Hierarchical Modeling Concepts
7. Module - 2: Basic Concepts, Modules and Ports 17-42

8. Module - 3: Gate-Level Modeling, Dataflow Modeling 43-75

9. Module - 4: Behavioral Modeling 76-92

10. Module - 5: Introduction to VHDL, Entities and Architectures 93-116

vii
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viii
VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 1

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

2 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 3

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

4 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 5

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

6 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 7

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

8 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 9

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

10 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 11

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

12 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 13

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

14 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE1 :OVERVIEW OF DIGITAL DESIGN WITH
17EC 53
VERILOG HDL

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 15

V ER ILOG HDL| MODULE1 :OV ERV IEW OF DIG ITA L DESIGN
17EC 53
WITH V ER ILOG HDL

16 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

18 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

20 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

22 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

24 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

26 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

28 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

30 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

32 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

34 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

36 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

38 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

17EC 53 V ER ILOG HDL| MODULE2 :BA SIC CONCEPTS

40 DEPT. OF ELECTR ONICS & COMMU NICA TION E N G G . |M I T MYSOR E

VERILOG HDL| MODULE2 :BASIC CONCEPTS 17EC 53