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Independent University, Bangladesh: "5-Bit" Asy NCH Ronou S C Ount Er & "M Od - 18" C Ou NT Er

The document is a lab report submitted by MD Akif Rahman (student ID: 1711396) for an independent university in Bangladesh. The objective of the project was to design a 5-bit asynchronous counter and a MOD-18 counter based on calculations from the student's ID. The student designed both counters using logic gates in Logic.ly and provided the circuit diagrams. Truth tables were presented to verify the functionality of the 5-bit counter through 31 states and the MOD-18 counter through 16 states in a repeating pattern.

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MD. Akif Rahman
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22 views

Independent University, Bangladesh: "5-Bit" Asy NCH Ronou S C Ount Er & "M Od - 18" C Ou NT Er

The document is a lab report submitted by MD Akif Rahman (student ID: 1711396) for an independent university in Bangladesh. The objective of the project was to design a 5-bit asynchronous counter and a MOD-18 counter based on calculations from the student's ID. The student designed both counters using logic gates in Logic.ly and provided the circuit diagrams. Truth tables were presented to verify the functionality of the 5-bit counter through 31 states and the MOD-18 counter through 16 states in a repeating pattern.

Uploaded by

MD. Akif Rahman
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Department of Electrical & Electronic Engineering

INDEPENDENT UNIVERSITY, BANGLADESH

O P EN - EN D ED L AB R EP O RT
OF
D IG IT A L LO G IC D ES IG N L AB (E E E 2 3 2 L )
S EC T IO N -2

TITLE OF THE PROJECT


“5- BIT” ASY NCH RONOU S C OUNT ER & “M OD -18” C OU NT ER

SUBMITTED BY
MD AKIF RAHMAN (1711396)

SUPERVISED BY
MD. TAWHID ISLAM OPU
ADJUNCT FACULTY, DEPT. OF EEE, IUB

S U M ME R 2 0 2 1
AUGUST 31, 2021
Objective
Suppose you are a logic design engineer at a chip designing company “ABC” & you have been assigned to design
an asynchronous counter of “n” bit where “n” is the minimum bits required to represent the summation of your
ID’s last non-zero four digits. You also have been asked to modify your design as a specific “MOD-m” counter
which will saturates its counting level up to “m” stages (after “m” stages, counter will repeat from the start)
where “m” is the summation of last three digits of your ID.

Now,

❖ Design & draw the above counter circuit through any logic gates from any logic chips,
❖ Identify your counter type,
❖ verify the truth table of your design through simulation,

Student ID: 1711396


Sum of last 4 digit for finding “n”: 1+3+9+6= 19
(19)10= (10011)2
Hence, n=5
Sum of last 3 digit for finding “m”: 3+9+6= 18
Hence, m=18

Motivation
From all the calculation above, my motive for the project is to design and draw 5-bit asynchronous counter and MOD-18
counter, which will be verified by its truth table. I will be designing the circuit with Logic.ly (website). Here for “5-bit”
asynchronous counter I will be using 5 J-K flip flops, Light Bulb (as O/P), clock, Not Gate, and Toggle Switch (to control the
circuit). For the “MOD-18” counter I will be using almost the same component as mentioned for “5-bit” in addition I will
also be using NAND Gate. After designing my circuit, I found out that it is up counter.

Circuit Design for Both the Counter

5-bit Asynchronous Counter MOD-18 Counter


Simulation of 5-Bit Counter

E= 0, D= 0, C= 0; B= 0; A = 0; O/P= 0 E= 0, D= 0, C= 0; B= 0; A= 1; O/P= 1 E= 0, D= 0, C= 0; B= 1; A= 0; O/P= 2

E= 0, D= 0, C= 0; B= 1; A= 1; O/P= 3 E= 0, D= 0, C= 1; B= 0; A= 0; O/P= 4 E= 0, D= 0, C= 1; B= 0; A= 1; O/P= 5

E= 0, D= 0, C= 1; B= 1; A= 0; O/P= 6 E= 0, D= 0, C= 1; B= 1; A= 1; O/ = 7 E= 0, D= 1, C= 0; B= 0; A= 0; O/P= 8

E= 0, D= 1, C = 0; B = 0; A = 1; O/P = 9 E= 0, D= 1, C= 0; B= 1; A= 0; O/P= 10 E= 0, D= 1, C= 0; B= 1; A= 1; O/P= 11

E= 0, D= 1, C= 1; B= 0; A= 0; O/P= 12 E= 0, D= 1, C= 1; B= 0; A= 1; O/P= 13 E= 0, D= 1, C= 1; B= 1; A= 0; O/P= 14


E= 0, D= 1, C= 1; B= 1; A= 1; O/P= 15 E= 1, D= 0, C= 0; B= 0; A= 0; O/P= 16 E= 1, D= 0, C= 0; B= 0; A= 1; O/P= 17

E= 1, D= 0, C= 0; B= 1; A= 0; O/P= 18 E= 1, D= 0, C= 0; B= 1; A= 1; O/P= 19 E= 1, D= 0, C= 1; B= 0; A= 0; O/P= 20

E= 1, D= 0, C= 1; B= 0; A= 1; O/P= 21 E= 1, D= 0, C= 1; B= 1; A= 0; O/P= 22 E= 1, D= 0, C= 1; B= 1; A= 1; O/P= 23

E= 1, D= 1, C= 0; B= 0; A= 0; O/P= 24 E= 1, D= 1, C= 0; B= 0; A= 1; O/P= 25 E= 1, D= 1, C= 0; B= 1; A= 0; O/P= 26

E= 1, D= 1, C= 0; B= 1; A= 1; O/P= 27 E= 1, D= 1, C= 1; B= 0; A= 0; O/P= 28 E= 1, D= 1, C= 1; B= 0; A= 1; O/P= 29


E= 1, D= 1, C= 1; B= 1; A= 0; O/P= 30 E= 1, D= 1, C= 1; B= 1; A= 1; O/P= 31 E= 0, D= 0, C= 0; B= 0; A= 0; O/P= 32

Truth Table

Clock Pulse No. E D C B A Decimal


0 0 0 0 0 0 0
1 0 0 0 0 1 1
2 0 0 0 1 0 2
3 0 0 0 1 1 3
4 0 0 1 0 0 4
5 0 0 1 0 1 5
6 0 0 1 1 0 6
7 0 0 1 1 1 7
8 0 1 0 0 0 8
9 0 1 0 0 1 9
10 0 1 0 1 0 10
11 0 1 0 1 1 11
12 0 1 1 0 0 12
13 0 1 1 0 1 13
14 0 1 1 1 0 14
15 0 1 1 1 1 15
16 1 0 0 0 0 16
17 1 0 0 0 1 17
18 1 0 0 1 0 18
19 1 0 0 1 1 19
20 1 0 1 0 0 20
21 1 0 1 0 1 21
22 1 0 1 1 0 22
23 1 0 1 1 1 23
24 1 1 0 0 0 24
25 1 1 0 0 1 25
26 1 1 0 1 0 26
27 1 1 0 1 1 27
28 1 1 1 0 0 28
29 1 1 1 0 1 29
30 1 1 1 1 0 30
31 1 1 1 1 1 31
32 0 0 0 0 0 0
Simulation of MOD-18 Counter

E= 0, D= 0, C= 0; B= 0; A= 0; O/P= 0 E= 0, D= 0, C= 0; B= 0; A= 1; O/P= 1 E= 0, D= 0, C= 0; B= 1; A= 0; O/P= 2

E= 0, D= 0, C= 0; B= 1; A= 1; O/P= 3 E= 0, D= 0, C= 1; B= 0; A= 0; O/P= 4 E= 0, D= 0, C= 1; B= 0; A= 1; O/P= 5

E= 0, D= 0, C= 1; B= 1; A= 0; O/P= 6 E= 0, D= 0, C= 1; B= 1; A= 1; O/ = 7 E= 0, D= 1, C= 0; B= 0; A= 0; O/P= 8

E= 0, D= 1, C = 0; B = 0; A = 1; O/P = 9 E= 0, D= 1, C= 0; B= 1; A= 0; O/P= 10 E= 0, D= 1, C= 0; B= 1; A= 1; O/P= 11

E= 0, D= 1, C= 1; B= 0; A= 0; O/P= 12 E= 0, D= 1, C= 1; B= 0; A= 1; O/P= 13 E= 0, D= 1, C= 1; B= 1; A= 0; O/P= 14


E= 0, D= 1, C= 1; B= 1; A= 1; O/P= 15 E= 1, D= 0, C= 0; B= 0; A= 0; O/P= 16 E= 0, D= 0, C= 0; B= 0; A= 1; O/P= 17

Truth Table

Clock Pulse E D C B A Decimal


No.
0 0 0 0 0 0 0
1 0 0 0 0 1 1
2 0 0 0 1 0 2
3 0 0 0 1 1 3
4 0 0 1 0 0 4
5 0 0 1 0 1 5
6 0 0 1 1 0 6
7 0 0 1 1 1 7
8 0 1 0 0 0 8
9 0 1 0 0 1 9
10 0 1 0 1 0 10
11 0 1 0 1 1 11
12 0 1 1 0 0 12
13 0 1 1 0 1 13
14 0 1 1 1 0 14
15 0 1 1 1 1 15
16 1 0 0 0 0 16
17 0 0 0 0 0 0

Discussion

For the 5-bit Up Counter, we connected 5 J-K flip flops. Each Flip flop has a different clock input signal. After the
first Flip flop, each Flip flop’s clock input is the previous Flip flop’s Q̅ output. Keeping all J, K, PRESET and CLEAR
inputs of all Flip flops high, we connect a clock input with an NGT Edge Detector with the first Flip flop and
watch the outputs change accordingly. The outputs match with the truth table after each clock pulse
sequentially.
For the modified asynchronous 5-bit MOD-18 counter, we kept the same J-K Flip flops connected with an NGT
clock input just like the 5-bit Up Counter. The only difference is that we connected a NAND gate’s input with the
Q outputs of the 1st and 5th Flip flop and the NAND gate’s output with the CLEAR inputs of all Flip flops. As a
result, the outputs again the matched the truth table values sequentially up to 16 (1 0 0 0 0).

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