CHAPTER - 2

8051 MICROCONTROLLER

By
Mr. Sandeep Chintoju
 CHAPTER 2
 The 8051 Architecture
 8051 Microcontroller -
Pin Diagram
 Input/output Ports
(P0, P1, P2, P3)
 Memory Organization
 Counter and Timers
(TMOD, TCON)
 Serial data
Input/output
(SMOD, SCON, PCON)
 Interrupts
(IE, IP)
 Brief History of 8051
• The first microprocessor 4004 was invented by Intel
Corporation. 8085 and 8086 microprocessors were also
invented by Intel.
• In 1981, Intel introduced an 8-bit microcontroller called
the 8051.
• It was referred as system on a chip because it had 128
bytes of RAM, 4K byte of on-chip ROM, two timers, one
serial port, and 4 ports (8-bit wide), all on a single chip.
• When it became widely popular, Intel allowed other
manufacturers to make and market different flavors of
8051 with its code compatible with 8051.
• It means that if you write your program for one flavor of
8051, it will run on other flavors too, regardless of the
manufacturer.
• This has led to several versions with different speeds and
amounts of on-chip RAM.
 MICROCONTROLLER – 8051
 Intel introduced 8051, referred as MCS-51, in
1981
 The 8051 is an 8-bit microcontroller
ƒThe CPU can work on only 8 bits of data at a
time.
 The 8051 had
ƒ 128 bytes of on-chip RAM
ƒ 4K bytes of on-chip ROM
ƒ Two timers
ƒ One serial port
ƒ Four I/O ports, each 8 bits wide
ƒ 5 interrupt sources
Various 8051 Microcontrollers
Various 8051 Microcontrollers (cont’)
 Block Diagram of 8051 MC

External interrupts

On-chip Timer/Counter

Interrupt ROM for

On-chip Timer 1 Counter
Control program
RAM Timer 0 Inputs
code

CPU

Bus Serial
4 I/O Ports
OSC Control Port

P0 P1 P2 P3 TxD RxD
Address/Data
 Features of 8051 Microcontroller
An 8051 microcontroller comes bundled with the following features
• 4KB bytes on-chip program memory (ROM)
• 128 bytes on-chip data memory (RAM)
• Four register banks (RB0, RB1, RB2, RB3)
• 8-bit bidirectional data bus
• 16-bit unidirectional address bus
• 32 general purpose registers + A reg + B reg each of 8-bit
• Two 16 bit Timers (T0 & T1)
• Five Six Interrupts (Three internal + two external Interrupts +
RESET)
• Four 8-bit ports (P0, P1, P2, P3)
• 16-bit program counter (PC) and 16-bit data pointer (DPTR)
• Full Duplex serial data transmitter and receiver (SBUF)
• Control registers (TMOD, TCON, SCON, PCON, IE, IP)
• The system bus connects all the support
devices to the CPU.
• The system bus consists of an 8-bit data bus, a
16-bit address bus and bus control signals.
• All other devices like program memory, ports,
data memory, serial interface, interrupt
control, timers, and the CPU are all interfaced
together through the system bus.
Architecture of 8051 MC
8051 Pin Diagram
 Pin Description of 8051

• Pins 1 to 8 − These 8-pins are

known as Port 1 and used for i/p or
o/p.
• Pin 9 − It is a RESET pin, which is
used to reset the microcontroller to
its initial values.
• Pins 10 to 17 − These 8-pins are
known as Port 3. This port is used
for i/p or o/p and serves some
special functions like interrupts,
timer input, control signals, serial
communication signals RxD and TxD,
etc.
 RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.
Port 3 has the additional function of providing some extremely
important signals

P3 Bit Function Pin

P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
Pin Description of 8051 (cont’)

• Pins 18 & 19 − These pins are

used for interfacing an external
crystal oscillator to get the system
clock.
• Pin 20 − GND
• Pins 21 to 28 − These pins are
known as Port 2. It serves as I/O
port. These lines provide higher
order address bus byte (A8-A15)
through which 8051 can access
64K bytes.
 XTAL Connection to 8051
Using a quartz crystal oscillator
We can observe the frequency on the XTAL2 pin.

C2
XTAL2
30pF

C1
XTAL1
30pF

GND
Pin Description of 8051 (cont’)

• Pin 29 − This is PSEN o/p pin which stands for

Program Store Enable. It is used to access the
external program memory (ROM).
• Pin 31 − This is EA pin which stands for External
Access input. It is used to enable/disable the
external memory interfacing.
If EA = 0 –> Only external 64KB is accessed by PC
If EA = 1 –> 4KB of internal ROM and 60KB of
external ROM will be accessed
• Pin 30 − This is ALE pin which stands for Address
Latch Enable. It is used to de-multiplex the
address-data signal of port 0.
If ALE = 0 –> Port-0 has data D0-D7
If ALE = 1 –> Port-0 has address A0-A7
Pin Description of 8051 (cont’)

• Pins 32 to 39 − These pins are

known as Port 0. It serves as I/O
port. Lower order address and
data bus signals (AD0 –AD7) are
multiplexed using this port.
• Pin 40 − (Vcc)This pin is used to
provide power supply to the
circuit.
 Registers

A
B
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R4 8051 16-bit Register
R5
R6
R7
Some 8-bit
Registers of the
8051
MEMORY ORGANIZATION
 ROM Memory mapping in 8051

4K Bytes
• 8051 has 4K bytes of ROM
0000H
• This is used for storing the program
code
0FFFH
• It is also known as program memory
8751
ranging from 0000H to FFFFH AT89C51
• This memory is accessed by “program
counter”
• EA pin which stands for External Access input.
• EA is used to enable/disable the external memory
interfacing.
If EA = 0 –> Only external 64KB is accessed by PC
If EA = 1 –> 4KB of internal RAM and 60KB of
external ROM will be accessed
0000H 0000H
ON CHIP
ROM (4KB)
0FFFH
OFF CHIP
1000H
ROM
(64 KB) OFF CHIP
ROM
(60 KB)
FFFFH FFFFH

If EA = 0 If EA = 1
 128 Bytes RAM memory space allocation in the 8051
7FH

For general 80 bytes

purpose data
memory Scratch pad RAM

30H
2FH
Addressable at Bit-Addressable RAM
16 bytes
bit level
20H
1FH
8 bytes Register Bank 3
18H
4 Register Banks 17H
each containing 8 bytes Register Bank 2
10H
8 registers 0FH
(R0 – R7 each of 8 bytes Register Bank 1 (Stack)
08H
8 bits) 07H 8 bytes Register Bank 0
00H
Internal RAM Organization
Bit Addressable RAM
 Processor Status Word (PSW)
• Processor Status Word (PSW) register is an 8-
bit register, it is also referred to as the flag
register.
8051 Timers/Counters
TMOD Register
 TMOD is not bit addressable register
the lower two bits (M0, M1) are used to set the timer mode
the upper two bits (GATE, C/T’) are used to specify operation

13 – bit timer mode

16 – bit timer mode

Gate = 1 -> enables 8 – bit auto reload mode

timers by H/W
Split Timer mode
Gate = 0 -> enables
timers by S/W Counter/Timer’ = 1 -> Timer 1/0 acts as a
counter by counting pulses from external
input pins;
Counter/Timer = 0 -> timer operation
 TCON (Timer Control) register
• TCON (timer control) register is an 8- bit
register.
• It is a bit addressable register.

Timer overflow (TF)

and Timer run (TR)
bits of both TR0 and
TR1
• TF1 : Timer-1 over flow flag bit
Set to 1 when timer-1 rolls from all 1’s to 0’s
• TR1: Timer-1 Run Control bit
Set to 1 by program to start timer-1 . Cleared to stop timer-1
• TF0 : Timer-0 over flow flag bit
Set to 1 when timer-0 rolls from all 1’s to 0’s
• TR0: Timer-0 Run Control bit
Set to 1 by program to start timer-1 . Cleared to stop timer-1
• IE1: External Interrupt-1 edge flag bit
Set to 1 when a high to low external interrupt edge signal is on P3.3 (INT1)
• IT1: External Interrupt-1 control bit
– Set to 1 by program to enable external interrupt-1
• IE0: External Interrupt-0 edge flag bit
Set to 1 when a high to low external interrupt edge signal is on P3.2 (INT0)
• IT0: External Interrupt-0 control bit
Set to 1 by program to enable external interrupt-0
• TCON register is a bit-addressable register
 Serial Data Input/Output
• The 8051 has a serial data communication
circuit that uses:
• SBUF register to hold data
• SCON to control data communication
• PCON to control data rates
• Pins RXD and TXD are connected to serial data
network to receive and transmit serial data.
SBUF: Serial Buffer Register
It is used to hold data to be transmitted
and data which is received.
 SCON register

Transmit interrupt flag bit

Receive interrupt flag bit

• REN: Receive Enable Bit:
Set to ‘1’ to enable reception
Cleared to ‘0’ to disable reception on RxD pin
• TI: Transmit Interrupt Flag bit
When 8051 finished the transfer of a 8-bit character, it
raises the TI flag to indicate that it is ready to transfer
another byte.
• RI: Receive Interrupt flag bit
The 8051 raises the RI flag to indicate that a byte has
been received and it should be picked up before it is
lost
 PCON Register
PCON Register is used to control the baud rate of
serial data transmission

SMOD BIT
 INTERRUPTS
• An interrupt is an external or internal event that interrupts the
microcontroller to inform it that a device needs its service.
• The 8051 has six interrupts based on manufacturers data sheet.
They are:
1) RESET (pin 9)
2) Two from the timer/counter overflow flags (TF0 & TF1)
3) Two from external interrupt inputs (INT0 & INT1)
P3.2 and P3.3 are for the external hardware interrupts INT0
and INT1
4) One from serial port (TI/RI) for transfer or receive (Serial
communication has a single interrupt that belongs to both receive
and transfer)
Six Interrupts in 8051 - IVT
• A single microcontroller can serve several
devices by two ways:
1) Interrupts method and
2) Polling method
• Polling method

• The microcontroller continuously monitors the status of a

given device.
• When the conditions met, it performs the service.
• After that, it moves on to monitor the next device until
every one is serviced.
• The polling method is not efficient, since it wastes much of
the microcontroller’s time by polling devices that do not
needs service.
• Interrupts method:
Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal

ƒ Upon receiving an interrupt signal, the microcontroller

interrupts whatever it is doing and serves the device

ƒThe program which is associated with the interrupt is called

the interrupt service routine (ISR) or interrupt handler
 Interrupt registers f 8051
• Based on the enable or disable of an interrupt
and priority of interrupt, it is classified into
two registers:
• IE register – Interrupt Enable register
• IP register – Interrupt Priority register
 IE register
• IE (interrupt enable) is responsible for enabling
(unmasking) and disabling (masking) the interrupts
IP (INTERRUPT PRIORITY) REGISTER
 IP (INTERRUPT PRIORITY) REGISTER
Lowest Highest
Priority Priority
• We can alter the sequence of interrupt priority by
assigning a higher priority to any one of the
interrupts by programming a register called IP
(interrupt priority).
• To give a higher priority to any of the interrupts,
we make the corresponding bit in the IP register
high
• When two or more interrupt bits in the IP register
are set to high. While these interrupts have a
higher priority than others, they are serviced
according to the sequence of Table provided in
the previous slide.