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MX RT1170 Processor Reference
Manual
Document Number: IMXRT1170RM
Rev. 1, 05/2021
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About this Document
1.1 Audience....................................................................................................................................................................... 27
1.2 Organization..................................................................................................................................................................27
1.3 Suggested Reading........................................................................................................................................................27
1.4 Conventions.................................................................................................................................................................. 28
1.5 Register Access.............................................................................................................................................................30
1.6 Acronyms and Abbreviations....................................................................................................................................... 32
Chapter 2
Introduction
2.1 Introduction...................................................................................................................................................................37
2.2 Features......................................................................................................................................................................... 39
2.3 Target Applications.......................................................................................................................................................42
2.4 Endianness Support.......................................................................................................................................................43
Chapter 3
Memory Maps
3.1 Memory system overview.............................................................................................................................................45
3.2 System memory map (CM7).........................................................................................................................................45
3.3 System memory map (CM4).........................................................................................................................................47
3.4 AIPS-1 Memory Map................................................................................................................................................... 48
3.5 AIPS-2 Memory Map................................................................................................................................................... 52
3.6 AIPS-3 Memory Map................................................................................................................................................... 54
3.7 AIPS-4 Memory Map................................................................................................................................................... 54
3.8 AIPS M7 Memory Map................................................................................................................................................ 56
3.9 PPB M7 Memory Map .................................................................................................................................................56
3.10 PPB M4 Memory Map .................................................................................................................................................57
Chapter 4
Interrupts, DMA Events, and XBAR Assignments
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4.1 Overview.......................................................................................................................................................................59
4.2 CM7 interrupts.............................................................................................................................................................. 59
4.3 CM4 interrupts.............................................................................................................................................................. 74
4.4 DMA Mux.....................................................................................................................................................................88
4.5 PIT Channel Assignments For Periodic DMA Triggering........................................................................................... 102
4.6 XBAR Resource Assignments......................................................................................................................................102
Chapter 5
Direct Memory Access Multiplexer (DMAMUX)
5.1 Chip-specific DMAMUX information......................................................................................................................... 119
5.2 Overview.......................................................................................................................................................................119
5.3 Functional description...................................................................................................................................................121
5.4 External signals.............................................................................................................................................................126
5.5 Application information................................................................................................................................................126
5.6 Initialization.................................................................................................................................................................. 129
5.7 Memory map/register definition................................................................................................................................... 129
Chapter 6
Enhanced Direct Memory Access (eDMA)
6.1 Chip-specific eDMA information................................................................................................................................. 133
6.2 Overview.......................................................................................................................................................................133
6.3 Functional description...................................................................................................................................................137
6.4 Initialization/application information........................................................................................................................... 143
6.5 Memory map/register definition................................................................................................................................... 158
Chapter 7
System Security
7.1 Chapter overview.......................................................................................................................................................... 221
7.2 Feature summary...........................................................................................................................................................221
7.3 Resource Management..................................................................................................................................................224
7.4 Secure Key Manager (KEYMGR)................................................................................................................................224
7.5 High-Assurance Boot (HAB)........................................................................................................................................225
7.6 Secure Non-Volatile Storage (SNVS) module............................................................................................................. 228
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7.7 Cryptographic Acceleration and Assurance Module (CAAM).................................................................................... 230
7.8 On-Chip OTP Controller (OCOTP_CTRL)..................................................................................................................231
7.9 Debug............................................................................................................................................................................232
7.10 Inline Encryption Engine (IEE).................................................................................................................................... 234
7.11 On-the-Fly AES Decryption (OTFAD)........................................................................................................................ 235
Chapter 8
System Debug
8.1 Overview.......................................................................................................................................................................237
8.2 Chip and Arm Platform Debug Architecture................................................................................................................ 237
8.3 Miscellaneous............................................................................................................................................................... 245
Chapter 9
JTAG Controller (JTAGC)
9.1 Chip-specific JTAG information.................................................................................................................................. 247
9.2 Overview.......................................................................................................................................................................247
9.3 Functional description...................................................................................................................................................248
9.4 External signal description............................................................................................................................................257
9.5 Initialization/application information........................................................................................................................... 258
9.6 Register description...................................................................................................................................................... 258
Chapter 10
System Boot
10.1 Chip-specific Boot Information.................................................................................................................................... 263
10.2 Overview.......................................................................................................................................................................271
10.3 Boot modes................................................................................................................................................................... 273
10.4 Device configuration.....................................................................................................................................................277
10.5 Device initialization...................................................................................................................................................... 279
10.6 Boot devices..................................................................................................................................................................282
10.7 Program image.............................................................................................................................................................. 327
10.8 External Memory Configuration Data (XMCD)...........................................................................................................335
10.9 Serial Boot (Serial Downloader)...................................................................................................................................345
10.10 Recovery devices.......................................................................................................................................................... 358
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10.11 SD/MMC manufacture mode........................................................................................................................................359
10.12 High-Assurance Boot (HAB)........................................................................................................................................359
10.13 ROM APIs.................................................................................................................................................................... 361
Chapter 11
External Signals and Pin Multiplexing
11.1 Overview.......................................................................................................................................................................373
Chapter 12
IOMUX Controller (IOMUXC)
12.1 Chip-specific IOMUXC information............................................................................................................................451
12.2 Overview.......................................................................................................................................................................451
12.3 Functional description...................................................................................................................................................453
12.4 Memory Map and register definition............................................................................................................................ 456
Chapter 13
General Purpose Input/Output (GPIO)
13.1 Chip-specific GPIO information...................................................................................................................................1399
13.2 Overview.......................................................................................................................................................................1399
13.3 Functional Description..................................................................................................................................................1401
13.4 External Signals............................................................................................................................................................ 1409
13.5 Application Information................................................................................................................................................1409
13.6 GPIO register descriptions............................................................................................................................................1410
Chapter 14
Clock and Power Management
14.1 Introduction...................................................................................................................................................................1429
14.2 Components of Clock and Power Management............................................................................................................1429
14.3 Power Management...................................................................................................................................................... 1430
14.4 Clock Generation.......................................................................................................................................................... 1440
Chapter 15
Clock Controller Module (CCM)
15.1 Chip-specific CCM information................................................................................................................................... 1449
15.2 Overview.......................................................................................................................................................................1449
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15.3 System Clocks...............................................................................................................................................................1451
15.4 Clock Tree.....................................................................................................................................................................1467
15.5 Functional description...................................................................................................................................................1473
15.6 External Signals............................................................................................................................................................ 1508
15.7 Analog IP (AI) Interface............................................................................................................................................... 1508
15.8 Programming Guidelines.............................................................................................................................................. 1510
15.9 Memory Map and register definition............................................................................................................................ 1513
Chapter 16
Crystal Oscillator (XTALOSC)
16.1 Chip-specific XTALOSC information..........................................................................................................................1675
16.2 Overview.......................................................................................................................................................................1675
16.3 Functional Description..................................................................................................................................................1676
16.4 External Signals............................................................................................................................................................ 1679
16.5 Memory Map and register definition............................................................................................................................ 1680
Chapter 17
Power Management Unit (PMU)
17.1 Chip-specific PMU information................................................................................................................................... 1701
17.2 Overview.......................................................................................................................................................................1701
17.3 Functional Description..................................................................................................................................................1702
17.4 External Signals............................................................................................................................................................ 1708
17.5 Memory Map and register definition............................................................................................................................ 1708
Chapter 18
PHY LDO (PHY_LDO)
18.1 Chip-specific PHY LDO information...........................................................................................................................1789
18.2 Overview.......................................................................................................................................................................1789
18.3 Memory Map and register definition............................................................................................................................ 1790
Chapter 19
General Power Controller (GPC)
19.1 Chip-specific General Power Controller (GPC) information....................................................................................... 1795
19.2 Overview.......................................................................................................................................................................1795
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19.3 Functional description...................................................................................................................................................1797
19.4 External Signals............................................................................................................................................................ 1805
19.5 Initialization.................................................................................................................................................................. 1805
19.6 Memory Map and register definition............................................................................................................................ 1806
Chapter 20
Power Gating and Memory Controller (PGMC)
20.1 Chip-specific Power Gating and Memory Controller (PGMC) information................................................................ 1935
20.2 Overview.......................................................................................................................................................................1935
20.3 Functional description...................................................................................................................................................1937
20.4 External Signals............................................................................................................................................................ 1942
20.5 Initialization.................................................................................................................................................................. 1942
20.6 Memory Map and register definition............................................................................................................................ 1943
Chapter 21
DCDC Converter (DCDC)
21.1 Chip-specific DCDC information................................................................................................................................. 1983
21.2 Overview.......................................................................................................................................................................1983
21.3 Functional description...................................................................................................................................................1985
21.4 External Signals............................................................................................................................................................ 1989
21.5 Initialization.................................................................................................................................................................. 1989
21.6 Application Information................................................................................................................................................1990
21.7 Memory Map and register definition............................................................................................................................ 1993
Chapter 22
Temperature Sensor (TMPSNS)
22.1 Chip-specific TMPSNS information.............................................................................................................................2031
22.2 Overview.......................................................................................................................................................................2031
22.3 Functional description...................................................................................................................................................2032
22.4 External Signals............................................................................................................................................................ 2034
22.5 Initialization.................................................................................................................................................................. 2034
22.6 Application Information................................................................................................................................................2034
22.7 Memory Map and register definition............................................................................................................................ 2035
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Chapter 23
State Save and Restore Controller (SSARC)
23.1 Chip-specific State Save and Restore Controller (SSARC) information......................................................................2049
23.2 Overview.......................................................................................................................................................................2049
23.3 Functional description...................................................................................................................................................2050
23.4 External Signals............................................................................................................................................................ 2053
23.5 Initialization.................................................................................................................................................................. 2053
23.6 Memory Map and register definition............................................................................................................................ 2053
Chapter 24
Secure Non-Volatile Storage (SNVS)
24.1 Chip-specific SNVS information..................................................................................................................................2071
24.2 Overview.......................................................................................................................................................................2071
24.3 SNVS functional description........................................................................................................................................ 2073
24.4 External Signals............................................................................................................................................................ 2078
24.5 Initialization of SNVS...................................................................................................................................................2079
24.6 Memory Map and register definition............................................................................................................................ 2080
Chapter 25
System Reset Controller (SRC)
25.1 Chip-specific SRC information.....................................................................................................................................2107
25.2 Overview.......................................................................................................................................................................2107
25.3 Functional Description..................................................................................................................................................2108
25.4 External Signals............................................................................................................................................................ 2117
25.5 Initialization.................................................................................................................................................................. 2117
25.6 Memory Map and register definition............................................................................................................................ 2118
Chapter 26
Fusemap
26.1 Overview.......................................................................................................................................................................2141
26.2 Boot Fusemap............................................................................................................................................................... 2143
26.3 Fusemap Descriptions Table.........................................................................................................................................2152
26.4 FlexRAM Partition Table............................................................................................................................................. 2156
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Chapter 27
On-Chip OTP Controller (OCOTP_CTRL)
27.1 Chip-specific OCOTP_CTRL information...................................................................................................................2159
27.2 Overview.......................................................................................................................................................................2159
27.3 Functional Description..................................................................................................................................................2161
27.4 External Signals............................................................................................................................................................ 2167
27.5 Fuse Map.......................................................................................................................................................................2167
27.6 Memory Map/Register Definition.................................................................................................................................2167
Chapter 28
External Memory Controllers
28.1 Overview.......................................................................................................................................................................2195
28.2 Smart External Memory Controller (SEMC) Overview...............................................................................................2195
28.3 eMMC/eSD/SDIO.........................................................................................................................................................2196
28.4 Flexible Serial Peripheral Interface.............................................................................................................................. 2196
Chapter 29
Smart External Memory Controller (SEMC)
29.1 Chip-specific SEMC information................................................................................................................................. 2199
29.2 Overview.......................................................................................................................................................................2199
29.3 Functional Description..................................................................................................................................................2202
29.4 External Signals............................................................................................................................................................ 2250
29.5 Initialization.................................................................................................................................................................. 2255
29.6 Application Information................................................................................................................................................2255
29.7 Memory Map and Register Definition..........................................................................................................................2257
Chapter 30
FlexSPI Controller (FLEXSPI)
30.1 Chip-specific FlexSPI information............................................................................................................................... 2331
30.2 Overview.......................................................................................................................................................................2334
30.3 Functional description...................................................................................................................................................2336
30.4 External Signals............................................................................................................................................................ 2394
30.5 Initialization.................................................................................................................................................................. 2395
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30.6 Application information................................................................................................................................................2396
30.7 Memory Map and register definition............................................................................................................................ 2414
30.8 AHB Memory Map definition...................................................................................................................................... 2490
Chapter 31
External ECC Controller (XECC)
31.1 Chip-specific XECC information................................................................................................................................. 2493
31.2 Overview.......................................................................................................................................................................2493
31.3 Functional description...................................................................................................................................................2495
31.4 External Signals............................................................................................................................................................ 2499
31.5 Initialization.................................................................................................................................................................. 2499
31.6 Memory Map and register definition............................................................................................................................ 2499
Chapter 32
Ultra Secured Digital Host Controller (uSDHC)
32.1 Chip-specific uSDHC information............................................................................................................................... 2525
32.2 Overview.......................................................................................................................................................................2525
32.3 Functional description...................................................................................................................................................2528
32.4 External signals.............................................................................................................................................................2561
32.5 Application of uSDHC..................................................................................................................................................2562
32.6 Software restrictions..................................................................................................................................................... 2588
32.7 uSDHC memory map/register definition...................................................................................................................... 2590
Chapter 33
ARM Cortex M7 Platform (M7)
33.1 Chip-specific Arm Cortex M7 information.................................................................................................................. 2665
33.2 Overview.......................................................................................................................................................................2667
33.3 Functional Description..................................................................................................................................................2668
33.4 External Signals............................................................................................................................................................ 2669
33.5 Memory Map and register definition............................................................................................................................ 2669
Chapter 34
ARM Cortex M4 Platform (M4)
34.1 Chip-specific Arm Cortex M4 information.................................................................................................................. 2673
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34.2 Overview.......................................................................................................................................................................2674
34.3 Configuration................................................................................................................................................................ 2676
34.4 Performance.................................................................................................................................................................. 2676
34.5 Platform sub-blocks...................................................................................................................................................... 2677
34.6 Debug............................................................................................................................................................................2679
34.7 Local Memory Controller (LMEM)..............................................................................................................................2681
34.8 Miscellaneous Control Module (MCM)....................................................................................................................... 2706
34.9 MCM Memory Map/Register Definition......................................................................................................................2707
Chapter 35
Messaging Unit (MU)
35.1 Chip-specific MU information......................................................................................................................................2731
35.2 Overview.......................................................................................................................................................................2731
35.3 Functional Description..................................................................................................................................................2733
35.4 External Signals............................................................................................................................................................ 2745
35.5 Initialization.................................................................................................................................................................. 2745
35.6 Application Information................................................................................................................................................2746
35.7 MU Processor A-side Memory Map/Register Definition.............................................................................................2748
35.8 MU Processor B-side Memory Map/Register Definition............................................................................................. 2762
Chapter 36
Network Interconnect Bus System (NIC-301)
36.1 Chip-specific NIC-301 information..............................................................................................................................2777
36.2 Overview ......................................................................................................................................................................2777
36.3 External Signals............................................................................................................................................................ 2778
36.4 Memory Map and Register Definition..........................................................................................................................2778
Chapter 37
On-Chip RAM Memory Controller (OCRAM)
37.1 Chip-specific OCRAM information............................................................................................................................. 2785
37.2 Overview.......................................................................................................................................................................2785
37.3 Functional Description..................................................................................................................................................2787
37.4 Programmable Registers............................................................................................................................................... 2789
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Chapter 38
MECC64
38.1 Chip-specific MECC information.................................................................................................................................2791
38.2 Overview.......................................................................................................................................................................2791
38.3 Functional description...................................................................................................................................................2793
38.4 Signals...........................................................................................................................................................................2795
38.5 Initialization.................................................................................................................................................................. 2796
38.6 Application information................................................................................................................................................2796
38.7 Memory Map and register definition............................................................................................................................ 2796
Chapter 39
FlexRAM
39.1 Chip-specific FlexRAM information............................................................................................................................2821
39.2 Overview.......................................................................................................................................................................2822
39.3 Functional description...................................................................................................................................................2824
39.4 Memory Map and Register Definition..........................................................................................................................2830
Chapter 40
AHB to IP Bridge (AIPS Lite)
40.1 Chip-specific AIPS Lite information............................................................................................................................ 2879
40.2 Overview.......................................................................................................................................................................2879
40.3 Functional Description..................................................................................................................................................2879
40.4 Memory Map/Register Definition ................................................................................................................................2880
Chapter 41
Semaphores (SEMA4)
41.1 Chip-specific SEMA4 information............................................................................................................................... 2881
41.2 Overview.......................................................................................................................................................................2881
41.3 Functional Description..................................................................................................................................................2883
41.4 External Signal Description.......................................................................................................................................... 2888
41.5 Initialization Information.............................................................................................................................................. 2888
41.6 Application Information................................................................................................................................................2888
41.7 Memory map and register definition.............................................................................................................................2890
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Chapter 42
Resource Domain Controller (RDC)
42.1 Chip-specific RDC information....................................................................................................................................2901
42.2 Overview.......................................................................................................................................................................2901
42.3 Functional Description .................................................................................................................................................2903
42.4 External Signals............................................................................................................................................................ 2909
42.5 Programming Interface................................................................................................................................................. 2910
42.6 RDC Memory Map/Register Definition....................................................................................................................... 2917
42.7 RDC SEMA42 Memory Map/Register Definition....................................................................................................... 2936
Chapter 43
Extended Resource Domain Controller 2 (XRDC2)
43.1 Chip-specific XRDC2 information............................................................................................................................... 2945
43.2 Overview.......................................................................................................................................................................2955
43.3 Functional description...................................................................................................................................................2957
43.4 External Signals............................................................................................................................................................ 2964
43.5 Initialization.................................................................................................................................................................. 2964
43.6 Application information................................................................................................................................................2964
43.7 Memory Map and register definition............................................................................................................................ 2965
Chapter 44
Display And Camera Overview
44.1 Overview.......................................................................................................................................................................2989
Chapter 45
CMOS Sensor Interface (CSI)
45.1 Chip-specific CSI information......................................................................................................................................2995
45.2 Overview.......................................................................................................................................................................2995
45.3 Functional Description..................................................................................................................................................2997
45.4 External Signals............................................................................................................................................................ 3017
45.5 Initialization.................................................................................................................................................................. 3017
45.6 CSI Memory Map/Register Definition......................................................................................................................... 3017
Chapter 46
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MIPI CSI2 (MIPI_CSI2)
46.1 Chip-specific MIPI CSI-2 information......................................................................................................................... 3055
46.2 Overview.......................................................................................................................................................................3055
46.3 Functional description...................................................................................................................................................3058
46.4 External Signals............................................................................................................................................................ 3070
46.5 Initialization.................................................................................................................................................................. 3070
46.6 Memory Map and register definition............................................................................................................................ 3071
Chapter 47
Enhanced LCD Interface (eLCDIF)
47.1 Chip-specific eLCDIF information...............................................................................................................................3095
47.2 Overview.......................................................................................................................................................................3095
47.3 Functional Description..................................................................................................................................................3097
47.4 External Signals............................................................................................................................................................ 3114
47.5 Initialization.................................................................................................................................................................. 3114
47.6 eLCDIF Memory Map/Register Definition.................................................................................................................. 3115
Chapter 48
LCDIF Interface v2 (LCDIF v2)
48.1 Chip-specific LCDIFv2 information.............................................................................................................................3145
48.2 Overview.......................................................................................................................................................................3145
48.3 Functional description...................................................................................................................................................3148
48.4 External Signals............................................................................................................................................................ 3155
48.5 Application information................................................................................................................................................3155
48.6 Memory Map and register definition............................................................................................................................ 3156
Chapter 49
MIPI DSI Host Controller (MIPI_DSI)
49.1 Chip-specific MIPI DSI information............................................................................................................................ 3187
49.2 Overview.......................................................................................................................................................................3187
49.3 Functional description...................................................................................................................................................3190
49.4 External Signals ........................................................................................................................................................... 3210
49.5 Application Information................................................................................................................................................3211
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49.6 Initialization.................................................................................................................................................................. 3211
49.7 Memory Map and register definition............................................................................................................................ 3212
Chapter 50
Video Mux Controller (VIDEO_MUX)
50.1 Chip-specific VIDEO MUX information..................................................................................................................... 3279
50.2 Overview.......................................................................................................................................................................3279
50.3 Functional description...................................................................................................................................................3281
50.4 External Signals............................................................................................................................................................ 3282
50.5 Initialization.................................................................................................................................................................. 3283
50.6 Memory Map and register definition............................................................................................................................ 3283
Chapter 51
Display Content Integrity Checker (DCIC)
51.1 Chip-specific DCIC information...................................................................................................................................3291
51.2 Overview.......................................................................................................................................................................3291
51.3 Functional Description..................................................................................................................................................3292
51.4 External Signals............................................................................................................................................................ 3296
51.5 System Considerations..................................................................................................................................................3296
51.6 DCIC Memory Map/Register Definition...................................................................................................................... 3297
Chapter 52
Pixel Pipeline (PXP)
52.1 Chip-specific PXP information.....................................................................................................................................3309
52.2 Overview.......................................................................................................................................................................3309
52.3 Functional Description..................................................................................................................................................3310
52.4 External Signals............................................................................................................................................................ 3345
52.5 Initialization.................................................................................................................................................................. 3345
52.6 PXP Memory Map/Register Definition........................................................................................................................ 3345
Chapter 53
Graphics Processing Unit (GPU2D)
53.1 Chip-specific GPU information.................................................................................................................................... 3383
53.2 Overview.......................................................................................................................................................................3383
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53.3 Functional description...................................................................................................................................................3385
53.4 Software Application Programming Interface (API)....................................................................................................3386
Chapter 54
Audio Overview
54.1 Audio Overview............................................................................................................................................................3389
Chapter 55
Asynchronous Sample Rate Converter (ASRC)
55.1 Chip-specific Asynchronous Sample Rate Converter (ASRC) information.................................................................3397
55.2 Overview.......................................................................................................................................................................3398
55.3 Functional Description..................................................................................................................................................3401
55.4 External Signals............................................................................................................................................................ 3410
55.5 Application Information................................................................................................................................................3411
55.6 ASRC Memory Map/Register Definition..................................................................................................................... 3412
Chapter 56
PDM Microphone Interface (PDM)
56.1 Chip-specific PDM Microphone Interface (PDM) information................................................................................... 3465
56.2 Overview.......................................................................................................................................................................3465
56.3 Functional Description..................................................................................................................................................3467
56.4 External Signals............................................................................................................................................................ 3484
56.5 Initialization.................................................................................................................................................................. 3485
56.6 Application Information................................................................................................................................................3489
56.7 PDM register descriptions.............................................................................................................................................3489
Chapter 57
Medium Quality Sound (MQS)
57.1 Chip-specific MQS information................................................................................................................................... 3515
57.2 Overview.......................................................................................................................................................................3515
57.3 Functional Description..................................................................................................................................................3516
57.4 External Signals............................................................................................................................................................ 3517
57.5 Application Information................................................................................................................................................3518
Chapter 58
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Synchronous Audio Interface (SAI)
58.1 Chip-specific SAI information......................................................................................................................................3519
58.2 Overview.......................................................................................................................................................................3520
58.3 Functional description...................................................................................................................................................3522
58.4 External signals.............................................................................................................................................................3533
58.5 Memory map and register definition.............................................................................................................................3533
Chapter 59
Sony/Philips Digital Interface (SPDIF)
59.1 Chip-specific SPDIF information................................................................................................................................. 3571
59.2 Overview.......................................................................................................................................................................3571
59.3 Functional Description..................................................................................................................................................3573
59.4 External Signals............................................................................................................................................................ 3583
59.5 Application Information................................................................................................................................................3584
59.6 SPDIF Memory Map/Register Definition.....................................................................................................................3585
Chapter 60
10/100 /1000 -Mbps Ethernet MAC (ENET/ENET1G)
60.1 Chip-specific ENET information..................................................................................................................................3611
60.2 Overview.......................................................................................................................................................................3611
60.3 Functional description...................................................................................................................................................3616
60.4 External Signals............................................................................................................................................................ 3682
60.5 Memory map/register definition................................................................................................................................... 3684
Chapter 61
Ethernet Quality Of Service (ENET_QOS)
61.1 Chip-specific ENET QOS information.........................................................................................................................3823
61.2 Overview.......................................................................................................................................................................3823
61.3 Functional Description..................................................................................................................................................3825
61.4 External signals.............................................................................................................................................................3974
61.5 Initialization.................................................................................................................................................................. 3978
61.6 Application Information................................................................................................................................................3981
61.7 Memory Map and register definition............................................................................................................................ 4002
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Chapter 62
Universal Serial Bus Controller (USB)
62.1 Chip-specific USB information.................................................................................................................................... 4873
62.2 Overview.......................................................................................................................................................................4873
62.3 Functional Description..................................................................................................................................................4875
62.4 External Signals............................................................................................................................................................ 4880
62.5 USB Operation Model.................................................................................................................................................. 4880
62.6 USB Non-Core Memory Map/Register Definition.......................................................................................................5047
62.7 USB Core Memory Map/Register Definition............................................................................................................... 5053
Chapter 63
Universal Serial Bus 2.0 Integrated PHY (USB-PHY)
63.1 Chip-specific USB-PHY information........................................................................................................................... 5141
63.2 Overview.......................................................................................................................................................................5141
63.3 Functional Description..................................................................................................................................................5142
63.4 External Signals............................................................................................................................................................ 5149
63.5 Initialization and Application Information................................................................................................................... 5149
63.6 Recommended Register Configuration for USB Certification..................................................................................... 5149
63.7 Register Macro Usage...................................................................................................................................................5150
63.8 USB PHY Memory Map/Register Definition...............................................................................................................5151
Chapter 64
USB Device Charger Detection Module (USBDCD)
64.1 Chip-specific USBDCD information............................................................................................................................5191
64.2 Overview.......................................................................................................................................................................5191
64.3 Functional description...................................................................................................................................................5193
64.4 External Signals............................................................................................................................................................ 5210
64.5 Initialization information.............................................................................................................................................. 5211
64.6 Application information................................................................................................................................................5211
64.7 Memory map/Register definition..................................................................................................................................5212
Chapter 65
Euro, MasterCard, Visa Subscriber Identification Module (EMVSIM)
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65.1 Chip-specific EMVSIM information............................................................................................................................ 5225
65.2 Overview.......................................................................................................................................................................5225
65.3 Functional Description..................................................................................................................................................5227
65.4 External Signals............................................................................................................................................................ 5243
65.5 Initialization.................................................................................................................................................................. 5243
65.6 Application Information................................................................................................................................................5246
65.7 Memory Map and Registers..........................................................................................................................................5251
Chapter 66
Flexible Controller Area Network (FLEXCAN)
66.1 Chip-specific FLEXCAN information..........................................................................................................................5283
66.2 Overview.......................................................................................................................................................................5283
66.3 Functional description...................................................................................................................................................5286
66.4 FlexCAN signal descriptions........................................................................................................................................ 5343
66.5 Initialization/application information........................................................................................................................... 5343
66.6 Memory map/register definition................................................................................................................................... 5345
Chapter 67
Flexible I/O (FlexIO)
67.1 Chip-specific FlexIO information.................................................................................................................................5425
67.2 Overview.......................................................................................................................................................................5425
67.3 Functional description...................................................................................................................................................5427
67.4 Application Information................................................................................................................................................5443
67.5 FlexIO Signal Descriptions...........................................................................................................................................5463
67.6 Memory Map and Registers..........................................................................................................................................5463
Chapter 68
Keypad Port (KPP)
68.1 Chip-specific KPP information.....................................................................................................................................5499
68.2 Overview ......................................................................................................................................................................5499
68.3 Functional Description..................................................................................................................................................5501
68.4 External Signals............................................................................................................................................................ 5509
68.5 Initialization/Application Information.......................................................................................................................... 5511
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Section number Title Page
68.6 Memory Map and Register Definition..........................................................................................................................5512
Chapter 69
Low Power Inter-Integrated Circuit (LPI2C)
69.1 Chip-specific LPI2C information................................................................................................................................. 5519
69.2 Overview.......................................................................................................................................................................5519
69.3 Functional description...................................................................................................................................................5522
69.4 Signal descriptions........................................................................................................................................................ 5534
69.5 Memory Map and Registers..........................................................................................................................................5535
Chapter 70
Low Power Serial Peripheral Interface (LPSPI)
70.1 Chip-specific LPSPI information..................................................................................................................................5579
70.2 Overview.......................................................................................................................................................................5579
70.3 Functional description...................................................................................................................................................5581
70.4 Signal descriptions........................................................................................................................................................ 5592
70.5 Memory map and registers............................................................................................................................................5593
Chapter 71
Low Power Universal Asynchronous Receiver/ Transmitter (LPUART)
71.1 Chip-specific LPUART information.............................................................................................................................5619
71.2 Overview.......................................................................................................................................................................5619
71.3 Functional description...................................................................................................................................................5622
71.4 External signals.............................................................................................................................................................5640
71.5 Register definition.........................................................................................................................................................5640
Chapter 72
Timers Overview
72.1 Overview.......................................................................................................................................................................5669
Chapter 73
Enhanced Flex Pulse Width Modulator (eFlexPWM)
73.1 Chip-specific FlexPWM information........................................................................................................................... 5673
73.2 Overview.......................................................................................................................................................................5673
73.3 Functional Description..................................................................................................................................................5676
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NXP Semiconductors 21
Section number Title Page
73.4 External Signals ........................................................................................................................................................... 5712
73.5 Resets............................................................................................................................................................................ 5714
73.6 Interrupts....................................................................................................................................................................... 5714
73.7 DMA............................................................................................................................................................................. 5716
73.8 PWM register descriptions............................................................................................................................................5717
Chapter 74
General Purpose Timer (GPT)
74.1 Chip-specific GPT information.....................................................................................................................................5791
74.2 Overview.......................................................................................................................................................................5791
74.3 External Signals............................................................................................................................................................ 5793
74.4 Clocks........................................................................................................................................................................... 5794
74.5 Functional Description..................................................................................................................................................5796
74.6 Initialization/ Application Information ........................................................................................................................ 5800
74.7 Memory map/register definition................................................................................................................................... 5801
Chapter 75
Periodic Interrupt Timer (PIT)
75.1 Chip-specific PIT information...................................................................................................................................... 5813
75.2 Introduction...................................................................................................................................................................5813
75.3 Modes of operation....................................................................................................................................................... 5815
75.4 Functional description...................................................................................................................................................5815
75.5 Initialization and application information.....................................................................................................................5819
75.6 Memory Map and Registers..........................................................................................................................................5820
Chapter 76
Quad Timer (TMR)
76.1 Chip-specific TMR information................................................................................................................................... 5829
76.2 Overview.......................................................................................................................................................................5829
76.3 Modes of Operation...................................................................................................................................................... 5831
76.4 Functional Description..................................................................................................................................................5831
76.5 Resets............................................................................................................................................................................ 5848
76.6 Clocks........................................................................................................................................................................... 5848
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22 NXP Semiconductors
Section number Title Page
76.7 Interrupts....................................................................................................................................................................... 5849
76.8 DMA............................................................................................................................................................................. 5851
76.9 Memory map/register definition................................................................................................................................... 5851
Chapter 77
Quadrature Decoder (QDC)
77.1 Chip-specific QDC information....................................................................................................................................5871
77.2 Overview.......................................................................................................................................................................5871
77.3 Functional Description..................................................................................................................................................5876
77.4 Memory Map and Registers..........................................................................................................................................5887
Chapter 78
System Watchdog Timer (WDOG 1,2)
78.1 Chip-specific System Watchdog information...............................................................................................................5915
78.2 Overview.......................................................................................................................................................................5915
78.3 Functional description...................................................................................................................................................5917
78.4 External signals.............................................................................................................................................................5926
78.5 Initialization.................................................................................................................................................................. 5927
78.6 WDOG Memory Map/Register Definition................................................................................................................... 5927
Chapter 79
CPU Watchdog Timer (WDOG 3,4)
79.1 Chip-specific CPU Watchdog information...................................................................................................................5935
79.2 Overview.......................................................................................................................................................................5936
79.3 Functional description...................................................................................................................................................5937
79.4 External signals.............................................................................................................................................................5943
79.5 Application Information................................................................................................................................................5944
79.6 Memory map and register definition.............................................................................................................................5945
Chapter 80
External Watchdog Module (EWM)
80.1 Chip-specific EWM information.................................................................................................................................. 5953
80.2 Overview.......................................................................................................................................................................5953
80.3 Functional Description..................................................................................................................................................5955
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NXP Semiconductors 23
Section number Title Page
80.4 EWM Signal Descriptions............................................................................................................................................ 5960
80.5 Memory Map/Register Definition.................................................................................................................................5960
Chapter 81
On Chip Cross Triggers Overview
81.1 Overview.......................................................................................................................................................................5969
Chapter 82
And-Or-Inverter (AOI)
82.1 Chip-specific AOI information..................................................................................................................................... 5971
82.2 Overview.......................................................................................................................................................................5971
82.3 Functional Description..................................................................................................................................................5974
82.4 External Signal Description.......................................................................................................................................... 5977
82.5 Memory Map and Register Descriptions...................................................................................................................... 5977
Chapter 83
Inter-Peripheral Crossbar Switch A (XBARA)
83.1 Chip-specific XBAR information................................................................................................................................. 5983
83.2 Overview.......................................................................................................................................................................5983
83.3 Functional Description..................................................................................................................................................5985
83.4 External Signals............................................................................................................................................................ 5987
83.5 Memory Map and Register Descriptions...................................................................................................................... 5988
Chapter 84
Inter-Peripheral Crossbar Switch B (XBARB)
84.1 Chip-specific XBAR information................................................................................................................................. 6033
84.2 Overview.......................................................................................................................................................................6033
84.3 Functional Description..................................................................................................................................................6034
84.4 External Signals............................................................................................................................................................ 6034
84.5 Memory Map and Register Descriptions...................................................................................................................... 6034
Chapter 85
Analog Overview
85.1 Overview.......................................................................................................................................................................6041
Chapter 86
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24 NXP Semiconductors
Section number Title Page
Analog Comparator (ACMP)
86.1 Chip-specific CMP information....................................................................................................................................6043
86.2 Overview.......................................................................................................................................................................6044
86.3 CMP functional description.......................................................................................................................................... 6049
86.4 DAC functional description.......................................................................................................................................... 6065
86.5 CMP external signals.................................................................................................................................................... 6069
86.6 Initialization.................................................................................................................................................................. 6069
86.7 Memory map/register definitions..................................................................................................................................6070
Chapter 87
Analog-to-Digital Converter (LPADC)
87.1 Chip-specific LPADC information............................................................................................................................... 6085
87.2 Overview.......................................................................................................................................................................6087
87.3 Functional description...................................................................................................................................................6089
87.4 External Signals............................................................................................................................................................ 6099
87.5 Initialization.................................................................................................................................................................. 6101
87.6 Application information................................................................................................................................................6102
87.7 LPADC register descriptions........................................................................................................................................ 6112
Chapter 88
ADC External Trigger Control (ADC_ETC)
88.1 Chip-specific ADC_ETC information.......................................................................................................................... 6145
88.2 Overview.......................................................................................................................................................................6145
88.3 Functional description...................................................................................................................................................6148
88.4 Initialization.................................................................................................................................................................. 6151
88.5 Application information................................................................................................................................................6151
88.6 Memory Map and register definition............................................................................................................................ 6154
Chapter 89
Digital-to-Analog Converters (DAC)
89.1 Chip-specific DAC information....................................................................................................................................6187
89.2 Overview.......................................................................................................................................................................6187
89.3 Functional description...................................................................................................................................................6189
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NXP Semiconductors 25
Section number Title Page
89.4 Memory map/register definition................................................................................................................................... 6191
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26 NXP Semiconductors
Chapter 1
About this Document
1.1 Audience
The reference manual is intended for the board-level product designers and product
software developers. This manual assumes that the reader has a background in computer
engineering and/or software engineering and understands the concepts of the digital
system design, microprocessor architecture, input/output (I/O) devices, industry standard
communication, and device interface protocols.
1.2 Organization
The reference manual describes the chip at a system level and provides an architectural
overview. It also describes the system memory map, system-level interrupt events,
external pins and pin multiplexing, external memory, system debug, system boot,
multimedia subsystem, power management, and system security.
1.3 Suggested Reading
This section lists additional resources that provide background for the information in the
reference manual, as well as general information about the architecture.
Table 1-1. Suggested Reading
Type Description Resource
Fact Sheet The Fact Sheet is an overview of the product key features i.MX RT Series Crossover Processor Fact
and its uses. Sheet
Reference The Reference Manual contains a comprehensive description
Manual of the structure and function (operation) of a device.
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 27
Conventions
Table 1-1. Suggested Reading (continued)
Type Description Resource
Chip Errata The Chip mask set Errata provides additional or corrective
information for a particular device mask set.
Application Provides additional information about particular device feature
Notes or function.
AN12077: Using the i.MX RT FlexRAM AN12077
AN12879: How to Enable Spread Spectrum for RT Family AN12879
AN12940: Use Case of RT1170 LCD Display System based AN12940
on MIPI DSI
Other Application Notes
Web Sites Product summary page on nxp.com with documentation,
software, and resources for the device.
Product documentation page on nxp.com with a list of all
documentation related to the device.
Community i.MX RT Community support forum for questions, support, i.MX RT Community
Forum and information about the device.
1.4 Conventions
The reference manual uses the following notational conventions:
cleared / set
When a bit has a value of zero, it is said to be cleared; when it has a value of one, it is
said to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
The book titles in the text are set in italics.
15
An integer in decimal.
0x
the prefix to denote a hexadecimal number.
0b
The prefix to denote a binary number. Binary values of 0 and 1 are written without a
prefix.
n'H4000CA00
The n-bit hexadecimal number.
BLK_REG_NAME
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28 NXP Semiconductors
Chapter 1 About this Document
The register names are all uppercase. The block mnemonic is prepended with an
underscore delimiter (_).
BLK_REG[FIELD]
The fields within registers appear in brackets. For example, ESR[RLS] refers to the
Receive Last Slot field of the ESAI Status Register.
BLK_REG[ n]
The bit number n within the BLK.REG register.
BLK_REG[ l:r]
The register bit ranges. The ranges are indicated by the left-most bit number l and the
right-most bit number r, separated by a colon (:). For example, ESR[15:0] refers to the
lower half word in the ESAI Status Register.
x, U
In some contexts, such as signal encodings, an unitalicized x indicates a "don't care" or
"uninitialized". The binary value can be 1 or 0.
x
An italicized x indicates an alphanumeric variable.
n, m
Italicized n or m represent integer variables.
!
Binary logic operator NOT.
&&
Binary logic operator AND.
||
Binary logic operator OR.
^ or <O+>
Binary logic operator XOR. For example, A <O+> B.
|
Bit-wise OR. For example, 0b0001 | 0b1000 yields the value of 0b1001.
&
Bit-wise AND. For example, 0b0001 & 0b1000 yields the value of 0b0000.
{A,B}
Concatenation, where the n-bit value A is prepended to the m-bit value B to form an (n
+m)-bit value. For example, {0, REGm [14:0]} yeilds a 16-bit value with 0 in the most
significant bit.
- or grey fill
Indicates a reserved bit field in a register. Although these bits can be written to with
ones or zeros, they always read zeros.
>>
Shift right logical one position.
<<
Shift left logical one position.
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NXP Semiconductors 29
Register Access
<=
Assignment.
==
Compare equal.
!=
Compare not equal.
>
Greater than.
<
Less than.
1.5 Register Access
1.5.1 Register Diagram Field Access Type Legend
This figure provides the interpretation of the notation used in the register diagrams for a
number of common field access types:
1 0 Fld Fld rtc 0
Reserved Reserved R/W Fld Read-only Write-only Write 1 Read Self- Reserved
returns 1 returns 0 field field field Fld to clear w1c to clear Fld clear bit Fld
on read on read
Figure 1-1. Register Field Conventions
NOTE
For reserved register fields, the software should mask off the
data in the field after a read (the software can't rely on the
contents of data read from a reserved field) and always write all
zeros.
1.5.2 Register Macro Usage
A common operation is to update one field without disturbing the contents of the
remaining fields in the register. Normally, this requires a read-modify-write (RMW)
operation, where the CPU reads the register, modifies the target field, then writes the
results back to the register. This is an expensive operation in terms of CPU cycles,
because of the initial register read.
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Chapter 1 About this Document
To address this issue, some hardware registers are implemented as a group, including
registers that can be used to either set, clear, or toggle (SCT) individual bits of the
primary register. When writing to an SCT register, all the bits set to 1 perform the
associated operation on the primary register, while the bits set to 0 are not affected. The
SCT registers always read back 0, and should be considered write-only. The SCT
registers are not implemented if the primary register is read-only.
With this architecture, it is possible to update one or more fields using only register
writes. First, all bits of the target fields are cleared by a write to the associated clear
register, then the desired value of the target fields is written to the set register. This
sequence of two writes is referred to as a clear-set (CS) operation.
A CS operation does have one potential drawback. Whenever a field is modified, the
hardware sees a value of 0 before the final value is written. For most fields, passing
through the 0 state is not a problem. Nonetheless, this behavior is something to consider
when using a CS operation.
Also, a CS operation is not required for fields that are one-bit wide. While the CS
operation works in this case, it is more efficient to simply set or clear the target bit (that
is, one write instead of two). A simple set or clear operation is also atomic, while a CS
operation is not.
Note that not all macros for set, clear, or toggle (SCT) are atomic. For registers that do
not provide hardware support for this functionality, these macros are implemented as a
sequence of read-modify-write operations. When an atomic operation is required, the
developer should pay attention to this detail, because unexpected behavior might result if
an interrupt occurs in the middle of the critical section comprising the update sequence.
A set of SCT registers is offered for registers in many modules on this device, as
described in this manual. In a module memory map table, the suffix _SET, _CLR, or
_TOG is added to the base name of the register. For example, the
CCM_ANALOG_PLL_ARM register has three other registers called
CCM_ANALOG_PLL_ARM_SET, CCM_ANALOG_PLL_ARM_CLR, and
CCM_ANALOG_PLL_ARM_TOG.
In the sub-section that describes one of these sets of registers, a short-hand convention is
used to denote that a register has the SCT register set. There is an italicized n appended to
the end of the short register name. Using the above example, the name used for this
register is CCM_ANALOG_PLL_ARMn. When you see this designation, there is a SCT
register set associated with the register, and you can verify this by checking it in the
memory map table. The address offset for each of these registers is given in the form of
the following example:
Address: 20C_8000h base + 0h offset + (4d × i), where i=0d to 3d
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NXP Semiconductors 31
Acronyms and Abbreviations
In this example, the address for each of the base registers and their three SCT registers
can be calculated as:
Register Address
CCM_ANALOG_PLL_ARM 20C_8000h
CCM_ANALOG_PLL_ARM_SET 20C_8004h
CCM_ANALOG_PLL_ARM_CLR 20C_8008h
CCM_ANALOG_PLL_ARM_TOG 20C_800Ch
1.6 Acronyms and Abbreviations
The table below contains acronyms and abbreviations used in this document.
Acronyms and Abbreviated Terms
Term Meaning
ACMP Analog Comparator
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AIPS Arm IP Bus
ALU Arithmetic Logic Unit
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
ASRC Asynchronous Sample Rate Converter
AXI Advanced eXtensible Interface
BIST Built-In Self Test
CA/CM Arm Cortex-A/Cortex-M
CAAM Cryptographic Acceleration and Assurance Module
CAN Controller Area Network
CCM Clock Controller Module
CM7 ARM Cortex M7 Core
CPU Central Processing Unit
CSI CMOS Sensor Interface
CSU Central Security Unit
CTI Cross Trigger Interface
D-cache Data cache
DAP Debug Access Port
DDR Double data rate
DMA Direct memory access
DPLL Digital phase-locked loop
Table continues on the next page...
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32 NXP Semiconductors
Chapter 1 About this Document
Term Meaning
DRAM Dynamic random access memory
ECC Error correcting codes
LPSPI Low-power SPI
EDMA Enhanced Direct Memory Access
EIM External Interface Module
ENET Ethernet
EPIT Enhanced Periodic Interrupt Timer
EPROM Erasable Programmable Read-Only Memory
ETF Embedded Trace FIFO
ETM Embedded Trace Macrocell
FIFO First-In-First-Out
GIC General Interrupt Controller
GPC General Power Controller
GPIO General-Purpose I/O
GPR General-Purpose Register
GPS Global Positioning System
GPT General-Purpose Timer
GPU Graphics Processing Unit
GPV Global Programmers View
HAB High-Assurance Boot
I-cache Instruction cache
I2C or I2C Inter-Integrated Circuit
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
IOMUX Input-Output Multiplexer
IP Intellectual Property
IrDA Infrared Data Association
JTAG Joint Test Action Group (a serial bus protocol usually used for test purposes)
ELCDIF Liquid Crystal Display Interface
LDO Low-Dropout
LIFO Last-In-First-Out
LRU Least-Recently Used
LPSR Low-Power State Retention
LSB Least-Significant Byte
LUT Look-Up Table
LVDS Low Voltage Differential Signaling
MAC Medium Access Control
MCM Miscellaneous Control Module
MMC Multimedia Card
MSB Most-Significant Byte
MT/s Mega Transfers per second
Table continues on the next page...
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NXP Semiconductors 33
Acronyms and Abbreviations
Term Meaning
OCRAM On-Chip Random-Access Memory
OCOTP On-Chip One-Time Programmable Controller
PCI Peripheral Component Interconnect
PCIe PCI express
PCMCIA Personal Computer Memory Card International Association
BPC Basic Power Controller
PIC Programmable Interrupt Controller
PMU Power Management Unit
POR Power-On Reset
PSRAM Pseudo-Static Random Access Memory
PWM Pulse Width Modulation
PXP Pixel Pipeline
QoS Quality of Service
R2D Radians to Degrees
RISC Reduced Instruction Set Computing
ROM Read-Only Memory
ROMCP ROM Controller with Patch
RTOS Real-Time Operating System
Rx Receive
SAI Synchronous Audio Interface
SCU Snoop Control Unit
SD Secure Digital
SDIO Secure Digital Input/Output
SDLC Synchronous Data Link Control
SDMA Smart DMA
SIM Subscriber Identification Module
SNVS Secure Non-Volatile Storage
SoC System-on-Chip
SPBA Shared Peripheral Bus Arbiter
SPDIF Sony Phillips Digital Interface
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
SRC System Reset Controller
TFT Thin-Film Transistor
TPIU Trace Port Interface Unit
TSGEN Time Stamp Generator
Tx Transmit
TZASC TrustZone Address Space Controller
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USDHC Ultra Secured Digital Host Controller
Table continues on the next page...
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34 NXP Semiconductors
Chapter 1 About this Document
Term Meaning
WDOG Watchdog
WLAN Wireless Local Area Network
WXGA Wide Extended Graphics Array
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NXP Semiconductors 35
Acronyms and Abbreviations
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36 NXP Semiconductors
Chapter 2
Introduction
2.1 Introduction
The i.MX RT1170 is a new processor family featuring NXP's advanced implementation
of the high performance Arm Cortex®-M7 Core and a power efficient Arm Cortex®-M4
Core. It offers high-performance processing optimized for lowest power consumption and
best real-time response.
The i.MX RT1170 has 2MB on-chip RAM in total, including a 512KB RAM which can
be flexibly configured as TCM or general-purpose on-chip RAM. The i.MX RT1170
integrates advanced power management module with DCDC and LDO that reduces
complexity of external power supply and simplifies power sequencing. The i.MX
RT1170 also provides various memory interfaces, including SDRAM, Raw NAND
FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperRAM/HyperFlash and a wide range
of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS,
displays, and camera sensors. Same as other i.MX processors, i.MX RT1170 also has rich
audio and video features, including MIPI CSI/DSI, LCD display, graphics accelerator,
camera interface, SPDIF and I2S audio interface.
2.1.1 Block Diagram
The functional block diagram is shown in the figure below. This diagram provides a view
of the chip's major functional components and core complexes.
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NXP Semiconductors 37
Introduction
System Control CPU Platform Connectivity
JTAGC eMMC5.0/ SD3.0 x2
Arm Cortex-M7
PLL,OSC UART x12
32KB I-cache 32KB D-cache
eDMA x2 FPU MPU NVIC I2C x6
WDOG x4, EWM x1 512KB TCM SPI x6
GPT x6 8x8 Keypad
ARM Cortex-M7
ARM Cortex-M4
Quadrature Enc/Dec x4 I2S/SAI x4
16KB I-cache 16KB D-cache
QuadTimer x4 SPDIF Tx/Rx
FPU MPU NVIC
FlexPWM x4 ASRC
256KB TCM
PIT x2 8-ch Digital Mic Input
Multimedia CAN-FD x3
RDC, SEMA4, MU
Parallel LCD MIPI DSI
USB2.0 OTG
Power Mgmt Parallel CSI MIPI CSI w/PHY x2
DCDC &LDO
Vector GPU Acceleration 10M/100M ENET x1
Temp Monitor w/IEEE 1588
2D Graphics Acceleration(PXP)
ADC/DAC Resize, CSC, Overlay, Rotation
1Gbps ENETx1
HSADCx3(24-ch)
LPADC x2 (20-ch) w/ AVB
External Memory
ACMP
ACMPx8,DACx2
x4, DAC x1 GPIO / HS GPIO
Dual-Channel QSPI FLASH x2
HyperRAM/HyperFLASH
Internal Memory EMVSIM x2
2MB SRAM/TCM External Memory Controller
8/16/32-bit SDRAM
FlexIO x2
256KB ROM Parallel NAND/ NOR Flash
Security
Crypto Secure SHA-1 / Tamper
RNG4 Secure RTC RSA4096 HAB Engine SHA-2 Detection
RAM
PUF / Encrypted
eFUSE AES-128/256 DES/3DES UDF CDOG Ellipse Curve XIP
Figure 2-1. Simplified Block Diagram
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38 NXP Semiconductors
Chapter 2 Introduction
2.1.2 System Bus Diagram
The system bus diagram is shown below.
DISPLAYMIX WAKEUPMIX 8/16/32-bit
SDRAM/
dma0 XBARA PSRAM/
eDMA NOR/
GPU m_a_0 2x XBARB
NAND
Parallel m_a_4 DMAMUX
CSI m_b_5 s_b_0 4x ACMP
Camera m_a_2 s_b_3 SIM_M7
eLCDIF 2x ADC 4/8/16-bit
Parallel m_a_3
s_b_1
OCRAM QSPI
LCDIFv2 ADC_ETC
LCD Flash
disp0
s_b_2
OCRAM
PXP m_a_1 s_a_0 m_b_1 DAC
disp1 2x AOI
s_a_1 m_b_2
VIDEO_MUX s_b_7 XECC SEMC
8x8
FlexSPI1 KPP Keypad
2x DCIC
NIC-301 CANFD (1,2)
MIPI CSI NIC-301 SIM_M7 FlexSPI2 CAN I/F
MIPI CSI2 SIM_DISP LPSR_M7 LPUART (1-10) UART
m_b_4 s_b_5 XECC
MIPI DSI LPI2C (1-4) I2C
MIPI DSI
m_b_3
s_b_6 XECC
LPSPI (1-4) SPI I/F
s_b_8 2x FLEXIO
s_c_0
m_b_0 s_b_4
Audio ASRC s_b_9
PWM m_b_6 IOMUXC
SAI (1,2,3)
I2S GPIO (1-6) GPIOs
MQS NIC-301 IEE
SPDIF SIM_M
2x EMVSIM
SPDIF
RX/TX 32x
FlexRAM
CM7
(512KB SRAM +128KB)
1G ENET 1G
m_c_1(RX) 4x eFlexPWM PWM
m_c_2(TX) ITCM
Ethernet FPU MPU NVIC 6x GPT Timers
ENET 10/100M m_c_3 DTCM0
I$ D$
10/100M ENET QoS m_c_8 32KB 32KB DTCM1 PIT (1) Triggers
OCRAM 4x TMR
Ethernet 2x uSDHC
m_c_5
m_c_6 Timers
GPIO (2,3) ECC (QuadTimer)
eSD/ USBO2 m_b_4 4x QDC
eMMC
CAAM m_c_0 EWM
2x WDOG (1,2)
Watchdog
OTG (System) Reset
aips1
w/ PHY m_d_0 s_d_0 AIPSTZ1 WDOG (CM7)
XB_PER s_d_2
m_d_1
MEGAMIX
s_d_1
s_d_5
LPSR_PER m_d_2
s_d_4 PDM MIC
SAI (4) I2S I/F
aips2
AIPSTZ2
CANFD (3) CAN I/F
aips3
AIPSTZ3 LPUART (11,12) UART
SNVSMIX LPI2C (5,6) I2C
CDOG AIPSTZ4 aips4
GPIO (13) LPSPI (5,6) SPI I/F
IOMUXC_SNVS PIT (2)
SIM_M7 s_f_2
Triggers
m_f_2
SRAM (4KB) dma1 m_f_3 ROMCP
eDMA s_f_4
(256KB) GPC
Tampers m_f_0 (c) s_f_1 LPSR_M7
SNVS_LP DMAMUX
m_f_1(s) s_f_0 LPSR_PER
XB_LPSR PGMC
SRC
PMIC SNVS_HP m_f_4
s_f_2 Power
Control MU DCDC
WDOG (CM4) SSARC Supply
RDC CCM
KEYMGR
SEMA4 CM4 Sys$
LMEM
Code TCM
GPIO (7-12)
XTALOSC
OCOTP 128KB Clocks/
FPU MPU NVIC 16KB IOMUXC_LPSR
SEMA42 TEMPSENSE
Code$ Sys TCM Oscillators
MMCAU MCM 16KB 128KB IOMUXC
PMU
LPSRMIX ANADIG
Figure 2-2. Bus Diagram
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NXP Semiconductors 39
Features
2.2 Features
The i.MX RT1170 processors are based on Arm®Cortex®-M7 Platform, and
Arm®Cortex®-M4 which have the following features:
Single Arm Cortex-M7 with:
• 32KB L1 Instruction Cache
• 32KB L1 Data Cache
• Single-precision and double-precision FPU (Floating Point Unit)
• Integrated Memory Protection Unit (MPU), up to 16 individual protection regions
• Up to 512KB I-TCM and D-TCM in total
• ECC support for cache and TCM
Single Arm Cortex-M4 with:
• 16KB L1 Instruction Cache
• 16KB L1 Data Cache
• Single-precision FPU defined by ARMv7-M Architecture FPv4-SP
• ECC support for TCM
• Integrated MPU with 8 individual protection regions
On Chip Memory:
• Boot ROM (256KB)
• On-chip RAM (2MB in total)
• FlexRAM - configurable 512KB RAM shared with M7 TCM and 256KB RAM
shared with M4 TCM
NOTE
When using the M4 boot mode, FlexRAM will not be
accessible until the M7 domain is released
• OCRAM - dedicated 1.25MB RAM
External Memory Interfaces:
• 8/16/32-bit SDRAM, up to SDRAM-133/SDRAM-166/SDRAM-200
• 8/16-bit SLC NAND FLASH, with ECC handled in software
• SD/eMMC
• Single/Dual channel Quad SPI FLASH with XIP support
• Parallel NOR FLASH with XIP support
• SPI NOR/NAND FLASH
• HyperRAM/HyperFLASH
• Synchronization mode for all devices
Graphics:
• Generic 2D Graphics engine (PXP)
• BitBlit
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40 NXP Semiconductors
Chapter 2 Introduction
• Flexible image composition options – alpha, chroma key
• Image rotation (90, 180, 270 degree rotation)
• Porter-Duff operation
• Image resize
• Color space conversion
• Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
• Standard 2D-DMA operation
• Vector Graphics Processing (GPU)
• Real-time hardware curve tesselation of lines, quadratic and cubic Bezier curves
• OpenVG 1.1 support
• 16x Line Anti-aliasing
• Vector Drawing
Display Interface:
• Parallel RGB LCD Interface (eLCDIF) that supports 8/16/24-bit I/F, up to WXGA
with 60fps, and Index color with 256 entry x 24bit color LUT
• Parallel RGB LCD Interface Version 2 (LCDIFv2) that is enhanced based on the
above version, supporting up to 8 layers of alpha blending
• MIPI Display Serial Interface (MIPI DSI) with 2-lane I/F and Smart LCD Display
with 8080 interface through SEMC
Camera Sensor Interface:
• Parallel Camera - CMOS Sensor Interface (CSI) with 8/16/24-bit input
• MIPI Camera Sensor Interface (MIPI CSI2) with 2-lane I/F
Audio:
• SPDIF Input and Output
• 4x Synchronous Audio Interface (SAI) modules supporting I2S, AC97, TDM, and
Codec/DSP interfaces
• MQS interface for medium quality audio via GPIO pads
• PDM microphone interface with 4 pairs inputs
• Asynchronous Sample Rate Converter (ASRC)
Connectivity:
• 2x USB 2.0 OTG controller with integrated PHY interfaces
• 2x Ultra Secure Digital Host Controller (uSDHC) interfaces
• 1x 10M/100M Ethernet controller with support for IEEE1588
• 1x Gigabit Ethernet controller with support for AVB
• 1x Gigabit Ethernet controller with Time Sensitive Networking (TSN) Capability
• 12x Universal asynchronous receiver/transmitter (UARTs) modules
• 6x I2C modules
• 6x SPI modules
• 3x CAN-FD modules
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NXP Semiconductors 41
Target Applications
Timers:
• 6x General Programmable Timer (GPT)
• 2x Periodical Interrupt Timer (PIT)
• 4x Quad Timer (QTimer)
• 4x FlexPWM
• 4x Quadrature Encoder/Decoder
• 4x WatchDog modules (WDOG)
Analog:
• 2x Analog-Digital-Converters (ADC) (up to 20 channels)
• 4x Analog Comparators (ACMP)
• 1x 12-bit Digital-Analog-Converter (DAC)
Security:
• High Assurance Boot (HAB)
• Random Number Generator (RNG4)
• Secure Non-volatile Storage (SNVS)
• Secure real-time clock (RTC)
• Zero Master Key (ZMK)
• Tamper Detection
• JTAG Controller (JTAGC)
• Cryptographic Acceleration and Assurance Module (CAAM)
• Inline Encryption Engine (IEE)
• On-the-Fly AES Decryption (OTFAD)
• Secure always-on RAM (4KB)
• Secure key management (KEYMGR) and protection
• Secure and trusted access control
• Code WatchDog Timer (CDOG)
• Manufacturing Protection
System Debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) and SWD debug interfaces
Power Management:
• Full PMIC integration, including on-chip DCDC and LDO
• Temperature sensor with programmable trim points
• GPC hardware power management controller
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42 NXP Semiconductors
Chapter 2 Introduction
2.3 Target Applications
This processor can be used in areas such as industrial HMI, IoT, high-end audio
appliance, medium/low-end instrument cluster, Point-of-Sale(PoS), motor control and
home appliances, etc.
2.4 Endianness Support
The chip supports only the Little Endian mode.
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Endianness Support
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44 NXP Semiconductors
Chapter 3
Memory Maps
3.1 Memory system overview
This section introduces the memory architecture of the chip.
NOTE
Accessing the reserved memory regions can result in
unpredictable behavior.
3.2 System memory map (CM7)
The table below shows the CM7 memory map:
Table 3-1. System memory map (CM7)
Start Address End Address Size Description
E010_0000 FFFF_FFFF 511MB Reserved
E000_0000 E00F_FFFF 1MB PPB M7
C000_0000 DFFF_FFFF 512MB SEMC3
A000_0000 BFFF_FFFF 512MB SEMC2
9000_0000 9FFF_FFFF 256MB SEMC1
8000_0000 8FFF_FFFF 256MB SEMC0
7FC0_0000 7FFF_FFFF 4MB FlexSPI2 RX FIFO
7F80_0000 7FBF_FFFF 4MB FlexSPI2 TX FIFO
6000_0000 7F7F_FFFF 504MB FlexSPI2/ FlexSPI2 ciphertext
4280_0000 5FFF_FFFF 472MB Reserved
4210_0000 427F_FFFF 7MB Reserved
4200_0000 420F_FFFF 1MB AIPS M7 (Peripheral, Platform)
41A0_0000 41FF_FFFF 6MB Reserved
4190_0000 419F_FFFF 1MB CDOG (Peripheral, AHB)
Table continues on the next page...
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NXP Semiconductors 45
System memory map (CM7)
Table 3-1. System memory map (CM7) (continued)
Start Address End Address Size Description
4180_0000 418F_FFFF 1MB GPU2D (Peripheral, AHB)
4170_0000 417F_FFFF 1MB Reserved
4160_0000 416F_FFFF 1MB Reserved
4150_0000 415F_FFFF 1MB Reserved
4140_0000 414F_FFFF 1MB SIM_M7 configuration port
4130_0000 413F_FFFF 1MB Reserved
4120_0000 412F_FFFF 1MB Reserved
4110_0000 411F_FFFF 1MB SIM_M configuration port
4100_0000 410F_FFFF 1MB SIM_DISP configuration port
40C0_0000 40FF_FFFF 4MB AIPS-4
4080_0000 40BF_FFFF 4MB AIPS-3
4040_0000 407F_FFFF 4MB AIPS-2
4000_0000 403F_FFFF 4MB AIPS-1
3000_0000 3FFF_FFFF 256MB FlexSPI1/ FlexSPI1 cipher text
2FC0_0000 2FFF_FFFF 4MB FlexSPI1 RX FIFO
2F80_0000 2FBF_FFFF 4MB FlexSPI1 TX FIFO
2040_0000 2F7F_FFFF 244MB Reserved
2038_0000 203F_FFFF 512KB OCRAM M7 (FlexRAM)
2036_0000 2037_FFFF 128KB OCRAM M7 (FlexRAM ECC)
2035_0000 2035_FFFF 64KB OCRAM2 ECC
2034_0000 2034_FFFF 64KB OCRAM1 ECC
202C_0000 2033_FFFF 512KB OCRAM2
2024_0000 202B_FFFF 512KB OCRAM1
2020_0000 2023_FFFF 256KB OCRAM M4 (LMEM 128KB SRAM_L + 128KB SRAM_U
backdoor) 1, 2
2010_0000 201F_FFFF 1MB Reserved
2008_0000 200F_FFFF 512KB Reserved
2000_0000 2007_FFFF 512KB DTCM (FlexRAM)
1000_0000 1FFF_FFFF 256MB Reserved
0800_0000 0FFF_FFFF 128MB Reserved
0040_0000 07FF_FFFF 124MB Reserved
0029_0000 003F_FFFF 1472KB Reserved
0028_0000 0028_FFFF 64KB CAAM Secure RAM
0024_0000 0027_FFFF 256KB Reserved
0020_0000 0023_FFFF 256KB Reserved
0010_0000 001F_FFFF 1MB Reserved
0008_0000 000F_FFFF 512KB Reserved
0000_0000 0007_FFFF 512KB ITCM (FlexRAM)
1. This is the remapping address for CM4 TCM. CM7 can access CM4 TCM through this aliased region.
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46 NXP Semiconductors
Chapter 3 Memory Maps
2. For dual core part, this memory space cannot be accessed by CM7 or other masters while CM4 is powered down. The
result is unpredictable in this condition.
NOTE
When the ECC feature is enabled, the users cannot utilise the
ECC memory region in RAM.
3.3 System memory map (CM4)
The table below shows the CM4 memory map:
Table 3-2. System memory map (CM4)
Start address End address Size Description
E010_0000 FFFF_FFFF 511MB Reserved
E000_0000 E00F_FFFF 1MB PPB M4
C000_0000 DFFF_FFFF 512MB SEMC3
A000_0000 BFFF_FFFF 512MB SEMC2
9000_0000 9FFF_FFFF 256MB SEMC1
8000_0000 8FFF_FFFF 256MB SEMC0
7FC0_0000 7FFF_FFFF 4MB FlexSPI2 RX FIFO
7F80_0000 7FBF_FFFF 4MB FlexSPI2 TX FIFO
6000_0000 7F7F_FFFF 504MB FlexSPI2/FlexSPI2 ciphertext
4280_0000 5FFF_FFFF 472MB Reserved
4210_0000 427F_FFFF 7MB Reserved
4200_0000 420F_FFFF 1MB Reserved
41A0_0000 41FF_FFFF 6MB Reserved
4190_0000 419F_FFFF 1MB CDOG (Peripheral, AHB)
4180_0000 418F_FFFF 1MB GPU2D (Peripheral, AHB)
4170_0000 417F_FFFF 1MB Reserved
4160_0000 416F_FFFF 1MB Reserved
4150_0000 415F_FFFF 1MB Reserved
4140_0000 414F_FFFF 1MB SIM_M7 configuration port
4130_0000 413F_FFFF 1MB Reserved
4120_0000 412F_FFFF 1MB Reserved
4110_0000 411F_FFFF 1MB SIM_M configuration port
4100_0000 410F_FFFF 1MB SIM_DISP configuration port
40C0_0000 40FF_FFFF 4MB AIPS-4
4080_0000 40BF_FFFF 4MB AIPS-3
4040_0000 407F_FFFF 4MB AIPS-2
4000_0000 403F_FFFF 4MB AIPS-1
3000_0000 3FFF_FFFF 256MB FlexSPI1/ FlexSPI1 ciphertext
Table continues on the next page...
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NXP Semiconductors 47
AIPS-1 Memory Map
Table 3-2. System memory map (CM4) (continued)
Start address End address Size Description
2FC0_0000 2FFF_FFFF 4MB FlexSPI1 RX FIFO
2F80_0000 2FBF_FFFF 4MB FlexSPI1 TX FIFO
2040_0000 2F7F_FFFF 244MB Reserved
2038_0000 203F_FFFF 512KB OCRAM M7 (FlexRAM)
2036_0000 2037_FFFF 128KB OCRAM M7 (FlexRAM ECC)
2035_0000 2035_FFFF 64KB OCRAM2 ECC
2034_0000 2034_FFFF 64KB OCRAM1 ECC
202C_0000 2033_FFFF 512KB OCRAM2
2024_0000 202B_FFFF 512KB OCRAM1
2020_0000 2023_FFFF 256KB OCRAM M4 (LMEM 128KB RAM_L + 128KB RAM_U
backdoor) 1
2002_0000 201F_FFFF 1920KB Reserved
2000_0000 2001_FFFF 128KB System TCM (LMEM RAM_U)
1FFE_0000 1FFF_FFFF 128KB Code TCM (LMEM RAM_L)
1800_0000 1FFD_FFFF 128MB Reserved
0800_0000 17FF_FFFF 256MB FlexSPI1 (alias)
0029_0000 07FF_FFFF 128448KB Reserved
0028_0000 0028_FFFF 64KB CAAM Secure RAM
0024_0000 0027_FFFF 256KB Reserved
0020_0000 0023_FFFF 256KB Reserved
0008_0000 001F_FFFF 1536KB Reserved
0004_0000 0007_FFFF 256KB Reserved
0000_0000 0003_FFFF 256KB Reserved
1. This is the remapping address for CM4 TCM. CM7 can access CM4 TCM through this aliased region.
NOTE
When the ECC feature is enabled, the users cannot utilize the
ECC memory region in RAM.
3.4 AIPS-1 Memory Map
The table below shows the AIPS-1 memory map (This memory map applies to CM4 and
CM7):
Table 3-3. AIPS-1 memory map
Start Address End Address Size NIC Port
4030_0000 403F_FFFF 1MB Reserved
4020_0000 402F_FFFF 1MB Reserved
Table continues on the next page...
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48 NXP Semiconductors
Chapter 3 Memory Maps
Table 3-3. AIPS-1 memory map (continued)
Start Address End Address Size NIC Port
401F_C000 401F_FFFF 16KB Reserved
401F_8000 401F_BFFF 16KB Reserved
401F_4000 401F_7FFF 16KB Reserved
401F_0000 401F_3FFF 16KB Reserved
401E_C000 401E_FFFF 16KB Reserved
401E_8000 401E_BFFF 16KB Reserved
401E_4000 401E_7FFF 16KB Reserved
401E_0000 401E_3FFF 16KB Reserved
401D_C000 401D_FFFF 16KB Reserved
401D_8000 401D_BFFF 16KB Reserved
401D_4000 401D_7FFF 16KB Reserved
401D_0000 401D_3FFF 16KB Reserved
401C_C000 401C_FFFF 16KB Reserved
401C_8000 401C_BFFF 16KB Reserved
401C_4000 401C_7FFF 16KB Reserved
401C_0000 401C_3FFF 16KB Reserved
401B_C000 401B_FFFF 16KB Reserved
401B_8000 401B_BFFF 16KB Reserved
401B_4000 401B_7FFF 16KB Reserved
401B_0000 401B_3FFF 16KB ACMP4
401A_C000 401A_FFFF 16KB ACMP3
401A_8000 401A_BFFF 16KB ACMP2
401A_4000 401A_7FFF 16KB ACMP1
401A_0000 401A_3FFF 16KB Reserved
4019_C000 4019_FFFF 16KB Reserved
4019_8000 4019_BFFF 16KB FLEXPWM4
4019_4000 4019_7FFF 16KB FLEXPWM3
4019_0000 4019_3FFF 16KB FLEXPWM2
4018_C000 4018_FFFF 16KB FLEXPWM1
4018_8000 4018_BFFF 16KB Reserved
4018_4000 4018_7FFF 16KB Reserved
4018_0000 4018_3FFF 16KB QDC4
4017_C000 4017_FFFF 16KB QDC3
4017_8000 4017_BFFF 16KB QDC2
4017_4000 4017_7FFF 16KB QDC1
4017_0000 4017_3FFF 16KB Reserved
4016_C000 4016_FFFF 16KB Reserved
4016_8000 4016_BFFF 16KB TMR4
4016_4000 4016_7FFF 16KB TMR3
Table continues on the next page...
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NXP Semiconductors 49
AIPS-1 Memory Map
Table 3-3. AIPS-1 memory map (continued)
Start Address End Address Size NIC Port
4016_0000 4016_3FFF 16KB TMR2
4015_C000 4015_FFFF 16KB TMR1
4015_8000 4015_BFFF 16KB EMVSIM2
4015_4000 4015_7FFF 16KB EMVSIM1
4015_0000 4015_3FFF 16KB Reserved
4014_C000 4014_FFFF 16KB Reserved
4014_8000 4014_BFFF 16KB Reserved
4014_4000 4014_7FFF 16KB Reserved
4014_0000 4014_3FFF 16KB GPIO6
4013_C000 4013_FFFF 16KB GPIO5
4013_8000 4013_BFFF 16KB GPIO4
4013_4000 4013_7FFF 16KB GPIO3
4013_0000 4013_3FFF 16KB GPIO2
4012_C000 4012_FFFF 16KB GPIO1
4012_8000 4012_BFFF 16KB Reserved
4012_4000 4012_7FFF 16KB Reserved
4012_0000 4012_3FFF 16KB LPSPI4
4011_C000 4011_FFFF 16KB LPSPI3
4011_8000 4011_BFFF 16KB LPSPI2
4011_4000 4011_7FFF 16KB LPSPI1
4011_0000 4011_3FFF 16KB LPI2C4
4010_C000 4010_FFFF 16KB LPI2C3
4010_8000 4010_BFFF 16KB LPI2C2
4010_4000 4010_7FFF 16KB LPI2C1
4010_0000 4010_3FFF 16KB GPT6
400F_C000 400F_FFFF 16KB GPT5
400F_8000 400F_BFFF 16KB GPT4
400F_4000 400F_7FFF 16KB GPT3
400F_0000 400F_3FFF 16KB GPT2
400E_C000 400E_FFFF 16KB GPT1
400E_8000 400E_BFFF 16KB IOMUXC
400E_4000 400E_7FFF 16KB IOMUXC_GPR
400E_0000 400E_3FFF 16KB KPP
400D_C000 400D_FFFF 16KB Reserved
400D_8000 400D_BFFF 16KB PIT1
400D_4000 400D_7FFF 16KB SEMC
400D_0000 400D_3FFF 16KB FlexSPI2
400C_C000 400C_FFFF 16KB FlexSPI1
400C_8000 400C_BFFF 16KB CAN2
Table continues on the next page...
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50 NXP Semiconductors
Chapter 3 Memory Maps
Table 3-3. AIPS-1 memory map (continued)
Start Address End Address Size NIC Port
400C_4000 400C_7FFF 16KB CAN1
400C_0000 400C_3FFF 16KB Reserved
400B_C000 400B_FFFF 16KB AOI2
400B_8000 400B_BFFF 16KB AOI1
400B_4000 400B_7FFF 16KB Reserved
400B_0000 400B_3FFF 16KB FlexIO2
400A_C000 400A_FFFF 16KB FlexIO1
400A_8000 400A_BFFF 16KB Reserved
400A_4000 400A_7FFF 16KB Reserved
400A_0000 400A_3FFF 16KB LPUART10
4009_C000 4009_FFFF 16KB LPUART9
4009_8000 4009_BFFF 16KB LPUART8
4009_4000 4009_7FFF 16KB LPUART7
4009_0000 4009_3FFF 16KB LPUART6
4008_C000 4008_FFFF 16KB LPUART5
4008_8000 4008_BFFF 16KB LPUART4
4008_4000 4008_7FFF 16KB LPUART3
4008_0000 4008_3FFF 16KB LPUART2
4007_C000 4007_FFFF 16KB LPUART1
4007_8000 4007_BFFF 16KB Reserved
4007_4000 4007_7FFF 16KB DMAMUX0
4007_0000 4007_3FFF 16KB EDMA
4006_C000 4006_FFFF 16KB IEE
4006_8000 4006_BFFF 16KB IEE_APC
4006_4000 4006_7FFF 16KB DAC
4006_0000 4006_3FFF 16KB Reserved
4005_C000 4005_FFFF 16KB Reserved
4005_8000 4005_BFFF 16KB Reserved
4005_4000 4005_7FFF 16KB LPADC2
4005_0000 4005_3FFF 16KB LPADC1
4004_C000 4004_FFFF 16KB Reserved
4004_8000 4004_BFFF 16KB ADC_ETC
4004_4000 4004_7FFF 16KB XBAR3
4004_0000 4004_3FFF 16KB XBAR2
4003_C000 4003_FFFF 16KB XBAR1
4003_8000 4003_BFFF 16KB WDOG3
4003_4000 4003_7FFF 16KB WDOG2
4003_0000 4003_3FFF 16KB WDOG1
4002_C000 4002_FFFF 16KB EWM
Table continues on the next page...
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NXP Semiconductors 51
AIPS-2 Memory Map
Table 3-3. AIPS-1 memory map (continued)
Start Address End Address Size NIC Port
4002_8000 4002_BFFF 16KB CM7 (FLEXRAM)
4002_4000 4002_7FFF 16KB XECC_SEMC
4002_0000 4002_3FFF 16KB XECC_FLEXSPI2
4001_C000 4001_FFFF 16KB XECC_FLEXSPI1
4001_8000 4001_BFFF 16KB MECC2
4001_4000 4001_7FFF 16KB MECC1
4001_0000 4001_3FFF 16KB Reserved
4000_C000 4000_FFFF 16KB Reserved
4000_8000 4000_BFFF 16KB Reserved
4000_4000 4000_7FFF 16KB Reserved
4000_0000 4000_3FFF 16KB Reserved
3.5 AIPS-2 Memory Map
The table below shows the AIPS-2 memory map (This memory map applies to CM4 and
CM7):
Table 3-4. AIPS-2 memory map
Start Address End Address Size NIC Port
4070_0000 407F_FFFF 1MB Reserved
4060_0000 406F_FFFF 1MB Reserved
4054_0000 405F_FFFF 768KB Reserved
404D_0000 4053_FFFF 448KB CAAM(Reserved)
404C_C000 404C_FFFF 16KB CAAM(Debug)
404C_8000 404C_BFFF 16KB CAAM(Debug)
404C_4000 404C_7FFF 16KB CAAM(Debug)
404C_0000 404C_3FFF 16KB CAAM(Debug)
404B_C000 404B_FFFF 16KB CAAM(Reserved)
404B_8000 404B_BFFF 16KB CAAM(Reserved)
404B_4000 404B_7FFF 16KB CAAM(Reserved)
404B_0000 404B_3FFF 16KB CAAM(Reserved)
404A_C000 404A_FFFF 16KB CAAM(RTIC)
404A_8000 404A_BFFF 16KB CAAM(RTIC)
404A_4000 404A_7FFF 16KB CAAM(RTIC)
404A_0000 404A_3FFF 16KB CAAM(RTIC)
4049_C000 4049_FFFF 16KB CAAM(Reserved)
4049_8000 4049_BFFF 16KB CAAM(Reserved)
Table continues on the next page...
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Chapter 3 Memory Maps
Table 3-4. AIPS-2 memory map (continued)
Start Address End Address Size NIC Port
4049_4000 4049_7FFF 16KB CAAM(Reserved)
4049_0000 4049_3FFF 16KB CAAM(Reserved)
4048_C000 4048_FFFF 16KB CAAM(JR3)
4048_8000 4048_BFFF 16KB CAAM(JR3)
4048_4000 4048_7FFF 16KB CAAM(JR3)
4048_0000 4048_3FFF 16KB CAAM(JR3)
4047_C000 4047_FFFF 16KB CAAM(JR2)
4047_8000 4047_BFFF 16KB CAAM(JR2)
4047_4000 4047_7FFF 16KB CAAM(JR2)
4047_0000 4047_3FFF 16KB CAAM(JR2)
4046_C000 4046_FFFF 16KB CAAM(JR1)
4046_8000 4046_BFFF 16KB CAAM(JR1)
4046_4000 4046_7FFF 16KB CAAM(JR1)
4046_0000 4046_3FFF 16KB CAAM(JR1)
4045_C000 4045_FFFF 16KB CAAM(JR0)
4045_8000 4045_BFFF 16KB CAAM(JR0)
4045_4000 4045_7FFF 16KB CAAM(JR0)
4045_0000 4045_3FFF 16KB CAAM(JR0)
4044_C000 4044_FFFF 16KB CAAM(General)
4044_8000 4044_BFFF 16KB CAAM(General)
4044_4000 4044_7FFF 16KB CAAM(General)
4044_0000 4044_3FFF 16KB CAAM(General)
4043_C000 4043_FFFF 16KB ENET_QOS
4043_8000 4043_BFFF 16KB USBPHY2
4043_4000 4043_7FFF 16KB USBPHY1
4043_0000 4043_3FFF 16KB USB OTG1
4042_C000 4042_FFFF 16KB USB OTG2
4042_8000 4042_BFFF 16KB Reserved
4042_4000 4042_7FFF 16KB ENET
4042_0000 4042_3FFF 16KB ENET_1G
4041_C000 4041_FFFF 16KB USDHC2
4041_8000 4041_BFFF 16KB USDHC1
4041_4000 4041_7FFF 16KB ASRC
4041_0000 4041_3FFF 16KB Reserved
4040_C000 4040_FFFF 16KB SAI3
4040_8000 4040_BFFF 16KB SAI2
4040_4000 4040_7FFF 16KB SAI1
4040_0000 4040_3FFF 16KB SPDIF
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AIPS-3 Memory Map
3.6 AIPS-3 Memory Map
The table below shows the AIPS-3 memory map (This memory map applies to CM4 and
CM7):
Table 3-5. AIPS-3 memory map
Start Address End Address Size NIC Port
40B0_0000 40BF_FFFF 1MB Reserved
40A0_0000 40AF_FFFF 1MB Reserved
4081_C000 4081_FFFF 16KB Reserved
4081_8000 4081_BFFF 16KB VIDEO_MUX
4081_4000 4081_7FFF 16KB PXP
4081_0000 4081_3FFF 16KB MIPI_CSI
4080_C000 4080_FFFF 16KB MIPI_DSI
4080_8000 4080_BFFF 16KB LCDIFv2
4080_4000 4080_7FFF 16KB eLCDIF
4080_0000 4080_3FFF 16KB CSI
3.7 AIPS-4 Memory Map
The table below shows the AIPS-4 memory map (This memory map applies to CM4 and
CM7):
Table 3-6. AIPS-4 memory map
Start Address End Address Size NIC Port
40F0_0000 40FF_FFFF 1MB Reserved
40E0_0000 40EF_FFFF 1MB Reserved
40CF_0000 40DF_FFFF 1088KB Reserved
40CE_C000 40CE_FFFF 16KB XRDC2 MGR M7
40CE_8000 40CE_BFFF 16KB XRDC2 MGR M7
40CE_4000 40CE_7FFF 16KB XRDC2 MGR M7
40CE_0000 40CE_3FFF 16KB XRDC2 MGR M7
40CD_C000 40CD_FFFF 16KB XRDC2 MGR M4
40CD_8000 40CD_BFFF 16KB XRDC2 MGR M4
40CD_4000 40CD_7FFF 16KB XRDC2 MGR M4
40CD_0000 40CD_3FFF 16KB XRDC2 MGR M4
40CC_C000 40CC_FFFF 16KB RDC_SEMAPHORE2
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Chapter 3 Memory Maps
Table 3-6. AIPS-4 memory map (continued)
Start Address End Address Size NIC Port
40CC_8000 40CC_BFFF 16KB SEMA4
40CC_0000 40CC_7FFF 32KB CCM
40CB_C000 40CB_FFFF 16KB Reserved
40CB_8000 40CB_BFFF 16KB SSARC_LP
40CB_4000 40CB_7FFF 16KB SSARC_HP (SRAM)
40CB_0000 40CB_3FFF 16KB PIT2
40CA_C000 40CA_FFFF 16KB OCOTP
40CA_8000 40CA_BFFF 16KB DCDC
40CA_4000 40CA_7FFF 16KB ROMCP
40CA_0000 40CA_3FFF 16KB GPIO13
40C9_C000 40C9_FFFF 16KB SNVS_SRAM
40C9_8000 40C9_BFFF 16KB IOMUXC_SNVS_GPR
40C9_4000 40C9_7FFF 16KB IOMUXC_SNVS
40C9_0000 40C9_3FFF 16KB SNVS
40C8_C000 40C8_FFFF 16KB Reserved
40C8_8000 40C8_BFFF 16KB PGMC
40C8_4000 40C8_7FFF 16KB ANALOG/ANADIG
40C8_0000 40C8_3FFF 16KB KEYMGR
40C7_C000 40C7_FFFF 16KB Reserved
40C7_8000 40C7_BFFF 16KB RDC
40C7_4000 40C7_7FFF 16KB Reserved
40C7_0000 40C7_3FFF 16KB GPIO12
40C6_C000 40C6_FFFF 16KB GPIO11
40C6_8000 40C6_BFFF 16KB GPIO10
40C6_4000 40C6_7FFF 16KB GPIO9
40C6_0000 40C6_3FFF 16KB GPIO8
40C5_C000 40C5_FFFF 16KB GPIO7
40C5_8000 40C5_BFFF 16KB Reserved
40C5_4000 40C5_7FFF 16KB Reserved
40C5_0000 40C5_3FFF 16KB Reserved
40C4_C000 40C4_FFFF 16KB MU-B
40C4_8000 40C4_BFFF 16KB MU-A
40C4_4000 40C4_7FFF 16KB RDC_SEMAPHORE1
40C4_0000 40C4_3FFF 16KB SAI4
40C3_C000 40C3_FFFF 16KB CAN3
40C3_8000 40C3_BFFF 16KB LPI2C6
40C3_4000 40C3_7FFF 16KB LPI2C5
40C3_0000 40C3_3FFF 16KB LPSPI6
40C2_C000 40C2_FFFF 16KB LPSPI5
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AIPS M7 Memory Map
Table 3-6. AIPS-4 memory map (continued)
Start Address End Address Size NIC Port
40C2_8000 40C2_BFFF 16KB LPUART12
40C2_4000 40C2_7FFF 16KB LPUART11
40C2_0000 40C2_3FFF 16KB PDM
40C1_C000 40C1_FFFF 16KB Reserved
40C1_8000 40C1_BFFF 16KB DMAMUX1 (LPSR)
40C1_4000 40C1_7FFF 16KB EDMA_LPSR
40C1_0000 40C1_3FFF 16KB WDOG4
40C0_C000 40C0_FFFF 16KB IOMUXC_LPSR_GPR
40C0_8000 40C0_BFFF 16KB IOMUXC_LPSR
40C0_4000 40C0_7FFF 16KB SRC
40C0_0000 40C0_3FFF 16KB GPC
3.8 AIPS M7 Memory Map
The table below shows the AIPS M7 memory map:
Table 3-7. AIPS M7 memory map
Start Address End Address Region Size Description
4201_0000 420F_FFFF AIPS M7 960KB Reserved
4200_C000 4200_FFFF 16KB GPIO_M7_3
4200_8000 4200_BFFF 16KB GPIO_M7_2
4200_0000 4200_7FFF 32KB Reserved
3.9 PPB M7 Memory Map
The table below shows the detailed PPB M7 memory map.
Table 3-8. PPB memory map for M7
Start Address End Address Region Size Allocation
E00F_F000 E00F_FFFF M7 Platform 4KB PPB ROM
E00F_E000 E00F_EFFF 4KB Processeor ROM
E00F_D000 E00F_DFFF 4KB SYS ROM
E008_3000 E00F_CFFF 488KB PPB Reserved
E008_2000 E008_2FFF 4KB PPB Reserved
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Chapter 3 Memory Maps
Table 3-8. PPB memory map for M7 (continued)
Start Address End Address Region Size Allocation
E008_1000 E008_1FFF 4KB PPB Reserved
E008_0000 E008_0FFF 4KB MCM
E004_9000 E007_FFFF CSSYS 220KB PPB Reserved
E004_8000 E004_8FFF 4KB CSSYS SWO
E004_7000 E004_7FFF 4KB CSSYS TSGEN
E004_6000 E004_6FFF 4KB CSSYS TPIU
E004_5000 E004_5FFF 4KB CSSYS ATB Funnel
E004_4000 E004_4FFF 4KB CSSYS CTI
E004_3000 E004_3FFF M7 Platform 4KB ATB Funnel
E004_2000 E004_2FFF 4KB CTI
E004_1000 E004_1FFF 4KB ETM
E004_0000 E004_0FFF 4KB PPB RESERVED
E000_0000 E003_FFFF M7 256KB M7 Internal Use
3.10 PPB M4 Memory Map
The table below shows the detailed PPB M4 memory map.
Table 3-9. PPB memory map for M4
Start Address End Address Region Size Allocation
E00F_F000 E00F_FFFF M4 Platform 4KB PPB ROM
E00F_E000 E00F_EFFF 4KB PPB Reserved
E00F_D000 E00F_DFFF 4KB PPB Reserved
E008_3000 E00F_CFFF 488KB PPB Reserved
E008_2000 E008_2FFF 4KB AHB_LMEM
E008_1000 E008_1FFF 4KB MMCAU
E008_0000 E008_0FFF 4KB MCM
E004_9000 E007_FFFF CSSYS 220KB PPB Reserved
E004_8000 E004_8FFF 4KB CSSYS SWO
E004_7000 E004_7FFF 4KB CSSYS TSGEN
E004_6000 E004_6FFF 4KB CSSYS TPIU
E004_5000 E004_5FFF 4KB CSSYS ATB Funnel
E004_4000 E004_4FFF 4KB CSSYS CTI
E004_3000 E004_3FFF M4 Platform 4KB ATB Funnel
E004_2000 E004_2FFF 4KB CTI
E004_1000 E004_1FFF 4KB ETM
E004_0000 E004_0FFF 4KB PPB Reserved
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PPB M4 Memory Map
Table 3-9. PPB memory map for M4 (continued)
Start Address End Address Region Size Allocation
E000_0000 E003_FFFF M4 256KB M4 Internal Use
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Chapter 4
Interrupts, DMA Events, and XBAR Assignments
4.1 Overview
This section describes the Interrupt assignments, DMA events, and XBAR resource
assignments.
4.2 CM7 interrupts
The Nested Vectored Interrupt Controller (NVIC) collects interrupt request sources and
provides an interface to the Cortex-M7 core.
The table below describes the Cortex-M7 interrupt sources:
Table 4-1. CM7 domain interrupt summary
IRQ Interrupt Source LOGIC Description
0 EDMA OR eDMA Channel 0 Transfer
Complete
0 OR eDMA Channel 16 Transfer
Complete
1 OR eDMA Channel 1 Transfer
Complete
1 OR eDMA Channel 17 Transfer
Complete
2 OR eDMA Channel 2 Transfer
Complete
2 OR eDMA Channel 18 Transfer
Complete
3 OR eDMA Channel 3 Transfer
Complete
3 OR eDMA Channel 19 Transfer
Complete
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
4 OR eDMA Channel 4 Transfer
Complete
4 OR eDMA Channel 20 Transfer
Complete
5 OR eDMA Channel 5 Transfer
Complete
5 OR eDMA Channel 21 Transfer
Complete
6 OR eDMA Channel 6 Transfer
Complete
6 OR eDMA Channel 22 Transfer
Complete
7 OR eDMA Channel 7 Transfer
Complete
7 OR eDMA Channel 23 Transfer
Complete
8 OR eDMA Channel 8 Transfer
Complete
8 OR eDMA Channel 24 Transfer
Complete
9 OR eDMA Channel 9 Transfer
Complete
9 OR eDMA Channel 25 Transfer
Complete
10 OR eDMA Channel 10 Transfer
Complete
10 OR eDMA Channel 26 Transfer
Complete
11 OR eDMA Channel 11 Transfer
Complete
11 OR eDMA Channel 27 Transfer
Complete
12 OR eDMA Channel 12 Transfer
Complete
12 OR eDMA Channel 28 Transfer
Complete
13 OR eDMA Channel 13 Transfer
Complete
13 OR eDMA Channel 29 Transfer
Complete
14 OR eDMA Channel 14 Transfer
Complete
14 OR eDMA Channel 30 Transfer
Complete
15 OR eDMA Channel 15 Transfer
Complete
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
15 OR eDMA Channel 31 Transfer
Complete
16 - Error Interrupt, Channels
0-15 / 16-31
17 CM7 - CTI trigger output0 interrupt
18 - CTI trigger output1 interrupt
19 - Core Platform exception IRQ
20 LPUART1 OR UART1 TX interrupt
20 OR UART1 RX interrupt
20 OR UART1 TX async interrupt
20 OR UART1 RX async interrupt
21 LPUART2 OR UART2 TX interrupt
21 OR UART2 RX interrupt
21 OR UART2 TX async interrupt
21 OR UART2 RX async interrupt
22 LPUART3 OR UART3 TX interrupt
22 OR UART3 RX interrupt
22 OR UART3 TX async interrupt
22 OR UART3 RX async interrupt
23 LPUART4 OR UART4 TX interrupt
23 OR UART4 RX interrupt
23 OR UART4 TX async interrupt
23 OR UART4 RX async interrupt
24 LPUART5 OR UART5 TX interrupt
24 OR UART5 RX interrupt
24 OR UART5 TX async interrupt
24 OR UART5 RX async interrupt
25 LPUART6 OR UART6 TX interrupt
25 OR UART6 RX interrupt
25 OR UART6 TX async interrupt
25 OR UART6 RX async interrupt
26 LPUART7 OR UART7 TX interrupt
26 OR UART7 RX interrupt
26 OR UART7 TX async interrupt
26 OR UART7 RX async interrupt
27 LPUART8 OR UART8 TX interrupt
27 OR UART8 RX interrupt
27 OR UART8 TX async interrupt
27 OR UART8 RX async interrupt
28 LPUART9 OR UART9 TX interrupt
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
28 OR UART9 RX interrupt
28 OR UART9 TX async interrupt
28 OR UART9 RX async interrupt
29 LPUART10 OR UART10 TX interrupt
29 OR UART10 RX interrupt
29 OR UART10 TX async interrupt
29 OR UART10 RX async interrupt
30 LPUART11 OR UART11 TX interrupt
30 OR UART11 RX interrupt
30 OR UART11 TX async interrupt
30 OR UART11 RX async interrupt
31 LPUART12 OR UART12 TX interrupt
31 OR UART12 RX interrupt
31 OR UART12 TX async interrupt
31 OR UART12 RX async interrupt
32 LPI2C1 OR LPI2C1 interrupt master
async
32 OR LPI2C1 interrupt slave async
32 OR LPI2C1 interrupt master
32 OR LPI2C1 interrupt slave
33 LPI2C2 OR LPI2C2 interrupt master
async
33 OR LPI2C2 interrupt slave async
33 OR LPI2C2 interrupt master
33 OR LPI2C2 interrupt slave
34 LPI2C3 OR LPI2C3 interrupt master
async
34 OR LPI2C3 interrupt slave async
34 OR LPI2C3 interrupt master
34 OR LPI2C3 interrupt slave
35 LPI2C4 OR LPI2C4 interrupt master
async
35 OR LPI2C4 interrupt slave async
35 OR LPI2C4 interrupt master
35 OR LPI2C5 interrupt slave
36 LPI2C5 OR LPI2C5 interrupt master
async
36 OR LPI2C5 interrupt slave async
36 OR LPI2C5 interrupt master
36 OR LPI2C5 interrupt slave
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
37 LPI2C6 OR LPI2C6 interrupt master
async
37 OR LPI2C6 interrupt slave async
37 OR LPI2C6 interrupt master
37 OR LPI2C6 interrupt slave
38 LPSPI1 - LPSPI1 interrupt request
39 LPSPI2 - LPSPI2 interrupt request
40 LPSPI3 - LPSPI3 interrupt request
41 LPSPI4 - LPSPI4 interrupt request
42 LPSPI5 - LPSPI5 interrupt request
43 LPSPI6 - LPSPI6 interrupt request
44 CAN1 OR Interrupt from Bus off
44 OR Interrupt from CAN line error
44 OR ORed interrupts from
ipi_int_MB
44 OR Rx warning interrupt
44 OR Tx warning interrupt
44 OR Interrupt from wake up
44 OR Bus off done interrupt
44 OR FD error interrupt
45 OR Correctable error interrupt
45 OR Non correctable error int host
45 OR Non correctable error int
internal
46 CAN2 OR Interrupt from Bus off
46 OR Interrupt from CAN line error
46 OR ORed interrupts from
ipi_int_MB
46 OR Rx warning interrupt
46 OR Tx warning interrupt
46 OR Interrupt from wake up
46 OR Bus off done interrupt
46 OR FD error interrupt
47 OR Correctable error interrupt
47 OR Non correctable error int host
47 OR Non correctable error int
internal
48 CAN3 OR Interrupt from Bus off
48 OR Interrupt from CAN line error
48 OR ORed interrupts from
ipi_int_MB
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
48 OR Rx warning interrupt
48 OR Tx warning interrupt
48 OR Interrupt from wake up
48 OR Bus off done interrupt
48 OR FD error interrupt
49 OR Correctable error interrupt
49 OR Non correctable error int host
49 OR Non correctable error int
internal
50 FlexRAM - FlexRAM address out of
range or access hit IRQ
51 KPP - Keypad Interrupt
52 Reserved - N/A
53 GPR_IRQ - SW interrupt
IOMUXC_GPR_GPR7[GINT]
54 eLCDIF - eLCDIF Interrupt
55 LCDIFv2 - LCDIFv2 Interrupt
56 CSI - CSI interrupt
57 PXP - PXP interrupt
58 MIPI_CSI - MIPI CSI interrupt
59 MIPI_DSI - MIPI DSI interrupt
60 GPU2D - GPU2D interrupt
61 GPIO6 - Combined interrupt indication
for GPIO6 signal 0 through 15
62 GPIO6 - Combined interrupt indication
for GPIO6 signal 16 through
31
63 DAC OR DAC interrupt
63 OR DAC async interrupt
64 KEYMGR - PUF interrupt
65 WDOG2 - Watchdog2 Timer reset
66 SNVS_HP - SRTC Consolidated Interrupt.
Non TZ.
67 - SRTC Security Interrupt. TZ.
68 SNVS_LP OR ON-OFF button press shorter
than 5 secs (pulse event)
68 SNVS_HP OR ON-OFF button press shorter
than 5 secs (pulse event)
69 CAAM - CAAM interrupt queue for JQ0
70 - CAAM interrupt queue for JQ1
71 - CAAM interrupt queue for JQ2
72 - CAAM interrupt queue for JQ3
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
73 - CAAM interrupt for
recoverable error
74 - CAAM interrupt for RTIC
75 CDOG - CDOG interrupt
76 SAI1 OR SAI RX interrupt
76 OR SAI RX async interrupt
76 OR SAI TX interrupt
76 OR SAI TX async interrupt
77 SAI2 OR SAI RX interrupt
77 OR SAI RX async interrupt
77 OR SAI TX interrupt
77 OR SAI TX async interrupt
78 SAI3 - SAI RX interrupt
79 - SAI TX interrupt
80 SAI4 - SAI RX interrupt
81 - SAI TX interrupt
82 SPDIF OR SPDIF RX interrupt
82 OR SPDIF TX interrupt
83 TMPSNS (Temperature - Global Ored interrupt of all
Sensor) TMPSNS individual interrupts
84 TMPSNS (Temperature OR TempSensor low
Sensor)
84 OR TempSensor high
85 - TempSensor panic
86 PMU - LPSR 1p8 brownout interrupt
87 - LPSR 1p0 brownout interrupt
88 LPADC1 OR ADC1 interrupt
88 OR ADC1 async interrupt
89 LPADC2 OR ADC2 interrupt
89 OR ADC2 async interrupt
90 USBPHY1 - USB1 wakeup interrupt when
USB1 core is power down
91 USBPHY2 - USB2 wakeup interrupt when
USB2 core is power down
92 RDC - RDC reconfiguration complete
interrupt
93 GPIO13 - Combined interrupt indication
for GPIO13 signal 0 through
31
94 Reserved - -
95 VIDEO_MUX OR DCIC1 Error Interrupt
95 OR DCIC1 Function Interrupt
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
96 OR DCIC2 Error Interrupt
96 OR DCIC2 Function Interrupt
97 ASRC - ASRC interrupt
98 CM7 - FlexRAM ECC fatal interrupt
99 CM7_GPIO2 OR Combined interrupt indication
for CM7_GPIO2 signal 0
through 31
99 CM7_GPIO3 OR Combined interrupt indication
for CM7_GPIO3 signal 0
through 31
100 GPIO1 - Combined interrupt indication
for GPIO1 signal 0 through 15
101 - Combined interrupt indication
for GPIO1 signal 16 through
31
102 GPIO2 - Combined interrupt indication
for GPIO2 signal 0 through 15
103 - Combined interrupt indication
for GPIO2 signal 16 through
31
104 GPIO3 - Combined interrupt indication
for GPIO3 signal 0 through 15
105 - Combined interrupt indication
for GPIO3 signal 16 through
31
106 GPIO4 - Combined interrupt indication
for GPIO4 signal 0 through 15
107 - Combined interrupt indication
for GPIO4 signal 16 through
31
108 GPIO5 - Combined interrupt indication
for GPIO5 signal 0 through 15
109 - Combined interrupt indication
for GPIO5 signal 16 through
31
110 FLEXIO1 OR IPI compare interrupt
110 OR IPI async compare interrupt
111 FLEXIO2 OR IPI compare interrupt
111 OR IPI async compare interrupt
112 WDOG1 - Watchdog1 Timer reset
113 WDOG3 OR Watchdog3 Timer reset
113 OR Watchdog Timer Async reset
114 EWM - EWM interrupt
115 OCOTP - Read FUSE error interrupt
116 - Read FUSE done interrupt
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
117 GPC - GPC interrupt
118 MU - ORed of all (tx,rx and gp)
interrupt
119 GPT1 - All GPT1 interrupts
120 GPT2 - All GPT2 interrupts
121 GPT3 - All GPT3 interrupts
122 GPT4 - All GPT4 interrupts
123 GPT5 - All GPT5 interrupts
124 GPT6 - All GPT6 interrupts
125 FLEXPWM1 OR capture 0 interrupt
125 OR compare 0 interrupt
125 OR reload 0 interrupt
126 OR capture 1 interrupt
126 OR compare 1 interrupt
126 OR reload 1 interrupt
127 OR capture 2 interrupt
127 OR compare 2 interrupt
127 OR reload 2 interrupt
128 OR capture 3 interrupt
128 OR compare 3 interrupt
128 OR reload 3 interrupt
129 OR fault interrupt
129 OR reload error interrupt
130 FLEXSPI1 - FlexSPI1 interrupt
131 FLEXSPI2 - FlexSPI2 interrupt
132 SEMC - SEMC interrupt
133 USDHC1 - uSDHC1 Enhanced SDHC
Interrupt Request
134 USDHC2 - uSDHC2 Enhanced SDHC
Interrupt Request
135 USB OTG2 - USB OTG2 interrupt
136 USB OTG1 - USB OTG1 interrupt
137 ENET OR MAC 0 Periodic Timer
Overflow
137 OR MAC 0 Time Stamp Available
137 OR MAC 0 Payload Receive Error
137 OR MAC 0 Transmit FIFO
Underrun
137 OR MAC 0 Collision Retry Limit
137 OR MAC 0 Late Collision
137 OR MAC 0 Ethernet Bus Error
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
137 OR MAC 0 MII Data Transfer
Done
137 OR MAC 0 Receive Buffer Done
137 OR MAC 0 Receive Frame Done
137 OR MAC 0 Transmit Buffer Done
137 OR MAC 0 Transmit Frame Done
137 OR MAC 0 Graceful Stop
137 OR MAC 0 Babbling Transmit
Error
137 OR MAC 0 Babbling Receive
Error
137 OR MAC 0 Wakeup Request
(sync)
137 OR MAC 0 Wakeup Request
(async)
138 - MAC 0 1588 Timer Interrupt –
synchronous
139 ENET_1G OR MAC 0 Receive Buffer Done
139 OR MAC 0 Receive Frame Done
139 OR MAC 0 Transmit Buffer Done
139 OR MAC 0 Transmit Frame Done
140 OR MAC 0 Receive Buffer Done
140 OR MAC 0 Receive Frame Done
140 OR MAC 0 Transmit Buffer Done
140 OR MAC 0 Transmit Frame Done
141 OR MAC 0 Periodic Timer
Overflow
141 OR MAC 0 Time Stamp Available
141 OR MAC 0 Payload Receive Error
141 OR MAC 0 Transmit FIFO
Underrun
141 OR MAC 0 Collision Retry Limit
141 OR MAC 0 Late Collision
141 OR MAC 0 Ethernet Bus Error
141 OR MAC 0 MII Data Transfer
Done
141 OR MAC 0 Receive Buffer Done
141 OR MAC 0 Receive Frame Done
141 OR MAC 0 Transmit Buffer Done
141 OR MAC 0 Transmit Frame Done
141 OR MAC 0 Graceful Stop
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
141 OR MAC 0 Babbling Transmit
Error
141 OR MAC 0 Babbling Receive
Error
141 OR MAC 0 Receive Flush Frame0
141 OR MAC 0 Receive Flush Frame1
141 OR MAC 0 Receive Flush Frame2
141 OR MAC 0 Wakeup Request
(sync)
141 OR MAC 0 Wakeup Request
(async)
141 OR MAC 0 Babbling Receive
Error
141 OR MAC 0 Wakeup Request (err)
142 - MAC 0 1588 Timer Interrupt –
synchronous
143 XBAR1 OR XBAR IRQ (XBAR_OUT0)
143 OR XBAR IRQ (XBAR_OUT1)
144 OR XBAR IRQ (XBAR_OUT2)
144 OR XBAR IRQ (XBAR_OUT3)
145 ADC_ETC - ADC_ETC done0 interrupt
146 - ADC_ETC done1 interrupt
147 - ADC_ETC done2 interrupt
148 - ADC_ETC done3 interrupt
149 - ADC_ETC err interrupt
150 Reserved - N/A
150 Reserved - N/A
150 Reserved - N/A
151 Reserved - N/A
151 Reserved - N/A
151 Reserved - N/A
152 Reserved - N/A
152 Reserved - N/A
152 Reserved - N/A
153 Reserved - N/A
153 Reserved - N/A
153 Reserved - N/A
154 Reserved - N/A
154 Reserved - N/A
155 PIT1 OR PIT1 channel 0 interrupt
155 OR PIT1 channel 1 interrupt
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
155 OR PIT1 channel 2 interrupt
155 OR PIT1 channel 3 interrupt
156 PIT2 OR PIT2 channel 0 interrupt
156 OR PIT2 channel 1 interrupt
156 OR PIT2 channel 2 interrupt
156 OR PIT2 channel 3 interrupt
157 ACMP1 OR ACMP1 interrupt
157 OR ACMP1 async interrupt for
STOP mode wake up
158 ACMP2 OR ACMP2 interrupt
158 OR ACMP2 async interrupt for
STOP mode wake up
159 ACMP3 OR ACMP3 interrupt
159 OR ACMP3 async interrupt for
STOP mode wake up
160 ACMP4 OR ACMP4 interrupt
160 OR ACMP4 async interrupt for
STOP mode wake up
161 Reserved - N/A
162 Reserved - N/A
163 Reserved - N/A
164 Reserved - N/A
165 QDC1 OR Index marker interrupt
165 OR Home marker interrupt
165 OR Watchdog timeout interrupt
165 OR Compare interrupt
165 OR Simultaneous input switching
interrupt
166 QDC2 OR Index marker interrupt
166 OR Home marker interrupt
166 OR Watchdog timeout interrupt
166 OR Compare interrupt
166 OR Simultaneous input switching
interrupt
167 QDC3 OR Index marker interrupt
167 OR Home marker interrupt
167 OR Watchdog timeout interrupt
167 OR Compare interrupt
167 OR Simultaneous input switching
interrupt
168 QDC4 OR Index marker interrupt
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
168 OR Home marker interrupt
168 OR Watchdog timeout interrupt
168 OR Compare interrupt
168 OR Simultaneous input switching
interrupt
169 Reserved - N/A
170 Reserved - N/A
171 TMR1 OR Interrupt request for timer #0
171 OR Interrupt request for timer #1
171 OR Interrupt request for timer #2
171 OR Interrupt request for timer #3
172 TMR2 OR Interrupt request for timer #0
172 OR Interrupt request for timer #1
172 OR Interrupt request for timer #2
172 OR Interrupt request for timer #3
173 TMR3 OR Interrupt request for timer #0
173 OR Interrupt request for timer #1
173 OR Interrupt request for timer #2
173 OR Interrupt request for timer #3
174 TMR4 OR Interrupt request for timer #0
174 OR Interrupt request for timer #1
174 OR Interrupt request for timer #2
174 OR Interrupt request for timer #3
175 SEMA4 - SEMA4 CP0 interrupt
176 - SEMA CP1 interrupt
177 FLEXPWM2 OR capture 0 interrupt
177 OR compare 0 interrupt
177 OR reload 0 interrupt
178 OR capture 1 interrupt
178 OR compare 1 interrupt
178 OR reload 1 interrupt
179 OR capture 2 interrupt
179 OR compare 2 interrupt
179 OR reload 2 interrupt
180 OR capture 3 interrupt
180 OR compare 3 interrupt
180 OR reload 3 interrupt
181 OR fault interrupt
181 OR reload error interrupt
182 FLEXPWM3 OR capture 0 interrupt
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CM7 interrupts
Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
182 OR compare 0 interrupt
182 OR reload 0 interrupt
183 OR capture 1 interrupt
183 OR compare 1 interrupt
183 OR reload 1 interrupt
184 OR capture 2 interrupt
184 OR compare 2 interrupt
184 OR reload 2 interrupt
185 OR capture 3 interrupt
185 OR compare 3 interrupt
185 OR reload 3 interrupt
186 OR fault interrupt
186 OR reload error interrupt
187 FLEXPWM4 OR capture 0 interrupt
187 OR compare 0 interrupt
187 OR reload 0 interrupt
188 OR capture 1 interrupt
188 OR compare 1 interrupt
188 OR reload 1 interrupt
189 OR capture 2 interrupt
189 OR compare 2 interrupt
189 OR reload 2 interrupt
190 OR capture 3 interrupt
190 OR compare 3 interrupt
190 OR reload 3 interrupt
191 OR fault interrupt
191 OR reload error interrupt
192 Reserved - N/A
193 Reserved - N/A
194 Reserved - N/A
195 Reserved - N/A
196 Reserved - N/A
197 Reserved - N/A
198 Reserved - N/A
199 Reserved - N/A
200 PDM OR HWVAD event interrupt
200 OR HWVAD event async interrupt
201 OR HWVAD error interrupt
201 OR HWVAD error async interrupt
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Table 4-1. CM7 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Description
202 OR filter interrupt
202 OR filter async interrupt
203 OR error interrupt
203 OR error async interrupt
204 EMVSIM1 OR EMVSIM1 interrupt (data_irq)
204 OR EMVSIM1 interrupt
205 EMVSIM2 OR EMVSIM2 interrupt (data_irq)
205 OR EMVSIM2 interrupt
206 MECC1 - MECC1 interrupt
207 MECC1 - MECC1 fatal interrupt
208 MECC2 - MECC2 interrupt
209 MECC2 - MECC2 fatal interrupt
210 XECC_FLEXSPI1 - XECC_FLEXSPI1 interrupt
211 XECC_FLEXSPI1 - XECC_FLEXSPI1 fatal
interrupt
212 XECC_FLEXSPI2 - XECC_FLEXSPI2 interrupt
213 XECC_FLEXSPI2 - XECC_FLEXSPI2 fatal
interrupt
214 XECC_SEMC - XECC_SEMC interrupt
215 XECC_SEMC - XECC_SEMC fatal interrupt
216 ENET_QOS OR LPI Rx exit interrupt output
216 OR Interrupt signal to host system
216 OR Channel 0 Transmit Interrupt
signal to host system
216 OR Channel 1 Transmit Interrupt
signal to host system
216 OR Channel 2 Transmit Interrupt
signal to host system
216 OR Channel 3 Transmit Interrupt
signal to host system
216 OR Channel 4 Transmit Interrupt
signal to host system
216 OR Channel 0 Receive Interrupt
signal to host system
216 OR Channel 1 Receive Interrupt
signal to host system
216 OR Channel 2 Receive Interrupt
signal to host system
216 OR Channel 3 Receive Interrupt
signal to host system
216 OR Channel 4 Receive Interrupt
signal to host system
217 - Interrupt from PMT
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CM4 interrupts
4.3 CM4 interrupts
The Nested Vectored Interrupt Controller (NVIC) collects up to 218 interrupt requests
from all i.MX sources and provides an interface to the Cortex M4 core.
The table below describes the M4 interrupt sources:
Table 4-2. CM4 domain interrupt summary
IRQ Interrupt Source LOGIC Interrupt Description
0 EDMA_LPSR OR eDMA_LPSR Channel 0
Transfer Complete
0 OR eDMA_LPSR Channel 16
Transfer Complete
1 OR eDMA_LPSR Channel 1
Transfer Complete
1 OR eDMA_LPSR Channel 17
Transfer Complete
2 OR eDMA_LPSR Channel 2
Transfer Complete
2 OR eDMA_LPSR Channel 18
Transfer Complete
3 OR eDMA_LPSR Channel 3
Transfer Complete
3 OR eDMA_LPSR Channel 19
Transfer Complete
4 OR eDMA_LPSR Channel 4
Transfer Complete
4 OR eDMA_LPSR Channel 20
Transfer Complete
5 OR eDMA_LPSR Channel 5
Transfer Complete
5 OR eDMA_LPSR Channel 21
Transfer Complete
6 OR eDMA_LPSR Channel 6
Transfer Complete
6 OR eDMA_LPSR Channel 22
Transfer Complete
7 OR eDMA_LPSR Channel 7
Transfer Complete
7 OR eDMA_LPSR Channel 23
Transfer Complete
8 OR eDMA_LPSR Channel 8
Transfer Complete
8 OR eDMA_LPSR Channel 24
Transfer Complete
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
9 OR eDMA_LPSR Channel 9
Transfer Complete
9 OR eDMA_LPSR Channel 25
Transfer Complete
10 OR eDMA_LPSR Channel 10
Transfer Complete
10 OR eDMA_LPSR Channel 26
Transfer Complete
11 OR eDMA_LPSR Channel 11
Transfer Complete
11 OR eDMA_LPSR Channel 27
Transfer Complete
12 OR eDMA_LPSR Channel 12
Transfer Complete
12 OR eDMA_LPSR Channel 28
Transfer Complete
13 OR eDMA_LPSR Channel 13
Transfer Complete
13 OR eDMA_LPSR Channel 29
Transfer Complete
14 OR eDMA_LPSR Channel 14
Transfer Complete
14 OR eDMA_LPSR Channel 30
Transfer Complete
15 OR eDMA_LPSR Channel 15
Transfer Complete
15 OR eDMA_LPSR Channel 31
Transfer Complete
16 - Error Interrupt, Channels
0-15 / 16-31
17 Reserved - N/A
18 Reserved - N/A
19 CM4 - CorePlatform exception IRQ
20 LPUART1 OR UART1 TX interrupt
20 OR UART1 RX interrupt
20 OR UART1 TX async interrupt
20 OR UART1 RX async interrupt
21 LPUART2 OR UART2 TX interrupt
21 OR UART2 RX interrupt
21 OR UART2 TX async interrupt
21 OR UART2 RX async interrupt
22 LPUART3 OR UART3 TX interrupt
22 OR UART3 RX interrupt
22 OR UART3 TX async interrupt
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
22 OR UART3 RX async interrupt
23 LPUART4 OR UART4 TX interrupt
23 OR UART4 RX interrupt
23 OR UART4 TX async interrupt
23 OR UART4 RX async interrupt
24 LPUART5 OR UART5 TX interrupt
24 OR UART5 RX interrupt
24 OR UART5 TX async interrupt
24 OR UART5 RX async interrupt
25 LPUART6 OR UART6 TX interrupt
25 OR UART6 RX interrupt
25 OR UART6 TX async interrupt
25 OR UART6 RX async interrupt
26 LPUART7 OR UART7 TX interrupt
26 OR UART7 RX interrupt
26 OR UART7 TX async interrupt
26 OR UART7 RX async interrupt
27 LPUART8 OR UART8 TX interrupt
27 OR UART8 RX interrupt
27 OR UART8 TX async interrupt
27 OR UART8 RX async interrupt
28 LPUART9 OR UART9 TX interrupt
28 OR UART9 RX interrupt
28 OR UART9 TX async interrupt
28 OR UART9 RX async interrupt
29 LPUART10 OR UART10 TX interrupt
29 OR UART10 RX interrupt
29 OR UART10 TX async interrupt
29 OR UART10 RX async interrupt
30 LPUART11 OR UART11 TX interrupt
30 OR UART11 RX interrupt
30 OR UART11 TX async interrupt
30 OR UART11 RX async interrupt
31 LPUART12 OR UART12 TX interrupt
31 OR UART12 RX interrupt
31 OR UART12 TX async interrupt
31 OR UART12 RX async interrupt
32 LPI2C1 OR LPI2C1 interrupt master
async
32 OR LPI2C1 interrupt slave async
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
32 OR LPI2C1 interrupt master
32 OR LPI2C1 interrupt slave
33 LPI2C2 OR LPI2C2 interrupt master
async
33 OR LPI2C2 interrupt slave async
33 OR LPI2C2 interrupt master
33 OR LPI2C2 interrupt slave
34 LPI2C3 OR LPI2C3 interrupt master
async
34 OR LPI2C3 interrupt slave async
34 OR LPI2C3 interrupt master
34 OR LPI2C3 interrupt slave
35 LPI2C4 OR LPI2C4 interrupt master
async
35 OR LPI2C4 interrupt slave async
35 OR LPI2C4 interrupt master
35 OR LPI2C5 interrupt slave
36 LPI2C5 OR LPI2C5 interrupt master
async
36 OR LPI2C5 interrupt slave async
36 OR LPI2C5 interrupt master
36 OR LPI2C5 interrupt slave
37 LPI2C6 OR LPI2C6 interrupt master
async
37 OR LPI2C6 interrupt slave async
37 OR LPI2C6 interrupt master
37 OR LPI2C6 interrupt slave
38 LPSPI1 - LPSPI1 interrupt request
39 LPSPI2 - LPSPI2 interrupt request
40 LPSPI3 - LPSPI3 interrupt request
41 LPSPI4 - LPSPI4 interrupt request
42 LPSPI5 - LPSPI5 interrupt request
43 LPSPI6 - LPSPI6 interrupt request
44 CAN1 OR Interrupt from Bus off
44 OR Interrupt from CAN line error
44 OR Ored interrupts from
ipi_int_MB
44 OR Rx warning interrupt
44 OR Tx warning interrupt
44 OR Interrupt from wake up
44 OR Bus off done interrupt
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
44 OR FD error interrupt
45 OR Correctable error interrupt
45 OR Non correctable error int host
45 OR Non correctable error int
internal
46 CAN2 OR Interrupt from Bus off
46 OR Interrupt from CAN line error
46 OR Ored interrupts from
ipi_int_MB
46 OR Rx warning interrupt
46 OR Tx warning interrupt
46 OR Interrupt from wake up
46 OR Bus off done interrupt
46 OR FD error interrupt
47 OR Correctable error interrupt
47 OR Non correctable error int host
47 OR Non correctable error int
internal
48 CAN3 OR Interrupt from Bus off
48 OR Interrupt from CAN line error
48 OR Ored interrupts from
ipi_int_MB
48 OR Rx warning interrupt
48 OR Tx warning interrupt
48 OR Interrupt from wake up
48 OR Bus off done interrupt
48 OR FD error interrupt
49 OR Correctable error interrupt
49 OR Non correctable error int host
49 OR Non correctable error int
internal
50 Reserved - N/A
51 KPP - Keypad Interrupt
52 Reserved - N/A
53 GPR_IRQ - SW interrupt
IOMUXC_GPR_GPR7[GINT]
54 eLCDIF - eLCDIF Interrupt
55 LCDIFv2 - LCDIFv2 Interrupt
56 CSI - CSI interrupt
57 PXP - PXP interrupt
58 MIPI_CSI - MIPI CSI interrupt
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
59 MIPI_DSI - MIPI DSI interrupt
60 GPU2D - GPU2D interrupt
61 GPIO12 - Combined interrupt indication
for GPIO12 signal 0 through
15
62 GPIO12 - Combined interrupt indication
for GPIO12 signal 16 through
31
63 DAC OR DAC interrupt
63 OR DAC async interrupt
64 KEYMGR - PUF interrupt
65 WDOG2 - Watchdog2 Timer reset
66 SNVS_HP - SRTC Consolidated Interrupt.
Non TZ.
67 - SRTC Security Interrupt. TZ.
68 SNVS_LP OR ON-OFF button press (source
SPOF)
68 SNVS_HP OR ON-OFF button press (source
BI)
69 CAAM - CAAM interrupt queue for JQ0
70 - CAAM interrupt queue for JQ1
71 - CAAM interrupt queue for JQ2
72 - CAAM interrupt queue for JQ3
73 - CAAM interrupt for
recoverable error
74 - CAAM interrupt for RTIC
75 CDOG - CDOG interrupt
76 SAI1 OR SAI RX interrupt
76 OR SAI RX async interrupt
76 OR SAI TX interrupt
76 OR SAI TX async interrupt
77 SAI2 OR SAI RX interrupt
77 OR SAI RX async interrupt
77 OR SAI TX interrupt
77 OR SAI TX async interrupt
78 SAI3 - SAI RX interrupt
79 - SAI TX interrupt
80 SAI4 - SAI RX interrupt
81 - SAI TX interrupt
82 SPDIF OR SPDIF Rx interrupt
82 OR SPDIF Tx interrupt
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
83 TMPSNS (Temperature - Global ORed interrupt of all
Sensor) Tempsense individual
interrupts
84 TMPSNS (Temperature OR TempSensor low
Sensor)
84 OR TempSensor high
85 - TempSensor panic
86 PMU - LPSR 1p8 brownout interrupt
87 - LPSR 1p0 brownout interrupt
88 LPADC1 OR ADC1 interrupt
88 OR ADC1 async interrupt
89 LPADC2 OR ADC2 interrupt
89 OR ADC2 async interrupt
90 USBPHY1 - USB1 wakeup interrupt when
USB1 core is powered down
91 USBPHY2 - USB2 wakeup interrupt when
USB2 core is powered down
92 RDC - RDC reconfiguration complete
interrupt
93 GPIO13 - Combined interrupt indication
for GPIO13 signal 0 through
31
94 Reserved - -
95 VIDEO_MUX OR DCIC1 Error Interrupt
95 OR DCIC1 Function Interrupt
96 OR DCIC2 Error Interrupt
96 OR DCIC2 Function Interrupt
97 ASRC - ASRC interrupt
98 CM7_IMXRT - FlexRAM ECC fatal interrupt
99 GPIO7 OR Combined interrupt indication
for GPIO7 signal 0 through 31
99 GPIO8 OR Combined interrupt indication
for GPIO8 signal 0 through 31
99 GPIO9 OR Combined interrupt indication
for GPIO9 signal 0 through 31
99 GPIO10 OR Combined interrupt indication
for GPIO10 signal 0 through
31
99 GPIO11 OR Combined interrupt indication
for GPIO11 signal 0 through
31
100 GPIO1 - Combined interrupt indication
for GPIO1 signal 0 through 15
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
101 - Combined interrupt indication
for GPIO1 signal 16 through
31
102 GPIO2 - Combined interrupt indication
for GPIO2 signal 0 through 15
103 - Combined interrupt indication
for GPIO2 signal 16 through
31
104 GPIO3 - Combined interrupt indication
for GPIO3 signal 0 through 15
105 - Combined interrupt indication
for GPIO3 signal 16 through
31
106 GPIO4 - Combined interrupt indication
for GPIO4 signal 0 through 15
107 - Combined interrupt indication
for GPIO4 signal 16 through
31
108 GPIO5 - Combined interrupt indication
for GPIO5 signal 0 through 15
109 - Combined interrupt indication
for GPIO5 signal 16 through
31
110 FLEXIO1 OR IPI compare interrupt
110 OR IPI async compare interrupt
111 FLEXIO2 OR IPI compare interrupt
111 OR IPI async compare interrupt
112 WDOG1 - Watchdog1 Timer reset
113 WDOG4 OR Watchdog4 Timer reset
113 OR Watchdog4 Timer Async reset
114 EWM - EWM IRQ
115 OCOTP - Read FUSE error interrupt
116 - Read FUSE done interrupt
117 GPC - GPC interrupt
118 MU - ORed of all (tx,rx and gp)
interrupt
119 GPT1 - All GPT1 interrupts
120 GPT2 - All GPT2 interrupts
121 GPT3 - All GPT3 interrupts
122 GPT4 - All GPT4 interrupts
123 GPT5 - All GPT5 interrupts
124 GPT6 - All GPT6 interrupts
125 FLEXPWM1 OR capture 0 interrupt
125 OR compare 0 interrupt
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
125 OR reload 0 interrupt
126 OR capture 1 interrupt
126 OR compare 1 interrupt
126 OR reload 1 interrupt
127 OR capture 2 interrupt
127 OR compare 2 interrupt
127 OR reload 2 interrupt
128 OR capture 3 interrupt
128 OR compare 3 interrupt
128 OR reload 3 interrupt
129 OR fault interrupt
129 OR reload error interrupt
130 FLEXSPI1 - FlexSPI1 interrupt
131 FLEXSPI2 - FlexSPI2 interrupt
132 SEMC - SEMC interrupt
133 USDHC1 - uSDHC1 Enhanced SDHC
Interrupt Request
134 USDHC2 - uSDHC2 Enhanced SDHC
Interrupt Request
135 USB OTG2 - USB OTG2 interrupt
136 USB OTG1 - USB OTG1 interrupt
137 ENET OR MAC 0 Periodic Timer
Overflow
137 OR MAC 0 Time Stamp Available
137 OR MAC 0 Payload Receive Error
137 OR MAC 0 Transmit FIFO
Underrun
137 OR MAC 0 Collision Retry Limit
137 OR MAC 0 Late Collision
137 OR MAC 0 Ethernet Bus Error
137 OR MAC 0 MII Data Transfer
Done
137 OR MAC 0 Receive Buffer Done
137 OR MAC 0 Receive Frame Done
137 OR MAC 0 Transmit Buffer Done
137 OR MAC 0 Transmit Frame Done
137 OR MAC 0 Graceful Stop
137 OR MAC 0 Babbling Transmit
Error
137 OR MAC 0 Babbling Receive
Error
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
137 OR MAC 0 Wakeup Request
(sync)
137 OR MAC 0 Wakeup Request
(async)
138 - MAC 0 1588 Timer Interrupt –
synchronous
139 ENET_1G OR MAC 0 Receive Buffer1 Done
139 OR MAC 0 Receive Frame1 Done
139 OR MAC 0 Transmit Buffer1 Done
139 OR MAC 0 Transmit Frame1
Done
140 OR MAC 0 Receive Buffer2 Done
140 OR MAC 0 Receive Frame2 Done
140 OR MAC 0 Transmit Buffer2 Done
140 OR MAC 0 Transmit Frame2
Done
141 OR MAC 0 Periodic Timer
Overflow
141 OR MAC 0 Time Stamp Available
141 OR MAC 0 Payload Receive Error
141 OR MAC 0 Transmit FIFO
Underrun
141 OR MAC 0 Collision Retry Limit
141 OR MAC 0 Late Collision
141 OR MAC 0 Ethernet Bus Error
141 OR MAC 0 MII Data Transfer
Done
141 OR MAC 0 Receive Buffer Done
141 OR MAC 0 Receive Frame Done
141 OR MAC 0 Transmit Buffer Done
141 OR MAC 0 Transmit Frame Done
141 OR MAC 0 Graceful Stop
141 OR MAC 0 Babbling Transmit
Error
141 OR MAC 0 Babbling Receive
Error
141 OR MAC 0 Receive Flush Frame0
141 OR MAC 0 Receive Flush Frame1
141 OR MAC 0 Receive Flush Frame2
141 OR MAC 0 Wakeup Request
(sync)
141 OR MAC 0 Wakeup Request
(async)
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
141 OR MAC 0 Babbling Receive
Error
141 OR MAC 0 Wakeup Request (err)
142 - MAC 0 1588 Timer Interrupt –
synchronous
143 XBAR1 OR XBAR IRQ (XBAR_OUT0)
143 OR XBAR IRQ (XBAR_OUT1)
144 OR XBAR IRQ (XBAR_OUT2)
144 OR XBAR IRQ (XBAR_OUT3)
145 ADC_ETC - ADC_ETC done0 interrupt
146 - ADC_ETC done1 interrupt
147 - ADC_ETC done2 interrupt
148 - ADC_ETC done3 interrupt
149 - ADC_ETC err interrupt
150 Reserved - N/A
151 Reserved - N/A
152 Reserved - N/A
153 Reserved - N/A
154 Reserved - N/A
155 PIT1 OR PIT1 channel 0 interrupt
155 OR PIT1 channel 1 interrupt
155 OR PIT1 channel 2 interrupt
155 OR PIT1 channel 3 interrupt
156 PIT2 OR PIT2 channel 0 interrupt
156 OR PIT2 channel 1 interrupt
156 OR PIT2 channel 2 interrupt
156 OR PIT2 channel 3 interrupt
157 ACMP1 OR ACMP1 interrupt
157 OR ACMP1 async interrupt for
STOP mode wake up
158 ACMP2 OR ACMP2 interrupt
158 OR ACMP2 async interrupt for
STOP mode wake up
159 ACMP3 OR ACMP3 interrupt
159 OR ACMP3 async interrupt for
STOP mode wake up
160 ACMP4 OR ACMP4 interrupt
160 OR ACMP4 async interrupt for
STOP mode wake up
161 Reserved - N/A
162 Reserved - N/A
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
163 Reserved - N/A
164 Reserved - N/A
165 QDC1 OR Index marker interrupt
165 OR Home marker interrupt
165 OR Watchdog timeout interrupt
165 OR Compare interrupt
165 OR Simultaneous input switching
interrupt
166 QDC2 OR Index marker interrupt
166 OR Home marker interrupt
166 OR Watchdog timeout interrupt
166 OR Compare interrupt
166 OR Simultaneous input switching
interrupt
167 QDC3 OR Index marker interrupt
167 OR Home marker interrupt
167 OR Watchdog timeout interrupt
167 OR Compare interrupt
167 OR Simultaneous input switching
interrupt
168 QDC4 OR Index marker interrupt
168 OR Home marker interrupt
168 OR Watchdog timeout interrupt
168 OR Compare interrupt
168 OR Simultaneous input switching
interrupt
169 Reserved - N/A
170 Reserved - N/A
171 TMR1 OR Interrupt request for timer #0
171 OR Interrupt request for timer #1
171 OR Interrupt request for timer #2
171 OR Interrupt request for timer #3
172 TMR2 OR Interrupt request for timer #0
172 OR Interrupt request for timer #1
172 OR Interrupt request for timer #2
172 OR Interrupt request for timer #3
173 TMR3 OR Interrupt request for timer #0
173 OR Interrupt request for timer #1
173 OR Interrupt request for timer #2
173 OR Interrupt request for timer #3
174 TMR4 OR Interrupt request for timer #0
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CM4 interrupts
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
174 OR Interrupt request for timer #1
174 OR Interrupt request for timer #2
174 OR Interrupt request for timer #3
175 SEMA4 - SEMA4 CP0 interrupt
176 - SEMA4 CP1 interrupt
177 FLEXPWM2 OR capture 0 interrupt
177 OR compare 0 interrupt
177 OR reload 0 interrupt
178 OR capture 1 interrupt
178 OR compare 1 interrupt
178 OR reload 1 interrupt
179 OR capture 2 interrupt
179 OR compare 2 interrupt
179 OR reload 2 interrupt
180 OR capture 3 interrupt
180 OR compare 3 interrupt
180 OR reload 3 interrupt
181 OR fault interrupt
181 OR reload error interrupt
182 FLEXPWM3 OR capture 0 interrupt
182 OR compare 0 interrupt
182 OR reload 0 interrupt
183 OR capture 1 interrupt
183 OR compare 1 interrupt
183 OR reload 1 interrupt
184 OR capture 2 interrupt
184 OR compare 2 interrupt
184 OR reload 2 interrupt
185 OR capture 3 interrupt
185 OR compare 3 interrupt
185 OR reload 3 interrupt
186 OR fault interrupt
186 OR reload error interrupt
187 FLEXPWM4 OR capture 0 interrupt
187 OR compare 0 interrupt
187 OR reload 0 interrupt
188 OR capture 1 interrupt
188 OR compare 1 interrupt
188 OR reload 1 interrupt
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Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
189 OR capture 2 interrupt
189 OR compare 2 interrupt
189 OR reload 2 interrupt
190 OR capture 3 interrupt
190 OR compare 3 interrupt
190 OR reload 3 interrupt
191 OR fault interrupt
191 OR reload error interrupt
192 Reserved - N/A
193 Reserved - N/A
194 Reserved - N/A
195 Reserved - N/A
196 Reserved - N/A
197 Reserved - N/A
198 Reserved - N/A
199 Reserved - N/A
200 PDM OR HWVAD event interrupt
200 OR HWVAD event async interrupt
201 OR HWVAD error interrupt
201 OR HWVAD error async interrupt
202 OR filter interrupt
202 OR filter async interrupt
203 OR error interrupt
203 OR error async interrupt
204 EMVSIM1 OR EMVSIM1 interrupt (data_irq)
204 OR EMVSIM1 interrupt
205 EMVSIM2 OR EMVSIM2 interrupt (data_irq)
205 OR EMVSIM2 interrupt
206 MECC1 - MECC1 interrupt
207 - MECC1 Fatal interrupt
208 MECC2 - MECC2 interrupt
209 - MECC2 Fatal interrupt
210 XECC_FLEXSPI1 - XECC_FLEXSPI1 interrupt
211 - XECC_FLEXSPI1 Fatal
interrupt
212 XECC_FLEXSPI2 - XECC_FLEXSPI2 interrupt
213 - XECC_FLEXSPI2 Fatal
interrupt
214 XECC_SEMC - XECC_SEMC interrupt
215 - XECC_SEMC Fatal interrupt
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DMA Mux
Table 4-2. CM4 domain interrupt summary (continued)
IRQ Interrupt Source LOGIC Interrupt Description
216 ENET_QOS OR LPI Rx exit interrupt output
216 OR Interrupt signal to host system
216 OR Channel 0 Transmit Interrupt
signal to host system
216 OR Channel 1 Transmit Interrupt
signal to host system
216 OR Channel 2 Transmit Interrupt
signal to host system
216 OR Channel 3 Transmit Interrupt
signal to host system
216 OR Channel 4 Transmit Interrupt
signal to host system
216 OR Channel 0 Receive Interrupt
signal to host system
216 OR Channel 1 Receive Interrupt
signal to host system
216 OR Channel 2 Receive Interrupt
signal to host system
216 OR Channel 3 Receive Interrupt
signal to host system
216 OR Channel 4 Receive Interrupt
signal to host system
217 - Interrupt from PMT
4.4 DMA Mux
The table below shows the DMA request signals for the peripherals in the chip:
NOTE
The DMA Mux mapping is applicable to EDMA and
EDMA_LPSR.
Table 4-3. DMA Mux Mapping
Channel Module Gate Description
0 Reserved - Reserved
1 FLEXIO1 OR FlexIO1 shifter2 DMA
Request
OR FlexIO1 shifter2 Async DMA
Request
OR FlexIO1 shifter3 DMA
Request
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Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR FlexIO1 shifter3 Async DMA
Request
OR FlexIO1 timer2 DMA Request
OR FlexIO1 timer2 Async DMA
Request
OR FlexIO1 timer3 DMA Request
OR FlexIO1 timer3 Async DMA
Request
2 FLEXIO1 OR FlexIO1 shifter4 DMA
Request
OR FlexIO1 shifter4 Async DMA
Request
OR FlexIO1 shifter5 DMA
Request
OR FlexIO1 shifter5 Async DMA
Request
OR FlexIO1 timer4 DMA Request
OR FlexIO1 timer4 Async DMA
Request
OR FlexIO1 timer5 DMA Request
OR FlexIO1 timer5 Async DMA
Request
3 FLEXIO1 OR FlexIO1 shifter6 DMA
Request
OR FlexIO1 shifter6 Async DMA
Request
OR FlexIO1 shifter7 DMA
Request
OR FlexIO1 shifter7 Async DMA
Request
OR FlexIO1 timer6 DMA Request
OR FlexIO1 timer6 Async DMA
Request
OR FlexIO1 timer7 DMA Request
OR FlexIO1 timer7 Async DMA
Request
4 FLEXIO2 OR FlexIO2 shifter0 DMA
Request
OR FlexIO2 shifter0 Async DMA
Request
OR FlexIO2 shifter1 DMA
Request
OR FlexIO2 shifter1 Async DMA
Request
OR FlexIO2 timer0 DMA Request
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR FlexIO2 timer0 Async DMA
Request
OR FlexIO2 timer1 DMA Request
OR FlexIO2 timer1 Async DMA
Request
5 FLEXIO2 OR FlexIO2 shifter2 DMA
Request
OR FlexIO2 shifter2 Async DMA
Request
OR FlexIO2 shifter3 DMA
Request
OR FlexIO2 shifter3 Async DMA
Request
OR FlexIO2 timer2 DMA Request
OR FlexIO2 timer2 Async DMA
Request
OR FlexIO2 timer3 DMA Request
OR FlexIO2 timer3 Async DMA
Request
6 FLEXIO2 OR FlexIO2 shifter4 DMA
Request
OR FlexIO2 shifter4 Async DMA
Request
OR FlexIO2 shifter5 DMA
Request
OR FlexIO2 shifter5 Async DMA
Request
OR FlexIO2 timer4 DMA Request
OR FlexIO2 timer4 Async DMA
Request
OR FlexIO2 timer5 DMA Request
OR FlexIO2 timer5 Async DMA
Request
7 FLEXIO2 OR FlexIO2 shifter6 DMA
Request
OR FlexIO2 shifter6 Async DMA
Request
OR FlexIO2 shifter7 DMA
Request
OR FlexIO2 shifter7 Async DMA
Request
OR FlexIO2 timer6 DMA Request
OR FlexIO2 timer6 Async DMA
Request
OR FlexIO2 timer7 DMA Request
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Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR FlexIO2 timer7 Async DMA
Request
8 LPUART1 OR UART1 Tx FIFO DMA
Request
OR UART1 Tx FIFO Async DMA
Request
9 LPUART1 OR UART1 Rx FIFO DMA
Request
OR UART1 Rx FIFO Async DMA
Request
10 LPUART2 OR UART2 Tx FIFO DMA
Request
OR UART2 Tx FIFO Async DMA
Request
11 LPUART2 OR UART2 Rx FIFO DMA
Request
OR UART2 Rx FIFO Async DMA
Request
12 LPUART3 OR UART3 Tx FIFO Async DMA
Request
OR UART3 Tx FIFO DMA
Request
13 LPUART3 OR UART3 Rx FIFO DMA
Request
OR UART3 Rx FIFO Async DMA
Request
14 LPUART4 OR UART4 Tx FIFO DMA
Request
OR UART4 Tx FIFO Async DMA
Request
15 LPUART4 OR UART4 Rx FIFO DMA
Request
OR UART4 Rx FIFO Async DMA
Request
16 LPUART5 OR UART5 Tx FIFO DMA
Request
OR UART5 Tx FIFO Async DMA
Request
17 LPUART5 OR UART5 Rx FIFO DMA
Request
OR UART5 Rx FIFO Async DMA
Request
18 LPUART6 OR UART6 Tx FIFO DMA
Request
OR UART6 Tx FIFO Async DMA
Request
Table continues on the next page...
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
19 LPUART6 OR UART6 Rx FIFO DMA
Request
OR UART6 Rx FIFO Async DMA
Request
20 LPUART7 OR UART7 Tx FIFO DMA
Request
OR UART7 Tx FIFO Async DMA
Request
21 LPUART7 OR UART7 Rx FIFO DMA
Request
OR UART7 Rx FIFO Async DMA
Request
22 LPUART8 OR UART8 Tx FIFO DMA
Request
OR UART8 Tx FIFO Async DMA
Request
23 LPUART8 OR UART8 Rx FIFO DMA
Request
OR UART8 Rx FIFO Async DMA
Request
24 LPUART9 OR UART9 Tx FIFO DMA
Request
OR UART9 Tx FIFO Async DMA
Request
25 LPUART9 OR UART9 Rx FIFO DMA
Request
OR UART9 Rx FIFO Async DMA
Request
26 LPUART10 OR UART10 Tx FIFO DMA
Request
OR UART10 Tx FIFO Async DMA
Request
27 LPUART10 OR UART10 Rx FIFO DMA
Request
OR UART10 Rx FIFO Async DMA
Request
28 LPUART11 OR UART11 Tx FIFO DMA
Request
OR UART11 Tx FIFO Async DMA
Request
29 LPUART11 OR UART11 Rx FIFO DMA
Request
OR UART11 Rx FIFO Async DMA
Request
30 LPUART12 OR UART12 Tx FIFO DMA
Request
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR UART12 Tx FIFO Async DMA
Request
31 LPUART12 OR UART12 Rx FIFO DMA
Request
OR UART12 Rx FIFO Async DMA
Request
32 CSI - CSI Write DMA Request
33 PXP - PXP DMA Event
34 eLCDIF - eLCDIF DMA Event
35 LCDIFv2 - LCDIFv2 DMA Event
36 LPSPI1 OR LPSPI1 Rx FIFO DMA
Request
OR LPSPI1 Rx FIFO Async DMA
Request
37 LPSPI1 OR LPSPI1 Tx FIFO DMA
Request
OR LPSPI1 Tx FIFO Async DMA
Request
38 LPSPI2 OR LPSPI2 Rx FIFO DMA
Request
OR LPSPI2 Rx FIFO Async DMA
Request
39 LPSPI2 OR LPSPI2 Tx FIFO DMA
Request
OR LPSPI2 Tx FIFO Async DMA
Request
40 LPSPI3 OR LPSPI3 Rx FIFO DMA
Request
OR LPSPI3 Rx FIFO Async DMA
Request
41 LPSPI3 OR LPSPI3 Tx FIFO DMA
Request
OR LPSPI3 Tx FIFO Async DMA
Request
42 LPSPI4 OR LPSPI4 Rx FIFO DMA
Request
OR LPSPI4 Rx FIFO Async DMA
Request
43 LPSPI4 OR LPSPI4 Tx FIFO DMA
Request
OR LPSPI4 Tx FIFO Async DMA
Request
44 LPSPI5 OR LPSPI5 Rx FIFO DMA
Request
Table continues on the next page...
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR LPSPI5 Rx FIFO Async DMA
Request
45 LPSPI5 OR LPSPI5 Tx FIFO DMA
Request
OR LPSPI5 Tx FIFO Async DMA
Request
46 LPSPI6 OR LPSPI6 Rx FIFO DMA
Request
OR LPSPI6 Rx FIFO Async DMA
Request
47 LPSPI6 OR LPSPI6 Tx FIFO DMA
Request
OR LPSPI6 Tx FIFO Async DMA
Request
48 LPI2C1 OR I2C1 Master Rx FIFO DMA
Request
OR I2C1 Master Rx FIFO Async
DMA Request
OR I2C1 Slave Rx FIFO DMA
Request
OR I2C1 Slave Rx FIFO Async
DMA Request
OR I2C1 Master Tx FIFO DMA
Request
OR I2C1 Master Tx FIFO Async
DMA Request
OR I2C1 Slave Tx FIFO DMA
Request
OR I2C1 Slave Tx FIFO Async
DMA Request
49 LPI2C2 OR I2C2 Master Rx FIFO DMA
Request
OR I2C2 Master Rx FIFO Async
DMA Request
OR I2C2 Slave Rx FIFO DMA
Request
OR I2C2 Slave Rx FIFO Async
DMA Request
OR I2C2 Master Tx FIFO DMA
Request
OR I2C2 Master Tx FIFO Async
DMA Request
OR I2C2 Slave Tx FIFO DMA
Request
OR I2C2 Slave Tx FIFO Async
DMA Request
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
50 LPI2C3 OR I2C3 Master Rx FIFO DMA
Request
OR I2C3 Master Rx FIFO Async
DMA Request
OR I2C3 Slave Rx FIFO DMA
Request
OR I2C3 Slave Rx FIFO Async
DMA Request
OR I2C3 Master Tx FIFO DMA
Request
OR I2C3 Master Tx FIFO Async
DMA Request
OR I2C3 Slave Tx FIFO DMA
Request
OR I2C3 Slave Tx FIFO Async
DMA Request
51 LPI2C4 OR I2C4 Master Rx FIFO DMA
Request
OR I2C4 Master Rx FIFO Async
DMA Request
OR I2C4 Slave Rx FIFO DMA
Request
OR I2C4 Slave Rx FIFO Async
DMA Request
OR I2C4 Master Tx FIFO DMA
Request
OR I2C4 Master Tx FIFO Async
DMA Request
OR I2C4 Slave Tx FIFO DMA
Request
OR I2C4 Slave Tx FIFO Async
DMA Request
52 LPI2C5 OR I2C5 Master Rx FIFO DMA
Request
OR I2C5 Master Rx FIFO Async
DMA Request
OR I2C5 Slave Rx FIFO DMA
Request
OR I2C5 Slave Rx FIFO Async
DMA Request
OR I2C5 Master Tx FIFO DMA
Request
OR I2C5 Master Tx FIFO Async
DMA Request
OR I2C5 Slave Tx FIFO DMA
Request
Table continues on the next page...
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR I2C5 Slave Tx FIFO Async
DMA Request
53 LPI2C6 OR I2C6 Master Rx FIFO DMA
Request
OR I2C6 Master Rx FIFO Async
DMA Request
OR I2C6 Slave Rx FIFO DMA
Request
OR I2C6 Slave Rx FIFO Async
DMA Request
OR I2C6 Master Tx FIFO DMA
Request
OR I2C6 Master Tx FIFO Async
DMA Request
OR I2C6 Slave Tx FIFO DMA
Request
OR I2C6 Slave Tx FIFO Async
DMA Request
54 SAI1 - SAI1 Rx FIFO DMA Request
55 SAI1 - SAI1 Tx FIFO DMA Request
56 SAI2 - SAI2 Rx FIFO DMA Request
57 SAI2 - SAI2 Tx FIFO DMA Request
58 SAI3 - SAI3 Rx FIFO DMA Request
59 SAI3 - SAI3 Tx FIFO DMA Request
60 SAI4 - SAI4 Rx FIFO DMA Request
61 SAI4 - SAI4 Tx FIFO DMA Request
62 SPDIF - SPDIF RX DMA Request
63 SPDIF - SPDIF TX DMA Request
64 ADC_ETC - ADC_ETC DMA Request
65 FLEXIO1 OR FlexIO1 shifter0 DMA
Request
OR FlexIO1 shifter0 Async DMA
Request
OR FlexIO1 shifter1 DMA
Request
OR FlexIO1 shifter1 Async DMA
Request
OR FlexIO1 timer0 DMA Request
OR FlexIO1 timer0 Async DMA
Request
OR FlexIO1 timer1 DMA Request
OR FlexIO1 timer1 Async DMA
Request
66 LPADC1 - ADC1 DMA Request
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
67 LPADC2 - ADC2 DMA Request
68 Reserved - Reserved
69 ACMP1 - ACMP1 DMA Request
70 ACMP2 - ACMP2 DMA Request
71 ACMP3 - ACMP3 DMA Request
72 ACMP4 - ACMP4 DMA Request
73-76 Reserved - Reserved
77 FLEXSPI1 - FlexSPI1 Rx FIFO DMA
Request
78 FLEXSPI1 - FlexSPI1 Tx FIFO DMA
Request
79 FLEXSPI2 - FlexSPI2 Rx FIFO DMA
Request
80 FLEXSPI2 - FlexSPI2 Tx FIFO DMA
Request
81 XBAR1 - XBAR1_OUT0 DMA request
82 XBAR1 - XBAR1_OUT1 DMA request
83 XBAR1 - XBAR1_OUT2 DMA request
84 XBAR1 - XBAR1_OUT3 DMA request
85 FLEXPWM1 - FlexPWM1 sub-module0
capture register read DMA
request
86 FLEXPWM1 - FlexPWM1 sub-module1
capture register read DMA
request
87 FLEXPWM1 - FlexPWM1 sub-module2
capture register read DMA
request
88 FLEXPWM1 - FlexPWM1 sub-module3
capture register read DMA
request
89 FLEXPWM1 - FlexPWM1 sub-module0
value registers write DMA
request
90 FLEXPWM1 - FlexPWM1 sub-module1
value registers write DMA
request
91 FLEXPWM1 - FlexPWM1 sub-module2
value registers write DMA
request
92 FLEXPWM1 - FlexPWM1 sub-module3
value registers write DMA
request
93 FLEXPWM2 - FlexPWM2 sub-module0
capture register read DMA
request
Table continues on the next page...
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
94 FLEXPWM2 - FlexPWM2 sub-module1
capture register read DMA
request
95 FLEXPWM2 - FlexPWM2 sub-module2
capture register read DMA
request
96 FLEXPWM2 - FlexPWM2 sub-module3
capture register read DMA
request
97 FLEXPWM2 - FlexPWM2 sub-module0
value registers write DMA
request
98 FLEXPWM2 - FlexPWM2 sub-module1
value registers write DMA
request
99 FLEXPWM2 - FlexPWM2 sub-module2
value registers write DMA
request
100 FLEXPWM2 - FlexPWM2 sub-module3
value registers write DMA
request
101 FLEXPWM3 - FlexPWM3 sub-module0
capture register read DMA
request
102 FLEXPWM3 - FlexPWM3 sub-module1
capture register read DMA
request
103 FLEXPWM3 - FlexPWM3 sub-module2
capture register read DMA
request
104 FLEXPWM3 - FlexPWM3 sub-module3
capture register read DMA
request
105 FLEXPWM3 - FlexPWM3 sub-module0
value registers write DMA
request
106 FLEXPWM3 - FlexPWM3 sub-module1
value registers write DMA
request
107 FLEXPWM3 - FlexPWM3 sub-module2
value registers write DMA
request
108 FLEXPWM3 - FlexPWM3 sub-module3
value registers write DMA
request
109 FLEXPWM4 - FlexPWM4 sub-module0
capture register read DMA
request
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
110 FLEXPWM4 - FlexPWM4 sub-module1
capture register read DMA
request
111 FLEXPWM4 - FlexPWM4 sub-module2
capture register read DMA
request
112 FLEXPWM4 - FlexPWM4 sub-module3
capture register read DMA
request
113 FLEXPWM4 - FlexPWM4 sub-module0
value registers write DMA
request
114 FLEXPWM4 - FlexPWM4 sub-module1
value registers write DMA
request
115 FLEXPWM4 - FlexPWM4 sub-module2
value registers write DMA
request
116 FLEXPWM4 - FlexPWM4 sub-module3
value registers write DMA
request
117-132 Reserved - Reserved
133 QTIMER1 - QTIMER1 timer0 capture
register read DMA request
134 QTIMER1 - QTIMER1 timer1 capture
register read DMA request
135 QTIMER1 - QTIMER1 timer2 capture
register read DMA request
136 QTIMER1 - QTIMER1 timer3 capture
register read DMA request
137 QTIMER1 OR QTimer1 timer0 cmpld1
register write DMA request
OR QTimer1 timer1 cmpld2
register write DMA request
138 QTIMER1 OR QTimer1 timer1 cmpld1
register write DMA request
OR QTimer1 timer0 cmpld2
register write DMA request
139 QTIMER1 OR QTimer1 timer2 cmpld1
register write DMA request
OR QTimer1 timer3 cmpld2
register write DMA request
140 QTIMER1 OR QTimer1 timer3 cmpld1
register write DMA request
OR QTimer1 timer2 cmpld2
register write DMA request
Table continues on the next page...
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DMA Mux
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
141 QTIMER2 - QTIMER2 timer0 capture
register read DMA request
142 QTIMER2 - QTIMER2 timer1 capture
register read DMA request
143 QTIMER2 - QTIMER2 timer2 capture
register read DMA request
144 QTIMER2 - QTIMER2 timer3 capture
register read DMA request
145 QTIMER2 OR QTimer2 timer0 cmpld1
register write DMA request
OR QTimer2 timer1 cmpld2
register write DMA request
146 QTIMER2 OR QTimer2 timer1 cmpld1
register write DMA request
OR QTimer2 timer0 cmpld2
register write DMA request
147 QTIMER2 OR QTimer2 timer2 cmpld1
register write DMA request
OR QTimer2 timer3 cmpld2
register write DMA request
148 QTIMER2 OR QTimer2 timer3 cmpld1
register write DMA request
OR QTimer2 timer2 cmpld2
register write DMA request
149 QTIMER3 - QTIMER3 timer0 capture
register read DMA request
150 QTIMER3 - QTIMER3 timer1 capture
register read DMA request
151 QTIMER3 - QTIMER3 timer2 capture
register read DMA request
152 QTIMER3 - QTIMER3 timer3 capture
register read DMA request
153 QTIMER3 OR QTimer3 timer0 cmpld1
register write DMA request
OR QTimer3 timer1 cmpld2
register write DMA request
154 QTIMER3 OR QTimer3 timer1 cmpld1
register write DMA request
OR QTimer3 timer0 cmpld2
register write DMA request
155 QTIMER3 OR QTimer3 timer2 cmpld1
register write DMA request
OR QTimer3 timer3 cmpld2
register write DMA request
156 QTIMER3 OR QTimer3 timer3 cmpld1
register write DMA request
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
OR QTimer3 timer2 cmpld2
register write DMA request
157 QTIMER4 - QTIMER4 timer0 capture
register read DMA request
158 QTIMER4 - QTIMER4 timer1 capture
register read DMA request
159 QTIMER4 - QTIMER4 timer2 capture
register read DMA request
160 QTIMER4 - QTIMER4 timer3 capture
register read DMA request
161 QTIMER4 OR QTimer4 timer0 cmpld1
register write DMA request
OR QTimer4 timer1 cmpld2
register write DMA request
162 QTIMER4 OR QTimer4 timer1 cmpld1
register write DMA request
OR QTimer4 timer0 cmpld2
register write DMA request
163 QTIMER4 OR QTimer4 timer2 cmpld1
register write DMA request
OR QTimer4 timer3 cmpld2
register write DMA request
164 QTIMER4 OR QTimer4 timer3 cmpld1
register write DMA request
OR QTimer4 timer2 cmpld2
register write DMA request
165-180 Reserved - Reserved
181 PDM OR PDM DMA request
OR PDM DMA async request
182 ENET - ENET Timer0 DMA Request
183 ENET - ENET Timer1 DMA Request
184 ENET_1G - ENET_1G Timer0 DMA
Request
185 ENET_1G - ENET_1G Timer1 DMA
Request
186 CAN1 - CAN1 DMA Request
187 CAN2 - CAN2 DMA Request
188 CAN3 - CAN3 DMA Request
189 DAC - DAC DMA Request
190 Reserved - Reserved
191 ASRC - ASRC pair A input DMA
request
192 ASRC - ASRC pair B input DMA
request
Table continues on the next page...
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PIT Channel Assignments For Periodic DMA Triggering
Table 4-3. DMA Mux Mapping (continued)
Channel Module Gate Description
193 ASRC - ASRC pair C input DMA
request
194 ASRC - ASRC pair A output DMA
request
195 ASRC - ASRC pair B output DMA
request
196 ASRC - ASRC pair C output DMA
request
197 EMVSIM1 - EMVSIM1 TX DMA Request
198 EMVSIM1 - EMVSIM1 RX DMA Request
199 EMVSIM2 - EMVSIM2 TX DMA Request
200 EMVSIM2 - EMVSIM2 RX DMA Request
201 ENET_QOS - ENET_QOS PPS0 output
DMA Request
202 ENET_QOS - ENET_QOS PPS1 output
DMA Request
203-207 Reserved - Reserved
4.5 PIT Channel Assignments For Periodic DMA Triggering
This table shows the PIT channel to DMA channel correspondence.
Table 4-4. PIT Channel Assignments For Periodic DMA Triggering
DMA Channel Number PIT Channel
eDMA Channel 0 PIT1 Channel 0
eDMA Channel 1 PIT1 Channel 1
eDMA Channel 2 PIT1 Channel 2
eDMA Channel 3 PIT1 Channel 3
eDMA_LPSR Channel 0 PIT2 Channel 0
eDMA_LPSR Channel 1 PIT2 Channel 1
eDMA_LPSR Channel 2 PIT2 Channel 2
eDMA_LPSR Channel 3 PIT2 Channel 3
4.6 XBAR Resource Assignments
This table shows the XBAR resource assignments in the chip.
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
NOTE
ADC_ETC0_COCO0 ... ADC_ETC1_COCO3 in the table are
corresponding to coco0 ... coco7, also ADC_ETC0_TRIG0 ...
ADC_ETC1_TRIG3 corresponding to trg0 ... trg7, see the
figure "ADC_ETC block diagram" in the ADC_ETC chapter.
Table 4-5. XBAR1 Input Assignments
Assigned Input XBAR1 Input Gate
LOGIC LOW XBAR1_IN00 -
LOGIC HIGH XBAR1_IN01 -
GND XBAR1_IN02 -
GND XBAR1_IN03 -
IOMUX_XBAR_INOUT04 XBAR1_IN04 -
IOMUX_XBAR_INOUT05 XBAR1_IN05 -
IOMUX_XBAR_INOUT06 XBAR1_IN06 -
IOMUX_XBAR_INOUT07 XBAR1_IN07 -
IOMUX_XBAR_INOUT08 XBAR1_IN08 -
IOMUX_XBAR_INOUT09 XBAR1_IN09 -
IOMUX_XBAR_INOUT10 XBAR1_IN10 -
IOMUX_XBAR_INOUT11 XBAR1_IN11 -
IOMUX_XBAR_INOUT12 XBAR1_IN12 -
IOMUX_XBAR_INOUT13 XBAR1_IN13 -
IOMUX_XBAR_INOUT14 XBAR1_IN14 -
IOMUX_XBAR_INOUT15 XBAR1_IN15 -
IOMUX_XBAR_INOUT16 XBAR1_IN16 -
IOMUX_XBAR_INOUT17 XBAR1_IN17 -
IOMUX_XBAR_INOUT18 XBAR1_IN18 -
IOMUX_XBAR_INOUT19 XBAR1_IN19 -
IOMUX_XBAR_INOUT20 XBAR1_IN20 -
IOMUX_XBAR_INOUT21 XBAR1_IN21 -
IOMUX_XBAR_INOUT22 XBAR1_IN22 -
IOMUX_XBAR_INOUT23 XBAR1_IN23 -
IOMUX_XBAR_INOUT24 XBAR1_IN24 -
IOMUX_XBAR_INOUT25 XBAR1_IN25 -
IOMUX_XBAR_INOUT26 XBAR1_IN26 -
IOMUX_XBAR_INOUT27 XBAR1_IN27 -
IOMUX_XBAR_INOUT28 XBAR1_IN28 -
IOMUX_XBAR_INOUT29 XBAR1_IN29 -
IOMUX_XBAR_INOUT30 XBAR1_IN30 -
IOMUX_XBAR_INOUT31 XBAR1_IN31 -
IOMUX_XBAR_INOUT32 XBAR1_IN32 -
IOMUX_XBAR_INOUT33 XBAR1_IN33 -
Table continues on the next page...
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XBAR Resource Assignments
Table 4-5. XBAR1 Input Assignments (continued)
Assigned Input XBAR1 Input Gate
IOMUX_XBAR_INOUT34 XBAR1_IN34 -
IOMUX_XBAR_INOUT35 XBAR1_IN35 -
IOMUX_XBAR_INOUT36 XBAR1_IN36 -
IOMUX_XBAR_INOUT37 XBAR1_IN37 -
IOMUX_XBAR_INOUT38 XBAR1_IN38 -
IOMUX_XBAR_INOUT39 XBAR1_IN39 -
IOMUX_XBAR_INOUT40 XBAR1_IN40 -
GND XBAR1_IN41 -
ACMP1_OUT XBAR1_IN42 -
ACMP2_OUT XBAR1_IN43 -
ACMP3_OUT XBAR1_IN44 -
ACMP4_OUT XBAR1_IN45 -
GND XBAR1_IN46-49 -
QTIMER1_TIMER0 XBAR1_IN50 -
QTIMER1_TIMER1 XBAR1_IN51 -
QTIMER1_TIMER2 XBAR1_IN52 -
QTIMER1_TIMER3 XBAR1_IN53 -
QTIMER2_TIMER0 XBAR1_IN54 -
QTIMER2_TIMER1 XBAR1_IN55 -
QTIMER2_TIMER2 XBAR1_IN56 -
QTIMER2_TIMER3 XBAR1_IN57 -
QTIMER3_TIMER0 XBAR1_IN58 -
QTIMER3_TIMER1 XBAR1_IN59 -
QTIMER3_TIMER2 XBAR1_IN60 -
QTIMER3_TIMER3 XBAR1_IN61 -
QTIMER4_TIMER0 XBAR1_IN62 -
QTIMER4_TIMER1 XBAR1_IN63 -
QTIMER4_TIMER2 XBAR1_IN64 -
QTIMER4_TIMER3 XBAR1_IN65 -
GND XBAR1_IN66-73 -
FLEXPWM1_PWM0_OUT_TRIG0 XBAR1_IN74 -
FLEXPWM1_PWM0_OUT_TRIG1 XBAR1_IN75 -
FLEXPWM1_PWM1_OUT_TRIG0 XBAR1_IN76 -
FLEXPWM1_PWM1_OUT_TRIG1 XBAR1_IN77 -
FLEXPWM1_PWM2_OUT_TRIG0 XBAR1_IN78 -
FLEXPWM1_PWM2_OUT_TRIG1 XBAR1_IN79 -
FLEXPWM1_PWM3_OUT_TRIG0 XBAR1_IN80 -
FLEXPWM1_PWM3_OUT_TRIG1 XBAR1_IN81 -
FLEXPWM2_PWM0_OUT_TRIG0 XBAR1_IN82 OR
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-5. XBAR1 Input Assignments (continued)
Assigned Input XBAR1 Input Gate
FLEXPWM2_PWM0_OUT_TRIG1 XBAR1_IN82 OR
FLEXPWM2_PWM1_OUT_TRIG0 XBAR1_IN83 OR
FLEXPWM2_PWM1_OUT_TRIG1 XBAR1_IN83 OR
FLEXPWM2_PWM2_OUT_TRIG0 XBAR1_IN84 OR
FLEXPWM2_PWM2_OUT_TRIG1 XBAR1_IN84 OR
FLEXPWM2_PWM3_OUT_TRIG0 XBAR1_IN85 OR
FLEXPWM2_PWM3_OUT_TRIG1 XBAR1_IN85 OR
FLEXPWM3_PWM0_OUT_TRIG0 XBAR1_IN86 OR
FLEXPWM3_PWM0_OUT_TRIG1 XBAR1_IN86 OR
FLEXPWM3_PWM1_OUT_TRIG0 XBAR1_IN87 OR
FLEXPWM3_PWM1_OUT_TRIG1 XBAR1_IN87 OR
FLEXPWM3_PWM2_OUT_TRIG0 XBAR1_IN88 OR
FLEXPWM3_PWM2_OUT_TRIG1 XBAR1_IN88 OR
FLEXPWM3_PWM3_OUT_TRIG0 XBAR1_IN89 OR
FLEXPWM3_PWM3_OUT_TRIG1 XBAR1_IN89 OR
FLEXPWM4_PWM0_OUT_TRIG0 XBAR1_IN90 OR
FLEXPWM4_PWM0_OUT_TRIG1 XBAR1_IN90 OR
FLEXPWM4_PWM1_OUT_TRIG0 XBAR1_IN91 OR
FLEXPWM4_PWM1_OUT_TRIG1 XBAR1_IN91 OR
FLEXPWM4_PWM2_OUT_TRIG0 XBAR1_IN92 OR
FLEXPWM4_PWM2_OUT_TRIG1 XBAR1_IN92 OR
FLEXPWM4_PWM3_OUT_TRIG0 XBAR1_IN93 OR
FLEXPWM4_PWM3_OUT_TRIG1 XBAR1_IN93 OR
GND XBAR1_IN94-101 -
PIT1_TRIGGER0 XBAR1_IN102 -
PIT1_TRIGGER1 XBAR1_IN103 -
PIT1_TRIGGER2 XBAR1_IN104 -
PIT1_TRIGGER3 XBAR1_IN105 -
QDC1_POSMATCH XBAR1_IN106 -
QDC2_POSMATCH XBAR1_IN107 -
QDC3_POSMATCH XBAR1_IN108 -
QDC4_POSMATCH XBAR1_IN109 -
GND XBAR1_IN110-111 -
EDMA_DONE0 XBAR1_IN112 -
EDMA_DONE1 XBAR1_IN113 -
EDMA_DONE2 XBAR1_IN114 -
EDMA_DONE3 XBAR1_IN115 -
EDMA_DONE4 XBAR1_IN116 -
EDMA_DONE5 XBAR1_IN117 -
Table continues on the next page...
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XBAR Resource Assignments
Table 4-5. XBAR1 Input Assignments (continued)
Assigned Input XBAR1 Input Gate
EDMA_DONE6 XBAR1_IN118 -
EDMA_DONE7 XBAR1_IN119 -
EDMA_LPSR_DONE0 XBAR1_IN120 -
EDMA_LPSR_DONE1 XBAR1_IN121 -
EDMA_LPSR_DONE2 XBAR1_IN122 -
EDMA_LPSR_DONE3 XBAR1_IN123 -
EDMA_LPSR_DONE4 XBAR1_IN124 -
EDMA_LPSR_DONE5 XBAR1_IN125 -
EDMA_LPSR_DONE6 XBAR1_IN126 -
EDMA_LPSR_DONE7 XBAR1_IN127 -
AOI1_OUT0 XBAR1_IN128 -
AOI1_OUT1 XBAR1_IN129 -
AOI1_OUT2 XBAR1_IN130 -
AOI1_OUT3 XBAR1_IN131 -
AOI2_OUT0 XBAR1_IN132 -
AOI2_OUT1 XBAR1_IN133 -
AOI2_OUT2 XBAR1_IN134 -
AOI2_OUT3 XBAR1_IN135 -
ADC_ETC0_COCO0 XBAR1_IN136 -
ADC_ETC0_COCO1 XBAR1_IN137 -
ADC_ETC0_COCO2 XBAR1_IN138 -
ADC_ETC0_COCO3 XBAR1_IN139 -
ADC_ETC1_COCO0 XBAR1_IN140 -
ADC_ETC1_COCO1 XBAR1_IN141 -
ADC_ETC1_COCO2 XBAR1_IN142 -
ADC_ETC1_COCO3 XBAR1_IN143 -
GND XABR1_IN144-155 -
Table 4-6. XBAR2 Input Assignments
Assigned Input XBAR2 Input Gate
LOGIC LOW XBAR2_IN00 -
LOGIC HIGH XBAR2_IN01 -
ACMP1_OUT XBAR2_IN02 -
ACMP2_OUT XBAR2_IN03 -
ACMP3_OUT XBAR2_IN04 -
ACMP4_OUT XBAR2_IN05 -
GND XBAR2_IN06-09 -
QTIMER1_TIMER0 XBAR2_IN10 -
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-6. XBAR2 Input Assignments (continued)
Assigned Input XBAR2 Input Gate
QTIMER1_TIMER1 XBAR2_IN11 -
QTIMER1_TIMER2 XBAR2_IN12 -
QTIMER1_TIMER3 XBAR2_IN13 -
QTIMER2_TIMER0 XBAR2_IN14 -
QTIMER2_TIMER1 XBAR2_IN15 -
QTIMER2_TIMER2 XBAR2_IN16 -
QTIMER2_TIMER3 XBAR2_IN17 -
QTIMER3_TIMER0 XBAR2_IN18 -
QTIMER3_TIMER1 XBAR2_IN19 -
QTIMER3_TIMER2 XBAR2_IN20 -
QTIMER3_TIMER3 XBAR2_IN21 -
QTIMER4_TIMER0 XBAR2_IN22 -
QTIMER4_TIMER1 XBAR2_IN23 -
QTIMER4_TIMER2 XBAR2_IN24 -
QTIMER4_TIMER3 XBAR2_IN25 -
GND XBAR2_IN26-33 -
FLEXPWM1_PWM0_OUT_TRIG0 XBAR2_IN34 OR
FLEXPWM1_PWM0_OUT_TRIG1 XBAR2_IN34 OR
FLEXPWM1_PWM1_OUT_TRIG0 XBAR2_IN35 OR
FLEXPWM1_PWM1_OUT_TRIG1 XBAR2_IN35 OR
FLEXPWM1_PWM2_OUT_TRIG0 XBAR2_IN36 OR
FLEXPWM1_PWM2_OUT_TRIG1 XBAR2_IN36 OR
FLEXPWM1_PWM3_OUT_TRIG0 XBAR2_IN37 OR
FLEXPWM1_PWM3_OUT_TRIG1 XBAR2_IN37 OR
FLEXPWM2_PWM0_OUT_TRIG0 XBAR2_IN38 OR
FLEXPWM2_PWM0_OUT_TRIG1 XBAR2_IN38 OR
FLEXPWM2_PWM1_OUT_TRIG0 XBAR2_IN39 OR
FLEXPWM2_PWM1_OUT_TRIG1 XBAR2_IN39 OR
FLEXPWM2_PWM2_OUT_TRIG0 XBAR2_IN40 OR
FLEXPWM2_PWM2_OUT_TRIG1 XBAR2_IN40 OR
FLEXPWM2_PWM3_OUT_TRIG0 XBAR2_IN41 OR
FLEXPWM2_PWM3_OUT_TRIG1 XBAR2_IN41 OR
FLEXPWM3_PWM0_OUT_TRIG0 XBAR2_IN42 OR
FLEXPWM3_PWM0_OUT_TRIG1 XBAR2_IN42 OR
FLEXPWM3_PWM1_OUT_TRIG0 XBAR2_IN43 OR
FLEXPWM3_PWM1_OUT_TRIG1 XBAR2_IN43 OR
FLEXPWM3_PWM2_OUT_TRIG0 XBAR2_IN44 OR
FLEXPWM3_PWM2_OUT_TRIG1 XBAR2_IN44 OR
FLEXPWM3_PWM3_OUT_TRIG0 XBAR2_IN45 OR
Table continues on the next page...
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XBAR Resource Assignments
Table 4-6. XBAR2 Input Assignments (continued)
Assigned Input XBAR2 Input Gate
FLEXPWM3_PWM3_OUT_TRIG1 XBAR2_IN45 OR
FLEXPWM4_PWM0_OUT_TRIG0 XBAR2_IN46 OR
FLEXPWM4_PWM0_OUT_TRIG1 XBAR2_IN46 OR
FLEXPWM4_PWM1_OUT_TRIG0 XBAR2_IN47 OR
FLEXPWM4_PWM1_OUT_TRIG1 XBAR2_IN47 OR
FLEXPWM4_PWM2_OUT_TRIG0 XBAR2_IN48 OR
FLEXPWM4_PWM2_OUT_TRIG1 XBAR2_IN48 OR
FLEXPWM4_PWM3_OUT_TRIG0 XBAR2_IN49 OR
FLEXPWM4_PWM3_OUT_TRIG1 XBAR2_IN49 OR
GND XBAR2_IN50-57 -
PIT1_TRIGGER0 XBAR2_IN58 -
PIT1_TRIGGER1 XBAR2_IN59 -
ADC_ETC0_COCO0 XBAR2_IN60 -
ADC_ETC0_COCO1 XBAR2_IN61 -
ADC_ETC0_COCO2 XBAR2_IN62 -
ADC_ETC0_COCO3 XBAR2_IN63 -
ADC_ETC1_COCO0 XBAR2_IN64 -
ADC_ETC1_COCO1 XBAR2_IN65 -
ADC_ETC1_COCO2 XBAR2_IN66 -
ADC_ETC1_COCO3 XBAR2_IN67 -
GND XBAR2_IN68-75 -
QDC1_POSMATCH XBAR2_IN76 -
QDC2_POSMATCH XBAR2_IN77 -
QDC3_POSMATCH XBAR2_IN78 -
QDC4_POSMATCH XBAR2_IN79 -
GND XBAR2_IN80-81 -
EDMA_DONE0 XBAR2_IN82 -
EDMA_DONE1 XBAR2_IN83 -
EDMA_DONE2 XBAR2_IN84 -
EDMA_DONE3 XBAR2_IN85 -
EDMA_DONE4 XBAR2_IN86 -
EDMA_DONE5 XBAR2_IN87 -
EDMA_DONE6 XBAR2_IN88 -
EDMA_DONE7 XBAR2_IN89 -
EDMA_LPSR_DONE0 XBAR2_IN90 -
EDMA_LPSR_DONE1 XBAR2_IN91 -
EDMA_LPSR_DONE2 XBAR2_IN92 -
EDMA_LPSR_DONE3 XBAR2_IN93 -
EDMA_LPSR_DONE4 XBAR2_IN94 -
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-6. XBAR2 Input Assignments (continued)
Assigned Input XBAR2 Input Gate
EDMA_LPSR_DONE5 XBAR2_IN95 -
EDMA_LPSR_DONE6 XBAR2_IN96 -
EDMA_LPSR_DONE7 XBAR2_IN97 -
GND XBAR2_IN98-99 -
Table 4-7. XBAR3 Input Assignments
Assigned Input XBAR3 Input Gate
LOGIC LOW XBAR3_IN00 -
LOGIC HIGH XBAR3_IN01 -
ACMP1_OUT XBAR3_IN02 -
ACMP2_OUT XBAR3_IN03 -
ACMP3_OUT XBAR3_IN04 -
ACMP4_OUT XBAR3_IN05 -
GND XBAR3_IN06-09 -
QTIMER1_TIMER0 XBAR3_IN10 -
QTIMER1_TIMER1 XBAR3_IN11 -
QTIMER1_TIMER2 XBAR3_IN12 -
QTIMER1_TIMER3 XBAR3_IN13 -
QTIMER2_TIMER0 XBAR3_IN14 -
QTIMER2_TIMER1 XBAR3_IN15 -
QTIMER2_TIMER2 XBAR3_IN16 -
QTIMER2_TIMER3 XBAR3_IN17 -
QTIMER3_TIMER0 XBAR3_IN18 -
QTIMER3_TIMER1 XBAR3_IN19 -
QTIMER3_TIMER2 XBAR3_IN20 -
QTIMER3_TIMER3 XBAR3_IN21 -
QTIMER4_TIMER0 XBAR3_IN22 -
QTIMER4_TIMER1 XBAR3_IN23 -
QTIMER4_TIMER2 XBAR3_IN24 -
QTIMER4_TIMER3 XBAR3_IN25 -
GND XBAR3_IN26-33 -
FLEXPWM1_PWM0_OUT_TRIG0 XBAR3_IN34 OR
FLEXPWM1_PWM0_OUT_TRIG1 XBAR3_IN34 OR
FLEXPWM1_PWM1_OUT_TRIG0 XBAR3_IN35 OR
FLEXPWM1_PWM1_OUT_TRIG1 XBAR3_IN35 OR
FLEXPWM1_PWM2_OUT_TRIG0 XBAR3_IN36 OR
FLEXPWM1_PWM2_OUT_TRIG1 XBAR3_IN36 OR
FLEXPWM1_PWM3_OUT_TRIG0 XBAR3_IN37 OR
Table continues on the next page...
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XBAR Resource Assignments
Table 4-7. XBAR3 Input Assignments (continued)
Assigned Input XBAR3 Input Gate
FLEXPWM1_PWM3_OUT_TRIG1 XBAR3_IN37 OR
FLEXPWM2_PWM0_OUT_TRIG0 XBAR3_IN38 OR
FLEXPWM2_PWM0_OUT_TRIG1 XBAR3_IN38 OR
FLEXPWM2_PWM1_OUT_TRIG0 XBAR3_IN39 OR
FLEXPWM2_PWM1_OUT_TRIG1 XBAR3_IN39 OR
FLEXPWM2_PWM2_OUT_TRIG0 XBAR3_IN40 OR
FLEXPWM2_PWM2_OUT_TRIG1 XBAR3_IN40 OR
FLEXPWM2_PWM3_OUT_TRIG0 XBAR3_IN41 OR
FLEXPWM2_PWM3_OUT_TRIG1 XBAR3_IN41 OR
FLEXPWM3_PWM0_OUT_TRIG0 XBAR3_IN42 OR
FLEXPWM3_PWM0_OUT_TRIG1 XBAR3_IN42 OR
FLEXPWM3_PWM1_OUT_TRIG0 XBAR3_IN43 OR
FLEXPWM3_PWM1_OUT_TRIG1 XBAR3_IN43 OR
FLEXPWM3_PWM2_OUT_TRIG0 XBAR3_IN44 OR
FLEXPWM3_PWM2_OUT_TRIG1 XBAR3_IN44 OR
FLEXPWM3_PWM3_OUT_TRIG0 XBAR3_IN45 OR
FLEXPWM3_PWM3_OUT_TRIG1 XBAR3_IN45 OR
FLEXPWM4_PWM0_OUT_TRIG0 XBAR3_IN46 OR
FLEXPWM4_PWM0_OUT_TRIG1 XBAR3_IN46 OR
FLEXPWM4_PWM1_OUT_TRIG0 XBAR3_IN47 OR
FLEXPWM4_PWM1_OUT_TRIG1 XBAR3_IN47 OR
FLEXPWM4_PWM2_OUT_TRIG0 XBAR3_IN48 OR
FLEXPWM4_PWM2_OUT_TRIG1 XBAR3_IN48 OR
FLEXPWM4_PWM3_OUT_TRIG0 XBAR3_IN49 OR
FLEXPWM4_PWM3_OUT_TRIG1 XBAR3_IN49 OR
GND XBAR3_IN50-57 -
PIT1_TRIGGER0 XBAR3_IN58 -
PIT1_TRIGGER1 XBAR3_IN59 -
ADC_ETC0_COCO0 XBAR3_IN60 -
ADC_ETC0_COCO1 XBAR3_IN61 -
ADC_ETC0_COCO2 XBAR3_IN62 -
ADC_ETC0_COCO3 XBAR3_IN63 -
ADC_ETC1_COCO0 XBAR3_IN64 -
ADC_ETC1_COCO1 XBAR3_IN65 -
ADC_ETC1_COCO2 XBAR3_IN66 -
ADC_ETC1_COCO3 XBAR3_IN67 -
GND XBAR3_IN68-75 -
QDC1_POSMATCH XBAR3_IN76 -
QDC2_POSMATCH XBAR3_IN77 -
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-7. XBAR3 Input Assignments (continued)
Assigned Input XBAR3 Input Gate
QDC3_POSMATCH XBAR3_IN78 -
QDC4_POSMATCH XBAR3_IN79 -
GND XBAR3_IN80-81 -
EDMA_DONE0 XBAR3_IN82 -
EDMA_DONE1 XBAR3_IN83 -
EDMA_DONE2 XBAR3_IN84 -
EDMA_DONE3 XBAR3_IN85 -
EDMA_DONE4 XBAR3_IN86 -
EDMA_DONE5 XBAR3_IN87 -
EDMA_DONE6 XBAR3_IN88 -
EDMA_DONE7 XBAR3_IN89 -
EDMA_LPSR_DONE0 XBAR3_IN90 -
EDMA_LPSR_DONE1 XBAR3_IN91 -
EDMA_LPSR_DONE2 XBAR3_IN92 -
EDMA_LPSR_DONE3 XBAR3_IN93 -
EDMA_LPSR_DONE4 XBAR3_IN94 -
EDMA_LPSR_DONE5 XBAR3_IN95 -
EDMA_LPSR_DONE6 XBAR3_IN96 -
EDMA_LPSR_DONE7 XBAR3_IN97 -
GND XBAR3_IN98-99 -
Table 4-8. XBAR1 Output Assignments
XBAR1 Output Assigned Output Gate
XBAR1_OUT00 DMA_CH_MUX_REQ_81 -
XBAR1_OUT01 DMA_CH_MUX_REQ_82 -
XBAR1_OUT02 DMA_CH_MUX_REQ_83 -
XBAR1_OUT03 DMA_CH_MUX_REQ_84 -
XBAR1_OUT04 IOMUX_XBAR_INOUT04 -
XBAR1_OUT05 IOMUX_XBAR_INOUT05 -
XBAR1_OUT06 IOMUX_XBAR_INOUT06 -
XBAR1_OUT07 IOMUX_XBAR_INOUT07 -
XBAR1_OUT08 IOMUX_XBAR_INOUT08 -
XBAR1_OUT09 IOMUX_XBAR_INOUT09 -
XBAR1_OUT10 IOMUX_XBAR_INOUT10 -
XBAR1_OUT11 IOMUX_XBAR_INOUT11 -
XBAR1_OUT12 IOMUX_XBAR_INOUT12 -
XBAR1_OUT13 IOMUX_XBAR_INOUT13 -
XBAR1_OUT14 IOMUX_XBAR_INOUT14 -
Table continues on the next page...
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XBAR Resource Assignments
Table 4-8. XBAR1 Output Assignments (continued)
XBAR1 Output Assigned Output Gate
XBAR1_OUT15 IOMUX_XBAR_INOUT15 -
XBAR1_OUT16 IOMUX_XBAR_INOUT16 -
XBAR1_OUT17 IOMUX_XBAR_INOUT17 -
XBAR1_OUT18 IOMUX_XBAR_INOUT18 -
XBAR1_OUT19 IOMUX_XBAR_INOUT19 -
XBAR1_OUT20 IOMUX_XBAR_INOUT20 -
XBAR1_OUT21 IOMUX_XBAR_INOUT21 -
XBAR1_OUT22 IOMUX_XBAR_INOUT22 -
XBAR1_OUT23 IOMUX_XBAR_INOUT23 -
XBAR1_OUT24 IOMUX_XBAR_INOUT24 -
XBAR1_OUT25 IOMUX_XBAR_INOUT25 -
XBAR1_OUT26 IOMUX_XBAR_INOUT26 -
XBAR1_OUT27 IOMUX_XBAR_INOUT27 -
XBAR1_OUT28 IOMUX_XBAR_INOUT28 -
XBAR1_OUT29 IOMUX_XBAR_INOUT29 -
XBAR1_OUT30 IOMUX_XBAR_INOUT30 -
XBAR1_OUT31 IOMUX_XBAR_INOUT31 -
XBAR1_OUT32 IOMUX_XBAR_INOUT32 -
XBAR1_OUT33 IOMUX_XBAR_INOUT33 -
XBAR1_OUT34 IOMUX_XBAR_INOUT34 -
XBAR1_OUT35 IOMUX_XBAR_INOUT35 -
XBAR1_OUT36 IOMUX_XBAR_INOUT36 -
XBAR1_OUT37 IOMUX_XBAR_INOUT37 -
XBAR1_OUT38 IOMUX_XBAR_INOUT38 -
XBAR1_OUT39 IOMUX_XBAR_INOUT39 -
XBAR1_OUT40 IOMUX_XBAR_INOUT40 -
XBAR1_OUT41 ACMP1_SAMPLE -
XBAR1_OUT42 ACMP2_SAMPLE -
XBAR1_OUT43 ACMP3_SAMPLE -
XBAR1_OUT44 ACMP4_SAMPLE -
XBAR1_OUT45 - XBAR1_OUT48 Reserved -
XBAR1_OUT49 FLEXPWM1_PWM0_EXTA -
XBAR1_OUT50 FLEXPWM1_PWM1_EXTA -
XBAR1_OUT51 FLEXPWM1_PWM2_EXTA -
XBAR1_OUT52 FLEXPWM1_PWM3_EXTA -
XBAR1_OUT53 FLEXPWM1_PWM0_EXT_SYNC -
XBAR1_OUT54 FLEXPWM1_PWM1_EXT_SYNC -
XBAR1_OUT55 FLEXPWM1_PWM2_EXT_SYNC -
XBAR1_OUT56 FLEXPWM1_PWM3_EXT_SYNC -
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-8. XBAR1 Output Assignments (continued)
XBAR1 Output Assigned Output Gate
XBAR1_OUT57 FLEXPWM1_EXT_CLK -
XBAR1_OUT58 FLEXPWM1_FAULT0 -
XBAR1_OUT59 FLEXPWM1_FAULT1 -
XBAR_OUT60 FLEXPWM1_FAULT2 OR
FLEXPWM2_FAULT2 OR
FLEXPWM3_FAULT2 OR
FLEXPWM4_FAULT2 OR
XBAR_OUT61 FLEXPWM1_FAULT3 OR
FLEXPWM2_FAULT3 OR
FLEXPWM3_FAULT3 OR
FLEXPWM4_FAULT3 OR
XBAR1_OUT62 FLEXPWM1_EXT_FORCE -
XBAR1_OUT63 FLEXPWM2_PWM0_EXTA -
XBAR1_OUT64 FLEXPWM2_PWM1_EXTA -
XBAR1_OUT65 FLEXPWM2_PWM2_EXTA -
XBAR1_OUT66 FLEXPWM2_PWM3_EXTA -
XBAR1_OUT67 FLEXPWM2_PWM0_EXT_SYNC -
XBAR1_OUT68 FLEXPWM2_PWM1_EXT_SYNC -
XBAR1_OUT69 FLEXPWM2_PWM2_EXT_SYNC -
XBAR1_OUT70 FLEXPWM2_PWM3_EXT_SYNC -
XBAR1_OUT71 FLEXPWM2_EXT_CLK -
XBAR1_OUT72 FLEXPWM2_FAULT0 -
XBAR1_OUT73 FLEXPWM2_FAULT1 -
XBAR1_OUT74 FLEXPWM2_EXT_FORCE -
XBAR1_OUT75 FLEXPWM3_PWM0_EXTA OR
FLEXPWM4_PWM0_EXTA OR
XBAR1_OUT76 FLEXPWM3_PWM1_EXTA OR
FLEXPWM4_PWM1_EXTA OR
XBAR1_OUT77 FLEXPWM3_PWM2_EXTA OR
FLEXPWM4_PWM2_EXTA OR
XBAR1_OUT78 FLEXPWM3_PWM3_EXTA OR
FLEXPWM4_PWM3_EXTA OR
XBAR1_OUT79 FLEXPWM3_EXT_CLK OR
FLEXPWM4_EXT_CLK OR
XBAR1_OUT80 FLEXPWM3_PWM0_EXT_SYNC -
XBAR1_OUT81 FLEXPWM3_PWM1_EXT_SYNC -
XBAR1_OUT82 FLEXPWM3_PWM2_EXT_SYNC -
XBAR1_OUT83 FLEXPWM3_PWM3_EXT_SYNC -
XBAR1_OUT84 FLEXPWM3_FAULT0 -
Table continues on the next page...
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XBAR Resource Assignments
Table 4-8. XBAR1 Output Assignments (continued)
XBAR1 Output Assigned Output Gate
XBAR1_OUT85 FLEXPWM3_FAULT1 -
XBAR1_OUT86 FLEXPWM3_EXT_FORCE -
XBAR1_OUT87 FLEXPWM4_PWM0_EXT_SYNC -
XBAR1_OUT88 FLEXPWM4_PWM1_EXT_SYNC -
XBAR1_OUT89 FLEXPWM4_PWM2_EXT_SYNC -
XBAR1_OUT90 FLEXPWM4_PWM3_EXT_SYNC -
XBAR1_OUT91 FLEXPWM4_FAULT0 -
XBAR1_OUT92 FLEXPWM4_FAULT1 -
XBAR1_OUT93 FLEXPWM4_EXT_FORCE -
XBAR1_OUT94 -XBAR1_OUT107 Reserved -
XBAR1_OUT108 QDC1_PHASEA -
XBAR1_OUT109 QDC1_PHASEB -
XBAR1_OUT110 QDC1_INDEX -
XBAR1_OUT111 QDC1_HOME -
XBAR1_OUT112 QDC1_TRIGGER -
XBAR1_OUT113 QDC2_PHASEA -
XBAR1_OUT114 QDC2_PHASEB -
XBAR1_OUT115 QDC2_INDEX -
XBAR1_OUT116 QDC2_HOME -
XBAR1_OUT117 QDC2_TRIGGER -
XBAR1_OUT118 QDC3_PHASEA -
XBAR1_OUT119 QDC3_PHASEB -
XBAR1_OUT120 QDC3_INDEX -
XBAR1_OUT121 QDC3_HOME -
XBAR1_OUT122 QDC3_TRIGGER -
XBAR1_OUT123 QDC4_PHASEA -
XBAR1_OUT124 QDC4_PHASEB -
XBAR1_OUT125 QDC4_INDEX -
XBAR1_OUT126 QDC4_HOME -
XBAR1_OUT127 QDC4_TRIGGER -
XBAR1_OUT128 - XBAR1_OUT131 Reserved -
XBAR1_OUT132 CAN1 CAN1 external timer tick
XBAR1_OUT133 CAN2 CAN2 external timer tick
XBAR1_OUT134 - XBAR1_OUT137 Reserved -
XBAR1_OUT138 QTIMER1_TIMER0 Selectable by setting
IOMUXC_GPR_GPR12[QTIMER1_TRM
0_INPUT_SEL]
XBAR1_OUT139 QTIMER1_TIMER1 Selectable by setting
IOMUXC_GPR_GPR12[QTIMER1_TRM
1_INPUT_SEL]
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-8. XBAR1 Output Assignments (continued)
XBAR1 Output Assigned Output Gate
XBAR1_OUT140 QTIMER1_TIMER2 Selectable by setting
IOMUXC_GPR_GPR12[QTIMER1_TRM
2_INPUT_SEL]
XBAR1_OUT141 QTIMER1_TIMER3 Selectable by setting
IOMUXC_GPR_GPR12[QTIMER1_TRM
3_INPUT_SEL]
XBAR1_OUT142 QTIMER2_TIMER0 Selectable by setting
IOMUXC_GPR_GPR13[QTIMER2_TRM
0_INPUT_SEL]
XBAR1_OUT143 QTIMER2_TIMER1 Selectable by setting
IOMUXC_GPR_GPR13[QTIMER2_TRM
1_INPUT_SEL]
XBAR1_OUT144 QTIMER2_TIMER2 Selectable by setting
IOMUXC_GPR_GPR13[QTIMER2_TRM
2_INPUT_SEL]
XBAR1_OUT145 QTIMER2_TIMER3 Selectable by setting
IOMUXC_GPR_GPR13[QTIMER2_TRM
3_INPUT_SEL]
XBAR1_OUT146 QTIMER3_TIMER0 Selectable by setting
IOMUXC_GPR_GPR14[QTIMER3_TRM
0_INPUT_SEL]
XBAR1_OUT147 QTIMER3_TIMER1 Selectable by setting
IOMUXC_GPR_GPR14[QTIMER3_TRM
1_INPUT_SEL]
XBAR1_OUT148 QTIMER3_TIMER2 Selectable by setting
IOMUXC_GPR_GPR14[QTIMER3_TRM
2_INPUT_SEL]
XBAR1_OUT149 QTIMER3_TIMER3 Selectable by setting
IOMUXC_GPR_GPR14[QTIMER3_TRM
3_INPUT_SEL]
XBAR1_OUT150 QTIMER4_TIMER0 Selectable by setting
IOMUXC_GPR_GPR15[QTIMER4_TRM
0_INPUT_SEL]
XBAR1_OUT151 QTIMER4_TIMER1 Selectable by setting
IOMUXC_GPR_GPR15[QTIMER4_TRM
1_INPUT_SEL]
XBAR1_OUT152 QTIMER4_TIMER2 Selectable by setting
IOMUXC_GPR_GPR15[QTIMER4_TRM
2_INPUT_SEL]
XBAR1_OUT153 QTIMER4_TIMER3 Selectable by setting
IOMUXC_GPR_GPR15[QTIMER4_TRM
3_INPUT_SEL]
XBAR1_OUT154 EWM_IN -
XBAR1_OUT155 ADC_ETC0_TRIG0 -
XBAR1_OUT156 ADC_ETC0_TRIG1 -
XBAR1_OUT157 ADC_ETC0_TRIG2 -
XBAR1_OUT158 ADC_ETC0_TRIG3 -
Table continues on the next page...
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XBAR Resource Assignments
Table 4-8. XBAR1 Output Assignments (continued)
XBAR1 Output Assigned Output Gate
XBAR1_OUT159 ADC_ETC1_TRIG0 -
XBAR1_OUT160 ADC_ETC1_TRIG1 -
XBAR1_OUT161 ADC_ETC1_TRIG2 -
XBAR1_OUT162 ADC_ETC1_TRIG3 -
XBAR1_OUT163-170 Reserved -
XBAR1_OUT171 FLEXIO1_TRIG_IN0 -
XBAR1_OUT172 FLEXIO1_TRIG_IN1 -
XBAR1_OUT173 FLEXIO2_TRIG_IN0 -
XBAR1_OUT174 FLEXIO2_TRIG_IN1 -
XBAR1_OUT175-176 Reserved -
Table 4-9. XBAR2 Output Assignments
XBAR2 Output Assigned Output Gate
XBAR2_OUT00 AOI1_IN0 -
XBAR2_OUT01 AOI1_IN1 -
XBAR2_OUT02 AOI1_IN2 -
XBAR2_OUT03 AOI1_IN3 -
XBAR2_OUT04 AOI1_IN4 -
XBAR2_OUT05 AOI1_IN5 -
XBAR2_OUT06 AOI1_IN6 -
XBAR2_OUT07 AOI1_IN7 -
XBAR2_OUT08 AOI1_IN8 -
XBAR2_OUT09 AOI1_IN9 -
XBAR2_OUT10 AOI1_IN10 -
XBAR2_OUT11 AOI1_IN11 -
XBAR2_OUT12 AOI1_IN12 -
XBAR2_OUT13 AOI1_IN13 -
XBAR2_OUT14 AOI1_IN14 -
XBAR2_OUT15 AOI1_IN15 -
Table 4-10. XBAR3 Output Assignments
XBAR3 Output Assigned Output Gate
XBAR3_OUT0 AOI2_IN0 -
XBAR3_OUT1 AOI2_IN1 -
XBAR3_OUT2 AOI2_IN2 -
XBAR3_OUT3 AOI2_IN3 -
XBAR3_OUT4 AOI2_IN4 -
Table continues on the next page...
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Chapter 4 Interrupts, DMA Events, and XBAR Assignments
Table 4-10. XBAR3 Output Assignments (continued)
XBAR3 Output Assigned Output Gate
XBAR3_OUT5 AOI2_IN5 -
XBAR3_OUT6 AOI2_IN6 -
XBAR3_OUT7 AOI2_IN7 -
XBAR3_OUT8 AOI2_IN8 -
XBAR3_OUT9 AOI2_IN9 -
XBAR3_OUT10 AOI2_IN10 -
XBAR3_OUT11 AOI2_IN11 -
XBAR3_OUT12 AOI2_IN12 -
XBAR3_OUT13 AOI2_IN13 -
XBAR3_OUT14 AOI2_IN14 -
XBAR3_OUT15 AOI2_IN15 -
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XBAR Resource Assignments
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Chapter 5
Direct Memory Access Multiplexer (DMAMUX)
5.1 Chip-specific DMAMUX information
Table 5-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
DMA Mux Mapping DMAMUX DMA Mux
5.2 Overview
The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots,
to any of the 32 DMA channels.
5.2.1 Block diagram
The following figure illustrates the block diagram of DMAMUX.
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Overview
DMA channel #0
Source #1 DMAMUX
DMA channel #1
Source #2
Source #3
Source #x
Trigger #1
DMA channel #n
Trigger #z
Figure 5-1. DMAMUX block diagram
5.2.2 Features
The DMAMUX module provides these features:
• Up to 208 peripheral slots can be routed to 32 channels.
• 32 independently selectable DMA channel routers.
• Each channel output can be individually configured to be Always On and not
depend on any of the peripheral slots.
• The first 4 channels additionally provide a trigger functionality.
• Each channel router can be assigned to one of the possible peripheral DMA slots.
• On every memory map configuration change for a any channel, this module signals
to the DMA Controller to reset the internal state machine for that channel and it can
accept a new request based on the new configuration.
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
5.3 Functional description
The primary purpose of the DMAMUX is to provide flexibility in the system's use of the
available DMA channels.
As such, configuration of the DMAMUX is intended to be a static procedure done during
execution of the system boot code. However, if the procedure outlined in Enabling and
configuring sources is followed, the configuration of the DMAMUX may be changed
during the normal operation of the system.
Functionally, the DMAMUX channels may be divided into two classes:
• Channels that implement the normal routing functionality plus periodic triggering
capability
• Channels that implement only the normal routing functionality
5.3.1 Modes of operation
The following operating modes are available:
• Disabled mode
In this mode, the DMA channel is disabled. Because disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place, for example, changing the period of a DMA trigger.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The
operation of the DMAMUX in this mode is completely transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a
transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done in the registers of the periodic interrupt timer
(PIT). This mode is available only for channels 0 to 3.
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Functional description
5.3.2 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.
The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration
of the periodic triggering interval is done via configuration registers in the PIT. See the
section on periodic interrupt timer for more information on this topic.
Note
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.
Source #1
Source #2
Source #3
DMA channel #0
Trigger #1
DMA channel #m-1
Trigger #m
Source #x
Figure 5-2. DMAMUX triggered channels
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
The DMA channel triggering capability allows the system to schedule regular DMA
transfers, usually on the transmit side of certain peripherals, without the intervention of
the processor. This trigger works by gating the request from the peripheral to the DMA
until a trigger event has been seen. This is illustrated in the following figure.
Peripheral request
Trigger
DMA request
Figure 5-3. DMAMUX channel triggering: normal operation
After the DMA request has been serviced, the peripheral will negate its request,
effectively resetting the gating mechanism until the peripheral reasserts its request and
the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not
requesting a transfer, then that trigger will be ignored. This situation is illustrated in the
following figure.
Peripheral request
Trigger
DMA request
Figure 5-4. DMAMUX channel triggering: ignored trigger
This triggering capability may be used with any peripheral that supports DMA transfers,
and is most useful for two types of situations:
• Periodically polling external devices on a particular bus
As an example, the transmit side of an SPI is assigned to a DMA channel with a
trigger, as described above. After it has been set up, the SPI will request DMA
transfers, presumably from memory, as long as its transmit buffer is empty. By using
a trigger on this channel, the SPI transfers can be automatically performed every 5 μs
(as an example). On the receive side of the SPI, the SPI and DMA can be configured
to transfer receive data into memory, effectively implementing a method to
periodically read data from external devices and transfer the results into memory
without processor intervention.
• Using the GPIO ports to drive or sample waveforms
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Functional description
By configuring the DMA to transfer data to one or more GPIO ports, it is possible to
create complex waveforms using tabular data stored in on-chip memory. Conversely,
using the DMA to periodically transfer data from one or more GPIO ports, it is
possible to sample complex waveforms and store the results in tabular form in on-
chip memory.
A more detailed description of the capability of each trigger, including resolution, range
of values, and so on, may be found in the periodic interrupt timer section.
5.3.3 Always-enabled DMA sources
In addition to the peripherals that can be used as DMA sources, each DMA Channel can
be individually configured to function as an Always Enabled source. Unlike the
peripheral DMA sources, where the peripheral controls the flow of data during DMA
transfers, the always enabled channel provide no such "throttling" of the data transfers.
These sources are most useful in the following cases:
• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO
pins, either unthrottled (that is, as fast as possible), or periodically (using the DMA
triggering capability).
• Performing DMA transfers from memory to memory—Moving data from memory to
memory, typically as fast as possible, sometimes with software activation.
• Performing DMA transfers from memory to the external bus, or vice-versa—Similar
to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should
be explicitly started by software.
In cases where software should initiate the start of a DMA transfer, an always-enabled
DMA channel can be used to provide maximum flexibility. When activating a DMA
channel via software, subsequent executions of the minor loop require that a new start
event be sent. This can either be a new software activation, or a transfer request from the
DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop.
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
By configuring the DMA to transfer all of the data in a single minor loop (that is,
major loop counter = 1), no reactivation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the
DMA transfer will impose on the system. For this option, the DMA channel must be
disabled in the DMA channel MUX.
• Use explicit software reactivation.
In this option, the DMA is configured to transfer the data using both minor and major
loops, but the processor is required to reactivate the channel by writing to the DMA
registers after every minor loop. For this option, the DMA channel must be disabled
in the DMA channel MUX.
• Use an always-enabled DMA source.
In this option, the DMA is configured to transfer the data using both minor and major
loops, and the DMA channel MUX does the channel reactivation. For this option, the
DMA channel should be enabled and configured as "always enabled" channel. Note
that the reactivation of the channel can be continuous (DMA triggering is disabled)
or can use the DMA triggering capability. In this manner, it is possible to execute
periodic transfers of packets of data from one source to another, without processor
intervention.
NOTE
When a channel is configured as "Always Enabled", then
the peripheral DMA sources for that channel are ignored;
i.e. SOURCE field has no effect.
5.3.4 Clocks
The following table describes the clock sources for DMAMUX. Please see Clock
Controller Module (CCM) for clock setting, configuration and gating information.
Table 5-2. DMAMUX clock
Clock name Description
ipg_clk Peripheral clock
ipg_clk_s Peripheral access clock
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External signals
5.3.5 Reset
The reset state of each individual bit is shown in Memory map/register definition. In
summary, after reset, all channels are disabled and must be explicitly enabled before use.
5.4 External signals
The DMAMUX has no external pins.
5.5 Application information
This section provides instructions for initializing the DMA channel MUX.
5.5.1 Enabling and configuring sources
To enable a source with periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Configure the corresponding timer.
5. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.
NOTE
The following is an example. See the chip configuration details
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1, with periodic triggering
capability:
1. Write 0x00000000 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Configure a timer for the desired trigger interval.
4. Write 0xC0000005 to CHCFG1.
The following code example illustrates steps 1 and 4 above:
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE)
{
DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE;
DMAMUX_0.CHCFG[DMA_CH].B.ENBL = 1;
DMAMUX_0.CHCFG[DMA_CH].B.TRIG = 1;
}
To enable a source without periodic triggering:
1. Determine with which DMA channel the source will be associated. Note that only the
first 4 DMA channels have periodic triggering capability.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel
may be enabled at this point.
4. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that CHCFG[ENBL] is setwhile CHCFG[TRIG] is
cleared.
NOTE
The following is an example. See the chip configuration details
for the number of this device's DMA channels that have
triggering capability.
To configure source #5 transmit for use with DMA channel 1 with no periodic triggering
capability :
1. Write 0x00000000 to CHCFG1.
2. Configure channel 1 in the DMA, including enabling the channel.
3. Write 0x80000005 to CHCFG1.
The following code example illustrates steps 1 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes long is 32-bits */
volatile unsigned long *CHCFG0 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned long *CHCFG1 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned long *CHCFG2 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned long *CHCFG3 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned long *CHCFG4 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0010);
volatile unsigned long *CHCFG5 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0014);
volatile unsigned long *CHCFG6 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0018);
volatile unsigned long *CHCFG7 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x001C);
volatile unsigned long *CHCFG8 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0020);
volatile unsigned long *CHCFG9 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0024);
volatile unsigned long *CHCFG10= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0028);
volatile unsigned long *CHCFG11= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x002C);
volatile unsigned long *CHCFG12= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0030);
volatile unsigned long *CHCFG13= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0034);
volatile unsigned long *CHCFG14= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0038);
volatile unsigned long *CHCFG15= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x003C);
In File main.c:
#include "registers.h"
:
:
*CHCFG1 = 0x00000000;
*CHCFG1 = 0x80000005;
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Application information
To disable a source:
A particular DMA source may be disabled by not writing the corresponding source value
into any of the CHCFG registers. Additionally, some module-specific configuration may
be necessary. See the appropriate section for more details.
To switch the source of a DMA channel:
1. Disable the DMA channel in the DMA and reconfigure the channel for the new
source.
2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel.
3. Select the source to be routed to the DMA channel. Write to the corresponding
CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are
set.
To switch DMA channel 8 from source #5 transmit to source #7 transmit:
1. In the DMA configuration registers, disable DMA channel 8 and reconfigure it to
handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't
have triggering capability.
2. Write 0x00000000 to CHCFG8.
3. Write 0x80000007 to CHCFG8. (In this example, setting CHCFG[TRIG] would have
no effect due to the assumption that channel 8 does not support the periodic
triggering functionality.)
The following code example illustrates steps 2 and 3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */
/* Following example assumes long is 32-bits */
volatile unsigned long *CHCFG0 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0000);
volatile unsigned long *CHCFG1 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0004);
volatile unsigned long *CHCFG2 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0008);
volatile unsigned long *CHCFG3 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x000C);
volatile unsigned long *CHCFG4 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0010);
volatile unsigned long *CHCFG5 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0014);
volatile unsigned long *CHCFG6 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0018);
volatile unsigned long *CHCFG7 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x001C);
volatile unsigned long *CHCFG8 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0020);
volatile unsigned long *CHCFG9 = (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0024);
volatile unsigned long *CHCFG10= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0028);
volatile unsigned long *CHCFG11= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x002C);
volatile unsigned long *CHCFG12= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0030);
volatile unsigned long *CHCFG13= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0034);
volatile unsigned long *CHCFG14= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x0038);
volatile unsigned long *CHCFG15= (volatile unsigned long *) (DMAMUX_BASE_ADDR+0x003C);
In File main.c:
#include "registers.h"
:
:
*CHCFG8 = 0x00000000;
*CHCFG8 = 0x80000007;
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
5.6 Initialization
5.6.1 Configuration options
Table 5-3. Channel Configuration Options
ENBL TRIG A_ON Function Mode
0 X X DMA channel is disabled Disabled Mode
1 0 0 DMA channel is enabled with no triggering (transparent) Normal Mode
1 1 0 DMA channel is enabled with triggering Periodic Trigger Mode
1 0 1 DMA channel is always enabled Always On Mode
Always On Trigger
1 1 1 DMA channel is always enabled with triggering
Mode
5.7 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the
DMAMUX.
5.7.1 DMAMUX register descriptions
5.7.1.1 DMAMUX memory map
DMAMUX0 base address: 4007_4000h
DMAMUX1 base address: 40C1_8000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 - 7C Channel a Configuration Register (CHCFG0 - CHCFG31) 32 RW 0000_0000
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Memory map/register definition
5.7.1.2 Channel a Configuration Register (CHCFG0 - CHCFG31)
Each of the DMA channels can be independently enabled/disabled and associated with
one of the DMA slots (peripheral slots or always-on slots) in the system.
NOTE
Setting multiple CHCFG registers with the same source value
will result in unpredictable behavior. This is true, even if a
channel is disabled (ENBL==0).
Before changing the trigger or source settings, a DMA channel
must be disabled via CHCFGn[ENBL].
5.7.1.2.1 Offset
For a = 0 to 31:
Register Offset
CHCFGa 0h + (a × 4h)
5.7.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
A_ON
TRIG
0
ENB
W
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
SOURCE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5.7.1.2.3 Fields
Field Description
31 DMA Mux Channel Enable
ENBL Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be
used to disable or reconfigure a DMA channel.
0 - DMA Mux channel is disabled
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Chapter 5 Direct Memory Access Multiplexer (DMAMUX)
Field Description
1 - DMA Mux channel is enabled
30 DMA Channel Trigger Enable
TRIG Enables the periodic trigger capability for the triggered DMA channel.
0 - Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
specified source to the DMA channel. (Normal mode)
1 - Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic
Trigger mode.
29 DMA Channel Always Enable
A_ON Enables the DMA Channel to be always ON. If TRIG bit is set, the module will assert request on every
trigger.
0 - DMA Channel Always ON function is disabled
1 - DMA Channel Always ON function is enabled
28-8 Reserved field
—
7-0 DMA Channel Source (Slot Number)
SOURCE Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific
DMA_CH_MUX information for details about the peripherals and their slot numbers.
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Memory map/register definition
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Chapter 6
Enhanced Direct Memory Access (eDMA)
6.1 Chip-specific eDMA information
Table 6-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
6.2 Overview
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data transfers with minimal intervention from a host
processor. The hardware microarchitecture includes:
• A DMA engine that performs:
• Source address and destination address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 32 channels
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Overview
6.2.1 Block diagram
The following figure illustrates the components of the eDMA system, including the
eDMA module ("engine").
eDMA system
Write address
Write data
0
1
2
Internal peripheral bus
To/From crossbar switch
Transfer Control
Descriptor (TCD)
n-1
64
eDMA engine Read data
Program model /
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 6-1. eDMA system block diagram
6.2.2 Block parts
The eDMA module comprises two major modules: the eDMA engine and the transfer-
control descriptor local memory.
Table 6-2 describes the eDMA engine submodules.
Table 6-2. eDMA engine submodules
Submodule Function
Address path The address path block:
• Provides registered versions of two channel Transfer Control Descriptors (TCDs)—channel
x (normal start) and channel y (preemption start)
• Manages all master bus-address calculations
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Chapter 6 Enhanced Direct Memory Access (eDMA)
Table 6-2. eDMA engine submodules (continued)
Submodule Function
All channels provide the same functionality. This structure enables preemption of data transfers
associated with an active channel (after completion of a read/write sequence) if the eDMA engine
asserts a higher priority channel activation.
After eDMA activates a channel, it runs until the minor loop completes, unless preempted by a
higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) in which the
eDMA engine can preempt a large data move operation to minimize the time another channel
stalls.
When the eDMA engine selects a channel to execute, it reads the contents of the channel TCD
from local memory and loads it into one of the following:
• The address path channel x registers (normal start)
• The address path channel y registers (preemption start)
After the minor loop execution completes, the address path hardware writes the new values for
the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count
completes, the eDMA engine performs additional processing, including:
• Final address pointer updates
• Reloading the TCDn_CITER field
• A possible fetch of the next TCDn from memory as part of a scatter/gather operation.
Data path The data path block implements the bus master read/write data path. It includes a data buffer and
the necessary multiplex logic to support any required data alignment. The internal read data bus is
the primary input, and the internal write data bus is the primary output.
The address and data path modules directly support the two-stage pipelined internal bus. The
address path module represents the first stage of the bus pipeline (address phase). The data path
module implements the second stage of the pipeline (data phase).
Programming model/ This block implements:
channel arbitration • The first section of the eDMA programming model
• Channel arbitration logic
The programming model registers connect to the chip's internal peripheral bus. The eDMA
peripheral request inputs and interrupt request outputs also connect to this block (via control
logic).
Control The control block provides all control functions for the eDMA engine. For data transfers in which
the source size (SSIZE) and destination size (DSIZE) are equal, the eDMA engine performs a
series of source read/destination write operations until it has transferred the number of bytes
specified in the minor loop byte count (NBYTES). For TCDs in which the source and destination
sizes are not equal, the eDMA engine executes multiple accesses of the smaller size data for
each reference of the larger size. For example, if the source size (SSIZE) references 16-bit data
and the destination size (DSIZE) is 32-bit data, eDMA performs two reads, then one 32-bit write.
Table 6-3 explains the partitioning of the TCD local memory.
Table 6-3. Transfer control descriptor memory
Submodule Description
Memory controller The memory controller logic implements the required dual-ported controller, managing accesses
from the eDMA engine as well as references from the internal peripheral bus. If simultaneous
accesses occur, the eDMA engine receives priority and the peripheral transaction stalls.
Memory array The memory array provides TCD storage for the transfer profile for each channel.
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Overview
6.2.3 Features
The eDMA module is a highly programmable data-transfer engine optimized to minimize
any required intervention from the host processor. Use it for applications where you
statically know the size of the data to be transferred and do not define the size within the
transferred data itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 32-channel implementation performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch (AXBS) for bus mastering the data
movement
• TCD supports two-deep, nested transfer operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion notification via programmable interrupt requests
• One interrupt per channel. eDMA engine can generate an interrupt when major
iteration count completes
• Programmable error terminations per channel and logically summed together to
form one error interrupt to the interrupt controller
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Chapter 6 Enhanced Direct Memory Access (eDMA)
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
NOTE
In the discussion of this module, n is the channel number.
6.3 Functional description
The operation of the eDMA is described in the following subsections.
6.3.1 Modes of operation
eDMA operates in the following modes:
Table 6-4. Modes of operation
Mode Description
Normal In Normal mode, eDMA transfers data from a source to a destination. The source and destination
can be a memory block or an I/O block capable of operation with eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the
TCD.
• The minor loop is the sequence of read and write operations that transfers the NBYTES of
data for a service request.
• Each service request executes one iteration of the major loop, transferring NBYTES of data.
Debug DMA operation is configurable in Debug mode via Control (CR)
• If CR[EDBG] = 0, eDMA continues to operate normally when the chip is in debug mode.
• If CR[EDBG] = 1, eDMA stops transferring data when the chip enters debug mode. If a
channel is active when eDMA enters Debug mode, eDMA continues operation until the
channel retires.
Wait Before entering Wait mode, eDMA attempts to complete any transfer that is in progress. After the
transfer completes, the chip enters Wait mode.
6.3.2 eDMA basic data flow
The basic flow of a data transfer can be partitioned into three segments.
As shown in the following diagram, the first segment involves the channel activation:
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Functional description
eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer Control
Descriptor (TCD)
n-1
64
eDMA engine Read data
Program model /
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 6-2. eDMA operation, part 1
This example uses the assertion of the eDMA peripheral request signal to request service
for channel n. Channel activation via software and the TCDn_CSR[START] bit follows
the same basic flow as peripheral requests. The eDMA request input signal is registered
internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration. In the next cycle, the channel
arbitration executes, using either the fixed-priority or round-robin algorithm. After
arbitration is complete, the activated channel number is sent through the address path and
converted into the required address to access the local memory for TCDn. Next, the TCD
memory is accessed and the required descriptor read from the local memory and loaded
into the eDMA engine's internal register file. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the
internal register file.
The following diagram illustrates the second part of the basic data flow:
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Chapter 6 Enhanced Direct Memory Access (eDMA)
eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer Control
Descriptor (TCD)
n-1
64
eDMA engine Read data
Program model /
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 6-3. eDMA operation, part 2
The modules associated with the data transfer (address path, data path, and control)
execute sequentially through the required source reads and destination writes to perform
the data movement. The source reads are initiated and the fetched data is temporarily
stored in the data path block until it is gated onto the internal bus during the destination
write. This source read/destination write processing continues until the minor byte count
has transferred.
After the minor byte count has moved, the final phase of the basic data flow is performed.
In this segment, the address path logic performs the required updates to certain fields in
the appropriate TCD, for example, SADDR, DADDR, CITER. If the major iteration
count is exhausted, additional operations are performed. These include the final address
adjustments and reloading of the BITER field into the CITER. Assertion of an optional
interrupt request also occurs at this time, as does a possible fetch of a new TCD from
memory using the scatter/gather address pointer included in the descriptor (if scatter/
gather is enabled). The updates to the TCD memory and the assertion of an interrupt
request are shown in the following diagram.
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Functional description
eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer Control
Descriptor (TCD)
n-1
64
eDMA engine Read data
Program model /
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 6-4. eDMA operation, part 3
6.3.3 Fault reporting and handling
Channel errors are reported in the Error Status register (DMAx_ES) and can be caused
by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes is detailed below:
• The addresses and offsets must be aligned on 0-modulo transfer size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
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Chapter 6 Enhanced Direct Memory Access (eDMA)
• All source reads and destination writes must be configured to the natural boundary of
the programmed transfer size respectively.
• In fixed arbitration mode, a configuration error is caused by any two channel
priorities being equal. All channel priority levels must be unique when fixed
arbitration mode is enabled.
NOTE
When two channels have the same priority, a channel
priority error exists and is reported in the Error Status
register. However, the channel number is not reported in
the Error Status register. When all of the channel priorities
within a group are not unique, the channel number selected
by arbitration is undetermined.
To aid in Channel Priority Error (CPE) debug, set the Halt
On Error bit in the DMA’s Control register. If all channel
priorities within a group are not unique, the DMA is halted
after the CPE error is recorded. The DMA remains halted
and does not process any channel service requests. After all
of the channel priorities are set to unique numbers, the
DMA may be enabled again by clearing the HALT bit.
• If a scatter/gather operation is enabled upon channel completion, a configuration
error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-
byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration
error is reported when the link is attempted if the TCDn_CITER[ELINK] bit does
not equal the TCDn_BITER[ELINK] bit.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop
link errors, report as the channel activates and asserts an error interrupt request. A scatter/
gather configuration error is reported when the scatter/gather operation begins at major
loop completion, when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and
the appropriate bus error flag set. In this case, the state of the channel's transfer control
descriptor is updated by the eDMA engine with the current source address, destination
address, and current iteration count at the point of the fault. When a system bus error
occurs, the channel terminates after the next transfer. Due to pipeline effect, the next
transfer is already in progress when the bus error is received by the eDMA. If a bus error
occurs on the last read prior to beginning the write sequence, the write executes using the
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Functional description
data captured during the bus error. If a bus error occurs on the last write prior to
switching to the next read sequence, the read sequence executes before the channel
terminates due to the destination bus error.
A transfer may be canceled by software with the CR[CX] bit. When a cancel transfer
request is recognized, the DMA engine stops processing the channel. The current read-
write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of
a major or minor loop, the cancel request is discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the Error Status register
(DMAx_ES) is updated with the canceled channel number and ECX is set. The TCD of a
canceled channel contains the source and destination addresses of the last transfer saved
in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because
the aforementioned fields no longer represent the original parameters. When a transfer is
canceled by the error cancel transfer mechanism, the channel number is loaded into
DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be
generated if enabled.
NOTE
The cancel transfer request enables you to stop a large data
transfer when the full data transfer is no longer needed. The
cancel transfer bit does not abort the channel. It simply stops
the transferring of data and then retires the channel through its
normal shutdown sequence. The application software must
manage the context of the cancel. If an interrupt is desired (or
not), then the interrupt should be enabled (or disabled) before
the cancel request. The application software must clean up the
transfer control descriptor because the full transfer did not
occur.
The occurrence of any error causes the eDMA engine to stop normal processing of the
active channel immediately (it goes to its error processing states and the transaction to the
system bus still has pipeline effect), and the appropriate channel bit in the eDMA error
register is asserted. At the same time, the details of the error condition are loaded into the
Error Status register (DMAx_ES). The major loop complete indicators, setting the
transfer control descriptor DONE flag and the possible assertion of an interrupt request,
are not affected when an error is detected. After the error status has been updated, the
eDMA engine continues operating by servicing the next appropriate channel. A channel
that experiences an error condition is not automatically disabled. If a channel is
terminated by an error and then issues another service request before the error is fixed,
that channel executes and terminates with the same error condition.
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.3.4 Channel preemption
Channel preemption is enabled on a per-channel basis by setting DCHPRIn[ECP].
Channel preemption enables the executing channel’s data transfers to temporarily be
suspended in favor of starting a higher priority channel. After the preempting channel has
completed its minor loop data transfers, the preempted channel is restored and resumes
execution. After the restored channel completes one read/write sequence, it is again
eligible for preemption. If any higher priority channel is requesting service, the restored
channel is suspended and the higher priority channel is serviced. Nested preemption, that
is, attempting to preempt a preempting channel, is not supported. After a preempting
channel begins execution, it cannot be preempted. Preemption is available only when
fixed arbitration is selected.
A channel’s ability to preempt another channel can be disabled by setting
DCHPRIn[DPA]. When a channel’s preemption ability is disabled, that channel cannot
suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s
ECP setting. This enables a pool of low priority, large data-moving channels to be
defined. These low priority channels can be configured to not preempt each other, thus
preventing a low priority channel from consuming the preempt slot normally available to
a true, high priority channel.
6.3.5 Clocks
The following table describes the clock sources for eDMA. Please see Clock Controller
Module (CCM) for clock setting, configuration and gating information.
Table 6-5. eDMA clocks
Clock name Description
edma_hclk Module clock
ipg_clk Peripheral clock
6.4 Initialization/application information
The following sections discuss initialization of the eDMA and programming
considerations.
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6.4.1 eDMA initialization
To initialize the eDMA:
1. Write to the CR if a configuration other than the default is desired.
2. Write the channel priority levels to the DCHPRIn registers if a configuration other
than the default is desired.
3. Enable error interrupts in the EEI register if desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the ERQ register.
6. Request channel service via either:
• Software: setting TCDn_CSR[START]
• Hardware: slave device asserting its eDMA peripheral request signal
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels in the programming model. The eDMA engine reads the
entire TCD, including the TCD control and status fields, as shown in Table 6-6, for the
selected channel into its internal address path module.
As the TCD is read, the first transfer is initiated on the system bus, unless a configuration
error is detected. Transfers from the source, as defined by TCDn_SADDR, to the
destination, as defined by TCDn_DADDR, continue until the number of bytes specified
by TCDn_NBYTES have been transferred.
When the transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted,
further post-processing executes, such as interrupts, major loop channel linking, and
scatter/gather operations, if enabled.
Table 6-6. TCD control and status fields
TCDn_CSR field
Description
name
START Control bit to start channel explicitly when using a software-initiated DMA service (automatically
cleared by hardware)
ACTIVE Status bit indicating the channel is currently in execution
DONE Status bit indicating major loop completion (cleared by software when using a software-initiated
DMA service)
DREQ Control bit to disable DMA request at end of major loop completion when using a hardware-initiated
DMA service
BWC Control bits for throttling bandwidth control of a channel
ESG Control bit to enable scatter/gather feature
INTHALF Control bit to enable interrupt when major loop is half complete
INTMAJOR Control bit to enable interrupt when major loop completes
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The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
Current major
loop iteration
Source or destination memory count (CITER)
DMA request
• Minor loop 3
•
•
DMA request
• Minor loop Major loop 2
•
•
DMA request
• Minor loop 1
•
•
Figure 6-5. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings interrelate.
xADDR: (Starting address) xSIZE: (size of one
data transfer) Minor loop
(NBYTES in
• minor loop, Offset (xOFF): number of bytes added to
• often the same current address after each transfer
• value as xSIZE) (often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
• •
• •
Address (xADDR)
• • Size (xSIZE)
Minor loop Offset (xOFF)
• •
• • Modulo (xMOD)
• • Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
•
• Last minor loop to NBYTES
•
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
Figure 6-6. Memory array terms
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6.4.2 Programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency
in the descriptor data. Most programming errors are reported on a per-channel basis with
the exception of channel priority error (ES[CPE]).
For all error types other than group or channel priority errors, the channel number
causing the error is recorded in the Error Status register (DMAx_ES). If the error source
is not removed before the next activation of the problem channel, the error is detected and
recorded again.
Channel priority errors are identified within a group after that group has been selected as
the active group. For example:
1. The eDMA is configured for fixed group and fixed channel arbitration modes.
2. Group 1 is the highest priority and all channels are unique in that group.
3. Group 0 is the next highest priority and has two channels with the same priority
level.
4. If Group 1 has any service requests, those requests will be executed.
5. After all of Group 1 requests have completed, Group 0 will be the next active group.
6. If Group 0 has a service request, then an undefined channel in Group 0 will be
selected and a channel priority error will occur.
7. This repeats until the all of Group 0 requests have been removed or a higher priority
Group 1 request comes in.
In this sequence, for item 2, the eDMA acknowledge lines will assert only if the selected
channel is requesting service via the eDMA peripheral request signal. If interrupts are
enabled for all channels, the user will get an error interrupt, but the channel number for
the ERR register and the error interrupt request line may be wrong because they reflect
the selected channel. A group priority error is global and any request in any group will
cause a group priority error.
If priority levels are not unique, when any channel requests service, a channel priority
error is reported. The highest channel/group priority with an active request is selected,
but the lowest numbered channel with that priority is selected by arbitration and executed
by the eDMA engine. The hardware service request handshake signals, error interrupts,
and error reporting are associated with the selected channel.
6.4.3 Arbitration mode considerations
This section discusses arbitration considerations for the eDMA.
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6.4.3.1 Fixed group arbitration, Fixed channel arbitration
In this mode, the channel service request from the highest priority channel in the highest
priority group is selected to execute. If the eDMA is programmed so that the channels
within one group use "fixed" priorities, and that group is assigned the highest "fixed"
priority of all groups, that group can take all the bandwidth of the eDMA controller. That
is, no other groups will be serviced if there is always at least one DMA request pending
on a channel in the highest priority group when the controller arbitrates the next DMA
request. The advantage of this scenario is that latency can be small for channels that need
to be serviced quickly. Preemption is available in this scenario only.
6.4.3.2 Fixed group arbitration, Round-robin channel arbitration
The highest priority group with a request will be serviced. Lower priority groups will be
serviced if no pending requests exist in the higher priority groups.
Within each group, c hannels are serviced starting with the highest channel number and
rotating through to the lowest channel number without regard to the channel priority
levels assigned within the group.
This scenario could cause the same bandwidth consumption problem as indicated in
Fixed group arbitration, Fixed channel arbitration, but all the channels in the highest
priority group will be serviced. Service latency will be short on the highest priority group,
but could potentially be very much longer as the group priority decreases.
6.4.4 DMA transfer examples
This section presents examples of how to perform DMA transfers with the eDMA.
6.4.4.1 Single request
To perform a simple transfer of n bytes of data with one activation, set the major loop to
one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel
service request is acknowledged and the channel is selected to execute. After the transfer
is complete, TCDn_CSR[DONE] is set and an interrupt generates if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The
eDMA is programmed for one iteration of the major loop transferring 16 bytes per
iteration. The source memory has an 8-bit memory port located at 0x1000. The
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destination memory has a 32-bit port located at 0x2000. The address offsets are
programmed in increments to match the transfer size: one byte for the source and four
bytes for the destination. The final source and destination addresses are adjusted to return
to their beginning values.
TCDn_CITER = TCDn_BITER = 1
TCDn_NBYTES = 16
TCDn_SADDR = 0x1000
TCDn_SOFF = 1
TCDn_ATTR[SSIZE] = 0
TCDn_SLAST = -16
TCDn_DADDR = 0x2000
TCDn_DOFF = 4
TCDn_ATTR[DSIZE] = 2
TCDn_DLAST_SGA= –16
TCDn_CSR[INTMAJOR] = 1
TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized)
All other TCDn fields = 0
This generates the following event sequence:
1. User write to the TCDn_CSR[START] bit requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32 bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32 bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32 bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32 bits to location 0x200C → last iteration of the minor loop → major loop
complete.
6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 1 (TCDn_BITER).
7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1,
INT[n] = 1.
8. The channel retires and the eDMA goes idle or services the next channel.
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6.4.4.2 Multiple requests
The following example transfers 32 bytes via two hardware requests, but is otherwise the
same as the previous example. The only fields that change are the major loop iteration
count and the final address offsets. The eDMA is programmed for two iterations of the
major loop, transferring 16 bytes per iteration. After the channel's hardware requests are
enabled in the ERQ register, the slave device initiates channel service requests.
TCDn_CITER = TCDn_BITER = 2
TCDn_SLAST = –32
TCDn_DLAST_SGA = –32
This would generate the following sequence of events:
1. First hardware, that is, the eDMA peripheral, requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCDn data from local memory to internal register file.
5. The source to destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32 bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32 bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32 bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32 bits to location 0x200C → last iteration of the minor loop.
6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010,
TCDn_CITER = 1.
7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0.
8. The channel retires → one iteration of the major loop. The eDMA goes idle or
services the next channel.
9. Second hardware, that is, eDMA peripheral, requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
TCDn_CSR[ACTIVE] = 1.
12. eDMA engine reads channel TCD data from local memory to internal register file.
13. The source to destination transfers are executed as follows:
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a. Read byte from location 0x1010, read byte from location 0x1011, read byte from
0x1012, read byte from 0x1013.
b. Write 32 bits to location 0x2010 → first iteration of the minor loop.
c. Read byte from location 0x1014, read byte from location 0x1015, read byte from
0x1016, read byte from 0x1017.
d. Write 32 bits to location 0x2014 → second iteration of the minor loop.
e. Read byte from location 0x1018, read byte from location 0x1019, read byte from
0x101A, read byte from 0x101B.
f. Write 32 bits to location 0x2018 → third iteration of the minor loop.
g. Read byte from location 0x101C, read byte from location 0x101D, read byte
from 0x101E, read byte from 0x101F.
h. Write 32 bits to location 0x201C → last iteration of the minor loop → major loop
complete.
14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 2 (TCDn_BITER).
15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1,
INT[n] = 1.
16. The channel retires → major loop complete. The eDMA goes idle or services the next
channel.
6.4.4.3 Using the modulo feature
The modulo feature of the eDMA provides the ability to implement a circular data queue
in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and
destination in the TCD, and it specifies which lower address bits increment from their
original value after the address+offset calculation. All upper address bits remain the same
as in the original value. A setting of zero for this field disables the modulo feature.
The following table shows how the transfer addresses are specified based on the setting
of the MOD field. Here a circular buffer is created where the address wraps to the
original value while the 28 upper address bits (0x1234567x) retain their original value. In
this example the source address is set to 0x12345670, the offset is set to 4 bytes, and the
MOD field is set to 4, allowing for a 24 byte (16-byte) size queue.
Table 6-7. Modulo example
Transfer number Address
1 0x12345670
2 0x12345674
3 0x12345678
4 0x1234567C
Table continues on the next page...
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Table 6-7. Modulo example (continued)
Transfer number Address
5 0x12345670
6 0x12345674
6.4.5 Monitoring transfer descriptor status
This section discusses how to monitor eDMA status.
6.4.5.1 Testing for minor loop completion
There are two methods to test for minor loop completion when using software-initiated
service requests. The first is to read the TCDn_CITER field and test for a change.
Another method may be extracted from the sequence shown below. The second method is
to test TCDn_CSR[START] and TCDn_CSR[ACTIVE]. The minor-loop-complete
condition is indicated by both bits reading zero after TCDn_CSR[START] was set.
Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may
be missed if the channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
TCDn_CSR bits
Stage State
START ACTIVE DONE
1 1 0 0 Channel service request via software
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
The best method to test for minor-loop completion when using service requests initiated
by hardware, that is, peripherals, is to read the TCDn_CITER field and test for a change.
The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status bits execute the following sequence for a hardware-activated channel:
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TCDn_CSR bits
Stage State
START ACTIVE DONE
Channel service request via hardware (peripheral
1 0 0 0
request asserted)
2 0 1 0 Channel is executing
3a 0 0 0 Channel has completed the minor loop and is idle
3b 0 0 1 Channel has completed the major loop and is idle
For both activation types, the major-loop-complete status is explicitly indicated via the
TCDn_CSR[DONE] bit.
The TCDn_CSR[START] bit is cleared automatically when the channel begins execution
regardless of how the channel activates.
6.4.5.2 transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if read when a channel executes. The true values of SADDR, DADDR, and
NBYTES are the values the eDMA engine currently uses in its internal register file and
not the values in the TCD local memory for that channel. The addresses, SADDR and
DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an
indication of the progress of the transfer. All other values are read back from the TCD
local memory.
6.4.5.3 Checking channel preemption status
Preemption is available only when fixed arbitration is selected for both group and
channel arbitration modes. A preemptive situation is one in which a preempt-enabled
channel runs and a higher priority request becomes active. When the eDMA engine is not
operating in fixed group, fixed channel arbitration mode, determination of the actively
running relative priority outstanding requests become undefined. Channel and/or group
priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration
mode is selected.
The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout
the preemption. The preempted channel is temporarily suspended while the preempting
channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set
simultaneously in the global TCD map, a higher priority channel is actively preempting a
lower priority channel.
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6.4.6 Channel linking
Channel linking (or chaining) is a mechanism where one channel sets the
TCDn_CSR[START] bit of another channel (or itself), thus initiating a service request
for that channel. When properly enabled, the EDMA engine automatically performs this
operation at the major or minor loop completion.
The minor loop channel linking occurs at the completion of the minor loop (or one
iteration of the major loop). The TCDn_CITER[ELINK] field determines whether a
minor loop link is requested. When enabled, the channel link is made after each iteration
of the major loop except for the last. When the major loop is exhausted, only the major
loop channel link fields are used to determine if a channel link should be made. For
example, the initial fields of:
TCDn_CITER[ELINK] = 1
TCDn_CITER[LINKCH] = 0xC
TCDn_CITER[CITER] value = 0x4
TCDn_CSR[MAJOR_ELINK] = 1
TCDn_CSR[MAJOR_LINKCH] = 0x3
executes as:
1. Minor loop done → set TCD2_CSR[START] bit.
2. Minor loop done → set TCD2_CSR[START] bit.
3. Minor loop done → set TCD2_CSR[START] bit.
4. Minor loop done, major loop done → set TCD3_CSR[START] bit.
When minor loop linking is enabled (TCDn_CITER[ELINK] = 1), the
TCDn_CITER[CITER] field uses a nine-bit vector to form the current iteration count.
When minor loop linking is disabled (TCDn_CITER[ELINK] = 0), the
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The
bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER
value to increase the range of the CITER.
Note
The TCDn_CITER[ELINK] bit and the TCDn_BITER[ELINK]
bit must be equal or a configuration error is reported. The
CITER and BITER vector widths must be equal to calculate the
major loop, half-way done interrupt point.
The following table summarizes how a DMA channel can link to another DMA channel,
that is, use another channel's TCD, at the end of a loop.
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Table 6-8. Channel linking parameters
Desired link
TCD control field name Description
behavior
Enable channel-to-channel linking on minor loop completion (current
Link at end of CITER[ELINK]
iteration)
minor loop
CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration)
Link at end of CSR[MAJOR_ELINK] Enable channel-to-channel linking on major loop completion
major loop CSR[MAJOR_LINKCH] Link channel number when linking at end of major loop
6.4.7 Dynamic programming
This section provides recommended methods to change the programming model during
channel execution.
6.4.7.1 Dynamically changing the channel priority
The following two options are recommended for dynamically changing channel priority
levels:
1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities,
then switch back to Fixed Arbitration mode
2. Disable all the channels, change the channel priorities, then enable the appropriate
channels.
6.4.7.2 Dynamic channel linking
Dynamic channel linking is the process of setting TCDn_CSR[MAJORELINK] during
channel execution (see the diagram in TCD structure). This field is read from the TCD
local memory at the end of channel execution, thus enabling you to enable the feature
during channel execution.
Because you can change the configuration during execution, a coherency model is
needed. Consider the scenario where you attempt to execute a dynamic channel link by
enabling TCDn_CSR[MAJORELINK] at the same time the eDMA engine is retiring the
channel. TCDn_CSR[MAJORELINK] would be set in the programmer’s model, but it
would be unclear whether the actual link was made before the channel retired.
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The following coherency model is recommended when executing a dynamic channel link
request.
1. Write one to TCDn_CSR[MAJORELINK].
2. Read back TCDn_CSR[MAJORELINK].
3. Test the TCDn_CSR[MAJORELINK] request status:
• If TCDn_CSR[MAJORELINK] = 1, the dynamic link attempt was successful.
• If TCDn_CSR[MAJORELINK] = 0, the attempted dynamic link did not succeed
(the channel was already retiring).
For this request, the TCD local memory controller forces TCDn_CSR[MAJORELINK]
to zero on any writes to a channel’s TCD.word7 after that channel’s TCD.done bit is set,
indicating the major loop is complete.
NOTE
You must clear TCDn_CSR[DONE] before writing
TCDn_CSR[MAJORELINK]. The eDMA engine automatically
clears TCDn_CSR[DONE] after a channel begins execution.
6.4.7.3 Dynamic scatter/gather
Scatter/gather is the process of automatically loading a new TCD into a channel. It
enables a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the
DMA data to multiple destinations or gather it from multiple sources. When scatter/
gather is enabled and the channel has finished its major loop, a new TCD is fetched from
system memory and loaded into that channel’s descriptor location in eDMA
programmer’s model, thus replacing the current descriptor.
Because you are able to change the configuration during execution, a coherency model is
needed. Consider the scenario where you attempt to execute a dynamic scatter/gather
operation by enabling the TCDn_CSR[ESG] bit at the same time the eDMA engine is
retiring the channel. The ESG bit would be set in the programmer’s model, but it would
be unclear whether the actual scatter/gather request was honored before the channel
retired.
Two methods for this coherency model are shown in the following subsections. Method 1
has the advantage of reading the MAJORLINKCH field and the ESG bit with a single
read. For both dynamic channel linking and scatter/gather requests, the TCD local
memory controller forces the TCD MAJOR[ELINK] and ESG bits to zero on any writes
to a channel’s TCD word 7 if that channel’s TCD[DONE] bit is set, indicating the major
loop is complete.
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NOTE
The user must clear the TCDn_CSR[DONE] bit before writing
the MAJORELINK or ESG bits. The TCDn_CSR[DONE] bit is
cleared automatically by the eDMA engine after a channel
begins execution.
6.4.7.3.1 Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model described here
may be used for a dynamic scatter/gather request.
When TCDn_CSR[MAJORELINK] is zero, TCDn_CSR[MAJORLINKCH] is not used
by the eDMA. In this case, MAJORLINKCH may be used for other purposes. This
method uses the MAJORLINKCH field as a TCD identification (ID).
1. When the descriptors are built, write a unique TCD ID in
TCDn_CSR[MAJORLINKCH] for each TCD associated with a channel using
dynamic scatter/gather.
2. Write one to TCDn_CSR[DREQ].
Should a dynamic scatter/gather attempt fail, setting the DREQ bit prevents a future
hardware activation of the channel. This stops the channel from executing with a
destination address (DADDR) that was calculated using a scatter/gather address
(written in the next step) instead of a DLAST_SGA final offset value.
3. Write the TCDn_DLASTSGA register with the scatter/gather address.
4. Write one to TCDn_CSR[ESG].
5. Read back the 16-bit TCD control/status field.
6. Test the ESG request status and MAJORLINKCH value in the TCDn_CSR register:
If ESG = 1, the dynamic link attempt was successful.
If ESG = 0 and MAJORLINKCH (ID) did not change, the attempted dynamic link
did not succeed (the channel was already retiring).
If ESG = 0 and MAJORLINKCH (ID) changed, the dynamic link attempt was
successful (the new TCD’s ESG value cleared the ESG bit).
6.4.7.3.2 Method 2 (channel using major loop channel linking)
For a channel using major loop channel linking, the coherency model described here may
be used for a dynamic scatter/gather request. This method uses the TCD[DLAST_SGA]
field as a TCD identification (ID).
1. Write one to TCDn_CSR[DREQ].
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Should a dynamic scatter/gather attempt fail, setting TCDn_CSR[DREQ] prevents a
future hardware activation of the channel. This stops the channel from executing with
a destination address (DADDR) that was calculated using a scatter/gather address
(written in the next step) instead of a DLAST_SGA final offset value.
2. Write the TCDn_DLAST_SGA register with the scatter/gather address.
3. Write one to TCDn_CSR[ESG].
4. Read back TCDn_CSR[ESG].
5. Test the ESG request status:
If ESG = 1, the dynamic link attempt was successful.
If ESG = 0, read the 32-bit TCDn_DLAST_SGA field.
If ESG = 0 and TCDn_DLAST_SGA did not change, the attempted dynamic link did
not succeed (the channel was already retiring).
If ESG = 0 and TCDn_DLAST_SGA changed, the dynamic link attempt was
successful (the new TCD’s ESG value cleared the ESG bit).
6.4.8 Suspend/resume a DMA channel with active hardware
service requests
The DMA enables you to move data from memory or peripheral registers to another
location in memory or peripheral registers without CPU interaction. After the DMA and
peripherals have been configured and are active, it is rare to suspend a peripheral's
service request dynamically. In this scenario, there are certain restrictions to disabling a
DMA hardware service request. For coherency, a specific procedure must be followed.
This section provides guidance on how to coherently suspend and resume a Direct
Memory Access (DMA) channel when the DMA is triggered by a slave module such as
the Serial Peripheral Interface (SPI), ADC, or other module.
6.4.8.1 Suspend an active DMA channel
To suspend an active DMA channel:
1. Stop the DMA service request at the peripheral first. Confirm it has been disabled by
reading back the appropriate register in the peripheral.
2. Check the DMA's Hardware Request Status register (DMA_HRSn) to ensure there is
no service request to the DMA channel being suspended. Then disable the hardware
service request by clearing the ERQ bit on appropriate DMA channel.
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Memory map/register definition
6.4.8.2 Resume a DMA channel
To resume a DMA channel:
1. Enable the DMA service request on the appropriate channel by setting the relevant
ERQ bit.
2. Enable the DMA service request at the peripheral.
For example, assume the SPI is set as a master for transmitting data via a DMA service
request when the SPI_TXFIFO has an empty slot. The DMA transfers the next command
and data to the TXFIFO upon the request. You must suspend the DMA/SPI transfer loop
and perform the following steps:
1. Disable the DMA service request at the source by writing zero to
SPI_RSER[TFFF_RE]. Confirm that SPI_RSER[TFFF_RE] is zero.
2. Ensure there is no DMA service request from the SPI by verifying that
DMA_HRS[HRSn] is zero for the appropriate channel. If no service request is
present, disable the DMA channel by clearing the channel's ERQ bit. If a service
request is present, wait until the request has been processed and the HRS bit reads
zero.
6.5 Memory map/register definition
The eDMA programming model consists of registers that provide:
• Control and status functions
• Channel configuration functions
• TCD definition functions
6.5.1 TCD memory
Each channel requires a 32-byte TCD to define the desired data movement operation. The
channel descriptors are in local memory in sequential order: channel 0, channel 1, ...
channel 31. Each TCDn definition comprises 11 registers of 16 or 32 bits.
6.5.2 TCD initialization
Before activating a channel, you must initialize its TCD with the appropriate transfer
profile.
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6.5.3 TCD structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000h SADDR
0004h SMOD SSIZE DMOD DSIZE SOFF
NBYTES DMA_CR[EMLM] disabled
0008h
DMLOE
SMLOE
MLOFF or NBYTES NBYTES DMA_CR[EMLM] enabled
000Ch SLAST
0010h DADDR
CITER.ELINK
CITER or CITER DOFF
0014h
CITER.LINKCH
0018h DLAST_SGA
MAJOR.LINKCH
MAJOR.ELINK
INTMAJOR
BITER.ELINK
Reserved
INTHALF
ACTIVE
START
DONE
BITER or
DREQ
001Ch BITER BWC
ESG
BITER.LINKCH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
6.5.4 Reserved memory and fields
• Reading reserved fields in a register returns the value of zero.
• The eDMA ignores writes to reserved bits in a register.
• Reading or writing a reserved memory location generates a bus error.
6.5.5 DMA register descriptions
6.5.5.1 DMA memory map
DMA0 base address: 4007_0000h
DMA1 base address: 40C1_4000h
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Control (CR) 32 RW Table 6-8
4 Error Status (ES) 32 RO 0000_0000
C Enable Request (ERQ) 32 RW 0000_0000
14 Enable Error Interrupt (EEI) 32 RW 0000_0000
18 Clear Enable Error Interrupt (CEEI) 8 WORZ 00
19 Set Enable Error Interrupt (SEEI) 8 WORZ 00
1A Clear Enable Request (CERQ) 8 WORZ 00
1B Set Enable Request (SERQ) 8 WORZ 00
1C Clear DONE Status Bit (CDNE) 8 WORZ 00
1D Set START Bit (SSRT) 8 WORZ 00
1E Clear Error (CERR) 8 WORZ 00
1F Clear Interrupt Request (CINT) 8 WORZ 00
24 Interrupt Request (INT) 32 W1C 0000_0000
2C Error (ERR) 32 W1C 0000_0000
34 Hardware Request Status (HRS) 32 RO 0000_0000
44 Enable Asynchronous Request in Stop (EARS) 32 RW 0000_0000
100 Channel Priority (DCHPRI3) 8 RW 03
101 Channel Priority (DCHPRI2) 8 RW 02
102 Channel Priority (DCHPRI1) 8 RW 01
103 Channel Priority (DCHPRI0) 8 RW 00
104 Channel Priority (DCHPRI7) 8 RW 07
105 Channel Priority (DCHPRI6) 8 RW 06
106 Channel Priority (DCHPRI5) 8 RW 05
107 Channel Priority (DCHPRI4) 8 RW 04
108 Channel Priority (DCHPRI11) 8 RW 0B
109 Channel Priority (DCHPRI10) 8 RW 0A
10A Channel Priority (DCHPRI9) 8 RW 09
10B Channel Priority (DCHPRI8) 8 RW 08
10C Channel Priority (DCHPRI15) 8 RW 0F
10D Channel Priority (DCHPRI14) 8 RW 0E
10E Channel Priority (DCHPRI13) 8 RW 0D
10F Channel Priority (DCHPRI12) 8 RW 0C
110 Channel Priority (DCHPRI19) 8 RW 13
111 Channel Priority (DCHPRI18) 8 RW 12
112 Channel Priority (DCHPRI17) 8 RW 11
113 Channel Priority (DCHPRI16) 8 RW 10
114 Channel Priority (DCHPRI23) 8 RW 17
115 Channel Priority (DCHPRI22) 8 RW 16
116 Channel Priority (DCHPRI21) 8 RW 15
117 Channel Priority (DCHPRI20) 8 RW 14
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
118 Channel Priority (DCHPRI27) 8 RW 1B
119 Channel Priority (DCHPRI26) 8 RW 1A
11A Channel Priority (DCHPRI25) 8 RW 19
11B Channel Priority (DCHPRI24) 8 RW 18
11C Channel Priority (DCHPRI31) 8 RW 1F
11D Channel Priority (DCHPRI30) 8 RW 1E
11E Channel Priority (DCHPRI29) 8 RW 1D
11F Channel Priority (DCHPRI28) 8 RW 1C
1000 - 13E0 TCD Source Address (TCD0_SADDR - TCD31_SADDR) 32 RW Table 6-8
1004 - 13E4 TCD Signed Source Address Offset (TCD0_SOFF - TCD31_SOFF) 16 RW Table 6-8
1006 - 13E6 TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR) 16 RW Table 6-8
1008 - 13E8 TCD Minor Byte Count (Minor Loop Mapping Disabled) 32 RW Table 6-8
(TCD0_NBYTES_MLNO - TCD31_NBYTES_MLNO)
1008 - 13E8 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and 32 RW Table 6-8
Offset Disabled) (TCD0_NBYTES_MLOFFNO -
TCD31_NBYTES_MLOFFNO)
1008 - 13E8 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset 32 RW Table 6-8
Enabled) (TCD0_NBYTES_MLOFFYES -
TCD31_NBYTES_MLOFFYES)
100C - 13EC TCD Last Source Address Adjustment (TCD0_SLAST - 32 RW Table 6-8
TCD31_SLAST)
1010 - 13F0 TCD Destination Address (TCD0_DADDR - TCD31_DADDR) 32 RW Table 6-8
1014 - 13F4 TCD Signed Destination Address Offset (TCD0_DOFF - 16 RW Table 6-8
TCD31_DOFF)
1016 - 13F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 6-8
Disabled) (TCD0_CITER_ELINKNO - TCD31_CITER_ELINKNO)
1016 - 13F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 6-8
Enabled) (TCD0_CITER_ELINKYES - TCD31_CITER_ELINKYES)
1018 - 13F8 TCD Last Destination Address Adjustment/Scatter Gather Address 32 RW Table 6-8
(TCD0_DLASTSGA - TCD31_DLASTSGA)
101C - 13FC TCD Control and Status (TCD0_CSR - TCD31_CSR) 16 RW Table 6-8
101E - 13FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 6-8
Disabled) (TCD0_BITER_ELINKNO - TCD31_BITER_ELINKNO)
101E - 13FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking 16 RW Table 6-8
Enabled) (TCD0_BITER_ELINKYES - TCD31_BITER_ELINKYES)
6.5.5.2 Control (CR)
This register defines the basic operating configuration of the eDMA module. eDMA
arbitrates channel service requests in two groups of 16 channels each:
• Group 1 contains channels 31-16
• Group 0 contains channels 15-0
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You can configure arbitration within a group to use either a fixed-priority or a round-
robin scheme. For fixed-priority arbitration, eDMA selects and executes the highest-
priority channel that requests service. The channel priority registers assign the priorities
(see the Channel Priority (DCHPRI0 - DCHPRI31) registers). For round-robin
arbitration, the eDMA engine ignores channel priorities and cycles through channels
within each group from high to low channel number without regard to priority.
NOTE
For correct operation, you must write to this register only when
the eDMA channels are inactive—that is, when
TCDn_CSR[ACTIVE] = 0.
The group priorities operate in a similar fashion. In group fixed priority arbitration mode,
channel service requests in the highest priority group are executed first, where priority
level 1 is the highest and priority level 0 is the lowest. The group priorities are assigned
in the GRPnPRI fields of the Control register (CR). All group priorities must have unique
values prior to any channel service requests occurring; otherwise, a configuration error is
reported. For group round robin arbitration, eDMA ignores the group priorities and the
groups are cycled through (from high to low group number) without regard to priority.
Minor loop offsets are address-offset values to be added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) when the minor loop
completes. When you enable minor loop offsets, eDMA adds the minor loop offset
(MLOFF) value to the final source address (TCDn_SADDR), to the final destination
address (TCDn_DADDR), or to both, before it writes the addresses back into the TCD. If
the major loop is complete, eDMA ignores the minor loop offset, and uses the major loop
address offsets (TCDn_SLAST and TCDn_DLAST_SGA) to compute the next
TCDn_SADDR and TCDn_DADDR values.
Enabling minor loop mapping (EMLM = 1) redefines TCDn word2. eDMA uses a
portion of TCDn word2 for multiple fields:
• A source enable field (SMLOE) to specify the minor loop offset is to be applied to
the source address (TCDn_SADDR) when the minor loop completes
• A destination enable field (DMLOE) to specify the minor loop offset to be applied to
the destination address (TCDn_DADDR) when the minor loop completes
• The sign extended minor loop offset value (MLOFF).
eDMA uses the same offset value (MLOFF) for both source and destination minor loop
offsets. When you enable either minor loop offset (SMLOE = 1 or DMLOE = 1), the
NBYTES field reduces in size to 10 bits. When you disable both minor loop offsets
(SMLOE = 0 and and DMLOE = 0), the NBYTES field is a 30-bit vector.
When you disable minor loop mapping (EMLM = 0), the NBYTES field contains all 32
bits of TCDn word2.
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6.5.5.2.1 Offset
Register Offset
CR 0h
6.5.5.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VERSION
ACTIVE
CX
EC
X
W
Reset 0 u u u u u u u 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GRP1PRI
GRP0PRI
0
Reserved
ERCA
EMLM
HALT
HOE
CLM
ERG
EDB
W
G
A
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
6.5.5.2.3 Fields
Field Description
31 eDMA Active Status
ACTIVE 0 - eDMA is idle
1 - eDMA is executing a channel
30-24 eDMA version number
VERSION
23-18 Reserved
—
17 Cancel Transfer
CX When you write 1 to this field, the following actions take place:
• Stop the executing channel
• Force the minor loop to finish.
The cancellation takes effect after the last write of the current read/write sequence. This field is
automatically written with 0 after the cancellation completes. The cancellation retires the channel normally
as if the minor loop completed.
0 - Normal operation
1 - Cancel the remaining data transfer
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Field Description
16 Error Cancel Transfer
ECX When you write a 1 to this field, the following actions take place:
• Stop the executing channel
• Force the minor loop to finish.
The cancellation takes effect after the last write of the current read/write sequence. This field is
automatically reset to 0 after the cancellation completes. In addition to cancelling the transfer, eDMA:
• Treats the cancel as an error condition
• Updates the Error Status register (DMAx_ES)
• Optionally generates an error interrupt.
0 - Normal operation
1 - Cancel the remaining data transfer
15-11 Reserved
—
10 Channel Group 1 Priority
GRP1PRI Group 1 priority level when fixed priority group arbitration is enabled.
9 Reserved
—
8 Channel Group 0 Priority
GRP0PRI Group 0 priority level when fixed priority group arbitration is enabled.
7 Enable Minor Loop Mapping
EMLM When the value of this field is 0, TCDn.word2 is a 32-bit NBYTES field. When the value of this field is 1,
TCDn.word2 includes:
• Individual enable fields
• An offset field
• The NBYTES field.
The individual enable fields allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field reduces in size when either offset is enabled.
0 - Disabled
1 - Enabled
6 Continuous Link Mode
CLM When the value of this field is 0, a minor loop channel link made to itself goes through channel arbitration
before being activated again. When the value of this field is 1, a minor loop channel link made to itself
does not go through channel arbitration before being activated again. When the minor loop completes,
the channel activates again if that channel has a minor loop channel link enabled and the link channel is
itself. This effectively applies the minor loop offsets and restarts the next minor loop.
NOTE: Do not use continuous link mode with a channel linking to itself if there is only one minor loop
iteration per service request, for example, if the channel's NBYTES value is the same as either
the source or destination size. The same data transfer profile can be achieved by simply
increasing the NBYTES value, which provides more efficient, faster processing.
0 - Continuous link mode is off
1 - Continuous link mode is on
5 Halt eDMA Operations
HALT When this field is 1 the following actions take place:
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Field Description
• eDMA stalls the start of any new channels
• Executing channels are allowed to complete.
When you write 0 to this field, channel execution resumes.
0 - Normal operation
1 - eDMA operations halted
4 Halt On Error
HOE When this field is 1, any error causes the eDMA engine to write 1 to the HALT field. Subsequently, the
eDMA engine ignores all service requests until you write 0 to the HALT field.
0 - Normal operation
1 - Error causes HALT field to be automatically set to 1
3 Enable Round Robin Group Arbitration
ERGA When you write 1 to this field, eDMA uses round robin arbitration for selection among the groups.
Otherwise, eDMA uses fixed priority arbitration.
0 - Fixed priority arbitration
1 - Round robin arbitration
2 Enable Round Robin Channel Arbitration
ERCA When you write 1 to this field, eDMA uses round robin arbitration for channel selection. Otherwise, eDMA
uses fixed priority arbitration for channel selection.
0 - Fixed priority arbitration within each group
1 - Round robin arbitration within each group
1 Enable Debug
EDBG When this field is 0 and the chip enters Debug mode, eDMA continues operation. When this field is 1,
entry of the chip into Debug mode causes the eDMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel execution resumes when the chip exits Debug mode or you
write 0 to this field.
0 - When the chip is in Debug mode, the eDMA continues to operate.
1 - When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are
allowed to complete.
0 Reserved
—
6.5.5.3 Error Status (ES)
The ES register provides information concerning the most-recently recorded channel
error. Channel errors can be caused by:
• A configuration error, that is:
• An illegal setting in the transfer-control descriptor
• An illegal priority register setting in fixed arbitration
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Memory map/register definition
• An error termination to a bus master read or write cycle
• A cancel transfer with error field that is 1 when a transfer is canceled via the
corresponding cancel transfer control field
See Fault reporting and handling for more details.
6.5.5.3.1 Offset
Register Offset
ES 4h
6.5.5.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VLD 0 ECX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GPE CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.5.5.3.3 Fields
Field Description
31 Logical OR of all ERR status fields
VLD 0 - No ERR fields are 1
1 - At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
30-17 Reserved
—
16 Transfer Canceled
ECX 0 - No canceled transfers
1 - The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
15 Group Priority Error
GPE 0 - No group priority error.
1 - The most-recently recorded error was a configuration error among the group priorities. All group
priorities are not unique.
14 Channel Priority Error
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Field Description
CPE 0 - No channel priority error.
1 - The most-recently recorded error was a configuration error in the channel priorities within a group.
Channel priorities within a group are not unique.
13 Reserved
—
12-8 Error Channel Number or Canceled Channel Number
ERRCHN The channel number of the most-recently recorded error, excluding GPE and CPE errors or most-recently
recorded error canceled transfer.
7 Source Address Error
SAE 0 - No source address configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_SADDR field.
TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6 Source Offset Error
SOE 0 - No source offset configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_SOFF field.
TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
5 Destination Address Error
DAE 0 - No destination address configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_DADDR field.
TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
4 Destination Offset Error
DOE 0 - No destination offset configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_DOFF field.
TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3 NBYTES/CITER Configuration Error
NCE 0 - No NBYTES/CITER configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or
TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE],
or TCDn_CITER[CITER] = 0, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
2 Scatter/Gather Configuration Error
SGE When 1, this field indicates the most-recently recorded error was a configuration error detected in the
TCDn_DLASTSGA field. eDMA checks This field at the beginning of a scatter/gather operation after
major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32-byte boundary.
0 - No scatter/gather configuration error.
1 - The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
1 Source Bus Error
SBE 0 - No source bus error.
1 - The most-recently recorded error was a bus error on a source read.
0 Destination Bus Error
DBE 0 - No destination bus error.
1 - The most-recently recorded error was a bus error on a destination write.
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Memory map/register definition
6.5.5.4 Enable Request (ERQ)
The ERQ register provides a bit map for the 32 channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this
register; it is also affected by writes to the SERQ and CERQ registers. These registers are
provided so the request enable for a single channel can easily be modified without
needing to perform a read-modify-write sequence to this register.
DMA request input signals and this enable request field must be set to 1 before a
channel's hardware service request is accepted. The state of the DMA enable request field
does not affect a channel service request made explicitly through software or a linked
channel request.
NOTE
Disable a channel's hardware service request at the source
before writing 0 to the channel's ERQ field.
6.5.5.4.1 Offset
Register Offset
ERQ Ch
6.5.5.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ERQ31
ERQ30
ERQ29
ERQ28
ERQ27
ERQ26
ERQ25
ERQ24
ERQ23
ERQ22
ERQ21
ERQ20
ERQ19
ERQ18
ERQ17
W ERQ16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ERQ15
ERQ14
ERQ13
ERQ12
ERQ11
ERQ10
ERQ9
ERQ8
ERQ7
ERQ6
ERQ5
ERQ4
ERQ3
ERQ2
ERQ1
ERQ0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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6.5.5.4.3 Fields
Field Description
31 Enable DMA Request 31
ERQ31 0 - The DMA request signal for channel 31 is disabled
1 - The DMA request signal for channel 31 is enabled
30 Enable DMA Request 30
ERQ30 0 - The DMA request signal for channel 30 is disabled
1 - The DMA request signal for channel 30 is enabled
29 Enable DMA Request 29
ERQ29 0 - The DMA request signal for channel 29 is disabled
1 - The DMA request signal for channel 29 is enabled
28 Enable DMA Request 28
ERQ28 0 - The DMA request signal for channel 28 is disabled
1 - The DMA request signal for channel 28 is enabled
27 Enable DMA Request 27
ERQ27 0 - The DMA request signal for channel 27 is disabled
1 - The DMA request signal for channel 27 is enabled
26 Enable DMA Request 26
ERQ26 0 - The DMA request signal for channel 26 is disabled
1 - The DMA request signal for channel 26 is enabled
25 Enable DMA Request 25
ERQ25 0 - The DMA request signal for channel 25 is disabled
1 - The DMA request signal for channel 25 is enabled
24 Enable DMA Request 24
ERQ24 0 - The DMA request signal for channel 24 is disabled
1 - The DMA request signal for channel 24 is enabled
23 Enable DMA Request 23
ERQ23 0 - The DMA request signal for channel 23 is disabled
1 - The DMA request signal for channel 23 is enabled
22 Enable DMA Request 22
ERQ22 0 - The DMA request signal for channel 22 is disabled
1 - The DMA request signal for channel 22 is enabled
21 Enable DMA Request 21
ERQ21 0 - The DMA request signal for channel 21 is disabled
1 - The DMA request signal for channel 21 is enabled
20 Enable DMA Request 20
ERQ20 0 - The DMA request signal for channel 20 is disabled
1 - The DMA request signal for channel 20 is enabled
19 Enable DMA Request 19
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Memory map/register definition
Field Description
ERQ19 0 - The DMA request signal for channel 19 is disabled
1 - The DMA request signal for channel 19 is enabled
18 Enable DMA Request 18
ERQ18 0 - The DMA request signal for channel 18 is disabled
1 - The DMA request signal for channel 18 is enabled
17 Enable DMA Request 17
ERQ17 0 - The DMA request signal for channel 17 is disabled
1 - The DMA request signal for channel 17 is enabled
16 Enable DMA Request 16
ERQ16 0 - The DMA request signal for channel 16 is disabled
1 - The DMA request signal for channel 16 is enabled
15 Enable DMA Request 15
ERQ15 0 - The DMA request signal for channel 15 is disabled
1 - The DMA request signal for channel 15 is enabled
14 Enable DMA Request 14
ERQ14 0 - The DMA request signal for channel 14 is disabled
1 - The DMA request signal for channel 14 is enabled
13 Enable DMA Request 13
ERQ13 0 - The DMA request signal for channel 13 is disabled
1 - The DMA request signal for channel 13 is enabled
12 Enable DMA Request 12
ERQ12 0 - The DMA request signal for channel 12 is disabled
1 - The DMA request signal for channel 12 is enabled
11 Enable DMA Request 11
ERQ11 0 - The DMA request signal for channel 11 is disabled
1 - The DMA request signal for channel 11 is enabled
10 Enable DMA Request 10
ERQ10 0 - The DMA request signal for channel 10 is disabled
1 - The DMA request signal for channel 10 is enabled
9 Enable DMA Request 9
ERQ9 0 - The DMA request signal for channel 9 is disabled
1 - The DMA request signal for channel 9 is enabled
8 Enable DMA Request 8
ERQ8 0 - The DMA request signal for channel 8 is disabled
1 - The DMA request signal for channel 8 is enabled
7 Enable DMA Request 7
ERQ7 0 - The DMA request signal for channel 7 is disabled
1 - The DMA request signal for channel 7 is enabled
6 Enable DMA Request 6
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Field Description
ERQ6 0 - The DMA request signal for channel 6 is disabled
1 - The DMA request signal for channel 6 is enabled
5 Enable DMA Request 5
ERQ5 0 - The DMA request signal for channel 5 is disabled
1 - The DMA request signal for channel 5 is enabled
4 Enable DMA Request 4
ERQ4 0 - The DMA request signal for channel 4 is disabled
1 - The DMA request signal for channel 4 is enabled
3 Enable DMA Request 3
ERQ3 0 - The DMA request signal for channel 3 is disabled
1 - The DMA request signal for channel 3 is enabled
2 Enable DMA Request 2
ERQ2 0 - The DMA request signal for channel 2 is disabled
1 - The DMA request signal for channel 2 is enabled
1 Enable DMA Request 1
ERQ1 0 - The DMA request signal for channel 1 is disabled
1 - The DMA request signal for channel 1 is enabled
0 Enable DMA Request 0
ERQ0 0 - The DMA request signal for channel 0 is disabled
1 - The DMA request signal for channel 0 is enabled
6.5.5.5 Enable Error Interrupt (EEI)
The EEI register provides a bit map for the 32 channels to enable the error interrupt
signal for each channel. The state of any given channel's error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI
registers. These registers are provided so that the error interrupt enable for a single
channel can easily be modified without the need to perform a read-modify-write sequence
to the EEI register.
The DMA error indicator and the error interrupt enable field must be set to 1 before an
error interrupt request for a given channel is sent to the interrupt controller.
6.5.5.5.1 Offset
Register Offset
EEI 14h
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Memory map/register definition
6.5.5.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EEI31
EEI30
EEI29
EEI28
EEI27
EEI26
EEI25
EEI24
EEI23
EEI22
EEI21
EEI20
EEI19
EEI18
EEI17
EEI16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EEI15
EEI14
EEI13
EEI12
EEI11
EEI10
EEI
EEI
EEI
EEI
EEI
EEI
EEI
EEI
EEI
EEI
W
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.5.5.5.3 Fields
Field Description
31 Enable Error Interrupt 31
EEI31 0 - An error on channel 31 does not generate an error interrupt
1 - An error on channel 31 generates an error interrupt request
30 Enable Error Interrupt 30
EEI30 0 - An error on channel 30 does not generate an error interrupt
1 - An error on channel 30 generates an error interrupt request
29 Enable Error Interrupt 29
EEI29 0 - An error on channel 29 does not generate an error interrupt
1 - An error on channel 29 generates an error interrupt request
28 Enable Error Interrupt 28
EEI28 0 - An error on channel 28 does not generate an error interrupt
1 - An error on channel 28 generates an error interrupt request
27 Enable Error Interrupt 27
EEI27 0 - An error on channel 27 does not generate an error interrupt
1 - An error on channel 27 generates an error interrupt request
26 Enable Error Interrupt 26
EEI26 0 - An error on channel 26 does not generate an error interrupt
1 - An error on channel 26 generates an error interrupt request
25 Enable Error Interrupt 25
EEI25 0 - An error on channel 25 does not generate an error interrupt
1 - An error on channel 25 generates an error interrupt request
24 Enable Error Interrupt 24
EEI24 0 - An error on channel 24 does not generate an error interrupt
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Field Description
1 - An error on channel 24 generates an error interrupt request
23 Enable Error Interrupt 23
EEI23 0 - An error on channel 23 does not generate an error interrupt
1 - An error on channel 23 generates an error interrupt request
22 Enable Error Interrupt 22
EEI22 0 - An error on channel 22 does not generate an error interrupt
1 - An error on channel 22 generates an error interrupt request
21 Enable Error Interrupt 21
EEI21 0 - An error on channel 21 does not generate an error interrupt
1 - An error on channel 21 generates an error interrupt request
20 Enable Error Interrupt 20
EEI20 0 - An error on channel 20 does not generate an error interrupt
1 - An error on channel 20 generates an error interrupt request
19 Enable Error Interrupt 19
EEI19 0 - An error on channel 19 does not generate an error interrupt
1 - An error on channel 19 generates an error interrupt request
18 Enable Error Interrupt 18
EEI18 0 - An error on channel 18 does not generate an error interrupt
1 - An error on channel 18 generates an error interrupt request
17 Enable Error Interrupt 17
EEI17 0 - An error on channel 17 does not generate an error interrupt
1 - An error on channel 17 generates an error interrupt request
16 Enable Error Interrupt 16
EEI16 0 - An error on channel 16 does not generate an error interrupt
1 - An error on channel 16 generates an error interrupt request
15 Enable Error Interrupt 15
EEI15 0 - An error on channel 15 does not generate an error interrupt
1 - An error on channel 15 generates an error interrupt request
14 Enable Error Interrupt 14
EEI14 0 - An error on channel 14 does not generate an error interrupt
1 - An error on channel 14 generates an error interrupt request
13 Enable Error Interrupt 13
EEI13 0 - An error on channel 13 does not generate an error interrupt
1 - An error on channel 13 generates an error interrupt request
12 Enable Error Interrupt 12
EEI12 0 - An error on channel 12 does not generate an error interrupt
1 - An error on channel 12 generates an error interrupt request
11 Enable Error Interrupt 11
EEI11 0 - An error on channel 11 does not generate an error interrupt
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Memory map/register definition
Field Description
1 - An error on channel 11 generates an error interrupt request
10 Enable Error Interrupt 10
EEI10 0 - An error on channel 10 does not generate an error interrupt
1 - An error on channel 10 generates an error interrupt request
9 Enable Error Interrupt 9
EEI9 0 - An error on channel 9 does not generate an error interrupt
1 - An error on channel 9 generates an error interrupt request
8 Enable Error Interrupt 8
EEI8 0 - An error on channel 8 does not generate an error interrupt
1 - An error on channel 8 generates an error interrupt request
7 Enable Error Interrupt 7
EEI7 0 - An error on channel 7 does not generate an error interrupt
1 - An error on channel 7 generates an error interrupt request
6 Enable Error Interrupt 6
EEI6 0 - An error on channel 6 does not generate an error interrupt
1 - An error on channel 6 generates an error interrupt request
5 Enable Error Interrupt 5
EEI5 0 - An error on channel 5 does not generate an error interrupt
1 - An error on channel 5 generates an error interrupt request
4 Enable Error Interrupt 4
EEI4 0 - An error on channel 4 does not generate an error interrupt
1 - An error on channel 4 generates an error interrupt request
3 Enable Error Interrupt 3
EEI3 0 - An error on channel 3 does not generate an error interrupt
1 - An error on channel 3 generates an error interrupt request
2 Enable Error Interrupt 2
EEI2 0 - An error on channel 2 does not generate an error interrupt
1 - An error on channel 2 generates an error interrupt request
1 Enable Error Interrupt 1
EEI1 0 - An error on channel 1 does not generate an error interrupt
1 - An error on channel 1 generates an error interrupt request
0 Enable Error Interrupt 0
EEI0 0 - An error on channel 0 does not generate an error interrupt
1 - An error on channel 0 generates an error interrupt request
6.5.5.6 Clear Enable Error Interrupt (CEEI)
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The CEEI provides a simple memory-mapped mechanism to write 0 to a given field in
the EEI register to disable the error interrupt for a given channel. The data value on a
register write causes the corresponding field in the EEI register to be written to 0. Writing
1 to the CAEE field provides a global clear to 0 function, forcing the EEI contents to be
written to 0, disabling all DMA request inputs.
If the NOP field is written with 1, the command is ignored. This enables you to write 1 to
a single, byte-wide register with a 32-bit write that does not affect the other registers
addressed in the write. In such a case the other three bytes of the word must all have their
NOP field set to 1 so that these registers are not affected by the write.
Reads of this register return all zeroes.
6.5.5.6.1 Offset
Register Offset
CEEI 18h
6.5.5.6.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
NOP
CEE
CAE
W
0
E
Reset 0 0 0 0 0 0 0 0
6.5.5.6.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation, ignore the other fields in this register
6 Clear All Enable Error Interrupts
CAEE 0 - Write 0 only to the EEI field specified in the CEEI field
1 - Write 0 to all fields in EEI
5 Reserved
—
4-0 Clear Enable Error Interrupt
CEEI Writes 0 to the corresponding field in EEI
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Memory map/register definition
6.5.5.7 Set Enable Error Interrupt (SEEI)
The SEEI register provides a simple memory-mapped mechanism to write 1 to a given
field in the EEI register to enable the error interrupt for a given channel. The data value
on a register write causes the corresponding field in the EEI to be written to 1. Writing 1
to the SAEE field provides a global set to 1 function, forcing the entire EEI register
contents to be written with 1.
If the NOP field is 1, the command is ignored. This enables you to write 1 to a single,
byte-wide register with a 32-bit write that does not affect the other registers addressed in
the write. In such a case the other three bytes of the word must all have their NOP field
set to 1 so that these registers are not affected by the write.
Reads of this register return all zeroes.
6.5.5.7.1 Offset
Register Offset
SEEI 19h
6.5.5.7.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
NOP 0
0
SAE
W
SE
0
EI
E
Reset 0 0 0 0 0 0 0 0
6.5.5.7.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation, ignore the other fields in this register
6 Set All Enable Error Interrupts
SAEE 0 - Write 1 only to the EEI field specified in the SEEI field
1 - Writes 1 to all fields in EEI
5 Reserved
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Field Description
—
4-0 Set Enable Error Interrupt
SEEI Writes 1 to the corresponding field in EEI
6.5.5.8 Clear Enable Request (CERQ)
The CERQ provides a simple memory-mapped mechanism to write 0 to a given field in
the ERQ register to disable the DMA request for a given channel. The data value on a
register write causes the corresponding field in the ERQ register to be written with 0.
Setting the CAER field provides a global clear to 0 function, forcing the entire contents
of the ERQ register to be written with 0, disabling all DMA request inputs.
If the NOP field is 1, the command is ignored. This enables you to write 1 to a single,
byte-wide register with a 32-bit write that does not affect the other registers addressed in
the write. In such a case the other three bytes of the word must all have their NOP field
written with 1 so that these registers are not affected by the write.
Reads of this register return all zeroes.
NOTE
Disable a channel's hardware service request at the source
before writing 0 to the channel's ERQ field.
6.5.5.8.1 Offset
Register Offset
CERQ 1Ah
6.5.5.8.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
CAER 0
CERQ 0
NOP
W
0
Reset 0 0 0 0 0 0 0 0
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Memory map/register definition
6.5.5.8.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation, ignore the other fields in this register
6 Clear All Enable Requests
CAER 0 - Write 0 to only the ERQ field specified in the CERQ field
1 - Write 0 to all fields in ERQ
5 Reserved
—
4-0 Clear Enable Request
CERQ Writes 0 to the corresponding field in ERQ.
6.5.5.9 Set Enable Request (SERQ)
The SERQ provides a simple memory-mapped mechanism to write 1 to a given field in
the ERQ register to enable the DMA request for a given channel. The data value on a
register write causes the corresponding field in the ERQ register to be set. Writing 1 to
the SAER field provides a global set to 1 function, forcing the entire contents of ERQ
register to be 1.
If the NOP field is 1, the command is ignored. This enables you to write 1 to a single,
byte-wide register with a 32-bit write that does not affect the other registers addressed in
the write. In such a case the other three bytes of the word must all have their NOP field
written with 1 so that these registers are not affected by the write.
Reads of this register returns all zeroes.
6.5.5.9.1 Offset
Register Offset
SERQ 1Bh
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6.5.5.9.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
NOP
SAE
SER
W
0
R
Q
Reset 0 0 0 0 0 0 0 0
6.5.5.9.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation, ignore the other fields in this register
6 Set All Enable Requests
SAER 0 - Write 1 to only the ERQ field specified in the SERQ field
1 - Write 1 to all fields in ERQ
5 Reserved
—
4-0 Set Enable Request
SERQ Writes 1 to the corresponding field in ERQ.
6.5.5.10 Clear DONE Status Bit (CDNE)
The CDNE provides a simple memory-mapped mechanism to write 0 to the DONE field
in the TCD of the given channel. The data value on a register write causes the DONE
field in the corresponding TCD to be written with 0. Writing 1 to the CADN field
provides a global clear function, forcing all DONE fields to be written with 0.
If the NOP field is 1, the command is ignored. This enables you to write 1 to a single,
byte-wide register with a 32-bit write that does not affect the other registers addressed in
the write. In such a case the other three bytes of the word must all have their NOP field
written with 1 so that these registers are not affected by the write.
Reads of this register return all zeroes.
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Memory map/register definition
6.5.5.10.1 Offset
Register Offset
CDNE 1Ch
6.5.5.10.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
CDNE 0
CADN
NOP
W 0
Reset 0 0 0 0 0 0 0 0
6.5.5.10.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation; all other fields in this register are ignored.
6 Clears All DONE fields
CADN 0 - Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
1 - Writes 0 to all bits in TCDn_CSR[DONE]
5 Reserved
—
4-0 Clear DONE field
CDNE Writes 0 to the corresponding field in TCDn_CSR[DONE]
6.5.5.11 Set START Bit (SSRT)
The SSRT register provides a simple memory-mapped mechanism to write 1 to the
START field in the TCD of the given channel. The data value on a register write causes
the START field in the corresponding TCD to be written with 1. Writing 1 to the SAST
field provides a global set to 1 function, forcing all START fields to be written with 1.
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If the NOP field is 1, the command is ignored. This enables you to write 1 to a single,
byte-wide register with a 32-bit write that does not affect the other registers addressed in
the write. In such a case the other three bytes of the word must all have their NOP field
written with 1 so that these registers are not affected by the write.
Reads of this register return all zeroes.
6.5.5.11.1 Offset
Register Offset
SSRT 1Dh
6.5.5.11.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
0
NOP
SSR
SAS
W
0
T
T
Reset 0 0 0 0 0 0 0 0
6.5.5.11.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation; all other fields in this register are ignored.
6 Set All START fields (activates all channels)
SAST 0 - Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
1 - Write 1 to all bits in TCDn_CSR[START]
5 Reserved
—
4-0 Set START field
SSRT Sets the corresponding field in TCDn_CSR[START]
6.5.5.12 Clear Error (CERR)
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Memory map/register definition
The CERR provides a simple memory-mapped mechanism to write 0 to a given field in
the ERR register to disable the error condition field for a given channel. The given value
on a register write causes the corresponding field in the ERR register to be written with 0.
Writing 1 to the CAEI field provides a global clear to 0 function, forcing the ERR
register contents to be written with 0, clearing all channel error indicators. If the NOP
field is 1, the command is ignored. This enables you to write multiple-byte registers as a
32-bit word. Reads of this register return all zeroes.
6.5.5.12.1 Offset
Register Offset
CERR 1Eh
6.5.5.12.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
CAEI 0
0
NOP
CER
W
0
Reset 0 0 0 0 0 0 0 0
6.5.5.12.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation; all other fields in this register are ignored.
6 Clear All Error Indicators
CAEI 0 - Write 0 to only the ERR field specified in the CERR field
1 - Write 0 to all fields in ERR
5 Reserved
—
4-0 Clear Error Indicator
CERR Writes 0 to the corresponding field in ERR
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6.5.5.13 Clear Interrupt Request (CINT)
The CINT register provides a simple, memory-mapped mechanism to clear a given field
in the INT register to disable the interrupt request for a given channel. The given value on
a register write causes the corresponding field in the INT register to be cleared. Setting
the CAIR field provides a global clear function, forcing the entire contents of the INT to
be cleared, disabling all DMA interrupt requests.
If the NOP field is 1, the command is ignored. This enables you to set a single, byte-wide
register with a 32-bit write that does not affect the other registers addressed in the write.
In such a case the other three bytes of the word would all have their NOP field set to 1 so
that these registers are not affected by the write.
Reads of this register return all zeroes.
6.5.5.13.1 Offset
Register Offset
CINT 1Fh
6.5.5.13.2 Diagram
Bits 7 6 5 4 3 2 1 0
R
0
CAIR 0
CINT 0
NOP
W
0
Reset 0 0 0 0 0 0 0 0
6.5.5.13.3 Fields
Field Description
7 No Op Enable
NOP 0 - Normal operation
1 - No operation; all other fields in this register are ignored.
6 Clear All Interrupt Requests
CAIR 0 - Clear only the INT field specified in the CINT field
1 - Clear all bits in INT
5 Reserved
—
4-0 Clear Interrupt Request
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Memory map/register definition
Field Description
CINT Clears the corresponding field in INT
6.5.5.14 Interrupt Request (INT)
The INT register provides a bit map for the 32 channels signaling the presence of an
interrupt request for each channel. Depending on the appropriate bit setting in the
transfer-control descriptors, the eDMA engine generates an interrupt on data transfer
completion. The outputs of this register are directly routed to the interrupt controller.
During the interrupt-service routine associated with any given channel, it is the software's
responsibility to write 0 to the appropriate bit, negating the interrupt request. Typically, a
write to the CINT register in the interrupt service routine is used for this purpose.
The state of any given channel's interrupt request is directly affected by writes to this
register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit
position clears the corresponding channel's interrupt request. A 0 in any bit position has
no effect on the corresponding channel's current interrupt status. The CINT register is
provided so the interrupt request for a single channel can easily be cleared without the
need to perform a read-modify-write sequence to the INT register.
6.5.5.14.1 Offset
Register Offset
INT 24h
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.5.5.14.2 Diagram
Bits 31
W1C INT31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C INT30
W1C INT29
W1C INT28
W1C INT27
W1C INT26
W1C INT25
W1C INT24
W1C INT23
W1C INT22
W1C INT21
W1C INT20
W1C INT19
W1C INT18
W1C INT17
W1C INT16
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C INT15
W1C INT14
W1C INT13
W1C INT12
W1C INT11
W1C INT10
INT9
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
R
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.5.5.14.3 Fields
Field Description
31 Interrupt Request 31
INT31 0 - The interrupt request for channel 31 is cleared
1 - The interrupt request for channel 31 is active
30 Interrupt Request 30
INT30 0 - The interrupt request for channel 30 is cleared
1 - The interrupt request for channel 30 is active
29 Interrupt Request 29
INT29 0 - The interrupt request for channel 29 is cleared
1 - The interrupt request for channel 29 is active
28 Interrupt Request 28
INT28 0 - The interrupt request for channel 28 is cleared
1 - The interrupt request for channel 28 is active
27 Interrupt Request 27
INT27 0 - The interrupt request for channel 27 is cleared
1 - The interrupt request for channel 27 is active
26 Interrupt Request 26
INT26 0 - The interrupt request for channel 26 is cleared
1 - The interrupt request for channel 26 is active
25 Interrupt Request 25
INT25 0 - The interrupt request for channel 25 is cleared
1 - The interrupt request for channel 25 is active
24 Interrupt Request 24
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Memory map/register definition
Field Description
INT24 0 - The interrupt request for channel 24 is cleared
1 - The interrupt request for channel 24 is active
23 Interrupt Request 23
INT23 0 - The interrupt request for channel 23 is cleared
1 - The interrupt request for channel 23 is active
22 Interrupt Request 22
INT22 0 - The interrupt request for channel 22 is cleared
1 - The interrupt request for channel 22 is active
21 Interrupt Request 21
INT21 0 - The interrupt request for channel 21 is cleared
1 - The interrupt request for channel 21 is active
20 Interrupt Request 20
INT20 0 - The interrupt request for channel 20 is cleared
1 - The interrupt request for channel 20 is active
19 Interrupt Request 19
INT19 0 - The interrupt request for channel 19 is cleared
1 - The interrupt request for channel 19 is active
18 Interrupt Request 18
INT18 0 - The interrupt request for channel 18 is cleared
1 - The interrupt request for channel 18 is active
17 Interrupt Request 17
INT17 0 - The interrupt request for channel 17 is cleared
1 - The interrupt request for channel 17 is active
16 Interrupt Request 16
INT16 0 - The interrupt request for channel 16 is cleared
1 - The interrupt request for channel 16 is active
15 Interrupt Request 15
INT15 0 - The interrupt request for channel 15 is cleared
1 - The interrupt request for channel 15 is active
14 Interrupt Request 14
INT14 0 - The interrupt request for channel 14 is cleared
1 - The interrupt request for channel 14 is active
13 Interrupt Request 13
INT13 0 - The interrupt request for channel 13 is cleared
1 - The interrupt request for channel 13 is active
12 Interrupt Request 12
INT12 0 - The interrupt request for channel 12 is cleared
1 - The interrupt request for channel 12 is active
11 Interrupt Request 11
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Field Description
INT11 0 - The interrupt request for channel 11 is cleared
1 - The interrupt request for channel 11 is active
10 Interrupt Request 10
INT10 0 - The interrupt request for channel 10 is cleared
1 - The interrupt request for channel 10 is active
9 Interrupt Request 9
INT9 0 - The interrupt request for channel 9 is cleared
1 - The interrupt request for channel 9 is active
8 Interrupt Request 8
INT8 0 - The interrupt request for channel 8 is cleared
1 - The interrupt request for channel 8 is active
7 Interrupt Request 7
INT7 0 - The interrupt request for channel 7 is cleared
1 - The interrupt request for channel 7 is active
6 Interrupt Request 6
INT6 0 - The interrupt request for channel 6 is cleared
1 - The interrupt request for channel 6 is active
5 Interrupt Request 5
INT5 0 - The interrupt request for channel 5 is cleared
1 - The interrupt request for channel 5 is active
4 Interrupt Request 4
INT4 0 - The interrupt request for channel 4 is cleared
1 - The interrupt request for channel 4 is active
3 Interrupt Request 3
INT3 0 - The interrupt request for channel 3 is cleared
1 - The interrupt request for channel 3 is active
2 Interrupt Request 2
INT2 0 - The interrupt request for channel 2 is cleared
1 - The interrupt request for channel 2 is active
1 Interrupt Request 1
INT1 0 - The interrupt request for channel 1 is cleared
1 - The interrupt request for channel 1 is active
0 Interrupt Request 0
INT0 0 - The interrupt request for channel 0 is cleared
1 - The interrupt request for channel 0 is active
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Memory map/register definition
6.5.5.15 Error (ERR)
The ERR register provides a bit map for the 32 channels, signaling the presence of an
error for each channel. The eDMA engine signals the occurrence of an error condition by
setting the appropriate field in this register. The outputs of this register are enabled by the
contents of the EEI register, then logically summed across groups of 16 and 32 channels
to form several group error interrupt requests, which are then routed to the interrupt
controller. During the execution of the interrupt service routine associated with any DMA
errors, it is software's responsibility to reset the appropriate bit to 0, negating the error-
interrupt request. Typically, a write to the CERR in the interrupt service routine is used
for this purpose. The normal DMA channel completion indicators (setting the TCD
DONE field to 1 and the possible generation of an interrupt request) are not affected
when an error is detected.
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI fields. The state of any given
channel's error indicators is affected by writes to this register; it is also affected by writes
to the CERR. On writes to the ERR, a 1 in any bit position clears the corresponding
channel's error status. A 0 in any bit position has no effect on the corresponding channel's
current error status. The CERR is provided so the error indicator for a single channel can
easily be reset to 0.
6.5.5.15.1 Offset
Register Offset
ERR 2Ch
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.5.5.15.2 Diagram
Bits 31
W1C ERR3 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C ERR3
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR2
W1C ERR1
W1C ERR1
W1C ERR1
W1C ERR1
R
1
6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C ERR1
W1C ERR1
W1C ERR1
W1C ERR1
W1C ERR1
W1C ERR1
ERR
ERR
ERR
ERR
ERR
ERR
ERR
ERR
ERR
ERR
R
0
5
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.5.5.15.3 Fields
Field Description
31 Error In Channel 31
ERR31 0 - No error in this channel has occurred
1 - An error in this channel has occurred
30 Error In Channel 30
ERR30 0 - No error in this channel has occurred
1 - An error in this channel has occurred
29 Error In Channel 29
ERR29 0 - No error in this channel has occurred
1 - An error in this channel has occurred
28 Error In Channel 28
ERR28 0 - No error in this channel has occurred
1 - An error in this channel has occurred
27 Error In Channel 27
ERR27 0 - No error in this channel has occurred
1 - An error in this channel has occurred
26 Error In Channel 26
ERR26 0 - No error in this channel has occurred
1 - An error in this channel has occurred
25 Error In Channel 25
ERR25 0 - No error in this channel has occurred
1 - An error in this channel has occurred
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Memory map/register definition
Field Description
24 Error In Channel 24
ERR24 0 - No error in this channel has occurred
1 - An error in this channel has occurred
23 Error In Channel 23
ERR23 0 - No error in this channel has occurred
1 - An error in this channel has occurred
22 Error In Channel 22
ERR22 0 - No error in this channel has occurred
1 - An error in this channel has occurred
21 Error In Channel 21
ERR21 0 - No error in this channel has occurred
1 - An error in this channel has occurred
20 Error In Channel 20
ERR20 0 - No error in this channel has occurred
1 - An error in this channel has occurred
19 Error In Channel 19
ERR19 0 - No error in this channel has occurred
1 - An error in this channel has occurred
18 Error In Channel 18
ERR18 0 - No error in this channel has occurred
1 - An error in this channel has occurred
17 Error In Channel 17
ERR17 0 - No error in this channel has occurred
1 - An error in this channel has occurred
16 Error In Channel 16
ERR16 0 - No error in this channel has occurred
1 - An error in this channel has occurred
15 Error In Channel 15
ERR15 0 - No error in this channel has occurred
1 - An error in this channel has occurred
14 Error In Channel 14
ERR14 0 - No error in this channel has occurred
1 - An error in this channel has occurred
13 Error In Channel 13
ERR13 0 - No error in this channel has occurred
1 - An error in this channel has occurred
12 Error In Channel 12
ERR12 0 - No error in this channel has occurred
1 - An error in this channel has occurred
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Field Description
11 Error In Channel 11
ERR11 0 - No error in this channel has occurred
1 - An error in this channel has occurred
10 Error In Channel 10
ERR10 0 - No error in this channel has occurred
1 - An error in this channel has occurred
9 Error In Channel 9
ERR9 0 - No error in this channel has occurred
1 - An error in this channel has occurred
8 Error In Channel 8
ERR8 0 - No error in this channel has occurred
1 - An error in this channel has occurred
7 Error In Channel 7
ERR7 0 - No error in this channel has occurred
1 - An error in this channel has occurred
6 Error In Channel 6
ERR6 0 - No error in this channel has occurred
1 - An error in this channel has occurred
5 Error In Channel 5
ERR5 0 - No error in this channel has occurred
1 - An error in this channel has occurred
4 Error In Channel 4
ERR4 0 - No error in this channel has occurred
1 - An error in this channel has occurred
3 Error In Channel 3
ERR3 0 - No error in this channel has occurred
1 - An error in this channel has occurred
2 Error In Channel 2
ERR2 0 - No error in this channel has occurred
1 - An error in this channel has occurred
1 Error In Channel 1
ERR1 0 - No error in this channel has occurred
1 - An error in this channel has occurred
0 Error In Channel 0
ERR0 0 - No error in this channel has occurred
1 - An error in this channel has occurred
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Memory map/register definition
6.5.5.16 Hardware Request Status (HRS)
The HRS register provides a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals, as seen by
the DMA's arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Each HRS field for its respective channel is 1 when a hardware request is present on the
channel. After the request is completed and channel is free, the HRS field is
automatically changed to 0 by hardware.
6.5.5.16.1 Offset
Register Offset
HRS 34h
6.5.5.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRS31
HRS30
HRS29
HRS28
HRS27
HRS26
HRS25
HRS24
HRS23
HRS22
HRS21
HRS20
HRS19
HRS18
HRS17
HRS16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HRS15
HRS14
HRS13
HRS12
HRS11
HRS10
HRS
HRS
HRS
HRS
HRS
HRS
HRS
HRS
HRS
HRS
R
9
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.5.5.16.3 Fields
Field Description
31 Hardware Request Status Channel 31
HRS31 0 - A hardware service request for channel 31 is not present
1 - A hardware service request for channel 31 is present
30 Hardware Request Status Channel 30
HRS30 0 - A hardware service request for channel 30 is not present
1 - A hardware service request for channel 30 is present
29 Hardware Request Status Channel 29
HRS29 0 - A hardware service request for channel 29 is not preset
1 - A hardware service request for channel 29 is present
28 Hardware Request Status Channel 28
HRS28 0 - A hardware service request for channel 28 is not present
1 - A hardware service request for channel 28 is present
27 Hardware Request Status Channel 27
HRS27 0 - A hardware service request for channel 27 is not present
1 - A hardware service request for channel 27 is present
26 Hardware Request Status Channel 26
HRS26 0 - A hardware service request for channel 26 is not present
1 - A hardware service request for channel 26 is present
25 Hardware Request Status Channel 25
HRS25 0 - A hardware service request for channel 25 is not present
1 - A hardware service request for channel 25 is present
24 Hardware Request Status Channel 24
HRS24 0 - A hardware service request for channel 24 is not present
1 - A hardware service request for channel 24 is present
23 Hardware Request Status Channel 23
HRS23 0 - A hardware service request for channel 23 is not present
1 - A hardware service request for channel 23 is present
22 Hardware Request Status Channel 22
HRS22 0 - A hardware service request for channel 22 is not present
1 - A hardware service request for channel 22 is present
21 Hardware Request Status Channel 21
HRS21 0 - A hardware service request for channel 21 is not present
1 - A hardware service request for channel 21 is present
20 Hardware Request Status Channel 20
HRS20 0 - A hardware service request for channel 20 is not present
1 - A hardware service request for channel 20 is present
19 Hardware Request Status Channel 19
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Memory map/register definition
Field Description
HRS19 0 - A hardware service request for channel 19 is not present
1 - A hardware service request for channel 19 is present
18 Hardware Request Status Channel 18
HRS18 0 - A hardware service request for channel 18 is not present
1 - A hardware service request for channel 18 is present
17 Hardware Request Status Channel 17
HRS17 0 - A hardware service request for channel 17 is not present
1 - A hardware service request for channel 17 is present
16 Hardware Request Status Channel 16
HRS16 0 - A hardware service request for channel 16 is not present
1 - A hardware service request for channel 16 is present
15 Hardware Request Status Channel 15
HRS15 0 - A hardware service request for channel 15 is not present
1 - A hardware service request for channel 15 is present
14 Hardware Request Status Channel 14
HRS14 0 - A hardware service request for channel 14 is not present
1 - A hardware service request for channel 14 is present
13 Hardware Request Status Channel 13
HRS13 0 - A hardware service request for channel 13 is not present
1 - A hardware service request for channel 13 is present
12 Hardware Request Status Channel 12
HRS12 0 - A hardware service request for channel 12 is not present
1 - A hardware service request for channel 12 is present
11 Hardware Request Status Channel 11
HRS11 0 - A hardware service request for channel 11 is not present
1 - A hardware service request for channel 11 is present
10 Hardware Request Status Channel 10
HRS10 0 - A hardware service request for channel 10 is not present
1 - A hardware service request for channel 10 is present
9 Hardware Request Status Channel 9
HRS9 0 - A hardware service request for channel 9 is not present
1 - A hardware service request for channel 9 is present
8 Hardware Request Status Channel 8
HRS8 0 - A hardware service request for channel 8 is not present
1 - A hardware service request for channel 8 is present
7 Hardware Request Status Channel 7
HRS7 0 - A hardware service request for channel 7 is not present
1 - A hardware service request for channel 7 is present
6 Hardware Request Status Channel 6
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Field Description
HRS6 0 - A hardware service request for channel 6 is not present
1 - A hardware service request for channel 6 is present
5 Hardware Request Status Channel 5
HRS5 0 - A hardware service request for channel 5 is not present
1 - A hardware service request for channel 5 is present
4 Hardware Request Status Channel 4
HRS4 0 - A hardware service request for channel 4 is not present
1 - A hardware service request for channel 4 is present
3 Hardware Request Status Channel 3
HRS3 0 - A hardware service request for channel 3 is not present
1 - A hardware service request for channel 3 is present
2 Hardware Request Status Channel 2
HRS2 0 - A hardware service request for channel 2 is not present
1 - A hardware service request for channel 2 is present
1 Hardware Request Status Channel 1
HRS1 0 - A hardware service request for channel 1 is not present
1 - A hardware service request for channel 1 is present
0 Hardware Request Status Channel 0
HRS0 0 - A hardware service request for channel 0 is not present
1 - A hardware service request for channel 0 is present
6.5.5.17 Enable Asynchronous Request in Stop (EARS)
The EARS register is used to enable or disable the DMA requests in Enable Request
(ERQ) by AND'ing the bits of these two registers.
6.5.5.17.1 Offset
Register Offset
EARS 44h
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Memory map/register definition
6.5.5.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
EDREQ_31
EDREQ_30
EDREQ_29
EDREQ_28
EDREQ_27
EDREQ_26
EDREQ_25
EDREQ_24
EDREQ_23
EDREQ_22
EDREQ_21
EDREQ_20
EDREQ_19
EDREQ_18
EDREQ_17
EDREQ_16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EDREQ_15
EDREQ_14
EDREQ_13
EDREQ_12
EDREQ_11
EDREQ_10
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
EDREQ_
W
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.5.5.17.3 Fields
Field Description
31 Enable asynchronous DMA request in stop mode for channel 31.
EDREQ_31 0 - Disable asynchronous DMA request for channel 31
1 - Enable asynchronous DMA request for channel 31
30 Enable asynchronous DMA request in stop mode for channel 30.
EDREQ_30 0 - Disable asynchronous DMA request for channel 30
1 - Enable asynchronous DMA request for channel 30
29 Enable asynchronous DMA request in stop mode for channel 29.
EDREQ_29 0 - Disable asynchronous DMA request for channel 29
1 - Enable asynchronous DMA request for channel 29
28 Enable asynchronous DMA request in stop mode for channel 28.
EDREQ_28 0 - Disable asynchronous DMA request for channel 28
1 - Enable asynchronous DMA request for channel 28
27 Enable asynchronous DMA request in stop mode for channel 27.
EDREQ_27 0 - Disable asynchronous DMA request for channel 27
1 - Enable asynchronous DMA request for channel 27
26 Enable asynchronous DMA request in stop mode for channel 26.
EDREQ_26 0 - Disable asynchronous DMA request for channel 26
1 - Enable asynchronous DMA request for channel 26
25 Enable asynchronous DMA request in stop mode for channel 25.
EDREQ_25 0 - Disable asynchronous DMA request for channel 25
1 - Enable asynchronous DMA request for channel 25
24 Enable asynchronous DMA request in stop mode for channel 24.
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Field Description
EDREQ_24 0 - Disable asynchronous DMA request for channel 24
1 - Enable asynchronous DMA request for channel 24
23 Enable asynchronous DMA request in stop mode for channel 23.
EDREQ_23 0 - Disable asynchronous DMA request for channel 23
1 - Enable asynchronous DMA request for channel 23
22 Enable asynchronous DMA request in stop mode for channel 22.
EDREQ_22 0 - Disable asynchronous DMA request for channel 22
1 - Enable asynchronous DMA request for channel 22
21 Enable asynchronous DMA request in stop mode for channel 21.
EDREQ_21 0 - Disable asynchronous DMA request for channel 21
1 - Enable asynchronous DMA request for channel 21
20 Enable asynchronous DMA request in stop mode for channel 20.
EDREQ_20 0 - Disable asynchronous DMA request for channel 20
1 - Enable asynchronous DMA request for channel 20
19 Enable asynchronous DMA request in stop mode for channel 19.
EDREQ_19 0 - Disable asynchronous DMA request for channel 19
1 - Enable asynchronous DMA request for channel 19
18 Enable asynchronous DMA request in stop mode for channel 18.
EDREQ_18 0 - Disable asynchronous DMA request for channel 18
1 - Enable asynchronous DMA request for channel 18
17 Enable asynchronous DMA request in stop mode for channel 17.
EDREQ_17 0 - Disable asynchronous DMA request for channel 17
1 - Enable asynchronous DMA request for channel 17
16 Enable asynchronous DMA request in stop mode for channel 16.
EDREQ_16 0 - Disable asynchronous DMA request for channel 16
1 - Enable asynchronous DMA request for channel 16
15 Enable asynchronous DMA request in stop mode for channel 15.
EDREQ_15 0 - Disable asynchronous DMA request for channel 15
1 - Enable asynchronous DMA request for channel 15
14 Enable asynchronous DMA request in stop mode for channel 14.
EDREQ_14 0 - Disable asynchronous DMA request for channel 14
1 - Enable asynchronous DMA request for channel 14
13 Enable asynchronous DMA request in stop mode for channel 13.
EDREQ_13 0 - Disable asynchronous DMA request for channel 13
1 - Enable asynchronous DMA request for channel 13
12 Enable asynchronous DMA request in stop mode for channel 12.
EDREQ_12 0 - Disable asynchronous DMA request for channel 12
1 - Enable asynchronous DMA request for channel 12
11 Enable asynchronous DMA request in stop mode for channel 11.
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Memory map/register definition
Field Description
EDREQ_11 0 - Disable asynchronous DMA request for channel 11
1 - Enable asynchronous DMA request for channel 11
10 Enable asynchronous DMA request in stop mode for channel 10.
EDREQ_10 0 - Disable asynchronous DMA request for channel 10
1 - Enable asynchronous DMA request for channel 10
9 Enable asynchronous DMA request in stop mode for channel 9.
EDREQ_9 0 - Disable asynchronous DMA request for channel 9
1 - Enable asynchronous DMA request for channel 9
8 Enable asynchronous DMA request in stop mode for channel 8.
EDREQ_8 0 - Disable asynchronous DMA request for channel 8
1 - Enable asynchronous DMA request for channel 8
7 Enable asynchronous DMA request in stop mode for channel 7.
EDREQ_7 0 - Disable asynchronous DMA request for channel 7
1 - Enable asynchronous DMA request for channel 7
6 Enable asynchronous DMA request in stop mode for channel 6.
EDREQ_6 0 - Disable asynchronous DMA request for channel 6
1 - Enable asynchronous DMA request for channel 6
5 Enable asynchronous DMA request in stop mode for channel 5.
EDREQ_5 0 - Disable asynchronous DMA request for channel 5
1 - Enable asynchronous DMA request for channel 5
4 Enable asynchronous DMA request in stop mode for channel 4.
EDREQ_4 0 - Disable asynchronous DMA request for channel 4
1 - Enable asynchronous DMA request for channel 4
3 Enable asynchronous DMA request in stop mode for channel 3.
EDREQ_3 0 - Disable asynchronous DMA request for channel 3
1 - Enable asynchronous DMA request for channel 3
2 Enable asynchronous DMA request in stop mode for channel 2.
EDREQ_2 0 - Disable asynchronous DMA request for channel 2
1 - Enable asynchronous DMA request for channel 2
1 Enable asynchronous DMA request in stop mode for channel 1.
EDREQ_1 0 - Disable asynchronous DMA request for channel 1
1 - Enable asynchronous DMA request for channel 1
0 Enable asynchronous DMA request in stop mode for channel 0.
EDREQ_0 0 - Disable asynchronous DMA request for channel 0
1 - Enable asynchronous DMA request for channel 0
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.5.5.18 Channel Priority (DCHPRI0 - DCHPRI31)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within a group. The
channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1
is the next higher priority, then 2, 3, and so on. Software must program the channel
priorities with unique values; otherwise, a configuration error is reported. The range of
the priority value is limited to the values of 0 through 15. When read, the GRPPRI bits of
the DCHPRIn register reflect the current priority level of the group of channels in which
the corresponding channel resides. GRPPRI bits are not affected by writes to the
DCHPRIn registers. The group priority is assigned in the DMA control register.
6.5.5.18.1 Offset
Register Offset
DCHPRI3 100h
DCHPRI2 101h
DCHPRI1 102h
DCHPRI0 103h
DCHPRI7 104h
DCHPRI6 105h
DCHPRI5 106h
DCHPRI4 107h
DCHPRI11 108h
DCHPRI10 109h
DCHPRI9 10Ah
DCHPRI8 10Bh
DCHPRI15 10Ch
DCHPRI14 10Dh
DCHPRI13 10Eh
DCHPRI12 10Fh
DCHPRI19 110h
DCHPRI18 111h
DCHPRI17 112h
DCHPRI16 113h
DCHPRI23 114h
DCHPRI22 115h
DCHPRI21 116h
DCHPRI20 117h
DCHPRI27 118h
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Memory map/register definition
Register Offset
DCHPRI26 119h
DCHPRI25 11Ah
DCHPRI24 11Bh
DCHPRI31 11Ch
DCHPRI30 11Dh
DCHPRI29 11Eh
DCHPRI28 11Fh
6.5.5.18.2 Diagram
Bits 7 6 5 4 3 2 1 0
R GRPPRI
ECP DPA CHPRI
W
Reset See Register reset values.
6.5.5.18.3 Register reset values
Register Reset value
DCHPRI0 DMA0,DMA1: 00h
DCHPRI1 DMA0,DMA1: 01h
DCHPRI2 DMA0,DMA1: 02h
DCHPRI3 DMA0,DMA1: 03h
DCHPRI4 DMA0,DMA1: 04h
DCHPRI5 DMA0,DMA1: 05h
DCHPRI6 DMA0,DMA1: 06h
DCHPRI7 DMA0,DMA1: 07h
DCHPRI8 DMA0,DMA1: 08h
DCHPRI9 DMA0,DMA1: 09h
DCHPRI10 DMA0,DMA1: 0Ah
DCHPRI11 DMA0,DMA1: 0Bh
DCHPRI12 DMA0,DMA1: 0Ch
DCHPRI13 DMA0,DMA1: 0Dh
DCHPRI14 DMA0,DMA1: 0Eh
DCHPRI15 DMA0,DMA1: 0Fh
DCHPRI16 DMA0,DMA1: 10h
DCHPRI17 DMA0,DMA1: 11h
DCHPRI18 DMA0,DMA1: 12h
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Register Reset value
DCHPRI19 DMA0,DMA1: 13h
DCHPRI20 DMA0,DMA1: 14h
DCHPRI21 DMA0,DMA1: 15h
DCHPRI22 DMA0,DMA1: 16h
DCHPRI23 DMA0,DMA1: 17h
DCHPRI24 DMA0,DMA1: 18h
DCHPRI25 DMA0,DMA1: 19h
DCHPRI26 DMA0,DMA1: 1Ah
DCHPRI27 DMA0,DMA1: 1Bh
DCHPRI28 DMA0,DMA1: 1Ch
DCHPRI29 DMA0,DMA1: 1Dh
DCHPRI30 DMA0,DMA1: 1Eh
DCHPRI31 DMA0,DMA1: 1Fh
6.5.5.18.4 Fields
Field Description
7 Enable Channel Preemption. This field resets to 0.
ECP 0 - Channel n cannot be suspended by a higher priority channel's service request
1 - Channel n can be temporarily suspended by the service request of a higher priority channel
6 Disable Preempt Ability. This field resets to 0.
DPA 0 - Channel n can suspend a lower priority channel
1 - Channel n cannot suspend any channel, regardless of channel priority
5-4 Channel n Current Group Priority
GRPPRI Group priority assigned to this channel group when fixed-priority arbitration is enabled. This field is read-
only; writes are ignored.
3-0 Channel n Arbitration Priority
CHPRI Channel priority when fixed-priority arbitration is enabled.
6.5.5.19 TCD Source Address (TCD0_SADDR - TCD31_SADDR)
This register contains the source address of the transfer.
6.5.5.19.1 Offset
For n = 0 to 31:
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Memory map/register definition
Register Offset
TCDn_SADDR 1000h + (n × 20h)
6.5.5.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SADDR
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SADDR
W
Reset u u u u u u u u u u u u u u u u
6.5.5.19.3 Fields
Field Description
31-0 Source Address
SADDR Memory address pointing to the source data.
6.5.5.20 TCD Signed Source Address Offset (TCD0_SOFF -
TCD31_SOFF)
6.5.5.20.1 Offset
For n = 0 to 31:
Register Offset
TCDn_SOFF 1004h + (n × 20h)
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6.5.5.20.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SOFF
W
Reset u u u u u u u u u u u u u u u u
6.5.5.20.3 Fields
Field Description
15-0 Source address signed offset
SOFF Sign-extended offset applied to the current source address to form the next-state value as each source
read is completed.
6.5.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR)
6.5.5.21.1 Offset
For n = 0 to 31:
Register Offset
TCDn_ATTR 1006h + (n × 20h)
6.5.5.21.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SMOD SSIZE DMOD DSIZE
W
Reset u u u u u u u u u u u u u u u u
6.5.5.21.3 Fields
Field Description
15-11 Source Address Modulo
SMOD
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Memory map/register definition
Field Description
Any non-zero value in this field defines a specific address range specified to be the value after SADDR +
SOFF calculation is performed on the original register value. Setting this field provides the ability to
implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue
should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the
queue, freezing the desired number of upper address bits. The value programmed into this field specifies
the number of lower address bits allowed to change. For a circular queue application, the SOFF is
typically set to the transfer size to implement post-increment addressing with the SMOD function
constraining the addresses to a 0-modulo-size range.
00000 - Source address modulo feature is disabled
00001-11111 - Value defines address range used to set up circular data queue
10-8 Source data transfer size
SSIZE NOTE: 1. Using a reserved value causes a configuration error.
2. The eDMA defaults to privileged data access for all transactions.
000 - 8-bit
001 - 16-bit
010 - 32-bit
011 - 64-bit
100 - Reserved
101 - 32-byte burst (4 beats of 64 bits)
110 - Reserved
111 - Reserved
7-3 Destination Address Modulo
DMOD See the SMOD definition.
2-0 Destination data transfer size
DSIZE See the SSIZE definition.
6.5.5.22 TCD Minor Byte Count (Minor Loop Mapping Disabled)
(TCD0_NBYTES_MLNO - TCD31_NBYTES_MLNO)
This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
TCD_NBYTES_MLOFFYES), that defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, is enabled but
not used for this channel, or is enabled and used.
TCD word 2 is defined as follows if minor loop mapping is disabled (CR[EMLM] = 0).
If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and
TCD_NBYTES_MLOFFYES register descriptions for the definition of TCD word 2.
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6.5.5.22.1 Offset
For n = 0 to 31:
Register Offset
TCDn_NBYTES_MLNO 1008h + (n × 20h)
6.5.5.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
NBYTES
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NBYTES
W
Reset u u u u u u u u u u u u u u u u
6.5.5.22.3 Fields
Field Description
31-0 Minor Byte Transfer Count
NBYTES Number of bytes to be transferred in each service request of the channel. As a channel activates, the
appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes are
performed until the minor byte transfer count has transferred. This is an indivisible operation and cannot
be halted. It can, however, be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, and the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.
6.5.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping
Enabled and Offset Disabled) (TCD0_NBYTES_MLOFFNO -
TCD31_NBYTES_MLOFFNO)
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Memory map/register definition
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFYES), that defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, is enabled but
not used for this channel, or is enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• SMLOE = 0 and DMLOE = 0
If minor loop mapping is enabled and SMLOE = 1 or DMLOE = 1, refer to the
TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled,
refer to the TCD_NBYTES_MLNO register description.
6.5.5.23.1 Offset
For n = 0 to 31:
Register Offset
TCDn_NBYTES_MLOFF 1008h + (n × 20h)
NO
6.5.5.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
NBYTE
W
S
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NBYTES
W
Reset u u u u u u u u u u u u u u u u
6.5.5.23.3 Fields
Field Description
31 Source Minor Loop Offset Enable
SMLOE Specifies whether the minor loop offset is applied to the source address when the minor loop completes.
0 - The minor loop offset is not applied to the SADDR
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Field Description
1 - The minor loop offset is applied to the SADDR
30 Destination Minor Loop Offset Enable
DMLOE Specifies whether the minor loop offset is applied to the destination address when the minor loop
completes.
0 - The minor loop offset is not applied to the DADDR
1 - The minor loop offset is applied to the DADDR
29-0 Minor Byte Transfer Count
NBYTES Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes are performed until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via
preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, and the major iteration count is decremented and restored to the TCD memory. If the
major iteration count is completed, additional processing is performed.
6.5.5.24 TCD Signed Minor Loop Offset (Minor Loop Mapping and
Offset Enabled) (TCD0_NBYTES_MLOFFYES -
TCD31_NBYTES_MLOFFYES)
One of three registers (this register, TCD_NBYTES_MLNO, or
TCD_NBYTES_MLOFFNO), that defines the number of bytes to transfer per request.
Which register to use depends on whether minor loop mapping is disabled, is enabled but
not used for this channel, or is enabled and used.
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset is enabled (SMLOE or DMLOE = 1)
If minor loop mapping is enabled and SMLOE = 0 and DMLOE = 0, refer to the
TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled,
refer to the TCD_NBYTES_MLNO register description.
6.5.5.24.1 Offset
For n = 0 to 31:
Register Offset
TCDn_NBYTES_MLOFF 1008h + (n × 20h)
YES
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Memory map/register definition
6.5.5.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
MLOFF
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MLOFF NBYTES
W
Reset u u u u u u u u u u u u u u u u
6.5.5.24.3 Fields
Field Description
31 Source Minor Loop Offset Enable
SMLOE Specifies whether the minor loop offset is applied to the source address when the minor loop completes.
0 - The minor loop offset is not applied to the SADDR
1 - The minor loop offset is applied to the SADDR
30 Destination Minor Loop Offset Enable
DMLOE Specifies whether the minor loop offset is applied to the destination address when the minor loop
completes.
0 - The minor loop offset is not applied to the DADDR
1 - The minor loop offset is applied to the DADDR
29-10 If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the source or
destination address to form the next-state value after the minor loop completes.
MLOFF
9-0 Minor Byte Transfer Count
NBYTES Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes are performed until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via
preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, and the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
6.5.5.25 TCD Last Source Address Adjustment (TCD0_SLAST -
TCD31_SLAST)
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6.5.5.25.1 Offset
For n = 0 to 31:
Register Offset
TCDn_SLAST 100Ch + (n × 20h)
6.5.5.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SLAST
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST
W
Reset u u u u u u u u u u u u u u u u
6.5.5.25.3 Fields
Field Description
31-0 Last Source Address Adjustment
SLAST Adjustment value added to the source address at the completion of the major iteration count. This value
can be applied to restore the source address to the initial value, or adjust the address to reference the
next data structure.
This register uses two's complement notation; the overflow bit is discarded.
6.5.5.26 TCD Destination Address (TCD0_DADDR - TCD31_DADDR)
This register contains the destination address of the transfer.
6.5.5.26.1 Offset
For n = 0 to 31:
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Memory map/register definition
Register Offset
TCDn_DADDR 1010h + (n × 20h)
6.5.5.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DADDR
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DADDR
W
Reset u u u u u u u u u u u u u u u u
6.5.5.26.3 Fields
Field Description
31-0 Destination Address
DADDR Memory address pointing to the destination data.
6.5.5.27 TCD Signed Destination Address Offset (TCD0_DOFF -
TCD31_DOFF)
6.5.5.27.1 Offset
For n = 0 to 31:
Register Offset
TCDn_DOFF 1014h + (n × 20h)
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6.5.5.27.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DOFF
W
Reset u u u u u u u u u u u u u u u u
6.5.5.27.3 Fields
Field Description
15-0 Destination Address Signed Offset
DOFF Sign-extended offset applied to the current destination address to form the next-state value as each
destination write is completed.
6.5.5.28 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Disabled) (TCD0_CITER_ELINKNO -
TCD31_CITER_ELINKNO)
This register contains the minor-loop channel-linking configuration and the channel's
current iteration count. It is the same register as TCD Current Minor Loop Link, Major
Loop Count (Channel Linking Enabled) (TCD0_CITER_ELINKYES -
TCD31_CITER_ELINKYES), but its fields are defined differently based on the state of
the ELINK field. If the ELINK field is 0, this register is defined as follows.
6.5.5.28.1 Offset
For n = 0 to 31:
Register Offset
TCDn_CITER_ELINKNO 1016h + (n × 20h)
6.5.5.28.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CITER
ELINK
W
Reset u u u u u u u u u u u u u u u u
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Memory map/register definition
6.5.5.28.3 Fields
Field Description
15 Enable channel-to-channel linking on minor-loop complete
ELINK As the channel completes the minor loop, this field enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets TCDn_CSR[START] of the specified channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This field must be equal to BITER[ELINK]; otherwise, a configuration error is reported.
0 - Channel-to-channel linking is disabled
1 - Channel-to-channel linking is enabled
14-0 Current Major Iteration Count
CITER This field is the current major loop count for the channel. It is decremented each time the minor loop is
completed and updated in the transfer control descriptor memory. After the major iteration count is
exhausted, the channel performs a number of operations, for example, final source and destination
address calculations. It optionally generates an interrupt to signal channel completion before reloading
the CITER field from the Beginning Iteration Count (BITER) field.
NOTE: 1. When the CITER field is initially loaded by software, it must be set to the same value as
that contained in the BITER field.
2. If the channel is configured to execute a single service request, the initial values of BITER
and CITER should be 0x0001.
6.5.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (TCD0_CITER_ELINKYES -
TCD31_CITER_ELINKYES)
This register contains the minor-loop channel-linking configuration and the channel's
current iteration count. It is the same register as TCD Current Minor Loop Link, Major
Loop Count (Channel Linking Disabled) (TCD0_CITER_ELINKNO -
TCD31_CITER_ELINKNO), but its fields are defined differently based on the state of
the ELINK field. If the ELINK field is 1, this register is defined as follows.
6.5.5.29.1 Offset
For n = 0 to 31:
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Register Offset
TCDn_CITER_ELINKYE 1016h + (n × 20h)
S
6.5.5.29.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LINKCH
CITER
ELINK
W
0
Reset u u u u u u u u u u u u u u u u
6.5.5.29.3 Fields
Field Description
15 Enable channel-to-channel linking on minor-loop complete
ELINK As the channel completes the minor loop, this field enables linking to another channel, defined by the
LINKCH field. The link target channel initiates a channel service request via an internal mechanism that
sets TCDn_CSR[START] of the specified channel.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
linking.
NOTE: This field must be equal to BITER[ELINK]; otherwise, a configuration error is reported.
0 - Channel-to-channel linking is disabled
1 - Channel-to-channel linking is enabled
14 Reserved
—
13-9 Minor Loop Link Channel Number
LINKCH If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request to the channel defined by this field, by setting that channel's
TCDn_CSR[START].
8-0 Current Major Iteration Count
CITER This field is the current major loop count for the channel. It is decremented each time the minor loop is
completed and updated in the transfer control descriptor memory. After the major iteration count is
exhausted, the channel performs a number of operations, for example, final source and destination
address calculations. It optionally generates an interrupt to signal channel completion before reloading
the CITER field from the Beginning Iteration Count (BITER) field.
NOTE: 1. When the CITER field is initially loaded by software, it must be set to the same value as
that contained in the BITER field.
2. If the channel is configured to execute a single service request, the initial values of BITER
and CITER should be 0x0001.
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Memory map/register definition
6.5.5.30 TCD Last Destination Address Adjustment/Scatter Gather
Address (TCD0_DLASTSGA - TCD31_DLASTSGA)
6.5.5.30.1 Offset
For n = 0 to 31:
Register Offset
TCDn_DLASTSGA 1018h + (n × 20h)
6.5.5.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DLASTSGA
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLASTSGA
W
Reset u u u u u u u u u u u u u u u u
6.5.5.30.3 Fields
Field Description
31-0 Destination last address adjustment, or next memory address TCD for channel (scatter/gather)
DLASTSGA If (TCDn_CSR[ESG] = 0) then:
• This is the adjustment value added to the destination address at the completion of the major
iteration count. This value can apply to restore the destination address to the initial value or adjust
the address to reference the next data structure.
• This field uses two's complement notation for the final destination address adjustment.
Otherwise:
• This address points to the beginning of a 0-modulo 32-byte region containing the next TCD to be
loaded into this channel. This channel reload is performed as the major iteration count completes.
The scatter/gather address must be 0-modulo 32-byte; otherwise a configuration error is reported.
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6.5.5.31 TCD Control and Status (TCD0_CSR - TCD31_CSR)
6.5.5.31.1 Offset
For n = 0 to 31:
Register Offset
TCDn_CSR 101Ch + (n × 20h)
6.5.5.31.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
MAJORLINKCH
MAJORELINK
R
INTMAJOR
INTHALF
START
DREQ
DONE
BWC
ES
G
W
0
Reset u u u u u u u u u u u u u u u u
6.5.5.31.3 Fields
Field Description
15-14 Bandwidth Control
BWC Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces the eDMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the crossbar switch.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
00 - No eDMA engine stalls
01 - Reserved
10 - eDMA engine stalls for 4 cycles after each R/W
11 - eDMA engine stalls for 8 cycles after each R/W
13 Reserved
—
12-8 Major Loop Link Channel Number
MAJORLINKCH If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
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Memory map/register definition
Field Description
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel's START bit.
7 Channel Done
DONE This field indicates whether the eDMA has completed the major loop. The eDMA engine sets the value of
this field to 1 when the CITER count reaches zero. The value of this field is reset to 0 by the hardware
(when the channel is activated) or by software.
NOTE: This field must be 0 to write the MAJORELINK or ESG fields.
6 Channel Active
ACTIVE This field indicates whether the channel is currently in execution. The eDMA sets the value of this field to
1 when channel service begins, and resets it to 0 as the minor loop completes or when any error
condition is detected.
5 Enable channel-to-channel linking on major loop complete
MAJORELINK As the channel completes the major loop, this field controls linking to another channel, defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism
that sets TCDn_CSR[START] of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to when
TCDn_CSR[DONE] is set.
0 - Channel-to-channel linking is disabled
1 - Channel-to-channel linking is enabled
4 Enable Scatter/Gather Processing
ESG As the channel completes the major loop, this field controls scatter/gather processing in the current
channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0‑modulo 32‑bit
address containing a 32-byte data structure loaded as the TCD into local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written
to when TCDn_CSR[DONE] is set.
0 - The current channel's TCD is normal format
1 - The current channel's TCD specifies a scatter gather format
3 Disable Request
DREQ If the value of this field is 1, eDMA hardware automatically writes 0 to the corresponding ERQ field when
the current major iteration count reaches zero.
0 - The channel's ERQ field is not affected
1 - The channel's ERQ field value changes to 0 when the major loop is complete
2 Enable an interrupt when major counter is half complete.
INTHALF If the value of this field is 1, the channel generates an interrupt request by setting the appropriate field in
the INT register when the current major iteration count reaches the halfway point. Specifically, the
comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt
request is provided to support double-buffered, also known as ping-pong, schemes or other types of data
movement where the processor needs an early indication of the transfer's progress.
NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead.
0 - Half-point interrupt is disabled
1 - Half-point interrupt is enabled
1 Enable an interrupt when major iteration count completes.
INTMAJOR
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Field Description
If the value of this field is 1, the channel generates an interrupt request by setting the appropriate field in
the INT when the current major iteration count reaches zero.
0 - End of major loop interrupt is disabled
1 - End of major loop interrupt is enabled
0 Channel Start
START If the value of this field is 1, the channel is requesting service. eDMA hardware automatically writes 0 to
this field after the channel begins execution.
0 - Channel is not explicitly started
1 - Channel is explicitly started via a software initiated service request
6.5.5.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel
Linking Disabled) (TCD0_BITER_ELINKNO -
TCD31_BITER_ELINKNO)
If TCDn_BITER[ELINK] is 0, the TCDn_BITER register is defined as follows.
6.5.5.32.1 Offset
For n = 0 to 31:
Register Offset
TCDn_BITER_ELINKNO 101Eh + (n × 20h)
6.5.5.32.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ELINK
BITE
W
R
Reset u u u u u u u u u u u u u u u u
6.5.5.32.3 Fields
Field Description
15 Enables channel-to-channel linking on minor loop complete
ELINK
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Memory map/register definition
Field Description
As the channel completes the minor loop, this field enables linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets TCDn_CSR[START] of the specified channel. If channel linking is disabled, the BITER value
extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is
suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0 - Channel-to-channel linking is disabled
1 - Channel-to-channel linking is enabled
14-0 Starting Major Iteration Count
BITER As the TCD is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to
the value in the CITER field. As the major iteration count is exhausted, the contents of this field are
reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
6.5.5.33 TCD Beginning Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (TCD0_BITER_ELINKYES -
TCD31_BITER_ELINKYES)
If TCDn_BITER[ELINK] is 1, the TCDn_BITER register is defined as follows.
6.5.5.33.1 Offset
For n = 0 to 31:
Register Offset
TCDn_BITER_ELINKYE 101Eh + (n × 20h)
S
6.5.5.33.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LINKCH
ELINK
BITE
W
0
Reset u u u u u u u u u u u u u u u u
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Chapter 6 Enhanced Direct Memory Access (eDMA)
6.5.5.33.3 Fields
Field Description
15 Enables channel-to-channel linking on minor loop complete
ELINK As the channel completes the minor loop, this field enables linking to another channel, defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets TCDn_CSR[START] of the specified channel. If channel linking disables, the BITER value
extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is
suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
0 - Channel-to-channel linking is disabled
1 - Channel-to-channel linking is enabled
14 Reserved
—
13-9 Link Channel Number
LINKCH If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request at the channel defined by this field, by setting that channel's
TCDn_CSR[START].
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field.
8-0 Starting major iteration count
BITER As the TCD is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to
the value in the CITER field. As the major iteration count is exhausted, the contents of this field are
reloaded into the CITER field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, the
contents of this field are reloaded into the CITER field. If the channel is configured to execute a
single service request, the initial values of BITER and CITER should be 0x0001.
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Memory map/register definition
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Chapter 7
System Security
7.1 Chapter overview
This chapter provides an overview of the following chip security components, explaining
the purpose and features of each of them.
• System Boot ROM including High Assurance Boot (HAB)
• Secure Non-Volatile Storage (SNVS) with real-time clock, zero master key, and
tamper protection
• Random Number Generator (RNG)
• Cryptographic Acceleration and Assurance Module (CAAM)
• On-chip One-Time Programmable Element Controller (OCOTP_CTRL) with on-
chip electrical fuse arrays
• Secure key manager (KEYMGR) and protection
• Physical Unclonable Function (PUF)
• UnDocumented Function (UDF)
• JTAG Controller (JTAGC) and SWD debug interfaces
• Inline Encryption Engine (IEE)
• On-the-Fly AES Decryption (OTFAD)
• Resource Domain Controller (RDC) and Extended Resource Domain Controller
(XRDC) are used to support both single-core and multi-core use cases with
maximum flexible resource management
• Code WatchDog timer (CDOG)
The detailed description of each component can be found in the Security Reference
Manual for this chip.
7.2 Feature summary
This figure shows a simplified diagram of the security subsystem:
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Feature summary
CAAM
ECC - P521 RNG
Resource Mgmt
AES -256 RSA -4096
iROM (RDC, xRDC) SEMC
HAB v 4.5.5
Secure Key Module
OCRAM
IEE_APC FlexSPI
IEE
ARM
SNVS OTFAD
CORE
HP
MMCAU System Security Monitor
KEYMGR
Secure Time and Monotonic Counter LP
Secure JTAG Zeroizable Secret key
Debug Controller
Digital Low-Voltage Detector (LVD)
Tampers (CVT)
JTAG Security Control
Electrical Fuse Array (OCOTP)
Fuse Secret Key , Boot Image Version Control ,
Chip Unique Identification , SRK hash , Security Configuration
Figure 7-1. Security subsystem (simplified)
All platforms built using this chip share a general need for security, though the specific
security requirements vary greatly from platform to platform. For example, portable
consumer devices need to protect a different type and cost of assets than automotive or
industrial platforms. Each market must be protected against different kinds of attacks.
The platform designers need an appropriate set of countermeasures to meet the security
needs of their specific platform.
To help the platform designers to meet the requirements of each market, the chip
incorporates a range of security features. Most of these features provide protection
against specific kinds of attack, and can be configured for different levels according to
the required degree of protection. These features are designed to work together or
independently. They can be also integrated with the appropriate software to create
defensive layers. In addition, the chip includes a general-purpose accelerator that
enhances the performance of selected industry-standard cryptographic algorithms.
The security features include:
• High Assurance Boot and encrypted boot
• Secure storage
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Chapter 7 System Security
• Off-chip storage protection using AES-256 and the chip's unique hardware-only
key
• 4KB Secure RAM (SRAM) in SNVS
• Zeroizable Master Key (256 bits)
• SNVS General Purpose Registers (256 bits)
• Cryptographic Acceleration and Assurance Module (CAAM)
• Symmetric Engines - AES 128, 256 with baseline modes (additional modes
include GCM, CMAC), 3DES, DES
• Public Key Cryptography Engine (PKHA): RSA up to 4096 key length, elliptic
curve (supporting NIST, Brainpool)
• Manufacturing protection
• 64-bit multiplier for V2X performance requirements (500+ NIST P-256
signatures/sec)
• Cryptographic Hash Engine: SHA-1, SHA-2 224/256/384/512, MD5, and
HMAC
• Random Number Generator (RNG)
• True random entropy source
• NIST-certified Deterministic Random Bit Generator (Hash-based)
• Secure Hardware-only Cryptographic Key Management
• Encrypted boot
• Revision control check based on fuse values
• Data Encryption Key (DEK) includes IV
• Real-Time Integrity Checker (RTIC)
• Secure debug
• 128-bit OTP debug authentication key
• Electrical fuses (OTP Memory)
• Inline Encryption Engine (IEE)
• SDRAM encryption/decryption
• Secure scan
• OCRAM encryption/decryption
• I/O direct encrypted storage and retrieval (Stream support)
• FlexSPI decryption only (256-bit AES-XTS mode XIP)
• Transparency to software during encrypted access (no configuration, control, or
interrupts)
• Secure on-chip key loading using private bus
• AES-128 counter mode On-The-Fly Decryption (OTFAD)
• 128-bit key and 128-bit data sizes
• Receives 64-bit encrypted data from FlexSPI
• Hardware support for unwrapping key blobs
• Acts as a slave sub-module to FlexSPI
• Secure Non-Volatile Storage (SNVS)
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Resource Management
• Secure real-time clock (SRTC)
• Tamper protection
• DryICE
7.3 Resource Management
To support both single-core and multi-core use cases with max flexible resource
management, both Resource Domain Controller (RDC) and Extended Resource Domain
Controller 2 (XRDC) are used.
Bus parent Address Region System Bus Multi-processor Security Level Bus children
Protect Domain Protect Protect
CM7 CM7
peripherals
Privilege DID
Privilege
CID
IEE flag
Secure
Privilege DID
Addr
CID
Secure
Secure
CM4
xRDC memories
CM4
IEE_APC AIPSTZ/ PAC/MRC/
Attributes MSC
DEXSC
DMA
xRDC
IEE system
GPRs
MDAC DMA
controllers
SSARC RDC
DMA
CM7
xRDC
CM4
MGR
Figure 7-2. Resource Management
• RDC is used as first-level control:
• Protects the access to resources based on CPU domain assignment in RDC
• Resources of the chip are assigned to two CPU domains as follows
• Private resource : Used by either CPUs
• Shared resource: Used by both CPUs
• XRDC is used as second-level control:
• Protects the access to resources based on access type (Secure/non-secure access
and Privileged/user access)
• Each CPU has its own XRDC, which supports up to 16 domains
7.4 Secure Key Manager (KEYMGR)
The Key Manager is used to generate, manage, fetch and configure keys for SNVS,
OTFADs, and IEE. For better key generation and management, this block integrates
UnDocumented Function (UDF) and Physical Unclonable Function (PUF).
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Chapter 7 System Security
• UnDocumented Function (UDF)
• Provides a deterministic cryptographic function whose characteristics are not
standard nor documented.
• Generates a deterministic, one-way cryptographic function for obfuscation
purposes
• Supports the ability to include cryptographic “salt” to alter UDF calculation
• Provides mechanisms to lock and reset
• Physical Unclonable Function (PUF)
• Key generated by silicon entropy, which is silicon-unique and unclonable
fingerprint
7.5 High-Assurance Boot (HAB)
The HAB, which is the high-assurance boot feature in the system boot ROM, detects and
prevents the execution of unauthorized software (malware) during the boot sequence.
When the unauthorized software is permitted to gain control of the boot sequence, it can
be used for a variety of goals, such as exposing stored secrets, circumventing access
controls to sensitive data, services, or networks, or for re-purposing the platform. The
unauthorized software can enter the platform during upgrades or re-provisioning, or when
booting from the USB connections or removable devices.
The HAB protects against unauthorized software by:
• Using digital signatures to recognize the authentic software. This enables you to boot
the device to a known initial state and run the software signed by the device
manufacturer.
• Using code encryption to protect the confidential software during off-chip storage.
When activated, the HAB decrypts the software loaded into the RAM before
execution.
7.5.1 HAB process flow
The following figure shows the flow for creating and verifying digital signatures. The top
half of this figure shows the signing process, which is performed off-chip. The bottom
half shows the verification process performed on-chip during every system boot.
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High-Assurance Boot (HAB)
Figure 7-3. Code signing and authentication processes
The original software is programmed into the flash memory (or any other boot device)
along with the signature. The HAB uses a public key to recover the reference hash value
from the signature; it then compares the reference hash value to the current hash value
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Chapter 7 System Security
calculated from the software in the flash. If the contents of the flash are modified either
intentionally or unintentionally, the two hash values do not match and the verification
fails.
NOTE
Use OTFAD for providing software confidentiality when the
user code executes in place.
7.5.2 HAB feature summary
The HAB features:
• Enforced internal boot via on-chip masked ROM
• Authentication of software loaded from any boot device (including the USB
download)
• Authenticated decryption of software loaded from any boot device (including USB
download) using the AES keys (128-bit, 256-bit)
• CMS PKCS#1 signature verification using RSA public key (1024, 2048, 3072 or
4096) and the SHA256 hash algorithm
• ECDSA signature verification using ECC public key (P256, P384, P521) and the
SHA256 hash algorithm
• Public Key Infrastructure (PKI) support using X.509v3 certificates
• Root public key fingerprint in the manufacturer-programmable on-chip fuses
• Multiple root public keys with revocation by fuses
• Initialization of other security components
• Supports fall-through USB downloader if the primary or recovery boot fails
• Open configuration for development purposes and non-secure platforms
• Closed configuration for shipping secure platforms
On the chip, the HAB is integrated with these security features:
• The HAB initializes the SNVS security monitor state machine. A successful secure
boot with the HAB is required for the platform software to gain access to use the
CAAM master secret key selected by SNVS.
• The HAB reads the root public key fingerprint, revocation mask, and security
configuration from the OCOTP_CTRL.
• Depending on the algorithm, HAB will use the CAAM to accelerate some crypto
operations:
• ECC is accelerated by CAAM
• RSA is handled by software within HAB
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Secure Non-Volatile Storage (SNVS) module
• AES is accelerated by CAAM
• SHA is handled by HAB software or CAAM accelerated depending on the
signature command sequence file (CSF)
7.6 Secure Non-Volatile Storage (SNVS) module
• Provides a non-volatile real-time clock maintained by a coin-cell battery during
system power down for use in both the secure and non-secure platforms.
• Protects the secure real-time clock against rollback attacks in time-sensitive protocols
such as DRM and PKI
• Deters replay attacks in time-independent protocols such as certificate or firmware
revocations
• Handles security violation detection and reporting, to defend sensitive data and
operations against compromise, both at run-time and during system power-down
• Controls the access to the OTP master secret key used by the CAAM to protect
confidential data in the off-chip storage
• Provides non-volatile highly protected storage for an alternative master secret key
• Provides tamper detection
• Provides a 1K bit register (GPRs) protected by tamper
• Supports wakeup source
7.6.1 SNVS architecture
The SNVS is partitioned into two sections: a low-power part (SNVS_LP) and a high-
power part (SNVS_HP).
The SNVS_LP block is in the always-powered-up domain. It is isolated from the rest of
the logic by isolation cells which are library-instantiated cells that insure that the
powered-up logic is not corrupted when the power goes down in the rest of the chip.
The SNVS_LP has these functional units:
• Zeroizable Master Key
• Secure non-rollover real-time counter with alarm
• Non-rollover monotonic counter
• Digital Low-Voltage Detector (LVD)
• General-purpose register
• Control and status registers
• 4KB Secure RAM (SRAM)
• Tamper detection
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Chapter 7 System Security
The SNVS_HP is in the chip power-supply domain. The SNVS_HP provides an interface
between the SNVS_LP and the rest of the system. The access to the SNVS_LP registers
can be gained through the SNVS_HP only when it is powered up according to the access
permission policy.
The SNVS_HP has these functional units:
• IP bus interface
• SNVS_LP interface
• System Security Monitor (SSM)
• Zeroizable Master Key programming mechanism
• Master Key control block
• Non-secure real-time counter with alarm
• Control and status registers
• High Assurance Counter (HAC)
7.6.2 DryICE
The SNVS interface contains mixed logic called DryICE, which provides a 32 kHz
system clock, and has voltage, temperature, and clock (VTC) tamper detection monitors.
Once a tamper is detected for VTC, a security violation will be sent to the main digital
SNVS peripheral. Please see the IOMUXC SNVS GPRs for related DryICE
programming.
Table 7-1. DryICE Tampers
Tamper Monitor Description
Voltage Detector Checks whether voltages from battery and regulator are normal or not. If
the voltage is out-of-range, the out-of-range flag will assert high to SNVS
Digital tamper logic.
Temperature Detector Determins whether the current temperature is appropriate. If the
temperature is out-of-range, the out-of-range flag will assert high to SNVS
Digital tamper logic.
Clock Detector Monitors whether the internal 32 kHz crystal oscillator is in it's normal
operation. If the XTALOSC 32 kHz clock stops or is out-of-range, the
internal 32 kHz source will be switched, and the out-of-range flag will
assert high to SNVS Digital tamper logic.
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Cryptographic Acceleration and Assurance Module (CAAM)
VDD (Battery) voltage out-of-range
Voltage
VDD (1P8) Detector vdd_ok
volt_det_trim
Temperature
temp_det_trim Detector temp out-of-range
XTALI
XTALO clock out-of-range
Clock
clk_det_trim
Detector 32 kHz OUT
osc32k_trim
irc32k_trim
Figure 7-4. DryICE Block Diagram
7.7 Cryptographic Acceleration and Assurance Module
(CAAM)
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Chapter 7 System Security
7.7.1 CAAM Overview
CAAM is a cryptographic acceleration module that accelerates block encryption
algorithms, stream cipher algorithms, hashing algorithms, and random number
generation. It has an integrated DMA engine that allows CAAM to fetch its command
programs, read input data and write the resulting output.
CAAM works with the SNVS to provide platform assurance features, including support
for High Assurance Boot, detection of and response to potential tamper events, and short
term and long-term protection of secret data such as public keypairs, Digital Rights
Management keys and proprietary software.
CAAM provides the following features:
• Public Key Cryptography Engine (PKHA)
• RSA up to 4096 key length; Elliptic Curve (up to P-521)
• Manufacturing Protection
• Elliptic supports NIST, Brainpool
• 64-bit Multiplier for V2X performance requirements (500+ NIST P-256
signatures/sec)
• Symmetric Engines
• AES 128, 192, 256 with baseline modes
• AES additional modes include GCM, CMAC
• 3DES, DES
• Cryptographic Hash Engine
• SHA-1, SHA-2 224/256/384/512, MD5
• HMAC
• Random Number Generation (RNG)
• True random Entropy Source
• NIST-certified Deterministic Random Bit Generator (Hash-based)
7.8 On-Chip OTP Controller (OCOTP_CTRL)
The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with the
on-chip fuses. These fuses' uses include:
• Unique chip identifiers
• Mask revision numbers
• Cryptographic keys
• Security configuration
• Boot characteristics
• Various control signals requiring permanent non-volatility
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Debug
The OCOTP_CTRL provides:
• Shadow cache of fuse values, loaded at reset, before the system boot
• Ability to read and override the fuse values in the shadow cache (does not affect the
fuse element)
• Ability to read the fuses directly (ignoring the shadow cache)
• Ability to write (program) the fuses by software or JTAG
• Fuses and shadow cache bits enforce read-protect, override-protect, and write-protect
• Lock fuses for selected fuse fields
• Scan protection
• Volatile software-accessible signals which can be used for software control of
hardware elements (not requiring non-volatility).
7.9 Debug
The debug interface is connected to the DAP and CoreSight debug modules to allow
debug through the JTAG interface. The key features of the system debug is listed below.
For more information on the CoreSight debug components, please see the System Debug
chapter in the Reference Manual.
• 5-pin JTAG and SWD interface (fuse configured)
• Non-intrusive and halt-mode trace / debug options
• Secure Debug with 128-bit protection key
• ARM real-time trace interface (TPIU)
The security levels are selected via the eFuse configuration.
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Chapter 7 System Security
CSSYS
Trace
(4-bits)
TPIU ATB
DAP
CM4
AHB-AP
SWJ-DP CM7
AHB-AP
JTAGC
JTAG/SWD
TESTDP APB-AP
JTAG_MOD
Test
control
Test control from PADs TCU to
modules
Figure 7-5. System-Level Debug Architecture
7.9.1 JTAG Controller (JTAGC)
There is only one JTAG interface on the chip. Two JTAG modes are supported, which
are selected via the JTAG_MOD pin:
• Debug Mode (JTAG_MOD == 0)
• DAP and JTAGC share the same JTAG by using exclusive instructions.
• TESTDP will be bypassed.
• Test Mode (JTAG_MOD == 1)
• TESTDP is the only TAP controller in the daisy chain (IEEE1149.1 compliant).
The JTAGC provides debug access to hardware blocks, including the arm processor and
the system bus. This enables program control and manipulation as well as visibility to the
chip peripherals and memory.
The JTAG port must be accessible during initial platform development, manufacturing
tests, and general troubleshooting. Given its capabilities, the JTAGC provides these
security levels:
• JTAG Disabled - JTAG use is permanently blocked.
• No Debug Mode - All security sensitive JTAG features are permanently blocked.
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Inline Encryption Engine (IEE)
• Secure JTAG Mode - JTAG use is restricted (as in the No-Debug level) unless a
secret-key challenge/response protocol is successfully executed.
• JTAG Enabled - JTAG use is unrestricted.
The security levels are selected via the eFuse configuration.
JTAG controller is
JTAG_DISABLE = 0 No
disabled
Yes
JTAG_MOD pin = 0
Yes
SEC_CONFIG[1:0] == 11 SEC_CONFIG[1:0] != 11
or and
KTE == 1 KTE == 0
Yes
Yes
JTAG_SMODE[1:0] = 11 JTAG_SMODE[1:0] = 01 JTAG_SMODE[1:0] = 00
Yes Yes Yes
No debug mode Secure JTAG mode JTAG enable mode JTAG is enabled
Figure 7-6. Secure JTAGC Configuration
7.10 Inline Encryption Engine (IEE)
IEE provides a means to perform inline encryption and decryption.
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Chapter 7 System Security
It provides the following features:
• SDRAM encryption/decryption
• FlexSPI decryption only
• Secure scan
• Secure on-chip key loading
• I/O direct encrypted storage and retrieval (Stream Support)
7.11 On-the-Fly AES Decryption (OTFAD)
OTFAD works with FlexSPI to provide superior cryptographic decryption capabilities
without compromising system performance.
It has the following features:
• AES-128 Counter Mode On-the-Fly Decryption
• 128-bit key and 128-bit data sizes
• Receives 64-bit encrypted data from FlexSPI
• Functionally acts as a slave submodule to the FlexSPI
• Programming model mapped into the upper 1 KB of the FlexSPI’s IPS address
space
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On-the-Fly AES Decryption (OTFAD)
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Chapter 8
System Debug
8.1 Overview
This section describes the hardware and software debug and application development
features and resources of the chip. It describes the following:
• Core/platform-specific resources
• Resources associated with complex IP blocks
• Chip-wide resources
• Interface to the external debug and development tools
The debug and trace architecture is designed around the following:
• Arm CoreSight architecture, adapted to SoC (for core debug), including a cross-
trigger subsystem for cross-domain triggering of debug resources
• JTAG port used to interact with core under the debug by means of JTAGC, the JTAG
Controller
• DAP, the debug access port that supports the interface to the Arm RealView
Debugging tools and other third-party tools
• TPIU, a trace port interface unit that efficiently accesses the program trace
information from the system
• Various chip-wide resources, such as debug features built into the IP blocks and
critical signal visibility available through alternate pin functions or observability
muxes
8.2 Chip and Arm Platform Debug Architecture
The Arm Debug architecture is based on the CoreSight architecture by Arm. The
CoreSight architecture provides a system-wide solution to real-time debug and trace.
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The CoreSight architecture is embodied in a set of CoreSight components and compliant
processors that form the CoreSight systems. Its architecture maintains the traditional
requirements of debug and trace:
• To access the debug functionality without software interaction
• To connect to a running system without performing a reset
Full access to the processor debug capability is available by the Arm debug register map
through the Advanced Peripheral Bus (APB) slave port. The core includes a Processor
Debug Unit which stops program execution, examines and alters the processor and
coprocessor state, examines and alters the memory and input/output peripheral state, and
restarts the processor core.
The following diagram shows the system level debug architecture:
CSSYS
Trace
(4-bits)
TPIU ATB
DAP
CM4
AHB-AP
SWJ-DP CM7
AHB-AP
JTAGC
JTAG/SWD
TESTDP APB-AP
JTAG_MOD
Test
control
Test control from PADs TCU to
modules
Figure 8-1. System Level Debug Architecture
Table 8-1. List of supported MEM-APs
APSEL Access Port IDR
0 CM7 (AHB-AP) 0x84770001
1 CM4 (AHB-AP) 0x24770011
2 APB-AP 0x54770002
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Chapter 8 System Debug
8.2.1 Debug Features
• EmbeddedICE-RT logic
• Support for both the monitor-mode and halt-mode debugging:
• Core run/halt control, debug status/control
• Breakpoint/watchpoint control
• Core-mapped and memory-mapped resource examination/modification
• Data communication channel between the Arm core and the host debugger via JTAG
or SWD and the Debug Access Port (DAP) module
The chip includes Arm CoreSight components for debug and trace solutions.
8.2.2 Debug system components
The CoreSight components include:
• ETM (Embedded Trace Macrocell) supporting instruction trace
• ITM (Instrumentation Trace Macrocell)
• TPIU (Trace Port Interface)
• Cross Triggering logic for event routing (CTIs)
• Timestamp Generator (TSGEN)
• Data Watchpoint and Trace (DWT)
Other related IPs and functionality:
• Flash Patch and Breakpoint unit (FPB)
FPB for CM4 cannot be used since the flash address is beyond 0x20000000.
8.2.2.1 AMBA Trace Bus (ATB)
ATB transfers trace data though the chip CoreSight infrastructure. The trace sources are
ATB masters and the sinks are ATB slaves. The Arm (via PTM) cores are the data
generators. Link components such as the Trace Funnel and Replicator provide both the
master and slave interfaces.
The ATB protocol supports:
• Stalling of trace sources to enable the CoreSight components to funnel and combine
the sources into a single trace stream
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• Association of the trace data with the generating source using trace source IDs. The
CoreSight system can trace up to 111 different items at any time
• Capture and transfer of multiple byte bus widths, currently to 32 bits
• A flushing mechanism to force the historic trace to drain from any sources, links, or
sinks up to the point that the request is initiated
8.2.2.2 CoreSight Trace Port Interface (TPIU)
TPIU is one of the CoreSight trace sink components. It acts as a bridge between the on-
chip trace data and a data stream that is then driven out the trace port.
TPIU uses the ATB interface to accept trace data from a trace source, either directly or by
using a trace funnel. TPIU has 4 bit port connected to the chip pad.
The APB interface is the programming interface for the TPIU configuration.
The features of the sub-blocks are as follows:
• Formatter—Inserts source ID signals into the data packet stream so that the trace data
can be re-associated with the trace source.
• Asynchronous FIFO—Enables trace data to be driven out at a speed that is not
dependent on the on-chip bus clock.
• Register Bank—Contains the management, control and status registers for triggers,
flushing behavior and external control.
• Trace out—The Trace out block serializes the formatted data before it goes off-chip.
• Pattern Generator—The Pattern Generator unit provides a simple set of defined bit
sequences or patterns that can be output over the Trace Port and be detected by the
TPA or other associated Trace Capture Device (TCD). The TCD can use these
patterns to indicate if it is possible to increase or decrease the trace port clock speed.
The output of the TPIU is connected via external pins (MPS of TRACEDATA
(ARM_TRACEn), which can be 1, 2, or 4 bits). The system may utilize double data rate
pins to either use a lower clock speed than that of the 32-bit ATB interface, or use fewer
than 4 data pins for the output, based on the ability of the technology used. Given the
speed of the ATB, 4 data pins with double data rate is recommended, with the external
interface running at half the speed of the ATB. The speed of the external interface is from
TRACECLKIN (CSTRACE_CLK_ROOT). TRACECLK (ARM_TRACE_CLK) is
equal to TRACECLKIN / 2, and is divided in the TPIU to clock trace data at the trace
capture unit.
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Chapter 8 System Debug
TPIU used to be part of the Arm platform sub blocks in previous versions of i.MX
products, placing the TPIU off platform allows future debug trace sources from the chip
level to connect to the TPIU by means of a funnel.
For more information, see Arm Cortex M4 Platform chapter.
For more information, see Arm Cortex M7 Integration and Implementation Manual.
8.2.2.3 Embedded Trace Macrocell v3.5 (ETM)
The Cortex-M4 Embedded Trace Macrocell (ETM-M4) is a debug component that
enables a debugger to reconstruct program execution. The CoreSight ETM-M4 supports
only instruction trace. You can use it either with the CoreSight Trace Point Interface Unit
(TPIU).
The main features of an ETM are:
• Tracing of 16-bit and 32-bit Thumb instructions
• Four EmbeddedICE watchpoint inputs
• A Trace Start/Stop block with EmbeddedICE inputs
• One reduced function counter
• Two external inputs
• A 24-byte FIFO queue
• Global timestamping
8.2.2.4 ITM
The Cortex-M4 ITM is an application-driven trace source that supports printf style
debugging to trace Operating System (OS) and application events, and emits diagnostic
system information. The ITM emits trace information as packets. There are four sources
that can generate packets. If multiple sources generate packets at the same time, the ITM
arbitrates the order in which packets are output. The four sources in decreasing order of
priority are:
1. Software trace—Software can write directly to ITM stimulus registers. This emits
packets.
2. Hardware trace—The DWT generates these packets, and the ITM emits them.
3. Time stamping—Timestamps are emitted relative to packets. The ITM contains a 21-
bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of
the Serial Wire Viewer (SWV) output clocks the counter.
4. Global system timestamping. Timestamps can optionally be generated using a
system-wide 48-bit count value. The same count value can be used to insert
timestamps in the ETM trace stream, allowing coarse-grain correlation.
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8.2.2.5 Embedded Trace Macrocell (ETM)
Instruction trace, also known as ETM (Embedded Trace Macrocell) trace, is a
continuously collected sequence of every executed instruction for a selected portion of
the application. ETM generates trace packets and sends them to the trace bus. ETM does
not actually output every address or instruction that the processor has reached or
executed; it usually generates compressed information about the program flow and
outputs full addresses only if needed (for example, if a branch has taken place). Because
the debugger knows the application code image, the debugger can then reconstruct the
full instruction sequence from the trace data.
For more information about ETM, refer to Arm® CoreSight™ ETM-M7 Revision r0p1
Technical Reference Manual.
8.2.2.6 Instrumentation Trace Macrocell
The ITM (Instrumentation Trace Macrocell) generates trace information as packets.
There are four sources that can generate packets. If multiple sources generate packets at
the same time, the ITM arbitrates the order in which packets are output. The four sources
in decreasing order of priority are:
• Synchronization: DWT provides periodic requests to make ITM generate
synchronization packet. Trace capture hardware uses it to identify the alignment of
packet bytes in the bit-stream.
• Software Trace: Application software can write console messages directly to ITM
stimulus ports, and output them to the host as trace packets.
• Hardware trace: The DWT generates these packets, and the ITM outputs them.
• Timestamping: ITM can generate timestamp packets that are inserted in to the trace
stream, to help the host debugger to find out the timing of events. Timestamps are
generated relative to packets. The ITM receives a 64-bit counter to generate the
timestamp.
Trace data from ITM will be forwarded to TPIU and streamed out via the trace port.
For more information about ITM, refer to Armv7-M Architecture Reference Manual.
8.2.2.7 Cross-Trigger Interface (CTI)
The Cross-Trigger Interface (CTI) component is provided by Arm. A brief description of
the CTI is provided below.
This chip contains three CTIs in the following sections:
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Chapter 8 System Debug
• CM7 platform
• CM4 platform
• CSSYS
The CTIs in ARM cores have 8 trigger inputs and 8 trigger outputs that connect to logic
in the domain to be debugged or profiled. Each CTI includes a 4-channel interface to the
CTM. The CSSYS CTI also contains an 8 trigger IN/OUT along with the 4-channel
interface to CTM.
The diagram below shows the high-level connections.
Trig out 0
CM7 EDBGRQ
Trig in 0
CM7 HALTED
Trig out 2:1
CTI IRQ[1:0]
Trig out 6:3
EXTIN3:0]
ETM Trig in 7:4 CM7
EVENTM[3:0] CTI
Trig out 7 Channel 1
CM7 DBGRESTART Trig out 0
Trig in 1 Trig in
match[0] | match[4]
Trig out 1 TPIU
Trig in 2 Flush in
DWT match[1] | match[5]
Channel 0
Trig in 3 CSSYS
match[2] | match[6] CTM CTI
Trig out 0 Trig out 2
CM4 EDBGRQ Channel 2 Halt dbg
Trig in 0
CM4 HALTED Timestamp
MCM IRQ
Trig out 3:2 Generator
Trig in 7
ETM ETMTRIGOUT CM4
Trig out 5:4 CTI
EXTIN[1:0]
Trig in 6:4
DWT dwt_ etm_trigger[2:0]
CSSYS
Trig out 7
CM7 DBGRESTART
Figure 8-2. High-level connections
8.2.2.8 Cross-Trigger Matrix (CTM)
The CTM (Cross-Trigger Matrix) is provided by ARM. A brief description is provided
below. See the ARM documentation for more detail.
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The CTM is a relatively simple block with no configuration options. There is one
instance of CTM present in the ARM platform. It routes Cross Trigger Interfaces (CTI)
from Cortex-M7 and Cortex-M4 to Coresight CTI.
8.2.3 Chip-Specific JTAGC Features
8.2.3.1 JTAG Disable Mode
In addition to three different JTAG security modes that are implemented internally in the
JTAG Controller, there is an option to disable the JTAGC functionality by e-fuse
configuration. This creates additional JTAG mode "JTAG Disabled" with highest level of
JTAG protection. In this mode all JTAG features are disabled.
8.2.3.2 JTAG ID
Table 8-2. i.MX JTAG ID
Device Silicon revision JTAG ID
i.MX RT1170 Rev 1.0 088C_601Dh
8.2.3.3 JTAG-to-SWD change sequence
1. Send more than 50 TCK cycles with TMS (SWD_IO) = 1
2. Send the 16-bit sequence on TMS (SWD_IO) = 0111_1001_1110_1111 (MSB
transmitted first)
3. Send more than 50 TCK cycles with TMS (SWD_IO) = 1
NOTE
See the ARM documentation for the CoreSight DAP Lite for
restrictions.
8.2.4 JTAG controller main features
• IEEE P1149.1 interface to off-chip test and development equipment
• Three levels of security, ranging from no security to no JTAG accessibility to the
chip
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Chapter 8 System Debug
NOTE
The security levels are detailed in the Security Reference
Manual (SRM).
8.2.5 TAP port
The JTAGC supports the following standard JTAG pins:
• TRSTB
• TDI
• TDO
• TCK
• TMS
The figure below shows the TAP structure:
TAP (JTAGC)
Instruction Register 4-bit
TDI
Data Register 32-bit
TDO
TAP (CoreSight)
Instruction Register 4-bit
IR_SEL
TMS
TMS
Data Register 32-bit
Figure 8-3. Tap structure
Refer to Arm technical documentation for more details.
8.3 Miscellaneous
The Miscellaneous function described in this section provide useful general capabilities.
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Miscellaneous
8.3.1 Clock/Reset/Power
The DAP, ITM, and ETM existing in CM7 power domain will be powered off along with
CM7. Similarly, the DAP, ITM, and ETM existing in the CM4 power domain and will be
powered off along with CM4. The JTAG controller, TPIU and CoreSight DAP are in
WAKEUPMIX power domain.
The debug components can receive resets from the following sources:
• Debug Reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register of the
DAP) in the TCLK domain. This allows the debug tools to reset the debug logic.
• System POR reset
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Chapter 9
JTAG Controller (JTAGC)
9.1 Chip-specific JTAG information
Table 9-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
9.2 Overview
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format.
9.2.1 Block diagram
The following is a simplified block diagram of the JTAG Controller (JTAGC) block. See
the chip-specific configuration information within this chapter as well as Register
description for more information about the JTAGC registers.
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Functional description
JCOMP
Test Access Port (TAP)
TMS Controller
TCK
1-bit Bypass Register
32-bit Device Identification Register
TDI TDO
Boundary Scan Register
TAP Instruction Decoder
TAP Instruction Register
Figure 9-1. JTAG (IEEE 1149.1) block diagram
9.2.2 Features
The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the
following features:
• IEEE 1149.1-2001 TAP interface
• Four pins (TDI, TMS, TCK, and TDO )
• JCOMP input that provides reset control
• Instruction register that supports several IEEE 1149.1–2001 defined instructions as
well as several public and private device-specific instructions (see JTAGC block
instructions for a list of supported instructions).
• Bypass register, boundary scan register, and device identification register
• TAP controller state machine that controls the operation of the data registers,
instruction register, and associated circuitry
9.3 Functional description
This section explains the JTAGC functional description.
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Chapter 9 JTAG Controller (JTAGC)
9.3.1 Modes of operation
The JTAGC block uses JCOMP and a power-on reset indication as its primary reset
signals. Several IEEE 1149.1–2001 defined test modes are supported, as well as a bypass
mode.
9.3.1.1 Reset
The JTAGC block is placed in reset when:
• Power-on reset is asserted
• JCOMP is negated
• TMS input is held high for enough consecutive rising edges of TCK to sequence the
TAP controller state machine into the Test-Logic-Reset state
Holding TMS high for five consecutive rising edges of TCK guarantees entry into the
Test-Logic-Reset state regardless of the current TAP controller state. Asserting power-on
reset or setting JCOMP to a value other than the value required to enable the JTAGC
block results in asynchronous entry into the reset state.
When in reset, the following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the
test logic and allowing normal operation of the on-chip system logic to continue
unhindered.
• The instruction register is loaded with the IDCODE instruction.
9.3.1.2 IEEE 1149.1–2001 defined test modes
The JTAGC block supports several IEEE 1149.1–2001 defined test modes. A test mode
is selected by loading the appropriate instruction into the instruction register when the
JTAGC is enabled. Supported test instructions include EXTEST, HIGHZ, CLAMP,
SAMPLE, and SAMPLE/PRELOAD.
Each instruction defines the set of data register(s) that may operate and interact with the
on-chip system logic when the instruction is current. Only one test data register path is
enabled to shift data between TDI and TDO for each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the
EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are active. The single-bit
bypass register shift stage is enabled for serial access between TDI and TDO when the
following instructions are active:
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Functional description
• BYPASS
• HIGHZ
• CLAMP
The functionality of each test mode is explained in more detail in JTAGC block
instructions.
9.3.1.3 Bypass mode
When no test operation is required, the BYPASS instruction can be loaded to place the
JTAGC block into bypass mode. When in bypass mode, the single-bit bypass shift
register is used to provide a minimum-length serial path to shift data between TDI and
TDO.
9.3.2 JTAGC reset configuration
When in reset, the TAP controller is forced into the Test-Logic-Reset state, thus disabling
the test logic and allowing normal operation of the on-chip system logic. In addition, the
instruction register is loaded with the IDCODE instruction.
9.3.3 IEEE 1149.1-2001 (JTAG) TAP
The JTAGC block uses the IEEE 1149.1-2001 TAP for accessing registers. This port can
be shared with other TAP controllers on the MCU. Ownership of the port is determined
by the value of the currently loaded instruction.
Data is shifted between TDI and TDO through the selected register starting with the least
significant bit, as illustrated in the following figure. This applies for the instruction
register, test data registers, and the bypass register.
MSB LSB
TDI
Selected register TDO
TCK
Figure 9-2. Shifting data through a register
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Chapter 9 JTAG Controller (JTAGC)
9.3.4 TAP controller state machine
The TAP controller is a synchronous state machine that interprets the sequence of logical
values on the TMS pin.
The following figure shows the machine's states. The value shown next to each state is
the value of the TMS signal sampled on the rising edge of the TCK signal. As the figure
shows, holding TMS at logic 1 when clocking TCK through a sufficient number of rising
edges also causes the state machine to enter the Test-Logic-Reset state.
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Functional description
TEST LOGIC
RESET
1
0
1 1 1
RUN-TEST/IDLE SELECT-DR-SCAN SELECT-IR-SCAN
0
0 0
1 1
CAPTURE-DR CAPTURE-IR
0 0
SHIFT-DR SHIFT-IR
0 0
1 1
1 1
EXIT1-DR EXIT1-IR
0 0
PAUSE-DR PAUSE-IR
0 0
1 1
0 0
EXIT2-DR EXIT2-IR
1 1
UPDATE-DR UPDATE-IR
1 1
0 0
The value shown adjacent to each state transition in this figure represents the value of TMS at the time
of a rising edge of TCK.
Figure 9-3. IEEE 1149.1-2001 TAP controller finite state machine
9.3.4.1 Enabling the TAP controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
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Chapter 9 JTAG Controller (JTAGC)
9.3.4.2 Selecting an IEEE 1149.1-2001 register
Access to the JTAGC data registers is achieved by loading the instruction register with
any of the JTAGC block instructions when the JTAGC is enabled. Instructions are shifted
in via the Select-IR-Scan path and loaded in the Update-IR state. At this point, all data
register access is performed via the Select-DR-Scan path.
The Select-DR-Scan path is used to read or write the register data by shifting in the data
(LSB first) during the Shift-DR state. When reading a register, the register value is loaded
into the IEEE 1149.1-2001 shifter during the Capture-DR state. When writing a register,
the value is loaded from the IEEE 1149.1-2001 shifter to the register during the Update-
DR state. When reading a register, there is no requirement to shift out the entire register
contents. Shifting may be terminated after the required number of bits have been
acquired.
9.3.5 JTAGC block instructions
The JTAGC block implements the IEEE 1149.1-2001 defined instructions listed in the
following table. This section gives an overview of each instruction. See the IEEE
1149.1-2001 standard for more details. All undefined opcodes are reserved.
Table 9-2. 4-bit JTAG instructions
Instruction Code[3:0] Instruction summary
IDCODE 0000 Selects device identification register for shift
SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and
preloading without disturbing functional operation
SAMPLE 0011 Selects boundary scan register for shifting and sampling
without disturbing functional operation
EXTEST 0100 Selects boundary scan register and applies preloaded values
to output pins.
NOTE: Execution of this instruction asserts functional reset.
HIGHZ 0101 Selects bypass register and tristates all output pins.
NOTE: Execution of this instruction asserts functional reset.
ABORT (Arm JTAG-DP Reserved) 1000 This instruction goes the Arm JTAG-DP controller. See the
Arm JTAG-DP documentation for more information.
DPACC (Arm JTAG-DP Reserved) 1010 This instruction goes the Arm JTAG-DP controller. See the
Arm JTAG-DP documentation for more information.
APACC (Arm JTAG-DP Reserved) 1011 This instruction goes the Arm JTAG-DP controller. See the
Arm JTAG-DP documentation for more information.
CLAMP 1101 Selects bypass register and applies preloaded values to
output pins.
Table continues on the next page...
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Functional description
Table 9-2. 4-bit JTAG instructions (continued)
Instruction Code[3:0] Instruction summary
NOTE: Execution of this instruction asserts functional reset.
IDCODE (Arm JTAG-DP Reserved) 1110 This instruction goes the Arm JTAG-DP controller. See the
Arm JTAG-DP documentation for more information.
BYPASS 1111 Selects bypass register for data operations
9.3.5.1 IDCODE instruction
IDCODE selects the 32-bit device identification register as the shift path between TDI
and TDO. This instruction allows interrogation of the MCU to determine its version
number and other part identification data. IDCODE is the instruction placed into the
instruction register when the JTAGC block is reset.
9.3.5.2 SAMPLE/PRELOAD instruction
The SAMPLE/PRELOAD instruction has two functions:
• The SAMPLE portion of the instruction obtains a sample of the system data and
control signals present at the MCU input pins, and just before the boundary scan
register cells at the output pins. This sampling occurs on the rising edge of TCK in
the Capture-DR state when the SAMPLE/PRELOAD instruction is active. The
sampled data is viewed by shifting it through the boundary scan register to the TDO
output during the Shift-DR state. Both the data capture and the shift operation are
transparent to system operation.
• The PRELOAD portion of the instruction initializes the boundary scan register cells
before selecting the EXTEST or CLAMP instructions to perform boundary scan
tests. This is achieved by shifting in initialization data to the boundary scan register
during the Shift-DR state. The initialization data is transferred to the parallel outputs
of the boundary scan register cells on the falling edge of TCK in the Update-DR
state. The data is applied to the external output pins by the EXTEST or CLAMP
instruction. System operation is not affected.
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Chapter 9 JTAG Controller (JTAGC)
9.3.5.3 SAMPLE instruction
The SAMPLE instruction obtains a sample of the system data and control signals present
at the MCU input pins, and just before the boundary scan register cells at the output pins.
This sampling occurs on the rising edge of TCK in the Capture-DR state when the
SAMPLE instruction is active. The sampled data is viewed by shifting it through the
boundary scan register to the TDO output during the Shift-DR state. There is no defined
action in the Update-DR state. Both the data capture and the shift operation are
transparent to system operation.
9.3.5.4 EXTEST external test instruction
EXTEST selects the boundary scan register as the shift path between TDI and TDO. It
allows testing of off-chip circuitry and board-level interconnections by driving preloaded
data contained in the boundary scan register onto the system output pins. Typically, the
preloaded data is loaded into the boundary scan register using the SAMPLE/PRELOAD
instruction before the selection of EXTEST. EXTEST asserts the internal system reset for
the MCU to force a predictable internal state when performing external boundary scan
operations.
9.3.5.5 TEST_LEAKAGE instruction
The TEST_LEAKAGE instruction forces the jtag_leakage output signal to high. It is
intended to tristate all output pad buffers and disable all of the part's pad input buffers
except JCOMP and TEST. The jtag_leakage signal is asserted at the falling edge of TCK
following the TAP controller state machine transition from the Update-IR state to the
Run-Test-Idle state. When asserted, the part disables TCK, TMS, and TDI inputs and
forces them to a logic 1. The TAP controller state machine remains in the Run-Test-Idle
state until the JCOMP input is set to a value other than the JTAGC enable encoding.
TEST_LEAKAGE also asserts the internal system reset for the MCU to force a
predictable internal state.
9.3.5.6 ENABLE_SOC_DATA1 instruction
The ENABLE_SOC_DATA1 instruction captures SoC data and selects the SOC_DATA
register for connection as the shift path between TDI and TDO.
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Functional description
9.3.5.7 HIGHZ instruction
HIGHZ selects the bypass register as the shift path between TDI and TDO. When
HIGHZ is active all output drivers are placed in an inactive drive state (for example, high
impedance). HIGHZ also asserts the internal system reset for the MCU to force a
predictable internal state.
9.3.5.8 CLAMP instruction
CLAMP allows the state of signals driven from MCU pins to be determined from the
boundary scan register when the bypass register is selected as the serial path between TDI
and TDO. CLAMP enhances test efficiency by reducing the overall shift path to a single
bit (the bypass register) when conducting an EXTEST type of instruction through the
boundary scan register. CLAMP also asserts the internal system reset for the MCU to
force a predictable internal state.
9.3.5.9 BYPASS instruction
BYPASS selects the bypass register, creating a single-bit shift register path between TDI
and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no
test operation of the MCU is required. This allows more rapid movement of test data to
and from other components on a board that are required to perform test functions. When
the BYPASS instruction is active the system logic operates normally.
9.3.6 Boundary scan
The boundary scan technique allows signals at component boundaries to be controlled
and observed through the shift-register stage associated with each pad. Each stage is part
of a larger boundary scan register cell, and cells for each pad are interconnected serially
to form a shift-register chain around the border of the design. The boundary scan register
consists of this shift-register chain, and is connected between TDI and TDO when the
EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register
chain contains a serial input and serial output, as well as clock and control signals.
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Chapter 9 JTAG Controller (JTAGC)
9.4 External signal description
The JTAGC consists of a set of signals that connect to off-chip development tools and
allow access to test support functions. The JTAGC signals are outlined in the following
table and described in the following sections.
Table 9-3. JTAG signal properties
Name I/O Function Reset state
TCK Input Test clock Weak pulldown
TDI Input Test data in Weak pullup
TDO Output Test data out High Z1
TMS Input Test mode select Weak pullup
JCOMP Input JTAG compliancy Weak pulldown
1. TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A weak pull may be
implemented at the TDO pad for use when JTAGC is inactive.
9.4.1 Test clock input (TCK)
Test Clock Input (TCK) is an input pin used to synchronize the test logic and control
register access through the TAP.
9.4.2 Test data input (TDI)
Test Data Input (TDI) is an input pin that receives serial test instructions and data. TDI is
sampled on the rising edge of TCK.
9.4.3 Test data output (TDO)
Test Data Output (TDO) is an output pin that transmits serial output for test instructions
and data. TDO is tristateable and is actively driven only in the Shift-IR and Shift-DR
states of the TAP controller state machine, which is described in TAP controller state
machine.
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Initialization/application information
9.4.4 Test mode select (TMS)
Test Mode Select (TMS) is an input pin used to sequence the IEEE 1149.1-2001 test
control state machine. TMS is sampled on the rising edge of TCK.
9.4.5 JCOMP JTAG compliancy
The JCOMP signal provides IEEE 1149.1-2001 compatibility and provides the ability to
share the TAP. The JTAGC TAP controller is enabled when JCOMP is set to the JTAGC
enable encoding—otherwise the JTAGC TAP controller remains in reset.
9.5 Initialization/application information
The test logic is a static logic design, and TCK can be stopped in either a high or low
state without loss of data. However, the system clock is not synchronized to TCK
internally. Any mixed operation using both the test logic and the system functional logic
requires external synchronization.
To initialize the JTAGC block and enable access to registers, the following sequence is
required:
1. Set the JCOMP signal to the JTAGC enable value, thereby enabling the JTAGC TAP
controller.
2. Load the appropriate instruction for the test or action to be performed.
9.6 Register description
This section provides a detailed description of the JTAGC block registers accessible
through the TAP interface, including data registers and the instruction register. Individual
bit-level descriptions and reset states of each register are included. These registers are not
memory-mapped and can only be accessed through the TAP.
9.6.1 Instruction register
The JTAGC block uses a 4-bit instruction register as shown in the following figure.
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Chapter 9 JTAG Controller (JTAGC)
The instruction register allows instructions to be loaded into the block to select the test to
be performed, or the test data register to be accessed, or both. Instructions are shifted in
through TDI when the TAP controller is in the Shift-IR state, and latched on the falling
edge of TCK in the Update-IR state. The latched instruction value can only be changed in
the Update-IR and Test-Logic-Reset TAP controller states.
Synchronous entry into the Test-Logic-Reset state results in the IDCODE instruction
being loaded on the falling edge of TCK. Asynchronous entry into the Test-Logic-Reset
state results in asynchronous loading of the IDCODE instruction. During the Capture-IR
TAP controller state, the instruction shift register is loaded with the value 0b1, making
this value the register's read value when the TAP controller is sequenced into the Shift-IR
state.
Figure 9-4. Instruction register
9.6.2 Bypass register
The bypass register is a single-bit shift register path selected for serial data transfer
between TDI and TDO when the following instructions are active:
• BYPASS
• HIGHZ
• CLAMP
After entry into the Capture-DR state, the single-bit shift register is set to a logic 0.
Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.
9.6.3 Device identification register
The device identification (JTAG ID) register, shown in the following figure, allows the
revision number, part number, manufacturer, and design center responsible for the design
of the part to be determined through the TAP.
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Register description
The device identification register is selected for serial data transfer between TDI and
TDO when the IDCODE instruction is active. Entry into the Capture-DR state when the
device identification register is selected loads the IDCODE into the shift register to be
shifted out on TDO in the Shift-DR state. No action occurs in the Update-DR state.
Figure 9-5. Device identification register
The following table describes the device identification register functions. The device
identification register values are described in the chip-specific JTAGC information.
Table 9-4. Device identification register field descriptions
Field Function
PRN Part revision number
Contains the revision number of the part.
DC Design center
Indicates the design center.
PIN Part identification number
Contains the part number of the device.
MIC Manufacturer identity code
Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID .
IDCODE ID IDCODE register ID
Identifies this register as the device identification register and not the bypass register. Always set to 1.
9.6.4 Boundary scan register
The boundary scan register is connected between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE/PRELOAD instructions are active. It is used to:
• Capture input pin data
• Force fixed values on output pins
• Select a logic value and direction for bidirectional pins
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Chapter 9 JTAG Controller (JTAGC)
Each bit of the boundary scan register represents a separate boundary scan register cell,
as described in the IEEE 1149.1-2001 standard and discussed in Boundary scan. The size
of the boundary scan register and bit ordering is device-dependent and can be found in
the device BSDL file.
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Register description
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Chapter 10
System Boot
10.1 Chip-specific Boot Information
This device has various peripherals supported by the ROM bootloader.
Table 10-1. ROM Bootloader Peripheral PinMux
Peripheral Instance Port (IO function) PAD Mode Note
LPUART 1 LPUART1_TX GPIO_AD_24 ALT0 Can be used for serial downloader
mode. Refer to Serial Boot (Serial
LPUART1_RX GPIO_AD_25 ALT0
Downloader) for more information.
LPSPI 1 LPSPI1_SCK GPIO_AD_28 ALT0 Serial NOR/EEPROM connected to
one of the LPSPI ports can be used as
LPSPI1_PCS0 GPIO_AD_29 ALT0
a recovery device. Refer to Recovery
LPSPI1_SDO GPIO_AD_30 ALT0 devices for more information.
LPSPI1_SDI GPIO_AD_31 ALT0 NOTE: Recovery device boot is
2 LPSPI2_SCK GPIO_SD_B2_07 ALT6 disabled by default. The
RECOVERY_BOOT_EN fuse
LPSPI2_PCS0 GPIO_SD_B2_08 ALT6
must be blown in order to
LPSPI2_SDO GPIO_SD_B2_09 ALT6 enable this option. The SPI
LPSPI2_SDI GPIO_SD_B2_10 ALT6 INSTANCE fuse selects the
SPI instance.
3 LPSPI3_SCK GPIO_DISP_B1_04 ALT9
LPSPI3_PCS0 GPIO_DISP_B1_07 ALT9
LPSPI3_SDO GPIO_DISP_B1_06 ALT9
LPSPI3_SDI GPIO_DISP_B1_05 ALT9
4 LPSPI4_SCK GPIO_DISP_B2_12 ALT9
LPSPI4_PCS0 GPIO_DISP_B2_15 ALT9
LPSPI4_SDO GPIO_DISP_B2_14 ALT9
LPSPI4_SDI GPIO_DISP_B2_13 ALT9
SEMC NAND N/A SEMC_DATA00 GPIO_EMC_B1_00 ALT0 Parallel NAND flash connected to the
SEMC_DATA01 GPIO_EMC_B1_01 SEMC is a primary boot option. Refer
ALT0
to Parallel NAND flash Boot over
SEMC_DATA02 GPIO_EMC_B1_02 ALT0 SEMC for more information.
SEMC_DATA03 GPIO_EMC_B1_03 ALT0 NOTE: By default ROM reads from
SEMC_DATA04 GPIO_EMC_B1_04 ALT0 the 8-bit NAND device via the
bold pins.
SEMC_DATA05 GPIO_EMC_B1_05 ALT0
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Chip-specific Boot Information
Table 10-1. ROM Bootloader Peripheral PinMux (continued)
Peripheral Instance Port (IO function) PAD Mode Note
SEMC_DATA06 GPIO_EMC_B1_06 ALT0 The "I/O Port Size" fuse must
be blown to enable 16-bit
SEMC_DATA07 GPIO_EMC_B1_07 ALT0 NAND device support.
SEMC_DATA08 GPIO_EMC_B1_30 ALT0
The PCS_Selection fuse must
SEMC_DATA09 GPIO_EMC_B1_31 ALT0 be blown to select other PCS
SEMC_DATA10 GPIO_EMC_B1_32 ALT0 configurations.
SEMC_DATA11 GPIO_EMC_B1_33 ALT0
SEMC_DATA12 GPIO_EMC_B1_34 ALT0
SEMC_DATA13 GPIO_EMC_B1_35 ALT0
SEMC_DATA14 GPIO_EMC_B1_36 ALT0
SEMC_DATA15 GPIO_EMC_B1_37 ALT0
SEMC_ADDR09 GPIO_EMC_B1_18 ALT0
SEMC_ADDR11 GPIO_EMC_B1_19 ALT0
SEMC_ADDR12 GPIO_EMC_B1_20 ALT0
SEMC_BA1 GPIO_EMC_B1_22 ALT0
SEMC_CSX0 GPIO_EMC_B1_41 ALT0
SEMC_CSX1 GPIO_AD_26 ALT2
SEMC_CSX2 GPIO_AD_27 ALT2
SEMC_CSX3 GPIO_AD_28 ALT2
uSDHC 1 USDHC1_CD_B GPIO_AD_32 ALT4 eMMC/MMC or SD/eSD connected to
one of the USDHC ports is a primary
USDHC1_WP GPIO_AD_33 ALT4
boot option. Refer to Expansion device
USDHC1_VSELECT GPIO_AD_34 ALT4 for more information on USDHC boot.
USDHC1_RESET_B GPIO_AD_35 ALT4 For uSDHC2, the data lines are
USDHC1_CMD GPIO_SD_B1_00 ALT0 configured based on the bus width
selection.
USDHC1_CLK GPIO_SD_B1_01 ALT0
USDHC1_DATA0 GPIO_SD_B1_02 ALT0
USDHC1_DATA1 GPIO_SD_B1_03 ALT0
USDHC1_DATA2 GPIO_SD_B1_04 ALT0
USDHC1_DATA3 GPIO_SD_B1_05 ALT0
2 USDHC2_CD_B GPIO_AD_26 ALT11
USDHC2_WP GPIO_AD_27 ALT11
USDHC2_VSELECT GPIO_AD_28 ALT11
USDHC2_DATA3 GPIO_SD_B2_00 ALT0
USDHC2_DATA2 GPIO_SD_B2_01 ALT0
USDHC2_DATA1 GPIO_SD_B2_02 ALT0
USDHC2_DATA0 GPIO_SD_B2_03 ALT0
USDHC2_CLK GPIO_SD_B2_04 ALT0
USDHC2_CMD GPIO_SD_B2_05 ALT0
USDHC2_RESET_B GPIO_SD_B2_06 ALT0
USDHC2_DATA4 GPIO_SD_B2_08 ALT0
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Chapter 10 System Boot
Table 10-1. ROM Bootloader Peripheral PinMux (continued)
Peripheral Instance Port (IO function) PAD Mode Note
USDHC2_DATA5 GPIO_SD_B2_09 ALT0
USDHC2_DATA6 GPIO_SD_B2_10 ALT0
USDHC2_DATA7 GPIO_SD_B2_11 ALT0
FlexSPI1 NOR/ 1 FLEXSPI1_A_DQS GPIO_SD_B2_05 ALT1 This pin group is used for FlexSPI
NAND NOR/NAND boot if:
(Primary DQS pin)
(Primary Pin 1. The FLEXSPI_INSTANCE fuse/
FLEXSPI1_A_DQS GPIO_EMC_B2_18 ALT6
Group) boot pin is 0.
(Secondary DQS 2. The
Pin) FLEXSPI_PIN_GROUP_SEL
FLEXSPI1_A_SS0_ GPIO_SD_B2_06 ALT1 fuse bit is 0.
B
The fuse FLEXSPI_DQS_PIN_SEL
FLEXSPI1_A_SS1_B GPIO_SD_B1_02 ALT9 determines the DQS pin option.
FLEXSPI1_A_SCLK GPIO_SD_B2_07 ALT1 By default, ROM accesses the QSPI
FLEXSPI1_A_DATA GPIO_SD_B2_08 ALT1 NOR/NAND via the bold pins. This
0 default behavior can be overridden by
setting the
FLEXSPI1_A_DATA GPIO_SD_B2_09 ALT1
FLASH_CONNECTION_SEL fuse
1
field.
FLEXSPI1_A_DATA GPIO_SD_B2_10 ALT1
If QSPI, Hyperflash, or Octal memory
2
attached to FlexSPI is a primary boot
FLEXSPI1_A_DATA GPIO_SD_B2_11 ALT1 option. Refer to Serial NOR Flash Boot
3 via FlexSPI for more information. The
FLEXSPI1_B_DATA GPIO_SD_B2_00 ALT1 ROM will read the 512-byte FlexSPI
3 NOR configuration parameters
described in FlexSPI Serial NOR Flash
fLEXSPI1_B_DATA2 GPIO_SD_B2_01 ALT1 Boot Operation.
FLEXSPI1_B_DATA GPIO_SD_B2_02 ALT1 If Serial NAND memory attached to
1 FlexSPI is a primary boot option. Refer
FLEXSPI1_B_DATA GPIO_SD_B2_03 ALT1 to Serial NAND Flash Boot over
0 FlexSPI for more information.
FLEXSPI1_B_SCLK GPIO_SD_B2_04 ALT1
FLEXSPI1_B_DQS GPIO_SD_B1_05 ALT8
FLEXSPI1_B_SS0_B GPIO_SD_B1_04 ALT8
FLEXSPI1_B_SS1_B GPIO_SD_B1_03 ALT9
FlexSPI1 NOR/ 1 FLEXSPI1_A_DQS GPIO_AD_17 ALT3 This pin group is used for FlexSPI
NAND FLEXSPI1_A_SS0_ GPIO_AD_18 NOR/NAND boot if:
ALT3
(Secondary Pin B 1. FLEXSPI_INSTANCE fuse/boot
Group) FLEXSPI1_A_SCLK GPIO_AD_19 ALT3 pin is 0.
2. FLEXSPI_PIN_GROUP_SEL
FLEXSPI1_A_DATA GPIO_AD_20 ALT3 fuse bit is 1.
0
FLEXSPI1_A_DATA GPIO_AD_21 ALT3 NOTE: 1. Only PORTA is
1 supported via the 2nd
Pin group.
FLEXSPI1_A_DATA GPIO_AD_22 ALT3 2. The Maximum Flash
2 frequency supported on
FLEXSPI1_A_DATA GPIO_AD_23 ALT3 this port is 100MHz.
3
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Chip-specific Boot Information
Table 10-1. ROM Bootloader Peripheral PinMux (continued)
Peripheral Instance Port (IO function) PAD Mode Note
FLEXSPI1_B_SCLK GPIO_AD_16 ALT3 By default, ROM accesses the QSPI
NOR/NAND via the bold pins. This
FLEXSPI1_B_DATA GPIO_AD_15 ALT3
default behavior can be overridden by
0
setting the
FLEXSPI1_B_DATA GPIO_AD_14 ALT3 FLASH_CONNECTION_SEL fuse
1 field.
FLEXSPI1_B_DATA GPIO_AD_13 ALT3 If QSPI, Hyperflash, or Octal memory
2 attached to FlexSPI is a primary boot
FLEXSPI1_B_DATA GPIO_AD_12 ALT3 option. Refer to Serial NOR Flash Boot
3 via FlexSPI for more information. The
ROM will read the 512-byte FlexSPI
NOR configuration parameters
described in FlexSPI Serial NOR Flash
Boot Operation.
If Serial NAND memory attached to
FlexSPI is a primary boot option. Refer
to Serial NAND Flash Boot over
FlexSPI for more information.
FlexSPI2 NOR/ 2 FLEXSPI2_B_DATA GPIO_EMC_B1_41 ALT4 This pin group is used for FlexSPI
NAND 7 NOR/NAND boot if:
(Primary Pin FLEXSPI2_B_DATA GPIO_EMC_B2_00 ALT4 1. FLEXSPI_INSTANCE fuse/boot
Group) 6 pin is 1.
FLEXSPI2_B_DATA GPIO_EMC_B2_01 ALT4 2. FLEXSPI_PIN_GROUP_SEL
5 fuse bit is 0.
FLEXSPI2_B_DATA GPIO_EMC_B2_02 ALT4 By default, ROM accesses the QSPI
4 NOR/NAND via the bold pins. This
FLEXSPI2_B_DATA GPIO_EMC_B2_03 ALT4 default behavior can be overridden by
3 setting the
FLASH_CONNECTION_SEL fuse
FLEXSPI2_B_DATA GPIO_EMC_B2_04 ALT4 field.
2
If QSPI, Hyperflash, or Octal memory
FLEXSPI2_B_DATA GPIO_EMC_B2_05 ALT4
attached to FlexSPI is a primary boot
1
option. Refer to Serial NOR Flash Boot
FLEXSPI2_B_DATA GPIO_EMC_B2_06 ALT4 via FlexSPI for more information. The
0 ROM will read the 512-byte FlexSPI
FLEXSPI2_B_DQS GPIO_EMC_B2_07 ALT4 NOR configuration parameters
described in FlexSPI Serial NOR Flash
FLEXSPI2_B_SS0_B GPIO_EMC_B2_08 ALT4 Boot Operation.
FLEXSPI2_B_SCLK GPIO_EMC_B2_09 ALT4 If Serial NAND memory attached to
FLEXSPI2_A_SCLK GPIO_EMC_B2_10 ALT4 FlexSPI is a primary boot option. Refer
to Serial NAND Flash Boot over
FLEXSPI2_A_SS0_ GPIO_EMC_B2_11 ALT4
FlexSPI for more information.
B
FLEXSPI2_A_DQS GPIO_EMC_B2_12 ALT4
FLEXSPI2_A_DATA GPIO_EMC_B2_13 ALT4
0
FLEXSPI2_A_DATA GPIO_EMC_B2_14 ALT4
1
FLEXSPI2_A_DATA GPIO_EMC_B2_15 ALT4
2
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Chapter 10 System Boot
Table 10-1. ROM Bootloader Peripheral PinMux (continued)
Peripheral Instance Port (IO function) PAD Mode Note
FLEXSPI2_A_DATA GPIO_EMC_B2_16 ALT4
3
FLEXSPI2_A_DATA GPIO_EMC_B2_17 ALT4
4
FLEXSPI2_A_DATA GPIO_EMC_B2_18 ALT4
5
FLEXSPI2_A_DATA GPIO_EMC_B2_19 ALT4
6
FLEXSPI2_A_DATA GPIO_EMC_B2_20 ALT4
7
FlexSPI2 NOR/ 2 FLEXSPI2_A_SS0_ GPIO_SD_B1_00 ALT6 This pin group is used for FlexSPI
NAND B NOR/NAND boot if:
(Secondary Pin FLEXSPI2_A_SCLK GPIO_SD_B1_01 ALT6 1. FLEXSPI_INSTANCE fuse/boot
Group) FLEXSPI2_A_DATA GPIO_SD_B1_02 ALT6 pin is 1.
0 2. FLEXSPI_PIN_GROUP_SEL
fuse bit is 1.
FLEXSPI2_A_DATA GPIO_SD_B1_03 ALT6
1 NOTE: This pin group does not offer
FLEXSPI2_A_DATA GPIO_SD_B1_04 ALT6 a DQS pad, so only low-speed
2 read is supported when this
pin group is chosen.
FLEXSPI2_A_DATA GPIO_SD_B1_05 ALT6
3 By default, ROM accesses the QSPI
NOR/NAND via the bold pins. This
default behavior can be overridden by
setting the
FLASH_CONNECTION_SEL fuse
field.
If QSPI, Hyperflash, or Octal memory
attached to FlexSPI is a primary boot
option. Refer to Serial NOR Flash Boot
via FlexSPI for more information. The
ROM will read the 512-byte FlexSPI
NOR configuration parameters
described in FlexSPI Serial NOR Flash
Boot Operation.
If Serial NAND memory attached to
FlexSPI is a primary boot option. Refer
to Serial NAND Flash Boot over
FlexSPI for more information.
FlexSPI RESET - GPIO4_IO03 GPIO_SD_B1_00 ALT5 The FlexSPI RESET pin is used as the
dedicated RESET pin to restore the
(Primary RESET Pin)
Serial NOR/NAND device connected to
GPIO_MUX2_IO08 GPIO_EMC_B1_40 ALT5 the FlexSPI interface.
(Secondary RESET The FlexSPI RESET pin is enabled if
Pin) the RESET_PIN_EN fuse bit is blown.
The pin option is selected by
RESET_PIN_SEL fuse bit.
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Chip-specific Boot Information
NOTE
1. The boot ROM always tries to access Serial NOR/NAND
flash using SS0 as the chip selection signal, as well as
PORTA by default. It can access the Serial NOR/NAND
device via CS0 and PORTB, if the
FLASH_CONNECTION_SEL fuse is blown with a value
of 2.
2. For Octal NOR/NAND, connected to FlexSPI1, the upper
4-bit pads must connect to the PORTB_DATA pads.
3. For Octal NOR/NAND, connected to FlexSPI2, the upper
4-bit pads must connect to the same PORT with the upper
4-bit pads.
4. PORTB_SCLK serves as PORTA_SCLK_B for the 1.8V
HyperFLASH/HyperRAM.
5. A_SS1/B_SS1 is not supported by default.
6. The FlexSPI RESET pin is not used by default. This feature
can be enabled by the RESET_PIN_EN and
RESET_PIN_SEL fuses.
10.1.1 ROM settings and considerations for user applications
and debugging
The boot ROM configures the clocks of the boot core, bus, and other required controllers
to a high frequency of clock roots during boot for high-performance consideration. When
the user application needs to re-configure the clock roots, PLLs or the PFDs, the SoC
may crash if the clocks are not handled properly. To avoid such potential issues, below
are some suggestions:
• Switch the root clock of the boot core, bus, and other affected controllers to a fixed
clock root. before configuring the clocks.
• Configure the clock of each peripheral explicitly instead of relying on the default
settings listed in the Reference Manual.
The following tables provide the clock frequency configurations for Cortex-M7/Cortex-
M4 core boot.
Table 10-2. Normal Frequency Clock Configurations for Cortex-M7 Core Boot
BOOT_FREQ (0x9A0[3]) LPB_BOOT (0x9A0[5:4]) Core Clock Frequency (MHz)
0 0 400
1 200
2 100
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Chapter 10 System Boot
Table 10-2. Normal Frequency Clock Configurations for Cortex-M7 Core Boot (continued)
BOOT_FREQ (0x9A0[3]) LPB_BOOT (0x9A0[5:4]) Core Clock Frequency (MHz)
3 50
1 0 696
1 348
2 174
3 87
Table 10-3. Normal Frequency Clock Configurations for Cortex-M4 Core Boot
BOOT_FREQ (0x9A0[3]) LPB_BOOT (0x9A0[5:4]) Core Clock Frequency (MHz)
0 0 200
1 100
2 50
3 25
1 0 240
1 120
2 60
3 30
The following table provides the list of registers that are updated by ROM during ROM
execution.
Table 10-4. Registers modified by ROM
Module Register Value Note
CCM CLOCK_ROOT0_CONTROL The value varies at CM7 clock root
different frequencies
CLOCK_ROOT1_CONTROL CM4 clock root
CLOCK_ROOT2_CONTROL Bus clock root
CLOCK_ROOT3_CONTROL Bus LPSR clock root
CLOCK_ROOT20_CONTROL FlexSPI1 clock root
CLOCK_ROOT25_CONTROL LPUART1 clock root
CLOCK_GROUP0_CONTROL 0x00020002 FLEXRAM clock group
PLL PLL_480_CTRL 0x2020201B -
PLL_480_PFD 0x1820110D
PLL_528_CTRL 0x20802008
PLL_528_PFD 0x6058505B
OSC OSC_400M_CTRL1 0x00000000 -
OSC_400M_CTRL2 0x00000001
OSC_24M_CTRL 0x40000014
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Chip-specific Boot Information
Table 10-4. Registers modified by ROM (continued)
Module Register Value Note
USB-PHY USBPHYx_CTRL 0x2818C000 ROM sets the USB-PHY
registers if the device runs
USBPHYx_PLL_SIC 0x80F03040
under serial downloader
USBPHYx_PWD 0x00000000 mode.
The registers in the modules listed below may be updated if they are in use for specific
boot modes. ROM does not restore the registers in these modules after they are updated.
The user application should not rely on the default values of the registers in these
modules.
• FlexSPI1 - if the device boots from memory connected to FlexSPI1.
• FlexSPI2 - if the device boots from memory connected to FlexSPI2.
• uSDHC1 - if the device boots from memory connected to uSDHC1.
• uSDHC2 - if the device boots from memory connected to uSDHC2.
• SEMC - if the device boots from memory connected to SEMC.
• MECC - if the MECC_ENABLE Fuse bit is blown.
• FLEXRAM - if the FLEXRAMECC_ENABLE Fuse bit is blown.
• CAAM - HAB library uses some features in CAAM, and they cannot be restored
before leaving ROM.
• SNVS - if the SNVS state was changed by ROM in HAB closed mode.
• ANADIG_OSC - The OSC related configurations are not restored.
• ANADIG_MISC - The AI interface related settings are not restored.
• ANADIG_PMU - The ANADIG PMU related settings are not restored.
• CCM - The clock settings for the modules, such as the CM7 core, are not restored.
• ANADIG_PLL - The ANADIG_PLL related settings are not restored (e.g.
PLL_480_CTRL, PLL_480_PFD, PLL_528_CTRL, PLL_528_PFD).
• SCB->SHCSR - The UsageFault, MemManageFault, and BusFault enabling flags are
not cleared.
• IOMUXC - cannot fully be restored because some settings are still in use before
leaving ROM.
• IOMUXC_GPR - used in the IEE related test cases, cannot be cleared before leaving
ROM.
• WDOG3/WDOG4 - disabled by ROM.
• CDOG – CDOG was enabled and used as the hardware secure counter during ROM
execution, and ROM partially restores before leaving ROM due to the IP restriction.
• SRC GPR - ROM occupies SRC GPR0-GPR4 and GPR9.
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Chapter 10 System Boot
10.1.2 Debug behavior
The debug port is disabled on the SoC out of reset. ROM enables the debug port in either
of the following conditions:
• ROM is ready to jump to a valid user application.
• A debug request is received from the debug tool in the serial downloader mode or
before finishing the image validity check.
10.1.3 Manufacturing protection
The Manufacturing protection (MP) key pair is generated by HAB. ROM will request
generation of the (MP) key pair.
10.2 Overview
The boot process begins at any Reset where the hardware reset logic forces the Arm core
(boot core is determined by BT_CORE_SEL fuse setting) to begin execution starting
from the on-chip boot ROM.
If the BT_CORE_SEL fuse is blown, ROM will be executing from the M4 core instead
of the M7 core. Booting from the M4 core can be slower due to the slower ROM
execution time with the M4, especially if using HAB.
The boot ROM code uses the state of the internal register BOOT_MODE[1:0] as well as
the state of various eFuses and/or GPIO settings to determine the boot flow behavior of
the device.
The main features of the ROM include:
• Support for booting from various boot devices
• Serial downloader support (USB-HID and UART)
• Device Configuration Data (DCD)
• Digital signature based High-Assurance Boot (HAB)
• eXternal Memory Configuration Data (XMCD)
• Encrypted execute-in-place (XIP) on Serial NOR via FlexSPI interface powered by:
• Inline Encryption Engine (IEE)
• On-the-Fly AES Decryption (OTFAD)
The boot ROM supports boot device as below:
• Serial NOR Flash via FlexSPI
• Serial NAND Flash via FlexSPI
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Overview
• SLC RAWNAND Flash via SEMC
• SD/MMC via uSDHC
• SPI NOR/EEPROM via LPSPI
The boot ROM uses the state of the BOOT_MODE and eFuses to determine the boot
device. For development purposes, the eFuses used to determine the boot device may be
overridden using the GPIO pin inputs.
The boot ROM code also allows the downloading of programs to be run on the device.
An example is a provisioning program that can make further use of the serial connection
to provide a boot device with a new image. Typically, the provisioning program is
downloaded to the internal RAM and allows to program the boot devices, such as the
FlexSPI NOR flash. The ROM serial downloader uses a high-speed USB in a non-stream
mode connection.
The Device Configuration Data (DCD) feature allows the boot ROM code to obtain the
SOC configuration data from an external program image residing on the boot device. As
an example, the DCD can be used to program the SDRAM controller for optimal settings
improving the boot performance. The DCD is restricted to the memory areas and
peripheral addresses that are considered essential for the boot purposes (see Write data
command).
The External Memory Configuration Data (XMCD) allows the boot ROM code to
configure the SDRAM connected to the SEMC controller, or the HyperRAM/APMemory
PSRAM via the FlexSPI controller from an external program image residing on the boot
device. The XMCD aims to simplify the external RAM enablement, and it is a
replacement for the legacy Device Configuration Data (DCD).
A key feature of the boot ROM is the ability to perform a secure boot, also known as a
High-Assurance Boot (HAB). This is supported by the HAB security library which is a
subcomponent of the ROM code. The HAB uses a combination of hardware and software
together with the Public Key Infrastructure (PKI) protocol to protect the system from
executing unauthorized program images. Before the HAB allows the user image to
execute, the image must be signed. The signing process is done during the image build
process by the private key holder and the signatures are then included as a part of the
final program image. If configured to do so, the ROM verifies the signatures using the
public keys included in the program image. In addition to supporting the digital signature
verification to authenticate the program images, encrypted boot is also supported. The
encrypted boot can be used to prevent the cloning of the program image directly off the
boot device. A secure boot with HAB can be performed on all boot devices supported on
the chip in addition to the serial downloader. The HAB library in the boot ROM also
provides the API functions, allowing the additional boot chain components (e.g.,
bootloader, application) to extend the secure boot chain. The out-of-fab setting for the
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SEC_CONFIG is the open configuration, in which the ROM/HAB performs the image
authentication, but all authentication errors are ignored and the image is still allowed to
execute.
10.3 Boot modes
During boot, the ROM's behavior is defined by the boot mode pin settings, as described
in Boot mode pin settings.
10.3.1 Boot mode pin settings
The device has four boot modes (one is reserved for NXP use). The boot mode is selected
based on the binary value stored in the internal BOOT_MODE register.
The BOOT_MODE register is initialized by sampling the BOOT_MODE0 and
BOOT_MODE1 inputs on the rising edge of the POR_B. After these inputs are sampled,
their subsequent state does not affect the contents of the internal BOOT_MODE register.
The state of the internal BOOT_MODE register may be read from the BMOD[1:0] field
of the SRC Boot Mode Register (SRC_SBMR2). The available boot modes are: Boot
From Fuses, Serial Downloader, and Internal Boot. See this table for settings:
Table 10-5. Boot MODE pin settings
BOOT_MODE[1:0] Boot Type
00 Boot From Fuses
01 Serial Downloader
10 Internal Boot
11 Reserved
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Boot modes
10.3.2 High-level boot sequence
The figure found here show the high-level boot ROM code flow.
Reset
Bump ROM clock to
high frequencey
Check Boot Mode
Master boot (using fuses and/or
GPIOs)
Load & Authenticate
image
(FlexSPI
NOR/NAND/raw Serial boot
NAND/SD/eMMC) No
Load and authenticate
Recovery boot
Success? No No image via Serial Interface Success?
enabled?
(UART / USB-HID)
Yes
Yes
Execute Image Load & Authenticate Yes
image
(SPI EEPROM/NOR)
No Execute Image
No Manufacturing
Success?
Boot Enabled?
Yes Yes
Load & Authenticate
Execute Image image
(SD Card)
Success?
Yes
Execute Image
Figure 10-1. Boot flow
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10.3.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)
A value of 00b in the BOOT_MODE[1:0] register selects the Boot From Fuses mode.
This mode is similar to the Internal Boot mode described in Internal Boot mode
(BOOT_MODE[1:0] = 10b) with one difference. In this mode, the override from the
GPIO boot pins are ignored. The boot ROM code uses the boot eFuse settings only. This
mode also supports a secure boot using HAB.
If set to Boot From Fuses, the boot flow is controlled by the BT_FUSE_SEL eFuse value.
If BT_FUSE_SEL = 0, indicating that the boot device (for example, flash) was not
programmed yet, the boot flow jumps directly to the Serial Downloader. If
BT_FUSE_SEL = 1, the normal boot flow is followed, where the ROM attempts to boot
from the selected boot device.
The first time a board is used, the default eFuses may be configured incorrectly for the
hardware on the platform. In such case, the Boot ROM code may try to boot from a
device that does not exist. This may cause an electrical/logic violation on some pads.
Using the Boot From Fuses mode addresses this problem.
Setting the BT_FUSE_SEL=0 forces the ROM code to jump directly to the Serial
Downloader. This allows a bootloader to be downloaded which can then provision the
boot device with a program image and blow the BT_FUSE_SEL and the other boot
configuration eFuses. After the reset, the boot ROM code determines that the
BT_FUSE_SEL is blown (BT_FUSE_SEL = 1) and the ROM code performs an internal
boot according to the new eFUSE settings. This allows the user to set
BOOT_MODE[1:0]=00b on a production device and burn the fuses on the same device
(by forcing the entry to the Serial Downloader), without changing the value of the
BOOT_MODE[1:0] or the pullups/pulldowns on the BOOT_MODE pins.
10.3.4 Serial Downloader (BOOT_MODE[1:0] = 01b)
The Serial Downloader provides a means to download a Program Image to the on-chip
RAM over USB or UART serial connection. In this mode, typically a host PC can
communicate to the ROM bootloader using serial download protocol. Serial downloader
and the protocol are discussed in Serial Downloader.
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Boot modes
10.3.5 Internal Boot mode (BOOT_MODE[1:0] = 10b)
A value of 10b in the BOOT_MODE[1:0] register selects the Internal Boot mode. In this
mode, the processor continues to execute the boot code from the internal boot ROM.
The boot code performs the hardware initialization, loads the program image from the
chosen boot device, performs the image validation using the HAB library (see Boot
security settings), and then jumps to an address derived from the program image. If an
error occurs during the internal boot, the boot code jumps to the Serial Downloader (see
Serial Downloader (BOOT_MODE[1:0] = 01b)). A secure boot using the HAB is
possible in all the three boot modes.
When set to the Internal Boot, the boot flow may be controlled by a combination of eFuse
settings with an option of overriding the fuse settings using the General Purpose I/O
(GPIO) pins. The GPIO Boot Select FUSE (BT_FUSE_SEL) determines whether the
ROM uses the GPIO pins for a selected number of configuration parameters or eFuses in
this mode.
• If BT_FUSE_SEL = 1, all boot options are controlled by the eFuses described in
Boot eFuse descriptions.
• If BT_FUSE_SEL = 0, the specific boot configuration parameters may be set using
the GPIO pins rather than eFuses. The fuses that can be overridden when in this
mode are indicated in the GPIO column of Boot eFuse descriptions. GPIO boot
overrides provides the details of the GPIO pins.
The use of the GPIO overrides is intended for development since these pads are used for
other purposes in the deployed products. NXP recommends controlling the boot
configuration by the eFuses in the deployed products and reserving the use of the GPIO
mode for the development and testing purposes only.
10.3.6 Boot security settings
The internal boot modes use one of three security configurations.
• Closed: This level is intended for use with shipping-secure products. All HAB
functions are executed and the security hardware is initialized (the Security
Controller or SNVS enters the Secure state), the DCD is processed if present, and the
program image is authenticated by the HAB before its execution. All detected errors
are logged, and the boot flow is aborted with the control being passed to the serial
downloader. At this level, the execution does not leave the internal ROM unless the
target executable image is authenticated.
• Open: This level is intended for use in non-secure products or during the
development phases of a secure product. All HAB functions are executed in the same
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way as for a closed system. The security hardware is initialized (except for the SNVS
which is left in the Non-Secure state), the DCD is processed if present, and the
program image is authenticated by the HAB before its execution. All detected errors
are logged, but have no influence on the boot flow which continues as if the errors
did not occur. This configuration is useful for a secure product development because
the program image runs even if the authentication data is missing or incorrect, and
the error log can be examined to determine the cause of the authentication failure.
• Field Return: This level is intended for the parts returned from the shipped products.
10.4 Device configuration
This section describes the external inputs that control the behavior of the Boot ROM
code.
This includes the boot device selection (FlexSPI NOR FlexSPI NAND,SD, MMC, and so
on), boot device configuration (SD bus width, speed, and so on), and other. In general,
the source for this configuration comes from the eFuses embedded inside the chip.
However, certain configuration parameters can be sourced from the GPIO pins, allowing
further flexibility during the development process.
10.4.1 Boot eFuse descriptions
This table is a comprehensive list of the configuration parameters that the ROM uses.
Table 10-6. Boot eFuse descriptions
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
BT_FUSE_SEL OEM In the Internal Boot mode NA 0 If BOOT_MODE[1:0] = 10b:
BOOT_MODE[1:0] = 10,
• 0 - The bits of the SBMR are
the BT_FUSE_SEL fuse
overridden by the GPIO pins.
determines whether the
boot settings indicated by a • 1 - The specific bits of the SBMR are
Yes in the GPIO column are controlled by the eFuse settings.
controlled by the GPIO pins
or the eFuse settings in the If BOOT_MODE[1:0] = 00b:
On-Chip OTP Controller • 0—The BOOT configuration eFuses
(OCOTP). are not programmed yet. The boot
In the Boot From Fuse flow jumps to the serial downloader.
mode BOOT_MODE[1:0] =
00, the BT_FUSE_SEL fuse • 1—The BOOT configuration eFuses
indicates whether the bit are programmed. The regular boot
configuration eFuses are flow is performed.
programmed.
Table continues on the next page...
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Table 10-6. Boot eFuse descriptions (continued)
Fuse Config Definition GPIO1 Shipped Settings2
uratio value
n
UNIQUE_ID[63:0] NXP Device Unique ID, 64-bit NA Unique Settings vary—used by HAB
UID ID
BOOT_CFG1[7:0] OEM Boot configuration 1 Yes 0 Specific to the selected boot mode
BOOT_CFG2[3:0] OEM Boot configuration 2 Yes 0 Specific to the selected boot mode
LPB_BOOT OEM Low-Power Boot No 0 Divide (Core / Bus) based on Boot
frequencies:
00 - Div by 1
01 - Div by 2
10 - Div by 4
11 - Div by 8
WDOG_ENABLE OEM Watchdog reset counter No 0 WDOG1 enable:
enable
0—The watchdog reset counter is disabled
during the serial downloader.
1—The watchdog reset counter is enabled
during the serial downloader.
PAD_SETTINGS OEM Override values for the No 0 Override these IO PAD settings:
SD/MMC and NAND boot
• PAD_SETTINGS[0]—Slew Rate
modes
• PAD_SETTINGS[3:1]—Drive
Strength
• PAD_SETTINGS[5:4]—Speed
Settings
• PAD_SETTINGS[6]— Pull Up / Down
Configuration
• PAD_SETTINGS[7]—Hysteresis
Enable
1. This setting is overridden by the GPIO settings when the BT_FUSE_SEL fuse is intact. See GPIO Boot Overrides for the
corresponding GPIO pin.
2. 0 = intact fuse and 1= blown fuse
10.4.2 GPIO boot overrides
This table provides a list of the GPIO boot overrides:
Table 10-7. GPIO Boot Overrides
Package Pin Direction on reset eFuse
GPIO_LPSR_02/BOOT_MODE[0] Input Boot Mode selection
GPIO_LPSR_03/BOOT_MODE[1] Input
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Table 10-7. GPIO Boot Overrides (continued)
Package Pin Direction on reset eFuse
GPIO_DISP_B1_06 Input BOOT_CFG1[0]
GPIO_DISP_B1_07 Input BOOT_CFG1[1]
GPIO_DISP_B1_08 Input BOOT_CFG1[2]
GPIO_DISP_B1_09 Input BOOT_CFG1[3]
GPIO_DISP_B1_10 Input BOOT_CFG1[4]
GPIO_DISP_B1_11 Input BOOT_CFG1[5]
GPIO_DISP_B2_00 Input BOOT_CFG1[6]
GPIO_DISP_B2_01 Input BOOT_CFG1[7]
GPIO_DISP_B2_02 Input BOOT_CFG2[0]
GPIO_DISP_B2_03 Input BOOT_CFG2[1]
GPIO_DISP_B2_04 Input BOOT_CFG2[2]
GPIO_DISP_B2_05 Input BOOT_CFG2[3]
NOTE
Refer to the Fusemap chapter for more information on fuses
mapped to the GPIO pins.
The input pins above are sampled at boot, and can be used to override the corresponding
eFuse values, depending on the setting of the BT_FUSE_SEL fuse.
10.4.3 Device Configuration Data (DCD)
The DCD is the configuration information contained in the program image (external to
the ROM) that the ROM interprets to configure various on-chip peripherals. See Device
Configuration Data (DCD) for more details on DCD.
10.5 Device initialization
This section describes the details of the ROM and provides the initialization details.
This includes details on:
• The ROM memory map
• The RAM memory map
• On-chip blocks that the ROM must use or change the POR register default values
• Clock initialization
• Enabling the L1 I/D cache
• Exception handling and interrupt handling
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Device initialization
10.5.1 Internal ROM/RAM memory map
These figures show the internal ROM and RAM memory map:
0x0023_FFFF 0x2024_BFFF
ROM Code OCRAM1
(vector table, (BSS, RW,
ROM version, STACK , etc.)
ROM APIs,
etc.)
0x0020_0000 0x2024_0000
ROM Memory Map RAM Memory Map
Figure 10-2. Internal ROM and RAM memory map
NOTE
The RAM space occupied by ROM cannot be used as part of
the boot image. The entire OCRAM1 region can be used freely
after the boot. The above OCRAM1 region must be reserved if
the user application needs to call the HAB API for image
authentication.
10.5.2 Boot block activation
The boot ROM affects a number of different hardware blocks which are activated and
play a vital role in the boot flow.
The ROM configures and uses the following blocks (listed in an alphabetical order)
during the boot process. Note that the blocks actually used depend on the boot mode and
the boot device selection:
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Block Description
CCM Clock Control Module
FlexSPI Flexible SPI Interface which supports serial NOR, Serial NAND and serial RAM devices
OCOTP On Chip One Time Programmable Controller containing the eFuses
IOMUXC I/O Multiplexer Control which allows the GPIO use to override the eFuse boot settings
IOMUX GPR I/O Multiplexer control General Purpose Registers
LPSPI Low Power SPI interface which supports serial NOR/EEPROM devices
SNVS Secure Non-Volatile Storage
SRC System Reset Controller
USB Used for Serial download of a boot device provisioning program
uSDHC Ultra-Secure Digital Host Controller
WDOG 1 WatchDog Timer
CAAM Cryptographic Acceleration and Assurance Module
PIT Periodic Interrupt Timer
10.5.3 Enabling Caches
The boot ROM includes a feature that enables the caches to improve the boot speed.
L1 instruction cache is enabled at the start of image download. The L1 data cache is
enabled at the start of image authentication. Both the caches are disabled by ROM before
leaving the ROM execution.
By default, the L1-ICache and DCache are enabled by ROM. However, there are fuse bits
that can be programmed for ROM not to enable the L1 I/DCache at boot.
The Cache features are controlled by the BT_ICACHE_DISABLE fuse and
BT_DCACHE_DISABLE fuses. By default, both fuses are not blown meaning the ROM
uses the L1-ICache and L1-DCache of the Arm core. This improves the performance of
the HAB signature verification software.
10.5.4 Exception error handling
10.5.4.1 Fault handling
All types of Faults cause the NVIC_SystemReset(), including the following:
• HardFault, BusFault, MemMangeFault, UsageFault
• ROM boot flow mismatch (treated as a side-channel attack)
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10.5.4.2 Boot failure
ROM indicates the following failures if the boot failure indicator feature is enabled by the
BOOT_FAIL_IND_EN and "Boot Failure Indicator Pin Select" fuse fields.
• The primary/recovery/manufacturing boot failed before entering serial downloader
• The HAB API call failed
The ROM provides the WDOG feature if the WDOG_EN fuse is blown. The
"WDOG_Timeout Select" fuse field provides the pre-defined timeout value.
The ROM supports WDOG_B assertion if the WDOG_B_PIN_EN fuse bit is blown. The
WDOG_B_PIN_SEL fuse field specifies the WDOG_B pin.
ROM resets the device immediately upon detection of an illegal boot flow.
10.5.5 Persistent bits
Some modes of the boot ROM require the registers that keep their values after a warm
reset. The SRC General-Purpose registers are used for this purpose.
See this table for persistent bits list and description:
Table 10-8. Persistent bits
Bit name Bit location Description
PERSIST_SECONDARY_BOOT SRC_GPR9[30] This bit identifies which image must be used—
primary and secondary. Used only for eMMC/SD/
FlexSPI NOR boot.
PERSIST_REDUNDANT_BOOT SRC_GPR9[27:26] This field identifies which image must be used -
0/1/2/3. Used for both SPI NAND and SLC raw
NAND devices.
FLASH_STATE_CTX SRC_GPR2[31:0] Flash status context. This field logs the flash state
during boot, so that the flash driver can retrieve the
state of the flash and operate the flash devices
properly.
ROM_API_CTX SRC_GPR3[31:0] ROM API context. Reserved for ROM API use.
10.6 Boot devices
The chip supports the following boot flash devices:
• Serial NOR flash via FlexSPI Interface
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• Serial NAND Flash via FlexSPI Interface
• NAND Flash with SEMC interface, located on CS0, 8-bit/16-bit bus width.
• SD/MMC/eSD/SDXC/eMMC5.0 via uSDHC interface, supporting high capacity
cards
• Serial NOR/EEPROM boot via LPSPI
The selection of the external boot device type is controlled by the BOOT_CFG1[7:4]
eFUSEs. See this table for more details:
Table 10-9. Boot device selection
BOOT_CFG1[7:4] Boot device
0000b Serial NOR boot via FlexSPI
01xxb SD Boot via uSDHC
10xxb eMMC/MMC boot via uSDHC
001xb SLC NAND boot via SEMC
11xxb Serial NAND boot via FlexSPI
NOTE
A user can use the LPSPI to boot from Serial NOR/EEPROM.
Booting from Serial NOR/EEPROM via an LPSPI port is not
intended as the primary device, but as a recovery boot device if
the primary boot device fails.
In order to enable a recovery boot device,
EEPROM_RECOVERY_EN fuse must be set to 1, and other
fuses listed in Serial NOR/EEPROM eFUSE configuration
must be properly set.
10.6.1 Serial NOR Flash Boot via FlexSPI
10.6.1.1 Serial NOR eFUSE Configuration
Table 10-10. Fuse definition for Serial NOR over FlexSPI
Fuse Config Definitions GPIO Shipped Settings
Value
BOOT_CFG1[0] OEM xSPI FLASH Yes 0 0 – Disabled
Auto Probe
1 – Enabled
BOOT_CFG1[1] OEM Encrypted Yes 0 0 – Disabled
XIP
1 – Enabled
Table continues on the next page...
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Table 10-10. Fuse definition for Serial NOR over FlexSPI (continued)
Fuse Config Definitions GPIO Shipped Settings
Value
BOOT_CFG1[3:2] OEM xSPI FLASH Yes 0 0 – QuadSPI NOR
Auto Probe
1 – MXIC Octal
Type
2 – Micron Octal
3 – Adesto Octal
BOOT_CFG1[7:4] OEM Boot device Yes 0 0 – Serial NOR device is selected as
selection boot device
BOOT_CFG2[2:0] OEM xSPI Flash Yes 0 000b–Boot with default 0x03 Read
Type Enabled
001b–Reserved
010b–HyperFlash 1V8
011b–HyperFlash 3V0
100b–MXIC Octal Read
101b–Micron Octal Read
BOOT_CFG2[3] OEM FLEXSPI Yes 0 0 – FLEXSPI1
instance
1 – FLEXSPI2
0xC80[2:0] OEM xSPI FLASH No 0 0 – 100MHz
Frequency
(BOOT_CONFIG_ MISC) 1 – 120MHz
2 – 133MHz
3 – 166MHz
5 – 80MHz
6 – 60MHz
Others – Reserved
0xC80[4:3] OEM Hold time No 0 0 – 500us
before
(BOOT_CONFIG_ MISC) 1 – 1ms
access the
Flash device 2 – 3ms
3 – 10ms
0xC80[5] OEM RESET_PIN No 0 0 - Primary reset pin
_SEL
1 - Secondary reset pin
Reset pin
Please refer to Table 10-1 for details.
selection
0xC80[6] OEM JEDEC_HW No 0 0 - JEDEC hardware reset sequence
_RESET_EN is not performed
Enable 1 - JEDEC hardware reset sequence
JEDEC is performed before accessing the
hardware flash device
reset
sequence
0xC80[7] OEM RESET_PIN No 0 0 - External reset pin is not enabled
_EN
1 - External reset pin is enabled
Enable reset
pin
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Table 10-10. Fuse definition for Serial NOR over FlexSPI (continued)
Fuse Config Definitions GPIO Shipped Settings
Value
0xC80[11:8] OEM xSPI FLASH No 0 0 – Dummy cycles is auto-probed
Dummy
(BOOT_CONFIG_ MISC) Others – User specified dummy
Cycle
cycles for Read command
0xC80[15:12] OEM xSPI FLASH No 0 0 – Image size equals to Secondary
image size Image offset
(BOOT_CONFIG_ MISC)
1 – 1MB
2 – 2MB
... – ...
12 – 12MB
13 – 256KB
14 – 512KB
15 – 768KB
0xC80[23:16] OEM xSPI No 0 Offset = 256KB × fuse value
FLASH_SEC
(BOOT_CONFIG_ MISC)
_IMAGE_OF
FSET
0x9A0[9:8] FLASH_CO No 0 - Connected via PORTA CS0
NNECTION_
1 - Parallel Mode
SEL
2 - Connected Via PORTB CS0
Select the
FLASH
connection
options
0x9A0[10] FLEXSPI_PI No 0 - Primary group
N_GROUP_
1 - Secondary group
SEL
FlexSPI Pin
Group
Selection
0x9A0[11] FLEXSPI_D No 0 0 - Primary DQS Pin
QS_PIN_SE
1 - Secondary DQS Pin
L
FlexSPI DQS
Pin selection
NOTE
If the xSPI FLASH Auto Probe feature is enabled, the
following is the logic how this feature works with other fuse
combinations:
• Flash Type - If Flash type is 0, the "xSPI FLASH Auto
Probe Type" takes effect for the Flash type selection. If
Flash Type is greater than 1, the "Flash Type" fuse is used
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for Flash type selection, ROM will issue specific command
to probe the presence of Serial NOR FLASH.
• xSPI FLASH Frequency - This field is used for specifying
the Flash working frequency.
10.6.1.2 FlexSPI Serial NOR Flash Boot Operation
The Boot ROM attempts to boot from Serial NOR flash if the BOOT_CFG1 [7:4] fuses
are programmed to 0b’0000 as shown in the Serial NOR eFUSE Configuration table, then
the ROM will initialize FlexSPI interface. FlexSPI interface initialization is a two-step
process.
1. The ROM expects the 512-byte FlexSPI NOR configuration parameters (as explained
in the next section) to be present at offset 0x400 in Serial NOR flash attached to
FLEXSPI_A_SS0_B. The ROM can probe the presence of Serial NOR Flash and
generate these configuration parameters accordingly via the combination of Fuses in
the table above, or reads these configuration parameters using the read command
specified by BOOT_CFG 2[2:0] with serial clock operating at 30 MHz.
2. ROM configures FlexSPI interface with the parameters provided in configuration
block read from Serial NOR flash and starts the boot procedure. Refer to Table 10-18
for details regarding FlexSPI configuration parameters and to the FlexSPI NOR boot
flow chart for detailed boot flow chart of FlexSPI NOR.
Both booting an XIP and non XIP image are supported from Serial NOR Flash. For XIP
boot, the image has to be built for FlexSPI address space; and for non XIP, the image can
be built to execute from internal RAM.
NOTE
A non-XIP image's execute address space should NOT be
overlapped with the reserved OCRAM region described in the
section "Internal ROM/RAM memory map". And it is also
highly recommended to avoid using address space near
0x00000000, typically up to 0x00000003.
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10.6.1.3 FlexSPI NOR boot flow chart
Enter FlexSPI NOR
boot flow
ImageIndex
Fallback to the main
<= allowed No
boot flow
Image index?
Yes
Configure FlexSPI Pinmux and Clock to
30MHz to perform basic read operation or
flash probe operation
Get Configuration parameter
Configure IOMUX, LUT, controller and clock
based on the configuration parameter
Configure Flash device to desired mode
based on configuration parameter
Jump to the boot
Is OTFAD Encrypted XIP image
Yes Yes
Enabled? enabled?
Yes
No
Initiate the
Initiate the
Hardware Copy image to
KeyBlob Authenticate Image Is Image valid?
KeyBlob No destination RAM
unwrapping
Unwrapping via
via IEE
OTFAD
No
Set boot device
Is Operation parameter(initial IVT header
Yes Yes Image == XIP Yes
successful? image address, valid?
memory range, etc)
No
Set ImageIndex =
No No
ImageIndex + 1
Reset the target
Figure 10-3. FlexSPI NOR boot flow
10.6.2 Serial NAND Flash Boot over FlexSPI
The boot ROM supports a number of Serial NAND Flash devices from different vendors.
The Embedded Error Correction and Control (ECC) module in SPI NAND devices are
used to detect and correct the errors.
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10.6.2.1 Serial NAND eFUSE Configuration
The boot ROM determines the configuration of external Serial NAND flash by
parameters, either provided by eFUSE, or sampled on GPIO pins during boot. See below
table for parameters details.
Table 10-11. Fuse definition for Serial NAND over FlexSPI
Fuse Config Definitions GPIO Shipped Value Settings
BOOT_CFG1[1:0] OEM Search Stride for Yes 0 0 - 64
FCB and DBBT
1 - 128
Search strides in
terms of page 2 - 256
3 - 32
BOOT_CFG1[3:2] OEM Hold Time before Yes 0 0 - Hold time
access to Serial determined by
NAND Read Status
command
1 - 500us
2 - 1ms
3 - 3ms
BOOT_CFG1[4] OEM Column address Yes 0 0 - 12 bits
width
1 - 13 bits
BOOT_CFG1[5] OEM Default safe Yes 0 0 – High Speed
communication (50MHz)
frequency
1 – Low Speed
(30MHz)
BOOT_CFG1[7:6] OEM Primary boot Yes 0 00 – Serial NOR
device selection
11 – Serial NAND
BOOT_CFG2[0] OEM Boot Search Count Yes 0 0-1
of FCB and DBBT
1-2
BOOT_CFG2[2:1] OEM CS de-asserted Yes 0 0 – 100ns
interval between
1 – 200ns
two commands
2 – 400ns
3 – 50ns
BOOT_CFG2[3] OEM FlexSPI instance Yes 0 - FlexSPI1
1 - FlexSPI2
0x9A0[9:8] OEM FLASH_CONNECT No 0 Flash connection
ION_SEL section.
0 - PORTA
2 - PORTB
0x9A0[10] OEM FLEXSPI_PIN_GR No 0 FlexSPI Pin group
OUP_SEL selection.
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Table 10-11. Fuse definition for Serial NAND over FlexSPI (continued)
Fuse Config Definitions GPIO Shipped Value Settings
0 - Primary group
1 - 2nd pin group
0xC80[4:0] OEM PAGE_READ_TIM No 0 ROM waits an
E interval between
page read and read
cache command.
0 - 75μs
Others -
PAGE_READ_TIM
E * 10μs
This fuse takes
effect if the
BYPASS_READ_S
TATUS fuse is
blown.
0xC80[7] OEM SPI NAND BOOT - No 0 0 – Use default
Override Busy busy bit offset 0
Offset
1 – Override default
busy bit offset
using Busy bit
offset
0xC80[13:8] OEM SPI NAND BOOT - No 0
Busy Bit offset
0xC80[14] OEM BYPASS_ECC_RE No 0 Bypass ECC read if
AD the default does not
support ECC
feature.
0xC80[15] OEM BYPASS_READ_S No 0 Bypass the FLASH
TATUS busy check via
read status
command. Use
PAGE_READ_TIM
E FUSE field
instead.
0xC80[23:16] OEM Page Read No 0 Available only if it is
Command not 0
0xC80[31:24] OEM Cache Read No 0 Available only if it is
command not 0
NOTE
BOOT_CFGx sampled on GPIO pins depends on
BT_FUSE_SEL setting.
NOTE
All the fuse fields on 0xC80 are defined for the NAND FLASH
device which does not support the de-facto SPI NAND
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standard. For all the existing ECC-free SPI NAND FLASH,
these fuse fields are not needed.
10.6.2.2 FlexSPI NAND Flash Boot Flow and Boot Control Blocks
(BCB)
There are two BCB data structures:
• FCB
• DBBT
As part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for a Firmware Configuration Block (FCB) that contains the optimum NAND
timings, page address of Discovered Bad Block Table (DBBT) Search Area and start
page address of primary and secondary firmware.
The built-in HW ECC in Serial NAND device is used during data read, the FCB data
structure is protected using CRC checksum. Driver reads raw 2048 bytes of first sector
and runs through CRC check that determines whether FCB data is valid or not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments page
number to Search Stride number of pages to read for the next BCB until SearchCount
pages have been read.
If search fails to find a valid FCB, the NAND driver responds with an error and the boot
ROM enters into serial download mode.
The FCB contains the page address of DBBT Search Area, and the page address for
primary and secondary boot images. DBBT is searched in DBBT Search Area just like
how FCB is searched. After the FCB is read, the DBBT is loaded, and the primary or
secondary boot image is loaded using starting page address from FCB.
Figure 10-4 shows the state diagram of FCB search.
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START
Current Page = 0,
Search Stride = Stride Size Fuse Value,
Search Count = Boot Search Count Fuse Value
Read 1 page,
ReadCount ++
Current Page += Search
Stride
YES
Read Count <
Is Valid FCB? NO
Search Count
YES NO
Recovery Device/
FCB Found
Serial Loader
Figure 10-4. FCB Search Flow
After FCB is found, the boot ROM searches for the Discovered Bad Blocks Table
(DBBT). If DBBTSearchStartPage is 0 in the FCB, then ROM assumes that there are no
bad blocks in the NAND device boot area. See Figure 10-5 for the DBBT search flow.
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START
Current Page = DBBT Start Page,
Search Stride = Stride Size Fuse Value,
Search Count = 4
Read 1 page,
ReadCount ++
Current Page += Search
Stride
YES
Read Count <
Is Valid DBBT? NO
Search Count
YES
DBBT Found, Copy to NO
Internal RAM
DBBT Not Found
DBBT Found
Figure 10-5. DBBT Search Flow
If during primary image read there is a page with a number of errors higher than ECC can
correct, the boot ROM will turn on PERSIST_SECONDARY_BOOT bit and perform
SW reset (After SW reset, secondary image is used).
If during secondary image read there is a page with number of errors higher than ECC
can correct, the boot ROM goes to serial downloader.
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10.6.2.3 Firmware Configuration Block
The FCB is at the first page in the first good block. The FCB should be present at each
search stride of the search area.
The search area contains copies of the FCB at each stride distance, in case the first Serial
NAND block becomes corrupted, the ROM will find its copy in the next Serial NAND
block. The search area should span over at least two Serial NAND blocks. The location
information for DBBT search area and images are all specified in the FCB. The following
table shows the Flash Control Block Structure.
Table 10-12. Flash Control Block Structure
Name Offset Size Bytes Description
crcChecksum 0x000 4 Checksum
fingerprint 0x004 4 0x4E46_4342
ASCII: “NFCB”
version 0x008 4 0x0000_0001
DBBTSearchStartPage 0x00C 4 Start Page address for bad
block table search area
searchStride 0x010 2 Search stride for DBBT and
FCB search. Not used by
ROM Max value is 8.
searchCount 0x012 2 Copies of DBBT and FCB.
Not used by ROM, max value
is 8.
firmwareCopies 0x014 4 Firmware copies
Valid range 1-4.
Reserved 0x018 40 Reserved for future use
Must be set to 0.
firmwareInfoTable 0x40 64 This table consists of (up to 8
entries):
Field Size Descrip
tion
StartPag 4 Start
e page of
this
firmware
pageCo 4 Pages in
unt this
firmware
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Table 10-12. Flash Control Block Structure
(continued)
Name Offset Size Bytes Description
NOTE: The StartPage must
be the first page of a
NAND block.
Reserved 0x080 128 Reserved
Must be set to 0
spiNandConfigBlock 0x100 512 Serial NAND configuration
block over FlexSPI
Reserved 0x300 256 Must be set to 0
NOTE
1. The “crcChecksum” is calculated with an MPEG2 variant
of CRC-32. See Table 10-13 for more details.
2. The “crcChecksum” calculation starts from fingerprint to
the end of FCB, 1020 bytes in total.
3. The “spiNandConfigBlock” is FlexSPI NAND
configuration block which consists of common FlexSPI
memory configuration block and Serial NAND specified
configuration parameters.
Table 10-13. CRC-32 variant algorithm
Property Description
Width 32 bits
Polynomial 0x04C11DB7
Init Value 0xFFFFFFFF
Reflect in False
Reflect Out False
XOR Out 0x00000000
10.6.2.4 Discovered Bad Blocks Table (DBBT)
Table 10-14. DBBT Structure
Name Offset Size in Bytes Decription
crcChecksum 0x000 4 Checksum
Fingerprint 0x004 4 32-bit word with a value of
0x4442_4254, in ASCII
“DBBT”
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Table 10-14. DBBT Structure (continued)
Name Offset Size in Bytes Decription
Version 0x008 4 32-bit version number, this
version of DBBT is
0x00000001
- 0x00C 4 Reserved
badBlockNumber 0x010 4 Number of bad blocks
Reserved 0x014 12 Must be filled with 0x00s
Bad Block entries 0x020 1024 Each bad block entry is a 32-
bit value specifying the
(256*4)
number of a found bad block.
The number of valid bad block
entries is specified by the
badBlockNumber field, where
valid bad block entries are
stored sequentially starting at
the beginning of the bad block
entries segment. Unused bad
block entries (those beyond
the badBlockNumber) should
be filled with 0xFs.
NOTE
1. Maximum badBlockNumber is 256.
2. The "crcChecksum" is calculated with the same algorithm
as the one in FCB, from Fingerprint to the end of DBBT,
1052 bytes in total.
10.6.2.5 Bad block handling in ROM
During the firmware boot, at the block boundary, the Bad Block table is searched for a
match to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block checked.
10.6.3 Serial NOR and NAND Configuration based on FlexSPI
Interface
The ROM SW supports Serial NOR and Serial NAND based on FlexSPI module, using a
448-bytes common FlexSPI configuration block and several specified parameters for
Serial NOR and Serial NAND respectively. See the following sections for more details.
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10.6.3.1 FlexSPI Configuration Block
FlexSPI Configuration block consists of parameters regarding specific Flash devices
including read command sequence, quad mode enablement sequence (optional), etc.
Table 10-15. FlexSPI Configuration block
Name Offset Size(bytes) Description
Tag 0x000 4 0x42464346, ascii: 'FCFB'
Version 0x004 4 [07:00] bugfix = 0
[15:08] minor
[23:16] major = 1
[31:24] ascii ‘V’
- 0x008 4 Reserved
readSampleClkSrc 0x00C 1 0 – internal loopback
1 – loopback from DQS pad
3 – Flash provided DQS
csHoldTime 0x00D 1 Serial Flash CS Hold Time Recommend default value is 0x03
csSetupTime 0x00E 1 Serial Flash CS setup time
Recommended default value is 0x03
columnAdressWidth 0x00F 1 3 – For HyperFlash
12/13 – For Serial NAND, see the NAND FLASH datasheet to
find the correct value
0 – Other devices
deviceModeCfgEnable 0x010 1 Device Mode Configuration Enable feature
0 – Disabled
1 – Enabled
deviceModeType 0x011 1 0 - Generic
1 - Quad Enable
2 - SPI-to-xSPI mode
3 - xSPI-to-SPI mode
4 - SPI-to-NoCmd mode
waitTimeCfgCommands 0x012 2 Wait time for all configuration commands, unit 100us.
Available for device that support v1.1.0 FlexSPI configuration
block. If it is greater than 0, ROM will wait
waitTimeCfgCommands * 100us for all device memory
configuration commands instead of using read status to wait
until these commands complete.
deviceModeSeq 0x014 4 Sequence parameter for device mode configuration
Bit[7:0] - number of LUT sequences for Device mode
configuration command
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Table 10-15. FlexSPI Configuration block (continued)
Name Offset Size(bytes) Description
Bit[15:8] - starting LUT index of Device mode configuration
command
Bit[31:16] - must be 0
deviceModeArg 0x018 4 Device Mode argument, effective only when
deviceModeCfgEnable = 1
configCmdEnable 0x01C 1 Config Command Enable feature
0 – Disabled
1 – Enabled
- 0x01D 3 Reserved
configCmdSeqs 0x020 12 Sequences for Config Command, allow 3 separate
configuration command sequences.
- 0x02C 4 Reserved
cfgCmdArgs 0x030 12 Arguments for each separate configuration command
sequence.
- 0x03C 4 Reserved
controllerMiscOption 0x040 4 Bit0 – differential clock enable
Bit1 – CK2 enable, must set to 0 in this silicon
Bit2 – ParallelModeEnable
Bit3 – wordAddressableEnable
Bit4 – Safe Configuration Frequency enable set to 1 for the
devices that support DDR Read instructions
Bit5 – Pad Setting Override Enable
Bit6 – DDR Mode Enable, set to 1 for device supports DDR
read command
Bit 7 - Pad Setting Override Enable
Bit 8 - Second Pin group
Bit 9 - Second DQS pin group
Bit 10 - Write Mask Enable
Bit 11 - Write Opt1 Clear
deviceType 0x044 1 1 – Serial NOR
2 – Serial NAND
3 - Serial RAM (HyperRAM/APMemory)
sflashPadType 0x045 1 1 – Single pad
2 – Dual pads
4 – Quad pads
8 – Octal pads
serialClkFreq 0x046 1 Chip specific value, for this silicon
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
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Table 10-15. FlexSPI Configuration block (continued)
Name Offset Size(bytes) Description
4 – 80 MHz
5 – 100 MHz
6 – 120 MHz
7 – 133 MHz
8 – 166 MHz
Other value: 30 MHz
lutCustomSeqEnable 0x047 1 0 – Use pre-defined LUT sequence index and number
1 - Use LUT sequence parameters provided in this block
- 0x048 8 Reserved
sflashA1Size 0x050 4 For SPI NOR, need to fill with actual size
For SPI NAND, need to fill with actual size * 2
sflashA2Size 0x054 4 The same as above
sflashB1Size 0x058 4 The same as above
sflashB2Size 0x05C 4 The same as above
csPadSettingOverride 0x060 4 Set to 0 if it is not supported
sclkPadSettingOverride 0x064 4 Set to 0 if it is not supported
dataPadSettingOverride 0x068 4 Set to 0 if it is not supported
dqsPadSettingOverride 0x06C 4 Set to 0 if it is not supported
timeoutInMs 0x070 4 Maximum wait time during read busy status
0 – Disabled timeout checking feature
Other value – Timeout if the wait time exceeds this value
commandInterval 0x074 4 Unit: ns
Currently, it is used for SPI NAND only at high frequency
dataValidTime 0x078 4 Time from clock edge to data valid edge, unit ns. This field is
used when the FlexSPI Root clock is less than 100 MHz and
the read sample clock source is device provided DQS signal
without CK2 support.
[31:16] data valid time for DLLB in terms of 0.1 ns
[15:0] data valid time for DLLA in terms of 0.1 ns
busyOffset 0x07C 2 busy bit offset, valid range :0-31
busyBitPolarity 0x07E 2 0 – busy bit is 1 if device is busy
1 – busy bit is 0 if device is busy
lookupTable 0x080 256 Lookup table
lutCustomSeq 0x180 48 Customized LUT sequence, see below table for details.
0x1B0 16 Reserved for future use
Note:
1. To customize the LUT sequence for some specific device, users need to enable
“lutCustomSeqEnable” and fill in corresponding “lutCustomSeq” field specified by
command index below.
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2. For Serial (SPI) NOR, the pre-defined LUT index is as follows:
Table 10-16. LUT sequence definition for Serial
NOR
Command Index Name Index in lookup table Description
0 Read 0 Read command
Sequence
1 ReadStatus 1 Read Status
command
2 WriteEnable 3 Write Enable
command sequence
3 EraseSector 5 Erase Sector
Command
4 PageProgram 9 Page Program
Command
5 ChipErase 11 Full Chip Erase
6 Dummy 15 Dummy Command as
needed
7-12 Reserved 2,4,6,7,8,10,12,13,14 All reserved indexes
can be freely used for
other purpose
13 NOR_CMD_LUT_SE 13 Read SFDP sequence
Q_IDX_READ_SFDP in lookupTable id
stored in config block
14 NOR_CMD_LUT_SE 14 Restore 0-4-4/0-8-8
Q_IDX_RESTORE_N mode sequence id in
OCMD lookupTable stored in
config block
3. For Serial (SPI) NAND, the pre-defined LUT index is as follows:
Table 10-17. LUT sequence definition for Serial
NAND
Command Index Name Index in lookup table Description
0 ReadFromCache 0 Read from cache
1 ReadStatus 1 Read Status
2 WriteEnable 3 Write Enable
3 BlockErase 5 Erase block
4 ProgramLoad 9 Program Load
5 ReadPage 11 Read page to cache
6 ReadEccStatus 13 Read ECC Status
7 ProgramExecute 14 Program Execute
8 ReadFromCacheOdd 4 Read from Cache
while page in odd
plane
9 ProgramLoadOdd 10 Program Load for
pages within odd
blocks
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Table 10-17. LUT sequence definition for Serial NAND
(continued)
Command Index Name Index in lookup table Description
Reserved 2,6,7,8,12,15 All reserved indexes
can be freely used for
other purposes
NOTE
1. All the pre-defined LUT indexes are only applicable to
boot stage. User application can use the whole 16 LUT
entries freely based on their requirement.
2. The FlexSPI NOR ROM APIs occupy LUT index 0-5. User
application should NOT use these LUT indexes if the
ROM API is called in their application frequently.
10.6.3.2 Serial NOR configuration block (512 bytes)
Table 10-18. Serial NOR configuration block
Name Offset Size (Bytes) Description
memCfg 0 448 The common memory
configuration block, see
FlexSPI configuration block
for more details
pageSize 0x1C0 4 Page size in terms of bytes,
not used by ROM
sectorSize 0x1C4 4 Sector size in terms of bytes,
not used by ROM
ipCmdSerialClkFreq 0x1C8 1 Chip specific value, not used
by ROM
0 – No change, keep current
serial clock unchanged
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 80 MHz
5 – 100 MHz
6 – 120 MHz
– 133 MHz
isUniformBlockSize 0x1C9 1 Device has uniform block size
0 - No, block size != sector
size
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Table 10-18. Serial NOR configuration block (continued)
Name Offset Size (Bytes) Description
1 - Yes, block size = sector
size
isDataOrderSwapped 0x1CA 1 The data order is swapped in
OPI DDR mode
0 - Not swapped
1 - Swapped (this is
applicable to Macronix
MX25UM512/256/128 series
only)
Reserved 0x1CB 5 Reserved
blockSize 0x1D0 4 blockSize
flashStateCtx 0x1D4 4 Flash State Context after
being configured
[7:0] Flash POR Mode:
0x00 - Extended SPI mode
0x42 - QPI DDR mode
0x82 - OPI DDR mode
--
[15:8] Flash Current Mode:
0x00 - Extended SPI mode
0x42 - QPI DDR mode
0x82 - OPI DDR mode
--
[23:16] Reserved
--
[31:24] Flash Restoring
Sequence:
0x6 - Send 0x66_0x99
(Micron Octal Flash)
0x7 - Send 0x6699_0x9966
(Macronix Octal Flash)
0x8 - Send 0x06 0xFF
(Adesto Octal Flash)
Reserved 0x1D8 24 Reserved
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10.6.3.3 Serial NAND configuration block (512 bytes)
Table 10-19. Serial NAND configuration block
Name Offset Size (Bytes) Description
memCfg 0 448 The common memory
configuration block, see
FlexSPI configuration block
for more details
pageDataSize 0x1C0 4 Page size in terms of bytes,
usually, it is 2048 or 4096
pageTotalSize 0x1C4 4 It equals to 2 ^ width of
column adddress
pagesPerBlock 0x1C8 4 Pages in one block
bypassReadStatus 0x1CC 1 0 – Read Status Register
1 – Bypass Read status
register
bypassEccRead 0x1CD 1 0 – Perform ECC read
1 – Bypass ECC read
hasMultiPlanes 0x1CE 1 0 – Only 1 plane
1 – Has two planes
skippOddBlocks 0x1CF 1 0 – Read Odd blocks
1 – Skip Odd blocks
eccCheckCustomEnable 0x1D0 1 0 – Use the common ECC
check command and ECC
related masks
1 - Use ECC check related
masks provided in this
configuration block
ipCmdSerialClkFreq 0x1D1 1 Chip specific value, not used
by ROM
0 – No change, keep current
serial clock unchanged
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
5 – 80 MHz
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
readPageTimeUs 0x1D2 2 Wait time during page read,
this field will take effect on if
the bypassReadStatus is set
to 1.
NOTE: Only applicable to
ROM.
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Table 10-19. Serial NAND configuration block (continued)
Name Offset Size (Bytes) Description
eccStatusMask 0x1D4 4 ECC Status Mask
eccFailureMask 0x1D8 4 ECC Check Failure mask
blocksPerDevice 0x1DC 4 Blocks in a Serial NAND
Reserved 0x1ED 32 Reserved for future use
Below is an example of Serial NAND configuration block for Winbond
W25N01GVZEIG:
const flexspi_nand_config_t kSerialNandCfgBlk =
{
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.dataHoldTime = 3,
.dataSetupTime = 3,
.columnAddressWidth = 12,
.deviceModeCfgEnable = 1,
.deviceModeSeq = { 1, 2 },
.deviceType = kFlexSpiDeviceType_SerialNAND,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_50MHz,
.lutCustomSeqEnable = 0,
.sflashA1Size = 128 * 1024 * 1024U * 2, // Flash size = 2 * actual data size
(exclude spare space)
.lookupTable =
{
// Read cache 4 I/0
[4 * NOR_CMD_LUT_SEQ_IDX_READ] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB,
CADDR_SDR, FLEXSPI_4PAD, 0x10),
[4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD,
0x04, READ_SDR, FLEXSPI_4PAD, 0x80),
// Clear Status1 flag
[4 * 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x1F, CMD_SDR, FLEXSPI_1PAD,
0xA0),
[4 * 2 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, STOP, FLEXSPI_1PAD,
0x00),
// Read Page
[4 * NAND_CMD_LUT_SEQ_IDX_READPAGE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x13, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Read Status
[4 * NAND_CMD_LUT_SEQ_IDX_READSTATUS] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x0F, CMD_SDR, FLEXSPI_1PAD, 0xC0),
[4 * NAND_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(READ_SDR,
FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0),
// Write Enable
[4 * NAND_CMD_LUT_SEQ_IDX_WRITEENABLE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x06, STOP, FLEXSPI_1PAD, 0),
// Page Program Load 4x
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMLOAD] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x32, CADDR_SDR, FLEXSPI_1PAD, 0x10),
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMLOAD + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR,
FLEXSPI_4PAD, 0x40, STOP, FLEXSPI_1PAD, 0),
// Page Program Execute
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMEXECUTE] = FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0x10, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Erase Sector
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[4 * NAND_CMD_LUT_SEQ_IDX_ERASEBLOCK] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Read ECC status
[4 * NAND_CMD_LUT_SEQ_IDX_READECCSTAT] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x0F, CMD_SDR, FLEXSPI_1PAD, 0xC0),
[4 * NAND_CMD_LUT_SEQ_IDX_READECCSTAT + 1] = FLEXSPI_LUT_SEQ(READ_SDR,
FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0),
},
},
.pageDataSize = 2048,
.pageTotalSize = 4096,
.pagesPerBlock = 64,
};
10.6.4 Parallel NAND flash Boot over SEMC
The boot ROM supports a number of Parallel SLC NAND flash devices from different
vendors. Both the Error Correction and Control (ECC) module in NAND device and
software ECC algorithm (SECDED) in boot ROM can be used to detect the errors, based
on the fuse settings.
10.6.4.1 Parallel NAND eFuse Configuration
The boot ROM determines the configuration of external Parallel NAND flash by
parameters, either provided by eFuse, or sampled on GPIO pins, during boot. See below
table for parameters details:
Table 10-20. Fuse definition for Parallel NAND over SEMC
Fuse Config Definitions GPIO Shipped Settings
Value
BOOT_CFG1[0] OEM Boot Search count of Yes 0 0–1
FCB and DBBT
1–2
BOOT_CFG1[4:1] OEM Search stride for FCB Yes 0000 0000 – 64
and DBBT in terms of
Others – 2 ^
pages
BOOT_SEARCH_STRIDE
BOOT_CFG1[7:5] OEM Primary boot device Yes 000 001 – Parallel NAND
selection
BOOT_CFG>2[0] OEM NAND ONFI compliant Yes 0 0 – ONFI 1.0
1 – Non-ONFI
BOOT_CFG2 [1] OEM SEMC EDO Mode Yes 0 0 – EDO Mode
1 – Non-EDO Mode
BOOT_CFG2 [2] OEM SEMC Access Yes 0 0 – IPG
Command
1 – AXI
0x6E0[20:19] OEM SEMC BCH mode No 0 0 - BCH is not enabled
1 - BCH4
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Table 10-20. Fuse definition for Parallel NAND over SEMC (continued)
Fuse Config Definitions GPIO Shipped Settings
Value
2 - BCH8
0xC80[3] OEM I/O port size 0 - 8 bit
1 - 16 bit
0xC80[4] OEM ECC algorithm Yes 0 0 - NAND flash-built-in ECC
selection
1 - Software ECC (SECDED)
NOTE: For “ECC selection”
option, it can only be
set as Device ECC
When NAND device
has built-in ECC
module and the ECC
module is enabled by
default.
0xC80[5] OEM RDY pin polarity No 0 – Low active
1 – High active
0xC80[6] OEM Ready check type No 0 – Status Register
1 – R/B# pin
0xC80[7] OEM SEMC clock frequency 0 - 133MHz (2nd max)
1 - 166MHz (Max)
0xC80[10:8] OEM Row Column address No 000 Applicable only for Non-ONFI
mode device
00x – 5 bytes (CA2+RA3)
010 – 4 bytes (CA2+RA2)
011 – 3 bytes (CA2+RA1)
10x – 4 bytes (CA1+RA3)
110 – 3 bytes (CA1+RA2)
111 – 2 bytes (CA1+RA1)
0xC80[13:11] OEM Column address width No 000 Applicable only for Non-ONFI
device
000 – 12 bits
001 – 09 bits
010 – 10 bits
011 – 11 bits
100 – 13 bits
101 – 14 bits
110 – 15 bits
111 – 16 bits
0xC80[14] OEM Status command type No 0 Applicable only for Non-ONFI
device
0 – Common
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Table 10-20. Fuse definition for Parallel NAND over SEMC (continued)
Fuse Config Definitions GPIO Shipped Settings
Value
1 – Enhanced
0xC80[18:16] OEM Pages in block No 000 Applicable only for Non-ONFI
device
000 – 128 pages
001 – 8 pages
010 – 16 pages
011 – 32 pages
100 – 64 pages
101 – 256 pages
110 – 512 pages
111 – 1024 pages
0xC80[20:19] OEM PCS Selection No 0 PCS Selection
0 - CS0
1 - CS1
2 - CS2
3 - CS3
0xC80[24] OEM Device ECC initial No 0 Applicable only for ONFI 1.0
status device
0 – Enabled
1 – Disabled
0xC80[27:25] OEM ONFI timing mode No 000 - Mode0 -10MHz
001 - Mode1 -20MHz
010 - Mode2 -28MHz
011 - Mode3 -33MHz
100 - Mode4 -40MHz
101 - Mode5 -50MHz
11x - Fastest Mode
10.6.4.2 Parallel NAND Flash Boot Control Blocks (BCB)
There are two BCB data structures:
• Firmware Configuration Block (FCB)
• Discovered Bad Blocks Table (DBBT)
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As part of the Parallel NAND media initialization, the ROM driver uses proper Parallel
NAND parameters specified by FUSE to search for an FCB that contains the complete
Parallel NAND parameters, page address of DBBT Search Area and Image info,
including image copies, start page address and image size in terms of pages for each
image.
FCB data structure is protected using Embedded ECC module in Parallel NAND devices
or software ECC in ROM. The ROM driver reads 2048 bytes of first sector and checks
the ECC check status to determine whether FCB data is valid or not.
If the FCB is found, the complete NAND parameters (Parallel NAND configuration
block) are loaded for further reads, if the ECC fails, or the fingerprint does not match, or
the CRC checksum does not match, the Block Search state machine increments page
number to Search Stride number of pages to read for the next FCB until Search Count
pages have been read.
If search fails to find a valid FCB, the Parallel NAND driver responds with an error and
the boot ROM enters into Recovery boot mode (Secondary boot, if it is enabled, or Serial
download mode).
The FCB contains the page address of DBBT Search Area, and the info for images.
DBBT is searched in DBBT Search area just like how FCB is searched. After the FCB is
read, the DBBT is loaded, then the boot image is loaded using starting page address from
FCB.
10.6.4.3 Firmware Configuration Block (FCB)
The FCB is at the first page in the first good block. The FCB should be present at each
search stride of the search area.
The search area contains copies of the FCB at each stride distance, in case the first Serial
NAND block becomes corrupted, the ROM will find its copy in the next Parallel NAND
block. The search area should span over at least two Parallel NAND blocks. The location
information for DBBT search area and images are all specified in the FCB. Below Table
shows the FCB Structure.
Name offset Size (Bytes) Description
bcbHeader 0x000 12 See Table 10-21 for details
DBBTSerachAreaStartPage 0x00c 4 Start Page address for bad
block table search area
searchStride 0x010 2 Search stride for DBBT and
FCB search. Not used by
ROM Max value is 8.
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searchCount 0x012 2 Copies of DBBT and FCB.
Not used by ROM, max value
is 8.
firmwareCopies 0x014 4 Firmware copies
Valid range 1-4.
- 0x018 40 Reserved
firmwareTable 0x040 64 For details see Table 10-22
- 0x080 128 Reserved
nandConfig 0x100 256 Parallel NAND configuration
block over SEMC
- 0x200 512 Reserved
Table 10-21. Header Description
Field Size Description
crcChecksum 4 Checksum
fingerprint 4 0x4E46_4342
ASCII: “NFCB”
version 4 0x0000_0001
Table 10-22. Table Descriptions
Field Size Description
startPage 4 Start page of this firmware
pagesInFirmware 4 Pages in this firmware
NOTE
• The “crcChecksum” is calculated with an MPEG2 variant
of CRC-32.
• The “crcChecksum” calculation starts from fingerprint to
the end of FCB, 1020 bytes in total.
• The “nandConfig” is SEMC NAND configuration block
which consists of common SEMC memory configuration
block and Parallel NAND specified configuration
parameters. See Parallel NAND eFuse Configuration for
more details.
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10.6.4.4 Discovered Bad Blocks Table (DBBT)
Table 10-23. DBBT Structure
Name offset Size (Bytes) Description
bcbHeader 0x000 12 See Table 10-24 for details
- 0x00C 4 Reserved
badBlockNumber 0x010 4 Number of bad blocks
- 0x014 12 Reserved
badBlockTable 0x020 1024 Each bad block entry is a 32-bit value specifying
the number of a found bad block. The number of
(256*4)
valid bad block entries is specified by the
badBlockNumber field, where valid bad block
entries are stored sequentially starting at the
beginning of the bad block entries segment.
Unused bad block entries (those beyond the
badBlockNumber) should be filled with 0xFs.
Table 10-24. Header Description
Field Size Description
crcChecksum 4 Checksum
fingerprint 4 0x4442_4254
ASCII: “DBBT”
version 4 0x0000_0001
NOTE
• Maximum bad block number is 256.
• The "crcChecksum" is calculated with the same algorithm
as the one in FCB, from Fingerprint to the end of DBBT,
1052 bytes in total.
10.6.4.5 Bad block handling in ROM
During firmware boot, at the block boundary, the Bad Block table is searched for a match
to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block is checked.
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10.6.5 Parallel NAND configuration based on SEMC interface
The ROM SW supports Parallel NAND based on SEMC module, using an 80-bytes
common SEMC configuration block and several specified parameters for Parallel NAND.
See the following sections for more details.
10.6.5.1 SEMC Configuration Block
SEMC Configuration block consists of all parameters related to specific Flash devices.
Table 10-25. SEMC control block structure
Name offset Size (Bytes) Description
tag 0x000 4 0x434D4553, ascii:”SEMC”
version 0x004 4 0x00010000
[07:00] bugfix = 0
[15:08] minor = 0
[31:16] major = 1
deviceMemType 0x008 1 0 – NOR Flash
1 – NAND Flash
accessCommandType 0x009 1 0 – IPG bus command
1 – AXI32 command
- 0x00A 2 Reserved
asyncClkFreq 0x00C 1 0 – 33MHz
1 – 40MHz
2 – 50MHz
3 – 66MHz
4 – 108MHz
5 – 133MHz
6 – 166MHz
busTimeoutCycles 0x00D 1 0 – 255 * 1024 cycles
n – n * 1024 cycles
commandExecutionTimeoutC 0x00E 1 0 – 256 * 1024 cycles
ycles
n – n * 1024 cycles
readStrobeMode 0x00F 1 0 – Dummy read strobe
loopbacked internally
1 – Dummy read strobe
loopbacked from DQS pad
norMemConfig 0x010 64 See detail in Table SEMC
NOR control block structure
nandMemConfig 0x050 64 See detail in Table SEMC
NAND control block structure
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Table 10-26. SEMC NAND control block structure
Name offset Size (Bytes) Description
axiMemBaseAddress 0x00 4 SoC level Base Address for
NAND AXI command
axiMemSizeInByte 0x04 4 SoC level Memory size for
NAND AXI command
ipgMemBaseAddress 0x08 4 SoC level Base Address for
NAND IPG command
ipgMemSizeInByte 0x0c 4 SoC level Memory size for
NAND IPG command
edoMode 0x10 1 0 - EDO mode disabled
1 - EDO mode enabled
ioPortWidth 0x11 1 IO Port bit number
arrayAddressOption 0x12 1 0 – 5 bytes (CA2+RA3)
1 – 4 bytes (CA1+RA3)
2 – 4 bytes (CA2+RA2)
3 – 3 bytes (CA1+RA2)
4 – 3 bytes (CA2+RA1)
7 – 2 bytes (CA1+RA1)
columnAddressWidth 0x13 1 Column address bit number
burstLengthInBytes 0x14 1 Burst Length
columnAddressOption 0x15 1 0 - PageAreaAccess
1 - SpareAreaAccess
- 0x16 10 Reserved
cePortOutputSelection 0x20 1 0 – CSX0
1 – CSX1
2 – CSX2
3 – CSX3
4 – A8
rdyPortPolarity 0x21 1 0 – Low active
1 – High active
- 0x22 14 Reserved
ceSetupTime 0x30 1 value[3:0] + 1 cycles
ceMinHoldTime 0x31 1 value[3:0] + 1 cycles
ceMinIntervalTime 0x32 1 value[3:0] + 1 cycles
weLowTime 0x33 1 value[3:0] + 1 cycles
weHighTime 0x34 1 value[3:0] + 1 cycles
reLowTime 0x35 1 value[3:0] + 1 cycles
reHighTime 0x36 1 value[3:0] + 1 cycles
weHighToReLowTime 0x37 1 value[5:0] + 1 cycles
reHighToWeLowTime 0x38 1 value[5:0] + 1 cycles
aleToDataStartTime 0x39 1 value[5:0] + 1 cycles
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Table 10-26. SEMC NAND control block structure (continued)
Name offset Size (Bytes) Description
readyToReLowTime 0x3a 1 value[5:0] + 1 cycles
weHighToBusyTime 0x3b 1 value[5:0] + 1 cycles
asyncTurnaroundTime 0x3c 1 value[3:0] + 1 cycles
- 0x3d 3 Reserved
10.6.5.2 Parallel NAND Configuration Block (256 bytes)
Table 10-27. Parallel NAND control block structure
Name offset Size (Bytes) Description
memConfig 0x000 80 See SEMC control block
structure for more details
vendorType 0x050 1 0 – Micron
1 – Spansion
2 – Samsung
3 – Winbond
4 – Hynix
5 – Toshiba
6 – Macronix
cellTechnology 0x051 1 0 – SLC
1 – MLC
onfiVersion 0x052 1 0 – Non-ONFI
1 – ONFI 1.0
2 – ONFI 2.0
3 – ONFI 3.0
4 – ONFI 4.0
acTimingTableIndex 0x053 1 0 – User Defined
1 – ONFI 1.0 Mode0 10MHz
2 – ONFI 1.0 Mode1 20MHz
3 – ONFI 1.0 Mode2 28MHz
4 – ONFI 1.0 Mode3 33MHz
5 – ONFI 1.0 Mode4 40MHz
6 – ONFI 1.0 Mode5 50MHz
7 – Auto Detection
enableEccCheck 0x054 1 0 – Enabled
1 – Disabled
eccCheckType 0x055 1 0 – Software ECC
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Table 10-27. Parallel NAND control block structure (continued)
Name offset Size (Bytes) Description
1 – Device ECC
deviceEccStatus 0x056 1 0 – Enabled
1 – Disabled
swEccAlgorithm 0x057 1 0 – SEC Hamming Code
swEccBlockBytes 0x058 4 Software ECC block bytes
(256, 512)
readyCheckOption 0x05c 1 0 – Via Status Register
1 – Via R/B# signal
statusCommandType 0x05d 1 0 – Common (0x70)
1 – Enhanced (0x78)
readyCheckTimeoutInMs 0x05e 2 Ready Check timeout
readyCheckIntervalInUs 0x060 2 Ready Check interval
userOnfiAcTimingModeCode 0x080 1 userOnfiAcTimingModeCode
- 0x081 31 Reserved
bytesInPageDataArea 0x0a0 4 Page Main data size
bytesInPageSpareArea 0x0a4 4 Page Spare data size
pagesInBlock 0x0a8 4 Page number in one block
blocksInPlane 0x0ac 4 Block number in one plane
planesInDevice 0x0b0 4 Plane number in Device
- 0x0b4 44 Reserved
enableReadbackVerify 0x0e0 1 0 - Enabled
1 - Disabled
- 0x0e1 3 Reserved
readbackPageBufferAddress 0x0e4 4 Read back page buffer
address
- 0x0e8 24 Reserved
10.6.6 Expansion device
The ROM supports booting from the MMC/eMMC and SD/eSD compliant devices.
10.6.6.1 Expansion device eFUSE configuration
The SD/MMC/eSD/eMMC/SDXC boot can be performed using the USDHC ports. The
port can be configured based on either the setting of the BOOT_CFG1[1] (Port Select)
fuse or its corresponding GPIO overrides.
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All USDHC ports support the fast boot. See this table for details:
Table 10-28. USDHC eFuse Descriptions
Fuse Config Definition GPIO Shipped Settings
value
BOOT_CFG1[0] OEM Fast boot support Yes 0 MMC
0 - Normal boot
1 - Fast boot
BOOT_CFG1[1] OEM USDHC port selection Yes 0 0 - USDHC-1
1 - USDHC-2
BOOT_CFG1[2] OEM SD loopback clock Yes 0 0 - through the SD pad
source sel (for SDR50
1 - direct
and SDR104 only)
BOOT_CFG1[3] OEM SD power cycle enable Yes 0 0 - No power cycle
1 - Power cycle enabled via the
SD_RST pad
BOOT_CFG1[5:4] OEM SD/MMC speed mode, Yes 00 MMC:
and eMMC
0x - Normal speed mode
acknowledge enabled
selection 1x - High-speed mode
x0 - eMMC fast boot acknowledge
disable
x1 - eMMC fast boot acknowledge
enable
SD:
00 - Normal/SDR12
01 - High/SDR25
10 - SDR50
11 - SDR104
BOOT_CFG1[7:6] OEM Boot device selection Yes 00 01 - SD/eSD/SDXC boot from the
USDHC interface
10 - MMC/eMMC boot from the
USDHC interface
BOOT_CFG2[0] OEM SD2 voltage selection Yes 0 MMC:
0 - 3.3 V
1 - 1.8 V
BOOT_CFG2[2:1] OEM SD MMC bus width Yes 00 SD:
selection
x0 - 1-bit
x1 - 4-bit
NOTE: To use 1-bit mode, the user
has to disconnect the SD
card's DATA3 line from
SoC.
MMC:
00 - 4-bit
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Table 10-28. USDHC eFuse Descriptions (continued)
01 - 8-bit
10 - 4-bit DDR (MMC 4.4)
11 - 8-bit DDR (MMC 4.4)
0x970[0] OEM eMMC pre-idle enabled Yes 0 0 - Issue pre-idle command
selection
1 - Do not issue
0x970[1] OEM USDHC2 reset polarity Yes 0 0 - Reset active low
selection
1 - Reset active high
0x970[2] OEM USDHC1 reset polarity Yes 0 0 - Reset active low
selection
1 - Reset active high
0x970[3] OEM USDHC1 voltage Yes 0 0 - 3.3 V
selection
1 - 1.8 V
0x970[5] OEM Power stable cycle Yes 0 0 - 5 ms
selection
1 - 2.5 ms
0x970[7:6] OEM Power cycle selection Yes 00 00 - 20 ms
01 - 10 ms
10 - 5 ms
11 - 2.5 ms
0x970[9:8] OEM SD calibration step Yes 00 SD
00 - 1 delay cell
01 - 2 delay cells
10 - 4 delay cells
11 - 6 delay cells
0x970[10] OEM DLL override selection Yes 0 0 - DLL Slave Mode for SD/eMMC
(delay 10, step 2)
1 - DLL Override Mode for SD/
eMMC
0x970[15] OEM Disable SDMMC Yes 0 0 - Enable
Manufacture mode
1 - Disable
The boot code supports these standards:
• MMCv4.4 or less
• eMMCv4.4 or less
• SDv2.0 or less
• eSDv2.10 rev-0.9, with or without FAST_BOOT
• SDXCv3.0
The MMC/SD/eSD/SDXC/eMMC can be connected to any of the USDHC blocks and
can be booted by copying 4 KB of data from the MMC/SD/eSD/eMMC device to the
internal RAM. After checking the Image Vector Table header value (0xD1) from
program image, the ROM code performs a DCD check. After a successful DCD
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extraction, the ROM code extracts from the Boot Data Structure the destination pointer
and length of image to be copied to the RAM device from where the code execution
occurs.
The maximum image size to load into the SD/MMC boot is 32 MB. This is due to a
limited number of uSDHC ADMA Buffer Descriptors allocated by the ROM.
NOTE
The initial 4 KB of the program image must contain the IVT,
DCD, and the Boot Data structures.
Table 10-29. SD/MMC frequencies
SD MMC MMC (DDR mode)
Identification (KHz) 347.22
Normal-speed mode (MHz) 25 20 25
High-speed mode (MHz) 50 40 50
UHSI SDR50 (MHz) 100
UHSI SDR104 (MHz) 200
NOTE
The boot ROM code reads the application image length and the
application destination pointer from the image.
10.6.6.2 MMC and eMMC boot
This table provides the MMC and eMMC boot details.
Table 10-30. MMC and eMMC boot details
Normal boot mode During the initialization (normal boot mode), the MMC
frequency is set to 347.22 KHz. When the MMC card enters
the identification portion of the initialization, the voltage
validation is performed, and the ROM boot code checks the
high-voltage settings and the card capacity. The ROM boot
code supports both the high-capacity and low-capacity MMC/
eMMC cards. After the initialization phase is complete, the
ROM boot code switches to a higher frequency (20 MHz in
the normal boot mode or 40 MHz in the high-speed mode).
The eMMC is also interfaced via the USDHC and follows the
same flow as the MMC.
The boot partition can be selected for an MMC4.x card after
the card initialization is complete. The ROM code reads the
BOOT_PARTITION_ENABLE field in the Ext_CSD[179] to get
the boot partition to be set. If there is no boot partition
mentioned in the BOOT_PARTITION_ENABLE field or the
user partition was mentioned, the ROM boots from the user
partition.
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Table 10-30. MMC and eMMC boot details (continued)
eMMC4.3 or eMMC4.4 device supporting special boot mode If using an eMMC4.3 or eMMC4.4 device that supports the
special boot mode, it can be initiated by pulling the CMD line
low. If the BOOT ACK is enabled, the eMMC4.3/eMMC4.4
device sends the BOOT ACK via the DATA lines and the
ROM can read the BOOT ACK [S010E] to identify the
eMMC4.3/eMMC4.4 device. The eMMC4.3/eMMC4.4 device
with the "boot mode" feature can only be supported via the
ESDHCV3-3 and with or without the BOOT ACK. If the BOOT
ACK is enabled, the ROM waits 50 ms to get the BOOT ACK
and if the BOOT ACK is received by the ROM. If BOOT ACK
is disabled ROM waits 1 second for data. If the BOOT ACK or
data was received, the eMMC4.3/eMMC4.4 is booted in the
"boot mode", otherwise the eMMC4.3/eMMC4.4 boots as a
normal MMC card from the selected boot partition. This boot
mode can be selected by the BOOT_CFG1[0] (fast boot) fuse.
The BOOT ACK is selected by the BOOT_CFG1[4].
eMMC4.4 device If using the eMMC4.4 device, the Double Data Rate (DDR)
mode can be used. This mode can be selected by the
BOOT_CFG2[2:1] (bus width) fuse.
Start
Check data bus width fuse.
. Accordingly
do the IOMUX config
uSDHC Software Reset, Set RSTA
Set Identification Frequency
(Approx 400 KHz)
Check MMC and Fast Boot Yes
6
Selection Fuse
No
Set INITA to send 80 SDCLK to card
Card SW Reset (CMD0)
No
Command Successful? 5
Yes
SD MMC
1 Check SD/MMC Selection fuse 2
Figure 10-6. Expansion device boot flow (1 of 6)
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Set Strong pull-up
For CMD line
Start GPT with 1s delay MMC Boot Set MMC card CSD Set operating frequency MMC Boot
Voltage Validation (Issue CMD9) to 20 MHz Device Init
for CMD1
Set Weak pull-up Put card data Transfer
For CMD line Mode (Issue CMD7)
Issue CMD1 with HV Increment loop counter
Yes
No No
Command Successful? Command Successful?
No Yes
Command Successful? 5
No Send CMD13 to read
Yes Set RCA (Issue CMD3) status
Yes Loop Cntr < 3000 and Yes
Busy Bit == 1 Yes
looping period < 1s Card State ==
No 5
No Command Successful? TRANS?
No
Is Response OCR for Yes Yes
Card Is HC MMC
HC Get CID from card(Issue No
Spec ver >= 4.0?
CMD2)
No Yes
Card Is LC MMC
Send CMD8 to get
Ext_CSD
No Bus width No High Speed mode Extract the boot partition
fuse == 1? fuse == 0? to set
Yes Yes No
Send switch command Got valid partition?
Send switch command
to change bus width and
to set high frequency
DDR mode Yes
No No Send switch command
4 Switch Successful? Switch Successful? to select partition
Yes Yes
Change uSDHC bus Set operating frequency
width to 40 MHz
Start MMC Boot
Switch Command
Send CMD6 with switch
argument
No
Command Successful?
Yes
Set CMD13 poll timeout
to 100ms
Send CMD13 to read
status
No
Command Successful?
No Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes
Switch failed Switch succeeded Switch failed
End
Figure 10-7. Expansion device (MMC) boot flow (2 of 6)
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Issue CMD8 with HV
(3.3V) SD Boot
Voltage Validation
No Issue CMD8 with LV No
Command Successful? Command Successful?
(1.8V)
Yes Yes
Card is HC/LC HV SD
ver 2.x
Set ACMD41 ARG to LV Card is LC SD Card is LC SD
and HC ver 2.x ver 1.x
Set ACMD41 ARG to HV No
UHSI mode Set ACMD41 ARG bit 29
and HC selected? for FAST BOOT
Yes
Start GPT delay of1s for Set ACMD41 ARG to HV
Set ACMD41 ARG bit 24
ACMD41 and LC
for 1.8v switch
Issue CMD55
Set ACMD41 ARG bit 28
for SDXC power control
No
Command Successful?
Yes Yes
FAST_BOOT Yes
selected? No Loop Cntr < 3000 and
Issue ACMD41 2
looping period < 1s
No
No
Command Successful?
Yes
No UHSI mode No Yes
Busy Bit == 1 Issue ACMD41
selected?
Yes
Bit 24 of response No
2
0 set?
Yes
No Is Response OCR for Yes
Card is LC SD Card is HC SD
HC
Figure 10-8. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 1
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8 SD Boot
Switch Voltage
Send CMD11 to switch
voltage
No
Command Successful?
Yes
No
DATA lines driven low?
Yes
switch supply voltage
to 1.8v
delay for 5ms
set DATA line voltage
high poll timeout to
1ms
No
Voltage high No DATA lines
poll timeout? driven high?
Yes Yes
Switch failed Switch succeeded
2 7
Figure 10-9. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 2
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Get CID from card(Issue
CMD2)
SD Boot
Device Initialization
Yes Yes Set operating frequency
Command Successful? Get RCA (Issue CMD3) Command Successful?
to 20 MHz
No No
Put card data Transfer
5 Mode (Issue CMD7)
No
No
Card State == Send CMD13 to read Yes
TRANS? Command Successful?
status
Yes
Yes
UHSI mode selected? 9
No
Yes Yes Send ACMD6 with bus Command Successful?
Bus width Send CMD55 Command Successful?
fuse <> 1? width argument Yes
No No
No
Change USDHC bus Yes Set CMD13 poll timeout
Success? Check Status
width to 100ms
No
High Speed mode
fuse == 0? Yes
Send CMD6 with high Yes Set operating frequency
No Command Successful?
speed argument to 40 MHz
No
Send CMD43 to select
10
partition 1
No
Command Successful? 4
Yes Set CMD13 poll timeout
to 15ms
FAST_BOOT Yes
Card is eSD
selected? Set CMD13 poll timeout Check Status
No to 1s
9 SD Boot
UHSI init
Check response of
CMD7
Yes No
Card is locked?
No
No Send ACMD6 with Yes
Command Successful? Command Successful? Send CMD55
argument of 4 bit width
Yes
Set CMD13 poll timeout Yes Change USDHC bus
Check Status Success?
to 100ms width
No
No Send CMD6 with clock Get clock speed from
Command Successful?
speed argument fuse
Yes
Change USDHC clock Loopback clock Yes Set loopback clock bit in
speed fuse set? USDHC register
No
Init failed
11
Figure 10-10. Expansion device (MMCSD/eSD/SDXC) boot flow (4 of 6)
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Boot devices
SD Boot USB Boot
Check Status
Serial Boot
Start 5
Send CMD13 to read
status USB Flow
(Serial Boot)
No
Command Successful?
No
Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes
Failure Success Failure
End
4 SD/MMC Boot
Data Read
No Set block length 512
DDR Mode Selected?
bytes (Issue CMD16)
Yes
Init ADMA buffer Yes
Command Successful?
descriptors
No
Send CMD18 (multiple
block read)
Set CMD18 poll timeout
to 1s
Wait for command
completion or timeout
No
Command Successful? 5
Yes
End
Figure 10-11. Expansion device (SD/eSD) boot flow (5 of 6)
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6
eMMC 4.x Boot
Fast Boot
High Speed mode No Set operating frequency
fuse == 0? to 40 MHz
Yes
Set operating frequency
to 20 MHz
Change uSDHC bus
width and configure DLL
Setup ADMA BD[0]
length to 2K and BD[1]
to 32 bytes
Wait for block gap or Yes Wait for block gap or
Set CMD line low Reached block gap? timeout
timeout
No Analyze IVT and setup
Set uSDHC poll counter
to 50ms ADMA buffer descriptors
to final destination
Wait for acknowledge
token or timeout Continue data trasmition
Acknowledge token Yes Set GPT poll counter to Wait for block gap or
accepted? 1s timeout
No
End
2
SD Boot
11 sample point tuning
Set bottom boundary to
current value
Get start point and
ramping step from fuse
Increase current value
Set the USDHC into with ramping step
tuning mode
Yes
Set the USDHC into Exceed limit?
tuning mode
No
Configure the block
Set delay cell number to
length and block number
current value
Configure the block Send CMD19 to request
length and block number the tuning block
Send CMD19 to request
the tuning block Check the tuning status
Check the tuning status Yes
Tuning passed?
No
No
Exceed limit? No
Tuning passed?
Set upper boundary to
Yes last value
Yes
Increase current value
Tuning failed with ramping step Set delay cell number to
Tuning passed average of bottom and
upper boundary value
4 10
Figure 10-12. Expansion device boot flow (6 of 6)
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Boot devices
10.6.6.3 SD, eSD, and SDXC
After the normal boot mode initialization begins, the SD/eSD/SDXC frequency is set to
347.22 kHz. During the identification phase, the SD/eSD/SDXC card voltage validation
is performed. During the voltage validation, the boot code first checks with the high-
voltage settings; if that fails, it checks with the low-voltage settings.
The capacity of the card is also checked. The boot code supports the high-capacity and
low-capacity SD/eSD/SDXC cards after the voltage validation card initialization is done.
During the card initialization, the ROM boot code attempts to set the boot partition for all
SD, eSD, and SDXC devices. If this fails, the boot code assumes that the card is a normal
SD or SDXC card. If it does not fail, the boot code assumes it is an eSD card. After the
initialization phase is over, the boot code switches to a higher frequency (25 MHz in the
normal-speed mode or 50 MHz in the high-speed mode). The ROM also supports the
FAST_BOOT mode booting from the eSD card. This mode can be selected by the
BOOT_CFG1[0] (Fast Boot).
For the UHSI cards, the clock speed fuses can be set to SDR50 or SDR104 on USDHC1,
USDHC2 ports. This enables the voltage switch process to set the signaling voltage to 1.8
V during the voltage validation. The bus width is fixed at a 4-bit width and a sampling
point tuning process is needed to calibrate the number of the delay cells. If the SD
Loopback Clock eFuse is set, the feedback clock comes directly from the loopback SD
clock, instead of the card clock (by default). The SD clock speed can be selected by the
BOOT_CFG1[5:4], and the SD Loopback Clock is selected by the BOOT_CFG1[2].
The UHSI calibration start value (MMC_DLL_DLY[6:0]) and the step value
SD_CALIBRATION_STEP[1:0] can be set to optimize the sample point tuning process.
If the SD Power Cycle Enable eFuse is 1, the ROM sets the SD_RST pad low, waits for 5
ms, and then sets the SD_RST pad high. If the SD_RST pad is connected to the SD
power supply enable logic on board, it enables the power cycle of the SD card. This may
be crucial in case the SD logic is in the 1.8 V states and must be reset to the 3.3 V states.
The SDR50 and SDR104 boots are not supported on the USDHC1 and USDHC2 ports
because there are no reset signals for those ports when connected in the IOMUX.
10.6.6.4 Redundant boot support for expansion device
The ROM supports the redundant boot for an expansion device. The primary or
secondary image is selected, depending on the PERSIST_SECONDARY_BOOT setting.
(see Table 10-8).
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If the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address 0x0 for the
primary image.
If the PERSIST_SECONDARY_BOOT is 1, the boot ROM reads the secondary image
table from address 0x200 on the boot media and uses the address specified in the table.
Table 10-31. Secondary image table format
Reserved (chipNum)
Reserved (driveType)
tag
firstSectorNumber
Reserved (sectorCount)
Where:
• The tag is used as an indication of the valid secondary image table. It must be
0x00112233.
• The firstSectorNumber is the first 512-byte sector number of the secondary image.
For the secondary image support, the primary image must reserve the space for the
secondary image table. See this figure for the typical structures layout on an expansion
device.
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Boot devices
Reserved For MBR 0x00000000
(optional)
0x00000200
Reserved for Secondary
Image Table (optional)
0x00000400
Program Image (Starting
From IVT)
Media Partitions
Figure 10-13. Expansion device structures layout
For the Closed mode, if there are failures during primary image authentication, the boot
ROM turns on the PERSIST_SECONDARY_BOOT bit (see Table 10-8) and performs
the software reset. (After the software reset, the secondary image is used.)
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10.6.7 Serial NOR/EEPROM through LPSPI
The chip supports booting from serial memory devices, such as EEPROM and serial
flash, using the LPSPI.
These ports are available for serial boot: LPSPI interfaces.
10.6.7.1 Serial NOR/EEPROM eFUSE configuration
The boot ROM code determines the type of device using the following parameters,
provided by the eFUSE settings during boot.
Table 10-32. Serial NOR/EEPROM boot eFUSE descriptions
Fuse Config Definition GPIO Shipped Settings
value
RECOVERY_BOOT_ OEM EEPROM recovery No 0 0 - Disabled
EN (0xC70[24]) enable
1 - Enabled
SPI INSTANCE OEM Port select No 00 00 - LPSPI1
(0xC70[26:25])
01 - LPSPI2
10 - LPSPI3 (if applicable in the device)
11 - LPSPI4 (if applicable in the device)
SPI_MEM_SPEED OEM LPSPI Speed select No 00 00 - 20 MHz
(0xC70[28:27])
01 - 10 MHz
10 - 5 MHz
11 - 2 MHz
The LPSPIn block can be used as a boot device using the LPSPI interface for the serial
ROM boot. The SPI interface is configured to operate at speed specified by
SPI_MEM_SPEED fuse field.
The boot ROM copies 4 KB of data from the serial ROM device to the internal RAM.
After checking the Image Vector Table header value (0xD1) from the program image, the
ROM code performs a DCD check. After a successful DCD extraction, the ROM code
extracts the destination pointer and length of image from the Boot Data Structure to be
copied to the RAM device from where the code execution occurs.
NOTE
The Initial 4 KB of program image must contain the IVT, DCD,
and the Boot Data Structures.
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Program image
10.7 Program image
This section describes the data structures that are required to be included in the user's
program image. The program image consists of:
• Image vector table—a list of pointers located at a fixed address that the ROM
examines to determine where the other components of the program image are
located.
• Boot data—a table that indicates the program image location, program image size in
bytes, and the plugin flag.
• Device configuration data—IC configuration data.
• User code and data.
10.7.1 Image Vector Table and Boot Data
The Image Vector Table (IVT) is the data structure that the ROM reads from the boot
device supplying the program image containing the required data components to perform
a successful boot.
The IVT includes the program image entry point, a pointer to Device Configuration Data
(DCD) and other pointers used by the ROM during the boot process. The ROM locates
the IVT at a fixed address that is determined by the boot device connected to the Chip.
The IVT offset from the base address for each boot device type is defined in the table
below. The location of the IVT is the only fixed requirement by the ROM. The remainder
or the image memory map is flexible and is determined by the contents of the IVT.
Table 10-33. Image Vector Table Offset and Initial Load Region Size
Boot Device Type Image Vector Table Offset
FlexSPI NOR 4 Kbyte = 0x1000 bytes
SD/MMC/eSD/eMMC/SDXC 1 Kbyte = 0x400 bytes
SPI NOR/EEPROM 1 Kbyte = 0x400 bytes
SEMC NAND
FlexSPI NAND
Serial boot 0Kbyte = 0 byte
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Figure 10-14. Image Vector Table
10.7.1.1 Image vector table structure
The IVT has the following format where each entry is a 32-bit word:
Table 10-34. IVT format
header
entry: Absolute address of the first instruction to execute from the image
reserved1: Reserved and should be zero
dcd: Absolute address of the image DCD. The DCD is optional so this field may be set to NULL if no DCD is required. See
Device Configuration Data (DCD) for further details on the DCD.
boot data: Absolute address of the boot data
self: Absolute address of the IVT. Used internally by the ROM
csf: Absolute address of the Command Sequence File (CSF) used by the HAB library. See High-Assurance Boot (HAB) for
details on the secure boot using HAB. This field must be set to NULL if a CSF is not provided in the image
reserved2: Reserved and should be zero
Figure 10-15 shows the IVT header format:
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Program image
Tag Length Version
Figure 10-15. IVT header format
where:
Tag: A single byte field set to 0xD1
Length: a two byte field in big endian format containing the overall length of the IVT,
in bytes, including the header. (the length is fixed and must have a value of 32 bytes)
Version: A single byte field set to 0x40/0x41/0x42/0x43/0x44/0x45
10.7.1.2 Boot data structure
The boot data must follow the format defined in the table found here, each entry is a 32-
bit word.
Table 10-35. Boot data format
start Absolute address of the image
length Size of the program image
plugin Plugin flag (must be 0, not supported in this device, this field is ignored by the ROM)
10.7.2 Device Configuration Data (DCD)
Upon reset, the chip uses the default register values for all peripherals in the system.
However, these settings typically are not ideal for achieving the optimal system
performance and there are even some peripherals that must be configured before they can
be used.
The DCD is a configuration information contained in the program image (external to the
ROM) that the ROM interprets to configure various peripherals on the chip.
For example, some components (such as SDRAM) require some sequence of register
programming as a part of the configuration before it is ready to be used. The DCD feature
can be used to program the SEMC register to the optimal settings.
The ROM determines the location of the DCD table based on the information located in
the Image Vector Table (IVT). See Image Vector Table and Boot Data for more details.
The DCD table shown below is a big-endian byte array of the allowable DCD commands.
The maximum size of the DCD is limited to 1768 B.
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Header
[CMD]
[CMD]
...
Figure 10-16. DCD data format
The DCD header is 4 B with the following format:
Tag Length Version
Figure 10-17. DCD header format
where:
Tag: A single-byte field set to 0xD2
Length: a two-byte field in the big-endian format containing the overall length of the DCD
(in bytes) including the header
Version: A single-byte field set to 0x41
10.7.2.1 Write data command
The write data command is used to write a list of given 1-, 2- or 4-byte values (or
bitmasks) to a corresponding list of target addresses.
The Value/Mask fields are always 32-bits. If the parameter field specifies a smaller size,
then the extra bytes must be zero.
The format of the write data command (in a big-endian byte array) is shown in this table:
Table 10-36. Write data command format
Tag Length Parameter
Address
Value/Mask
[Address]
[Value/Mask]
Table continues on the next page...
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Program image
Table 10-36. Write data command format (continued)
...
[Address]
[Value/Mask]
where:
Tag: a single-byte field set to 0xCC
Length: a two-byte field in a big-endian format, containing the length of the Write Data
Command (in bytes) including the header
Address: the target address to which the data must be written
Value/Mask: the data value (or bitmask) to be written to the preceding address
The parameter field is a single byte divided into bitfields as follows:
Table 10-37. Write data command parameter field
7 6 5 4 3 2 1 0
flags bytes
where
bytes: the width of the target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only specific bits may be overwritten at the target address
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)
One or more target address and value/bitmask pairs can be specified. The same bytes' and
flags' parameters apply to all locations in the command.
When successful, this command writes to each target address in accordance with the flags
as follows:
Table 10-38. Interpretation of write data command flags
"Mask" "Set" Action Interpretation
0 0 *address = val_msk Write value
0 1 *address = val_msk Write value
1 0 *address &= ~val_msk Clear bitmask
1 1 *address |= val_msk Set bitmask
NOTE
If any of the target addresses does not have the same alignment
as the data width indicated in the parameter field, none of the
values are written.
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If any of the values are larger or any of the bitmasks are wider
than permitted by the data width indicated in the parameter
field, none of the values are written.
If any of the target addresses do not lie within the allowed
region, none of the values are written. The list of allowable
blocks and target addresses for the chip are provided below.
Table 10-39. Valid DCD address ranges
Address range Start address Last address
IOMUX Control (IOMUXC) registers 0x400E_8000 0x400E_8717
ANADIG PLL registers 0x40C8_4000 0x40C8_4393
CCM registers 0x40CC_0000 0x40CC_751F
SEMC registers 0x400D_4000 0x400D_412F
GPT1 registers 0x400E_C000 0x400E_C027
FlexSPI1 registers 0x400C_C000 0x400C_C42B
FlexSPI2 registers 0x400D_0000 0x400D_042B
10.7.2.2 Check data command
The check data command is used to test for a given 1-, 2-, or 4-byte bitmasks from a
source address.
The check data command is a big-endian byte array with the format shown in this table:
Table 10-40. Check data command format
Tag Length Parameter
Address
Mask
[Count]
where:
Tag: a single-byte field set to 0xCF
Length: a two-byte field in the big-endian format containing the length of the check data
command (in bytes) including the header
Address: the source address to test
Mask: the bit mask to test
Count: an optional poll count; If the count is not specified, this command polls
indefinitely
until the exit condition is met. If count = 0, this command behaves as for the NOP.
The parameter field is a single byte divided into bitfields, as follows:
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Program image
Table 10-41. Check data command parameter field
7 6 5 4 3 2 1 0
flags bytes
where
bytes: the width of target locations in bytes (either 1, 2, or 4)
flags: control flags for the command behavior
Data Mask = bit 3: if set, only the specific bits may be overwritten at a target address
(otherwise all bits may be overwritten)
Data Set = bit 4: if set, the bits at the target address are overwritten with this flag
(otherwise it is ignored)
This command polls the source address until either the exit condition is satisfied, or the
poll count is reached. The exit condition is determined by the flags as follows:
Table 10-42. Interpretation of check data command flags
"Mask" "Set" Action Interpretation
0 0 (*address & mask) == 0 All bits clear
0 1 (*address & mask) == mask All bits set
1 0 (*address & mask)!= mask Any bit clear
1 1 (*address & mask)!= 0 Any bit set
NOTE
If the source address does not have the same alignment as the
data width indicated in the parameter field, the value is not
read.
If the bitmask is wider than permitted by the data width
indicated in the parameter field, the value is not read.
10.7.2.3 NOP command
This command has no effect.
The format of the NOP command is a big-endian four-byte array, as shown in this table:
Table 10-43. NOP command format
Tag Length Undefined
where:
Tag: a single-byte field set to 0xC0
Length: a two-byte field in big endian containing the length of the NOP command in bytes
(fixed to a
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value of 4)
Undefined: this byte is ignored and can be set to any value.
10.8 External Memory Configuration Data (XMCD)
For comprehensive or feature-rich applications, the on-chip RAM may not be enough for
the application use. Usually, such an application requires a large capacity of RAM and
needs to run on the external RAM for high execution performance. However, enabling
the external RAM on the SoC is relatively complicated, and the settings are SoC specific.
The Boot ROM on the SoC simplifies the external RAM configuration by introducing the
XMDC. The XCMD data structure resides at offset 0x40 starting from IVT header.
The XMDC consists of a XMCD header and a memory specific configuration block. On
this SoC, the following types of external RAM devices are supported. Each type of RAM
device has a specific configuration block.
• HyperRAM/APMemory via FlexSPI – FlexSPI RAM configuration block
• SDRAM via SEMC – SEMC SDRAM Configuration block
10.8.1 XMCD header
The XMCD header resides at the fixed offset 0x40 from the IVT header. The header
definition is as follows.
Table 10-44. XMC Header Definition
[31:28] [27:24] [23:20] [19:16] [15:12] [11:0]
Tag Version Memory Interface Instance Configuration Configuration
Block Type block size
Valid value = 0xC Fixed value of '0' 0 - FlexSPI SoC defined 0 - Simplified Configuration block
instances Configuration size (including the
1 - SEMC
Option Block XMC Header itself).
1 - Full
Configuration Block
NOTE
There is an optional integrity check of the XMC by
programming the CRC checksum to the fuse. The ROM can
perform the integrity check before adopting the XMC block
settings. It calculates the CRC check based on the value of the
"Configuration block size" field. ROM determines whether to
enable the XMC integrity check by checking the
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XMC_CHECK_EN(0x970[14]) fuse field and the fuse word
0xC90. Details of the CRC algorithm used for the integrity
check are provided in the following table.
Table 10-45. CRC Algorithm Details
Description Value
Width 32
Polynomial 0x04C11BD7
Init Value 0xFFFFFFFF
Reflect In FALSE
Reflect Out FALSE
XOR Out 0x00000000
The following procedure shows the steps in the CRC calculation:
1. CRC initialization
• Set the initial CRC as 0xFFFFFFFF, which clears the CRC byte count to 0.
2. CRC calculation
• Start the calculation from the first byte of the XMC header. Total calculation
bytes are "Configuration block size" bytes.
3. CRC finalization
• Check if the CRC byte count is 4-bytes aligned. If it is not 4-bytes aligned, then
pad it with the necessary zeroes to finalize the CRC. Otherwise, return to the
current computed CRC.
10.8.2 FlexSPI RAM configuration block
The XMCD offers a simplified FlexSPI RAM configuration option block which can meet
the typical usage of the HyperRAM or APMemory devices.
However, the user application may need to enable the advanced features of the external
RAM which cannot be configured by the simplified configuration option. In this case, the
XMCD also offers the complete 512-bytes FlexSPI RAM configuration block which
supports flexible configuration.
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10.8.2.1 Simplified FlexSPI RAM configuration option
The simplified FlexSPI RAM configuration option structure is shown in the following
tables.
Table 10-46. Simplified FlexSPI RAM Configuration Option 0
[31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:0]
Tag Option Size device type Reserved Misc. Maximum Size in MB
Frequency
Fixed to 0x0C option words - 1 0 - HyperRAM Reserved For HyperRAM SoC specific 0 - Auto
definitions detection
1 - APMemory 0 - 1.8V
Others - Size in
1 - 3V
MB
Table 10-47. Simplified FlexSPI RAM Configuration Option 1
[31:28] [27:24] [23:20] [19:16] [15:8] [7:4] [3:0]
RAM_CONNEC Reserved DQS_PINMUX_ PINMUX ROUP Reserved write dummy read dummy
TION GROUP cycles cycles
0 - PORTA Reserved 0 - Default 0 - Primary Reserved 0 - Auto 0 - Auto
Group group detection detection
1 - PORTB
1 - Secondary 1 - Secondary Others - Others -
group group Specified Specified
dummy cycles dummy cycles
10.8.2.2 Full FlexSPI RAM configuration block
The following table lists the data structure of the full 512-bytes FlexSPI RAM
Configuration Block.
Table 10-48. Full HyperRAM/APMemory Configuration Block Structure
Name Offset Size(Bytes) Description
Tag 0x000 4 0x62666366, ascii: "fcfb"
Version 0x004 4 [07:00] bugfix
[15:08] minor
[23:16] major = 1
[31:24] ascii 'V'
Reserved 0x008 4 Reserved
readSampleClkSrc 0x00c 1 0 – Internal loopback
1 – loopback from DQS pad
2 - Reserved
3 – Flash provided DQS
Table continues on the next page...
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External Memory Configuration Data (XMCD)
Table 10-48. Full HyperRAM/APMemory Configuration Block Structure
(continued)
Name Offset Size(Bytes) Description
csHoldTime 0x00d 1 Serial Flash CS Hold Time
Recommend default value is 0x03
csSetupTime 0x00e 1 Serial Flash CS setup time
Recommended default value is 0x03
columnAdressWidth 0x00f 1 3 – For HyperFlash/HyperRAM
12/13 – For Serial NAND. See datasheet to find correct value.
0 – Other devices
deviceModeCfgEnable 0x010 1 Device Mode Configuration Enable feature
0 – Disabled
1 – Enabled
deviceModeType 0x11 1 Device Mode Type
0 – Generic
1 – Quad Enable
2 – SPI-to-xSPI Mode
3 – xSPI-to-SPI mode
waitTimeCfgCommands 0x12 2 Time in terms of 100us
This field is defined for the mode switch from SPI to xSPI mode or
vice versa.
deviceModeSeq 0x014 4 Sequence parameter for device mode configuration
[7:0] - Number of sequences
[15:8] - Sequence Index
[31:16] - Reserved, fixed to 0
deviceModeArg 0x018 4 Device Mode argument, effective only when deviceModeCfgEnable
=1
configCmdEnable 0x01c 1 Config Command Enable feature
0 – Disabled
1 – Enabled
configModeType 0x01d 3 This field has the same definititions as "deviceModeType"
byte 0 - configModeType for configCmdSeq[0]
byte 1 - configModeType for configCmdSeq[1]
byte 2 - configModeType for configCmdSeq[2]
configCmdSeqs 0x020 12 Sequences for Config Command allows 3 separate configuration
command sequences.
For each configCmdSeq, the definition of the word is:
[7:0] - Number of sequences
[15:8] - Sequence Index
[31:16] - Reserved, fixed to 0
Table continues on the next page...
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Table 10-48. Full HyperRAM/APMemory Configuration Block Structure
(continued)
Name Offset Size(Bytes) Description
Reserved 0x02c 4 Reserved
cfgCmdArgs 0x030 12 Arguments for each separate configuration command sequence.
Reserved 0x03c 4 Reserved
controllerMiscOption 0x040 4 Bit0 – differential clock enable
Bit1 – CK2 enable
Bit2 – ParallelModeEnable
Bit3 – wordAddressableEnable
Bit4 – Half-Speed access enable
Bit5 – Pad Setting Override Enable
Bit6 – DDR Mode Enable
Bit7 - Pad Setting Override Enable
Bit 8 - Second Pinmux group
Bit 9 - Second DQS pin mux group
Bit 10 - Write Mask Enable
Bit 11 - Write Opt1 Clear
deviceType 0x044 1 1 – Serial NOR
2 – Serial NAND
3 - Serial RAM
sflashPadType 0x045 1 1 – Single pad
2 – Dual pads
4 – Quad pads
8 – Octal pads
serialClkFreq 0x046 1 Chip specific value
lutCustomSeqEnable 0x047 1 0 – Use pre-defined LUT sequence index and number
1 - Use LUT sequence parameters provided in this block
Reserved 0x048 8 Reserved
sflashA1Size 0x050 4 For SPI NOR, need to fill with actual size
For SPI NAND, need to fill with actual size * 2
sflashA2Size 0x054 4 For SPI NOR, need to fill with actual size
For SPI NAND, need to fill with actual size * 2
sflashB1Size 0x058 4 For SPI NOR, need to fill with actual size
For SPI NAND, need to fill with actual size * 2
sflashB2Size 0x05c 4 For SPI NOR, need to fill with actual size
For SPI NAND, need to fill with actual size * 2
csPadSettingOverride 0x060 4 Set to 0 if it is not supported
sclkPadSettingOverride 0x064 4 Set to 0 if it is not supported
dataPadSettingOverride 0x068 4 Set to 0 if it is not supported
Table continues on the next page...
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Table 10-48. Full HyperRAM/APMemory Configuration Block Structure
(continued)
Name Offset Size(Bytes) Description
dqsPadSettingOverride 0x06c 4 Set to 0 if it is not supported
timeoutInMs 0x070 4 Maximum wait time during read/write
commandInterval 0x074 4 Unit: ns.
Currently, it is for SPI NAND at the high working frequency. For the
serial NAND and serial RAM device, this field is 0.
dataValidTime 0x078 4 Time from clock edge to data valid edge. Unit: ns.
This field takes effect when the FlexSPI Root clock is less than
100MHz, and the read sample clock source is a device provided
DQS signal without CK2 support.
[31:16] - data valid time for DLLB in terms of 0.1ns
[15:0] - data valid time for DLLA in terms of 0.1ns
busyOffset 0x07c 2 Busy bit offset. Valid range :0-31.
busyBitPolarity 0x07e 2 0 – 1 represents busy
1 – 0 represents busy
lookupTable 0x080 16*4*4 Lookup table
lutCustomSeq 0x180 4*12 Customized LUT sequence. See the note at the end of the table for
details.
Reserved 0x1b0 5*16 Reserved
NOTE
• LUT for read must be placed at LUT entry 0.
• LUT for write must be placed at LUT entry 9.
10.8.2.3 Example of XMCD for HyperRAM support
The following table shows an example of XMCD for HyperRAM support.
Table 10-49. Example XMCD block for HyperRAM
Offset Field Description
0 0xC000_0008 Tag = 0x0C
Version = 0
Memory Interface: FLEXSPI
Instance: 1 - First Instance
Configuration block type: Simplified
Configuration block size: 8 (4-byte
header + 4-byte option block)
1 0xC000_0700 Tag = 0x0C
Option_Size = 0
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Table 10-49. Example XMCD block for HyperRAM
Offset Field Description
DeviceType: HyperRAM
Reserved: 0
Misc: HyperRAM 1V8
Max Freq: 7
Memory Size: Auto-detection
10.8.3 SDRAM support
The XMCD also supports the SDRAM configuration via the SEMC SDRAM
Configuration Block, which offers both the simplified configuration option and the fully
customizable configuration block.
10.8.3.1 SEMC SDRAM configuration block structure
The SEMC SDRAM configuration block structure is shown in the following table.
Table 10-50. SDRAM Configuration Block structure
Offset Width (bytes) Field Description
0 1 magic_number Must be 0xA1
1 1 version Set to 1 for this implementation
2 1 config_option 0x00 - Simplified configuration. Select SDRAM CS0 as default
and can only configure clk_MHz, sdram0_size_kB, and
port_size.
0xFF - Full configuration. Must configure all fields.
3 1 clk_MHz Set the working frequency in the unit of MHz
4 4 sdram0_size_kB Set the memory size of SDRAM CS0 in the unit of kilobytes.
Range: 4~4*1024*1024
8 1 port_size Port size of SDRAM
0 - 8bit
1 - 16bit
2 - 32bit
Others - Invalid value
9 1 pin_config_pull Pull config of the SDRAM GPIO pin
0 – forbidden
1 – pull up
2 – pulldown
Table continues on the next page...
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Table 10-50. SDRAM Configuration Block structure
(continued)
Offset Width (bytes) Field Description
3 – no pull
Others - Invalid value
10 1 pin_config_drive_streng Driver config of SDRAM GPIO pin
th
0 – high driver
1 – normal driver
Others - Invalid value
11 1 mux_rdy SDRAM CSn device selection
1 - SDRAM CS1
2 - SDRAM CS2
3 - SDRAM CS3
Others – Invalid for SDRAM, select other external devices
NOTE: To select CS1/CS2/CS3, you can only use one of the
five items: mux_rdy, mux_csx0,
mux_csx1,mux_csx2 ,mux_csx3. If using one item,
the other items cannot be used, set them to 0.
12 1 mux_csx0 SDRAM CSn device selection
1 - SDRAM CS1
2 - SDRAM CS2
3 - SDRAM CS3
Others – Invalid for SDRAM, select other external devices
13 1 mux_csx1 SDRAM CSn device selection
1 - SDRAM CS1
2 - SDRAM CS2
3 - SDRAM CS3
Others – Invalid for SDRAM, select other external devices
14 1 mux_csx2 SDRAM CSn device selection
1 - SDRAM CS1
2 - SDRAM CS2
3 - SDRAM CS3
Others – Invalid for SDRAM, select other external devices
15 1 mux_csx3 SDRAM CSn device selection
1 - SDRAM CS1
2 - SDRAM CS2
3 - SDRAM CS3
Others – Invalid for SDRAM, select other external devices
16 1 bank Bank numbers of SDRAM device
0 – 4 banks
1 – 2 banks
Table continues on the next page...
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Table 10-50. SDRAM Configuration Block structure
(continued)
Offset Width (bytes) Field Description
Others - Invalid value
17 1 burst_len Burst length
0–1
1–2
2–4
3–8
Others - Invalid value
18 1 column_addr_bit_num Column address bit number
0 – 12bit
1 – 11bit
2 – 10bit
3 – 9bit
4 – 8bit
Others - Invalid value
19 1 cas _ latency CAS Latency
1–1
2–2
3–3
Others - Invalid value
20 1 write_recovery_ns Write recovery time in unit of nanosecond.
This could help to meet tWR timing requirement by the
SDRAM device.
21 1 refresh_recovery_ns Refresh recovery time in unit of nanosecond.
This could help to meet tRFC timing requirement by the
SDRAM device.
22 1 act2readwrite_ns Act to read/write wait time in unit of nanosecond.
This could help to meet tRCD timing requirement by the
SDRAM device.
23 1 precharge2act_ns Precharge to active wait time in unit of nanosecond.
This could help to meet tRP timing requirement by SDRAM
device.
24 1 act2act_banks_ns Active to active wait time between two different banks in unit
of nanosecond.
This could help to meet tRRD timing requirement by the
SDRAM device.
25 1 refresh2refresh_ns Auto refresh to auto refresh wait time in unit of nanosecond.
This could help to meet tRFC timing requirement by the
SDRAM device.
26 1 selfref_recovery_ns Self refresh recovery time in unit of nanosecond.
Table continues on the next page...
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Table 10-50. SDRAM Configuration Block structure
(continued)
Offset Width (bytes) Field Description
This could help to meet tXSR timing requirement by the
SDRAM device.
27 1 act2prechage_min_ns ACT to Precharge minimum time in unit of nanosecond
This could help to meet tRAS(min) timing requirement by
SDRAM device.
28 4 act2prechage_max_ns ACT to Precharge maximum time in unit of nanosecond.
This could help to meet tRAS(max) timing requirement by the
SDRAM device.
32 4 refreshperiod_perrow_n Refresh timer period in unit of nanosecond/
s
Set to (tREF(ms) * 1000000/rows) value.
36 4 mode_register Define the specific mode of operation of SDRAM.
Set to the value required by SDRAM device.
NOTE: The low bits of the input value must correspond to
the low bits of the mode register.
40 4 sdram0_base Base address of SDRAM CS0
Range: 0x80000000~0xDFFFFFFF
NOTE: SDRAM CS0~CS3 addresses cannot overlap and
when CSn is not being used, set the address to 0.
44 4 sdram1_base Base address of SDRAM CS1
Range: 0x80000000~0xDFFFFFFF
48 4 sdram2_base Base address of SDRAM CS2
Range: 0x80000000~0xDFFFFFFF
52 4 sdram3_base Base address of SDRAM CS3
Range: 0x80000000~0xDFFFFFFF
56 4 sdram1_size_kB Set the memory size of SDRAM CS1 in unit of kbytes
Range: 4~4*1024*1024
60 4 sdram2_size_kB Set the memory size of SDRAM CS2 in unit of kbytes
Range: 4~4*1024*1024
64 4 sdram3_size_kB Set the memory size of SDRAM CS3 in unit of kbytes
Range: 4~4*1024*1024
10.8.3.2 Example for SDRAM support (32-bit)
The following table shows an example for the SDRAM support (32-bit) on this device.
Table 10-51. Example SDRAM Configuration Block
Offset Field Description
0 0xC010_000D Tag = 0xC
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Table 10-51. Example SDRAM Configuration Block (continued)
Offset Field Description
Version = 0
Memory Interface: SEMC
Instance: 0 - ignored
Configuration block type: 0 - Ignored
(Handled inside the SDRAM
configuration structure)
Configuration block size: 13 (4-byte
header + 9-byte option block)
1 0xA600_01A1 Magic_number = 0xA1
Version = 1
Config_option: Simplified
SDRAM clock: 166MHz
2 0x0001_0000 SDRAM CS0 size: 64MBytes
3 0x02 Port_size: 32-bit
10.9 Serial Boot (Serial Downloader)
The Serial boot provides a means to download a boot image to the chip and execute the
image over the following serial peripherals:
• LPUART
• USB-HID
The default enabled peripherals for active peripheral detection is determined by the
combination of eFUSEs and Boot Mode pins.
The boot ROM can detect the active peripherals and shut down all inactive peripherals
before any communications between the host and the device.
The high-level serial boot flow is provided below. Details of communication protocols,
sequences, and flows can be found in the following sections.
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No
Serial Boot All peripherals UART is
Enter Serial Boot Yes No USB is enabled?
Enabled? are disabled? enabled?
Yes Yes No
No
Configure UART Configure USB
Lock the chip Yes
Program WDOG Enter Active
WDOG_ENABLE
for X seconds Yes peripheral
==1?
(Default X=64) detection
No No
Active WDOG_ENABLE
Peripheral No ==1 &WDOG Yes Reset
Detected? timeout
Yes
Establish
Read Remaining Read Initial Image Shutdown inactive
Communication to
Image from Host from Host peripherals
host
Yes No
WDOG_ENABLE
Successful? Successful? No ==1 & WDOG Yes
timeout
No
Yes
Image
Pass? No
authentication
Yes
Execute Image
Figure 10-18. Serial Boot Flow
The communication protocol for serial boot mode is compatible with the widely-used
MCUBOOT protocol in the NXP MCU products. Using simplified protocol, only two
types of phase are supported:
1. Command-only phase. “get-property” command is supported, but the supported
properties are limited to:
• Bootloader version
• Target version
• Maximum payload size in the packet
• Security State
• Last Status
For all other properties queried by the host, the boot ROM responds with unknown
property error code.
2. Data-only phase. Boot ROM treats the data from the host as data streaming; no
command phase is needed in this phase.
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10.9.1 MCU-BOOT protocol
The section demonstrates the general protocol for the packet transfers between the host
and the boot ROM. The description includes the transfer of packets for different
transactions, such as command with no data phase and data only phase. The next section
describes various packet types used in a transaction.
• Each command sent from the host is replied to with a response command.
• Each data sent from the host is replied with an ACK at the packet level.
• In all protocols (described in the following subsections), the Ack sent in response to
a Command or Data packet can arrive at any time before, during, or after the
Command/Data packet has processed.
Command-only phase
The protocol for command-only phase content:
• Command packet (from the host)
• Response command packet (to host)
Host Target
Data packet 0
Process Data
ACK
.
.
. packet
Last Data
Process Data
ACK
Figure 10-19. Protocol for a command-only phase
Data-only phase
The protocol for data-only phase content:
• A data packet (from the host)
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Host Target
Data packet 0
Process Data
ACK
.
.
.
Last Data packet
Process Data
ACK
Figure 10-20. Protocol for a data-only phase
There are 2 types of packet protocol defined for the peripherals with or without built-in
flow control.
• Serial packet protocol. It is defined for UART. A packet level flow control
mechanism and error-detection mechanism is designed in this protocol.
• HID packet protocol. It is defined for USB-HID, the USB built-in flow control and
error-detection is used behind this protocol.
In each protocol, several packet types are defined to let the boot ROM:
• Establish the communication to a host
• Recognize different phases (command-only/ data-only)
10.9.1.1 Packet Types for Serial Packet Protocol
There are 5 types of packets supported by the Serial Packet Protocol:
• Ping packet
• Ping Response packet
• Framing packet
• Command packet
• Data packet
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10.9.1.1.1 Ping packet
The ping packet is the first packet sent from a host to target, in order to establish a
connection on a UART peripheral for auto-baudrate detection. For other peripherals, it is
optional.
Table 10-52. Ping packet format
Byte # Value Name
0 0x5A Start Byte
1 0xA6 Packet Type: Ping packet
10.9.1.1.2 Ping response packet
In response to a Ping packet, the target sends a Ping Response packet.
Table 10-53. Ping response packet format
Byte # Value Parameter
0 0x5A Start Byte
1 0xA7 Packet Type: Ping Response packet
2 Protocol version: bug fix
3 Protocol version: minor
4 Protocol version: major
5 Protocol name: ‘P’ (0x50)
6 Reserved: set to 0
7 Reserved: set to 0
8 crc16_low
9 crc16_high
NOTE
1. Please refer to CRC algorithm for details regarding the
CRC algorithm.
2. Byte 0 - 7 are including in the CRC calculation.
Example ping packet:
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Figure 10-21. Ping Command Protocol
10.9.1.1.3 Framing Packet
The framing packet is for flow control and error detection, for the communications links
that do not have such features built-in. The framing packet structure sits between the link
layer and the command layer. It wraps command and data packets as well.
NOTE
Command packet is optional in ROM
Every framing packet containing data sent in one direction results in a synchronizing
response framing packet in the opposite direction.
The framing packet described in the section is for serial peripherals, including UART
The framing packet format for serial packet is provided below:
Table 10-54. Framing packet format
Byte # Data type Value Field Notes
0 Framing header 0x5a Start Byte Must be 0x5A
1 0xA5/0xA4 Packet Type 0xA5 for Data packet
0xA4 for command packet
2 2 Payload Size 16-bit little-endian, max size is 512 bytes
4 2 CRC-16 checksum CRC checksum covers the whole packet
including start byte, packet type, payload
size, and payload data, but does not
contain the CRC checksum bytes
6…n Payload payload data The payload of the data Max size is 512
A particular framing packet that contains only a start byte and a packet type is employed
for synchronization between the host and target. The format details are provided below:
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Table 10-55. Special Framing Packet Format
Byte # Value Parameter
0 0x5A Start Byte
1 0xAn Packet Type:
0xA1 - Ack: The previous packet was received successfully; the sending of
more data is allowed
0xA2 - NAK: The previous packet was corrupted, and needs to be re-sent.
0xA3 - Abort: Data transfer is aborted.
10.9.1.1.4 CRC algorithm
This section provides details about the CRC-16 algorithm.
The CRC is computed over each byte in the framing packet header, excluding the crc16
field itself, plus all the payload bytes. The CRC algorithm is the XMODEM variant of
CRC-16.
The Characteristics of the XMODEM variants are:
Table 10-56. Characteristics of the XMODEM variant
Name Value
width 16
polynomial 0x1021
init value 0x0000
reflect in false
reflect out false
xor out 0x0000
check result 0x31C3
10.9.1.1.5 Command Packet
The command packet carries a 32-bit command header and a list of 32-bit parameters.
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Command Header Format
Figure 10-22. Command Packet and Command Header Format
The header is followed by 32-bit parameters up to the value of the ParameterCount field
specified in the header. Because a command packet is 32 bytes long, only 7 parameters
can fit into the command packet.
Command packets are also used by the target to send responses back to the host.
Command packets and data packets are embedded into framing packets for all the
transfers.
The supported command and response list is provided in the following tables:
Table 10-57. Supported command list
Command Name
0x07 GetProperty
Table 10-58. Supported response list
Response Name
0xA0 Generic Response
0xA7 GetProperty Response - used for sending a response to
GetProperty command only
10.9.1.1.6 Data Packet
The data packet carries just the data that the host sends to target. The data packet is also
wrapped within a framing packet to ensure the correct packet data is received.
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The contents of a data packet are simply the data itself. There are no other fields so that
the most data per packet can be transferred. Framing packets are responsible for ensuring
that the correct packet data is received.
The host must send the data packet with the maximum payload size until the last packet,
the packet with smaller payload size is treated as the last packet during the transfer.
10.9.1.1.7 Response packet
The responses are carried using the same command packet format wrapped with framing
packet data. Types of responses supported in the boot ROM include:
• GenericResponse
• GetPropertyResponse
GenericResponse: After the boot ROM has processed a command, the boot ROM sends
a generic response with status and command tag information to the host. The generic
response is the last packet in the command protocol sequence. The generic response
packet contains the framing packet data and the command packet data (with generic
response tag = 0xA0) and a list of parameters. The parameter count field in the header is
always set to 2, for status code and command tag parameters.
The GenericResponse parameters are provided below:
Table 10-59. GenericResponse parameters
Byte # Parameter Description
0-3 Status code The status codes are errors encountered during the execution
of a command by the target. If a command succeeds, then a
success code is returned.
4-7 Command tag The command tag parameter identifies the response to the
command sent by the host.
NOTE
GenericResponse in ROM is only used as a response for all
unsupported commands, in which:
• Status = 10000 (Unknown command)
• Command tag = command tag in the Command header.
GetPropertyResponse: The target sends the GetPropertyResponse packet in response to
the host query that uses the GetProperty command. The GetPropertyResponse packet
contains the framing packet data and the command packet data, with the command/
response tag set to a GetPropertyResponse tag value (0xA7).
The parameter count field in the header is set to greater than 1, to always include the
status code and one or many property values.
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The GetPropertyResponse parameters are provided below:
Table 10-60. GetPropertyResponse parameters
Byte # Value Parameter
0-3 Status code
4-7 Property code
... ...
Can be up to maximum 6 property values. Limited to the size
of the 32-bit command packet and property type.
The possible status are:
• 0 - kStatus_Success
• 10300 - Unknown Property
10.9.1.2 Packet Types for USB-HID protocol
There are 3 types of packets supported in USB-HID protocol:
• Framing packet
• Command packet
• Data packet
10.9.1.2.1 HID reports
There are 4 HID reports defined and used by the boot ROM USB HID protocol. The
report ID determines the direction and type of packet sent in the report. Otherwise, the
contents of all reports are the same.
The HID reports for the USB-HID protocol are provided below:
Table 10-61. HID reports for the USB-HID protocol
Report ID Packet Type Direction
1 Command OUT (Host -> Device)
2 Data OUT (Host -> Device)
3 Command IN (Device -> Host)
10.9.1.2.2 Framing packet
The framing packet has a 4-byte framing header, in which the report ID and the packet
length is used for the packet type definition and the real payload size.
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Table 10-62. USB-HID Framing Packet
Byte # Data Type Value Note
0 Framing Header Report ID
1 Padding byte Must be 0
2 Packet Length LSB Max size is limited to 1016 bytes
3 Packet Length MSB
4 Payload Packet [0]
5 Packet [1]
…
N+4-1 Packet [N-1]
10.9.1.2.3 Command packet
The Report ID needs to be '1' for Command, and it must be '3' for Response. The payload
definition is the same with Serial Packet Protocol.
10.9.1.2.4 Data packet
The Report ID must be '2' in data packet. The payload definition is the same with Serial
Protocol.
10.9.2 Serial Boot via UART
10.9.2.1 UART Configuration details
Provided below are the details of UART configuration in boot ROM:
• 8-N-1 (8-bit data, No parity bit, 1 stop bit)
• Auto-baud detection is supported during Serial Boot. Maximum baudrate can be up
to 6mbps in high speed boot mode.
• The host tool needs to send out the data packet with maximum payload size (512
bytes) set in framing packet by packet, except for the last packet. ROM will end the
transfer if the payload size is less than the maximum payload size.
• The first packet on UART must be Ping to perform auto-baud detection.
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10.9.2.2 Example Communication sequences
1. Ping (for auto-baud detection)
Host: Ping packet [5a a6]
Device: Ping response < 5a a7 00 02 01 50 00 00 aa ea>
2. Command packet (Get-Property 1)
Host: Command [5a a4 0c 00 4b 33 07 00 00 02 01 00 00 00 00 00 00 00]
∙ 5a - Start Byte
∙ a4 - Packet Type: Command packet
∙ 0c 00 - Payload size(0x000c)
∙ 4b 33 - CRC checksum(0x334b)
∙ 07 00 00 02 01 00 00 00 00 00 00 00 - Payload (Get-property 1)
Device: Ack < 5a a1>
∙ 5a - Start Byte
∙ a1 - ACK
Device: GetPropertyResponse < 5a a4 0c 00 64 18 a7 00 00 02 00 00 00 00 00 01 02 4b>
∙ 5a - Start Byte
∙ a4 - Packet Type: Command packet
∙ 0c 00 - Payload size (0x000c)
∙ 64 18 - CRC Checksum (0x1864)
∙ a7 00 00 02 00 00 00 00 00 01 02 4b - Payload (GetPropertyResponse, status = 0,
property = 0x4b020100)
Host: Ack [5a a1]
∙ 5a - Start Byte
∙ a1 - ACK
3. Load Image
1. First Data packet:
Host: Data packet [5a a5 00 02 55 03 d1 00 20 41 …]
∙ 5a - Start Byte
∙ a5 - Packet Type: Data packet
∙ 00 02 - Payload size(0x0200)
∙ 55 03 - CRC Checksum(0x0355)
∙ d1 00 20 41 … - Payload (Data stream)
Device: Ack <5a a1>
∙ 5a - Start Byte
∙ a1 - ACK
2. Report the remaining data transfer following the same flow as the first data packet.
3. Last Data packet:
Host: Data packet [5a a5 84 00 37 39 07 46 38 …]
∙ 5a - Start Byte
∙ a5 - Packet Type: Data packet
∙ 84 00 - Payload size(0x0084)
∙ 37 39 - CRC Checksum(0x3937)
∙ 07 46 38 … - Payload (Data stream)
Device: Ack <5a a1>
Figure 10-23. Example Communication sequences
10.9.3 Serial Boot via USB-HID
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10.9.3.1 USB configuration details
The USB OTG function device driver supports a high speed (HS for UTMI) non-stream
mode with a maximal packet size of 512 B and a low-level USB OTG function.
The VID/PID and strings for the USB device driver are listed in the following table.
Table 10-63. VID/PID and strings for USB device driver
Descriptor Value
VID 0x1FC9
(NXP vendor ID)
PID1 0x013D
String Descriptor1 (manufacturer) NXP Semiconductors
String Descriptor2 (product) S Blank
String Descriptor4 NXP Flash
String Descriptor5 NXP Flash
1. Allocation based on the BPN (Before Part Number)
10.9.3.2 Endpoints
The HID peripheral uses 3 endpoints:
• Control (0)
• Interrupt IN (1)
• Interrupt OUT (2)
The interrupt OUT endpoint is optional for HID class devices, but the boot ROM uses it
as a pipe, where the firmware can NAK send requests from the USB host.
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10.9.3.3 Example Communication sequences
1. Command packet (Get-Property 1)
Host: Command [01 00 0c 00 07 00 00 02 01 00 00 00 00 00 00 00]
∙ 01 - Command report, Direction: OUT, Host to device
∙ 00 - Padding byte
∙ 0c 00 - Payload size(0x000c)
∙ 07 00 00 02 01 00 00 00 00 00 00 00 - payload
Device: Ack (USB Hardware Ack)
Device: GetPropertyResponse <03 00 0c 00 a7 00 00 02 00 00 00 00 00 01 02 4b 00 00 00
00 00 … 00>
∙ 03 - Command report, Direction: IN, Device to host
∙ 00 - Padding byte
∙ 0c 00 - Payload size(0x000c)
∙ a7 00 00 02 00 00 00 00 00 01 02 4b - Payload (GetPropertyResponse, status=0,
property=0x4b020100)
∙ 00 00 00 00 00 … 00 - Padding bytes
Host: Ack (USB Hardware Ack)
2. Load Image
1. First Data packet:
Host: Data packet [02 00 f8 03 d1 00 20 41 01 a4 00 00 00 00 00 00 00 …]
02 - Data report, Direction: OUT, Host to device
00 - Padding byte
f8 03 - Payload size(0x03f8)
d1 00 20 41 01 a4 00 00 00 00 00 00 00 … - Payload
Device: Ack (USB Hardware Ack)
2. Report the remaining data transfer following the same flow as the first data packet.
3. Last Data packet:
Host: Data packet [02 00 d4 00 20 c5 28 d9 00 f0 0b f8 00 …]
02 - Data report, Direction: OUT, Host to device
00 - Padding byte
d4 00 - Payload size(0x00d4)
20 c5 28 d9 00 f0 0b f8 00 … - Payload
Device: Ack (USB Hardware Ack)
Figure 10-24. Example Communication sequences
10.10 Recovery devices
The chip supports recovery devices. If the primary boot device fails, the boot ROM tries
to boot from the recovery device using one of the LPSPI ports.
To enable the recovery device, the recovery boot fuse must be set. Additionally, the serial
EEPROM fuses must be set as described in Serial NOR/EEPROM through LPSPI.
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10.11 SD/MMC manufacture mode
When the internal boot and recover boot (if enabled) failed, the boot goes to the
SD/MMC manufacture mode before the serial download mode. In the manufacture mode,
one bit bus width is used despite of the fuse setting.
BOOT_MODE==0 and
BOOT_MODE==1 BOOT_MODE==2
BT_FUSE_SEL==0
Y internal primary boot
SDMMC MFG
mode disabled?
N
N EEPROM recovery N
success?
enabled?
SDMMC MFG mode boot
Y Y
EEPROM recovery
Y
success?
N
N
success?
Serial downloader mode
application entry
Figure 10-25. SD/MMC manufacture boot flow
10.12 High-Assurance Boot (HAB)
The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying the areas of code or data in the programmable memory to
make it behave in an incorrect manner. The HAB also prevents the attempts to gain
access to features which must not be available.
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The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks detected a condition
that may be a security threat or if the areas of memory deemed to be important were
modified. The HAB uses the RSA/ECDSA digital signatures to enforce these policies.
CAAM OTFAD/
Flash
IEE
ROM
HAB
Core Processor
SNVS
IEE
RAM
Figure 10-26. Secure boot components
The figure above illustrates the components used during a secure boot using HAB. The
HAB interfaces with the SNVS to make sure that the system security state is as expected.
The HAB also uses the hardware block to accelerate the SHA-256 message digest
operations performed during the signature verifications. The HAB also includes a
software implementation of SHA-256 for cases where a hardware accelerator cannot be
used. The supported RSA key sizes are 1024, 2048, 3072, and 4096 bits. The supported
ECDSA key sizes are P256, P384, and P521. The main features supported by the HAB
are:
• X.509 public key certificate support
• CMS signature format support
NOTE
NXP provides the reference Code Signing Tool (CST) for key
generation and code signing for use with the HAB library. The
CST can be found by searching for "IMX_CST_TOOL" at
http://www.nxp.com
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10.12.1 HAB API vector table addresses
For devices that perform a secure boot, the HAB library may be called by the boot stages
that execute after the ROM code.
The HAB API vector table for this device is at address 0x0021_1C0C .
10.13 ROM APIs
10.13.1 Introduction
The ROM bootloader provides a set of ROM APIs to simplify the In-Application
Programming (IAP).
The ROM bootloader supports the following APIs:
• runBootloader API
• FlexSPI NOR FLASH Driver API
The ROM API root pointer is located at address 0x0021_001C. Please see the following
figure for details of the ROM API layout.
flexspi_nor_config_clock
flexspi_nor_set_clock_source
flexspi_nor_wait_busy
reserved
flexspi_nor_erase_block
flexspi_nor_erase_sector
flexspi_nor_get_config
flexspi_update_lut
flexspi_command_xfer
reserved
flexspi_nor_flash_read
flexspi_nor_flash_erase
flexspi_nor_flash_erase_all
flexspi_nor_flash_page_program
flexspi_nor_flash_init
flexspiNorDriver version
coyright string pointer
version
0x0021_001C Bootloader API Tree root runBootloader runBootloader
Figure 10-27. ROM API Structure
The ROM API structure definitions are as below:
1. Bootloader API Entry Structure
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typedef struct BootloaderTree
{
void (*runBootloader)(void *arg); //!< Function to start the bootloader executing.
standard_version_t version; //!< Bootloader version number.
const char *copyright; //!< Copyright string.
const flexspi_nor_flash_driver_t *flexspiNorDriver; //!< FlexSPI NOR FLASH Driver API.
} bootloader_tree_t;
2. FlexSPI NOR Driver API structure
typedef struct
uint32_t version;
status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src);
status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config);
status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
uint32_t reserved;
status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
void (*hw_reset)(uint32_t instance, uint32_t resetLogic);
status_t (*wait_busy)(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address);
status_t (*set_clock_source)(uint32_t instance, uint32_t clockSrc);
void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode);
} flexspi_nor_flash_driver_t;
10.13.2 FlexSPI NOR APIs
The ROM bootloader provides a set of Serial NOR FLASH APIs to simplify the external
FLASH enablement on the chip. The version of the FlexSPI NOR API in the chip's ROM
bootloader is 1.7.0.
10.13.2.1 FlexSPI NOR prototypes
10.13.2.1.1 flexspi_nor_flash_init
Initialize the Serial NOR device via FLEXSPI:
status_t flexspi_nor_flash_init(uint32_t instance, flexspi_nor_config_t *config)
{
return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
}
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Please see example code in FLASH API Example.
10.13.2.1.2 flexspi_nor_flash_page_program
Program data to specified Flash address:
status_t flexspi_nor_flash_page_program(uint32_t instance, flexspi_nor_config_t *config,
uint32_t dstAddr, const uint32_t *src)
{
return g_bootloaderTree->flexSpiNorDriver->program(instance, config, dstAddr, src);
}
Please see example code in FLASH API Example.
10.13.2.1.3 flexspi_nor_flash_erase_all
Erase the whole Flash array via FLEXSPI:
status_t flexspi_nor_flash_erase_all(uint32_t instance, flexspi_nor_config_t *config)
{
return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config);
}
Example code:
flexspi_nor_flash_erase_all(1,config);
10.13.2.1.4 flexspi_nor_get_config
Get the Flash configuration block via the serial_nor_config_option_t block. Please see
serial_nor_config_t definitions for more details.
status_t flexspi_nor_get_config(uint32_t instance, flexspi_nor_config_t *config,
serial_nor_config_option_t *option)
{
return g_bootloaderTree->flexSpiNorDriver->get_config(instance, config, option);
}
Please see example code in FLASH API Example.
10.13.2.1.5 flexspi_nor_flash_erase
Erase specified Flash region. The minimum erase unit is one sector.
status_t flexspi_nor_flash_erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t
start, uint32_t length)
{
return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
}
Please see example code in FLASH API Example.
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10.13.2.1.6 flexspi_nor_flash_read
Read the FLASH via FLEXSPI using IP read command:
status_t flexspi_nor_flash_read(uint32_t instance, flexspi_nor_config_t *config, uint32_t
*dst, uint32_t start, uint32_t bytes)
{
return g_bootloaderTree->flexSpiNorDriver->read(instance, config, dst, start, bytes);
}
Example code:
uint32_t pageBuffer[256/sizeof(uint32_t)];
flexspi_nor_flash_read(1, config, pageBuffer, 0, sizeof(pageBuffer));
10.13.2.1.7 flexspi_update_lut
Update the specified LUT entries:
status_t flexspi_update_lut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase,
uint32_t numberOfSeq)
{
return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase,
numberOfSeq);
}
Example code:
uint32_t chipEraseLUT[4] = {0x0460, 0, 0, 0};
flexspi_update_lut(1, 1, chipEraseLUT, 1);
10.13.2.1.8 flexspi_command_xfer
Execute LUT sequence specified by xfer:
status_t flexspi_command_xfer(uint32_t instance, flexspi_xfer_t *xfer)
{
return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
}
flexspi_xfer_t definition is as below:
//!@brief FlexSPI Transfer Context
typedef struct _FlexSpiXfer
{
flexspi_operation_t operation; //!< FlexSPI operation
uint32_t baseAddress; //!< FlexSPI operation base address
uint32_t seqId; //!< Sequence Id
uint32_t seqNum; //!< Sequence Number
bool isParallelModeEnable; //!< Is a parallel transfer
uint32_t *txBuffer; //!< Tx buffer
uint32_t txSize; //!< Tx size in bytes
uint32_t *rxBuffer; //!< Rx buffer
uint32_t rxSize; //!< Rx size in bytes
} flexspi_xfer_t;
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flexspi_operation_t definition is as below:
typedef enum _FlexSPIOperationType
{
kFlexSpiOperation_Command,
kFlexSpiOperation_Config,
kFlexSpiOperation_Write,
kFlexSpiOperation_Read,
kFlexSpiOperation_End = kFlexSpiOperation_Read,
} flexspi_operation_t;
Example code, assuming the LUT index 1 is the Flash WriteEnable command.
flexspi_xfer_t flashXfer =
{
kFlexSpiOperation_Command, 0, 1, 1, false, NULL, 0, NULL, 0
};
flexspi_command_xfer(0, &flashXfer);
10.13.2.1.9 flexspi_nor_set_clock_source
Set the clock source of the specified FLEXSPI instance:
status_t flexspi_nor_set_clock_source(uint32_t instance, uint32_t source)
{
return g_botloaderTree->flexSpiNorDriver->set_clock_source(instance, source);
}
Example code:
#define CLOCK_SOURCE_RC400M (2u)
flexspi_nor_set_clock_source(1, CLOCK_SOURCE_RC400M);
10.13.2.1.10 flexspi_nor_configure_clock
Configure the FLEXSPI NOR clock to specified frequency:
status_t flexspi_nor_configure_clock(uint32_t instance, uint32_t freq, uint32_t
sampleClkMode)
{
return g_bootloaderTree->flexSpiNorDriver->config_clock(instance, freq, sampleClkMode);
}
Example code:
enum
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_80MHz = 4,
kFlexSpiSerialClk_100MHz = 5,
kFlexSpiSerialClk_120MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
};
enum
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{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
flexspi_nor_configure_clock(1, kFlexSpiSerialClk_100MHz, kFlexSpiClk_DDR);
10.13.2.1.11 serial_nor_config_t definitions
serial_nor_config_t is defined as below:
typedef struct _serial_nor_config_option
{
union
{
struct
{
uint32_t max_freq : 4; //!< Maximum supported Frequency
uint32_t misc_mode : 4; //!< miscellaneous mode
uint32_t quad_mode_setting : 4; //!< Quad mode setting
uint32_t cmd_pads : 4; //!< Command pads
uint32_t query_pads : 4; //!< SFDP read pads
uint32_t device_type : 4; //!< Device type
uint32_t option_size : 4; //!< Option size, in terms of uint32_t, size = (option_size + 1) * 4
uint32_t tag : 4; //!< Tag, must be 0x0E
} B;
uint32_t U;
} option0;
union
{
struct
{
uint32_t dummy_cycles : 8; //!< Dummy cycles before read
uint32_t reserved0 : 8;
uint32_t pinmux_group : 4; //!< The pinmux group selection
uint32_t dqs_pinmux_group : 4; //!< The DQS Pinmux Group Selection
uint32_t reserved1 : 4;
uint32_t flash_connection : 4; //!< Flash connection option: 0 - Single Flash connected to port A, 1 -
//! Parallel mode, 2 - Single Flash connected to Port B
} B;
uint32_t U;
} option1;
} serial_nor_config_option_t;
Detailed information of serial_nor_config_option_t structure is shown in the following
table.
Table 10-64. serial_nor_config_option_t definition
Offset Field Description
0 Option0 See Table 10-65 for more details
4 Option1 Optional, valid only if the Option Size field in Option0 is non-zero. See
Table 10-66 for more details.
Table 10-65. Option0 definition
Field Bits Description
tag 31:28 The tag of the config option, fixed to 0x0C
option_size 27:24 Size in bytes = (Option Size + 1) × 4
It is 0 if only option0 is required
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Table 10-65. Option0 definition (continued)
Field Bits Description
device_type 23:20 Device Detection Type
0 - Read SFDP for SDR commands
1 - Read SFDP for DDR Read commands
2 - HyperFLASH 1V8
3 - HyperFLASH 3V
4 - Macronix Octal DDR
6 - Micron Octal DDR
8 - Adesto EcoXiP DDR
query_pad 19:16 Data pads during Query command
(read SFDP or read MID)
0-1
2-4
3–8
cmd_pad 15:12 Data pads during Flash access command
0-1
2-4
3–8
quad_mode_sett ing 11:8 Quad Mode Enable Setting
0 - Not configured
1 - Set bit 6 in Status Register 1
2 - Set bit 1 in Status Register 2
3 - Set bit 7 in Status Register 2
4 - Set bit 1 in Status Register 2 vis 0x31 command
NOTE: This field is valid only if a device is compliant with JESD216 only
(9 longword SDFP table).
misc_mode 7:4 Set to 0.
max_freq 3:0 Max Flash Operation speed
0 - Do not change FlexSPI clock setting
Others - See System Boot chapter for more details.
NOTE: The field has a restriction that the FlexSPI clock source must be
PLL480_PFD0. Keep it as 0 and manually configure the FLEXSPI
clock if another clock source is selected in user application.
Table 10-66. Option1 definition
Field Bits Description
flash_connection 31:28 Flash connection selection
0 - Single FLASH connected to Port A
1 - Parallel mode
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Table 10-66. Option1 definition (continued)
Field Bits Description
2 - Single FLASH connected to Port B
reserved 27:20 Reserved
pin_group 19:16 PinMux group
0 - Primary pin group
1 - Secondary pin group
reserved 15:8 Reserved
dummy_cycles 7:0 Dummy cycles for the read command
0 - Use detected dummy cycle
Others - dummy cycles provided in flash datasheet
NOTE
• These APIs only support FLASH devices connected to
SS0.
• The APIs always use 30MHz clock for the programming
option. Users will need to change the
"ipcmdSerialClkFreq" field in flexspi_nor_config_t field
after flexspi_nor_get_config option, if a higher
programming speed is expected.
• User application needs to set "max_freq" to 0 and manually
configure the FLEXSPI clock before calling the
flexspi_nor_get_config API, if the expected FLEXSPI
clock source is not the default clock source configured by
the ROM bootloader.
• The pad drive strength is configured to full-driver mode
(See IOMUXC chapter for more details). Users can change
the "dataPadOverride" and "sclkPadOverride" setting in
flexspi_nor_config_t structure after calling
flexspi_nor_get_config, if necessary.
10.13.2.1.12 Status codes for the FlexSPI NOR API
The following table lists all the error and status codes for the FlexSPI NOR API.
Table 10-67. Status and error codes for the FlexSPI NOR API
Status Code Description
kStatus_Success 0 Operation succeeded without error
kStatus_Fail 1 The operation failed with a generic error
kStatus_InvalidArgument 4 The requested argument is invalid
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Table 10-67. Status and error codes for the FlexSPI NOR API (continued)
Status Code Description
kStatus_Timeout 5 A timeout occurred
kStatus_FLEXSPI_SequenceExecutionT imeout 7000 The command timed out
kStatus_FLEXSPI_InvalidSequence 7001 Invalid LUT sequence
kStatus_FLEXSPI_DeviceTimeout 7002 The busy time exceeded the specified timeout value
kStatus_FLEXSPINOR_ProgramFail 20100 Program Command failed
kStatus_FLEXSPINOR_EraseSectorFail 20101 Erase sector command failed
kStatus_FLEXSPINOR_EraseAllFail 20102 Erase All command failed
kStatus_FLEXSPINOR_WaitTimeout 20103 The wait time exceeded the specified timeout value
kStatus_FlexSPINOR_NotSupported 20104 The operation is not supported
kStatus_FlexSPINOR_WriteAlignmentEr ror 20105 Write address is unaligned to page size
kStatus_FlexSPINOR_CommandFailure 20106 Command failed
kStatus_FlexSPINOR_SFDP_NotFound 20107 SFDP table was not found, used for
flexspi_nor_flash_get_config API
kStatus_FLEXSPINOR_Flash_NotFoun d 20109 Cannot detect a FLASH device
kStatus_FLEXSPINOR_DTRRead_Dum 20110 The dummy cycle for DDR/DTR read cannot be probed.
myProbeFailed
10.13.2.1.13 Typical options for the Serial NOR devices in the market
The following list provides typical options for the serial NOR flash devices in the market.
• QuadSPI NOR - Quad SDR Read: option0 = 0xc0000007 (133MHz)
• QuadSPI NOR - Quad DDR Read: option0 = 0xc0100003 (60MHz)
• HyperFLASH 1V8: option0 = 0xc0233008 (166MHz)
• HyperFLASH 3V0: option0 = 0xc0333005 (100MHz)
• MXIC OPI DDR (OPI DDR enabled by default): option=0xc0433007(133MHz)
• Micron Octal DDR: option0=0xc0600005 (100MHz)
• Micron OPI DDR: option0=0xc0603007 (133MHz), SPI->OPI DDR
• Micron OPI DDR (DDR read enabled by default): option0 = 0xc0633007 (133MHz)
• Adesto OPI DDR: option0=0xc0803007(133MHz)
10.13.2.1.14 FLASH API Example
The following is a typical use case of the FlexSPI NOR API.
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flexspi_nor_config_t config;
serial_nor_config_option_t option;
status_t status;
uint32_t address = 0x40000; // 256KB uint32_t
sector_size = 0x1000; // 4KB
uint32_t page_buffer[256/ sizeof(uint32_t)];
uint32_t instance = 1;
option.option0.U = 0xC0000007; // QuadSPI NOR, Frequency: 133MHz
status = flexspi_nor_get_config(instance, &config, &option);
if (status != kStatus_Success)
{
return status;
}
status = flexspi_nor_flash_init(instance, &config);
if (status != kStatus_Success)
{
return status;
}
status = flexspi_nor_flash_erase(instance, &config, address , sector_size); // Erase 1
sector
if (status != kStatus_Success)
{
return status;
}
// Fill data into the page_buffer;
for (uint32_t i=0; i<sizeof(page_buffer)/sizeof(page_buffer[0]); i++)
{
page_buffer[i] = (i << 24) | (i << 16) | (i << 8) | i;
}
// Program data to destination
status = flexspi_nor_flash_page_program(instance, &config, address, page_buffer); // program
1 page
if (status != kStatus_Success)
{
return status;
}
// Do cache maintenance here if the D-Cache is enabled
// Use memory mapped access to verify whether data are programmed into Flash correctly
uint32_t mem_address = 0x3000_0000 + address;
if (0 == memcmp((void*)mem_address, page_buffer, sizeof(page_buffer))
{
// Success
}
else
{
// Report error
}
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10.13.3 Enter Bootloader API
The ROM bootloader provides an API for the user application to safely boot from a
newly updated application after In-Application Programming (IAP) or re-enter serial
downloader mode for an image update.
API prototype
void runBootloader(void* arg)
{
g_bootloaderTree-> runBootloader(arg);
}
Table 10-68. ARG definition
Field Offset Description
Tag [31:24] Fixed value: 0xEB (Enter Boot)
boot mode [23:20] 0 - Determined by BMODE in SMBR2 or other Fuse combinations
1 - Serial downloader
Serial downloader media [19:16] 0 - Auto detection
1 - USB
2 - UART
Reserved [15:04] Reserved
Boot image selection [03: 00] 0 - Image 0
1 - Image 1
2 - Image 2
3 - Image 3
NOTE: It takes effect only if the boot mode is 0.
For FlexSPI NOR boot, the maximum Image index is 1. The address and
length of the backup image is specified in the fuse. Image 0 is always the
latest image. Image 1 always implies the backup image. If the dual image
boot feature is not implemented, the backup image means the 2nd image,
otherwise, the backup image means the "old" image.
For the NAND FLASH devices, the maximum image index is 3. The Image
address is specified in FCB.
Typical use cases:
1. Enter Serial downloader mode and select USB as the communication peripheral:
uint32_t arg = 0xeb100000;
runBootloader (&arg);
2. Select Image1 as the boot image after reliable update in user application:
uint32_t arg = 0xeb000001;
runBootloader (&arg);
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Chapter 11
External Signals and Pin Multiplexing
11.1 Overview
The chip contains a limited number of pins, most of which have multiple signal options.
These signal-to-pin and pin-to-signal options are selected by the input-output multiplexer
called IOMUX. The IOMUX is also used to configure other pin characteristics, such as
voltage level, drive strength, and hysteresis.
The muxing options table lists the external signals grouped by the module instance, the
muxing options for each signal, and the registers used to route the signal to the chosen
pad.
11.1.1 Muxing Options
NOTE
For information on external signals for ADC module, refer to
Chip-specific LPADC information
Table 11-1. Muxing Options
Instance Port Pad Mode
ACMP1 ACMP1_OUT GPIO_AD_17 ALT1
ACMP1_IN1 GPIO_AD_00 No muxing
ACMP1_IN2 GPIO_AD_01 No muxing
ACMP1_IN3 GPIO_AD_02 No muxing
ACMP1_IN4 GPIO_AD_03 No muxing
ACMP2 ACMP2_OUT GPIO_AD_18 ALT1
ACMP2_IN1 GPIO_AD_04 No muxing
ACMP2_IN2 GPIO_AD_05 No muxing
ACMP2_IN3 GPIO_AD_26 No muxing
ACMP2_IN4 GPIO_AD_27 No muxing
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ACMP3 ACMP3_OUT GPIO_AD_19 ALT1
ACMP3_IN1 GPIO_AD_28 No muxing
ACMP3_IN2 GPIO_AD_29 No muxing
ACMP3_IN3 GPIO_AD_30 No muxing
ACMP3_IN4 GPIO_AD_31 No muxing
ACMP4 ACMP4_OUT GPIO_AD_20 ALT1
ACMP4_IN1 GPIO_AD_32 No muxing
ACMP4_IN2 GPIO_AD_33 No muxing
ACMP4_IN3 GPIO_AD_34 No muxing
ACMP4_IN4 GPIO_AD_35 No muxing
ADC1 ADC1_CH0A GPIO_AD_06 No muxing
ADC1_CH0B GPIO_AD_07 No muxing
ADC1_CH1A GPIO_AD_08 No muxing
ADC1_CH1B GPIO_AD_09 No muxing
ADC1_CH2A GPIO_AD_10 No muxing
ADC1_CH2B GPIO_AD_11 No muxing
ADC1_CH3A GPIO_AD_12 No muxing
ADC1_CH3B GPIO_AD_13 No muxing
ADC1_CH4A GPIO_AD_14 No muxing
ADC1_CH4B GPIO_AD_15 No muxing
ADC1_CH5A GPIO_AD_16 No muxing
ADC1_CH5B GPIO_AD_17 No muxing
ADC2 ADC2_CH0A GPIO_AD_18 No muxing
ADC2_CH0B GPIO_AD_19 No muxing
ADC2_CH1A GPIO_AD_20 No muxing
ADC2_CH1B GPIO_AD_21 No muxing
ADC2_CH2A GPIO_AD_22 No muxing
ADC2_CH2B GPIO_AD_23 No muxing
ADC2_CH3A GPIO_AD_12 No muxing
ADC2_CH3B GPIO_AD_13 No muxing
ADC2_CH4A GPIO_AD_14 No muxing
ADC2_CH4B GPIO_AD_15 No muxing
ADC2_CH5A GPIO_AD_16 No muxing
ADC2_CH5B GPIO_AD_17 No muxing
ADC2_CH6A GPIO_AD_24 No muxing
ADC2_CH6B GPIO_AD_25 No muxing
ARM ARM_TRACE0 GPIO_DISP_B2_02 ALT3
ARM_TRACE1 GPIO_DISP_B2_03 ALT3
ARM_TRACE2 GPIO_DISP_B2_04 ALT3
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ARM_TRACE3 GPIO_DISP_B2_05 ALT3
ARM_TRACE_CLK GPIO_DISP_B2_06 ALT3
ARM_TRACE_SWO GPIO_DISP_B2_07 ALT3
ARM_TRACE_SWO GPIO_LPSR_11 ALT7
CCM CCM_CLKO1 GPIO_EMC_B1_40 ALT9
CCM_CLKO2 GPIO_EMC_B1_41 ALT9
CCM_ENET_REF_CLK_25M GPIO_EMC_B2_00 ALT1
CCM_ENET_REF_CLK_25M GPIO_AD_14 ALT9
CCM_ENET_REF_CLK_25M GPIO_DISP_B2_01 ALT9
CCM_CLK1_N CCM_CLK1_N No muxing
CCM_CLK1_P CCM_CLK1_P No muxing
CM4 ARM_CM4_EVENTI GPIO_LPSR_01 ALT3
ARM_CM4_EVENTO GPIO_LPSR_00 ALT3
CM7 ARM_CM7_EVENTI GPIO_DISP_B2_09 ALT3
ARM_CM7_EVENTO GPIO_DISP_B2_08 ALT3
DCDC DCDC_PSWITCH DCDC_PSWITCH No muxing
DCDC_LP DCDC_LP No muxing
DCDC_MODE DCDC_MODE No muxing
DCDC_LN DCDC_LN No muxing
DCDC_IN DCDC_IN No muxing
DCDC_INQ DCDC_INQ No muxing
EMVSIM1 EMVSIM1_CLK GPIO_AD_01 ALT0
EMVSIM1_CLK GPIO_EMC_B2_12 ALT8
EMVSIM1_PD GPIO_AD_04 ALT0
EMVSIM1_PD GPIO_EMC_B2_15 ALT8
EMVSIM1_POWER_FAIL GPIO_AD_05 ALT0
EMVSIM1_POWER_FAIL GPIO_EMC_B2_16 ALT8
EMVSIM1_RST GPIO_AD_02 ALT0
EMVSIM1_RST GPIO_EMC_B2_13 ALT8
EMVSIM1_SVEN GPIO_AD_03 ALT0
EMVSIM1_SVEN GPIO_EMC_B2_14 ALT8
EMVSIM1_IO GPIO_AD_00 ALT0
EMVSIM1_IO GPIO_EMC_B2_11 ALT8
EMVSIM2 EMVSIM2_CLK GPIO_DISP_B2_11 ALT1
EMVSIM2_CLK GPIO_AD_07 ALT2
EMVSIM2_PD GPIO_DISP_B2_14 ALT1
EMVSIM2_PD GPIO_AD_10 ALT2
EMVSIM2_POWER_FAIL GPIO_DISP_B2_15 ALT1
EMVSIM2_POWER_FAIL GPIO_AD_11 ALT2
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
EMVSIM2_RST GPIO_DISP_B2_12 ALT1
EMVSIM2_RST GPIO_AD_08 ALT2
EMVSIM2_SVEN GPIO_DISP_B2_13 ALT1
EMVSIM2_SVEN GPIO_AD_09 ALT2
EMVSIM2_IO GPIO_DISP_B2_10 ALT1
EMVSIM2_IO GPIO_AD_06 ALT2
ENET ENET_1588_EVENT0_IN GPIO_AD_34 ALT3
ENET_1588_EVENT0_OUT GPIO_AD_35 ALT3
ENET_1588_EVENT1_IN GPIO_AD_06 ALT6
ENET_1588_EVENT1_OUT GPIO_AD_07 ALT6
ENET_1588_EVENT2_IN GPIO_AD_08 ALT6
ENET_1588_EVENT2_OUT GPIO_AD_09 ALT6
ENET_1588_EVENT3_IN GPIO_AD_10 ALT6
ENET_1588_EVENT3_OUT GPIO_AD_11 ALT6
ENET_COL GPIO_AD_19 ALT6
ENET_CRS GPIO_AD_18 ALT6
ENET_MDC GPIO_EMC_B2_19 ALT1
ENET_MDC GPIO_AD_32 ALT3
ENET_MDIO GPIO_EMC_B2_20 ALT1
ENET_MDIO GPIO_AD_33 ALT3
ENET_RX_DATA0 GPIO_DISP_B2_06 ALT1
ENET_RX_DATA0 GPIO_AD_26 ALT3
ENET_RX_DATA1 GPIO_DISP_B2_07 ALT1
ENET_RX_DATA1 GPIO_AD_27 ALT3
ENET_RX_DATA2 GPIO_AD_17 ALT6
ENET_RX_DATA3 GPIO_AD_16 ALT6
ENET_REF_CLK GPIO_AD_29 ALT2
ENET_REF_CLK GPIO_DISP_B2_05 ALT2
ENET_REF_CLK GPIO_DISP_B2_13 ALT4
ENET_RX_CLK GPIO_AD_14 ALT6
ENET_RX_EN GPIO_DISP_B2_08 ALT1
ENET_RX_EN GPIO_AD_24 ALT3
ENET_RX_ER GPIO_DISP_B2_09 ALT1
ENET_RX_ER GPIO_AD_25 ALT3
ENET_TX_DATA0 GPIO_DISP_B2_02 ALT1
ENET_TX_DATA0 GPIO_AD_30 ALT3
ENET_TX_DATA1 GPIO_DISP_B2_03 ALT1
ENET_TX_DATA1 GPIO_AD_31 ALT3
ENET_TX_DATA2 GPIO_AD_13 ALT6
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ENET_TX_DATA3 GPIO_AD_12 ALT6
ENET_TX_CLK GPIO_DISP_B2_05 ALT1
ENET_TX_CLK GPIO_AD_29 ALT3
ENET_TX_EN GPIO_DISP_B2_04 ALT1
ENET_TX_EN GPIO_AD_28 ALT3
ENET_TX_ER GPIO_AD_15 ALT6
ENET_TX_ER GPIO_SD_B2_07 ALT8
ENET 1G ENET_1G_1588_EVENT0_IN GPIO_AD_34 ALT0
ENET_1G_1588_EVENT0_O GPIO_AD_35 ALT0
UT
ENET_1G_1588_EVENT1_IN GPIO_AD_00 ALT2
ENET_1G_1588_EVENT1_O GPIO_AD_01 ALT2
UT
ENET_1G_1588_EVENT2_IN GPIO_AD_02 ALT2
ENET_1G_1588_EVENT2_O GPIO_AD_03 ALT2
UT
ENET_1G_1588_EVENT3_IN GPIO_AD_04 ALT2
ENET_1G_1588_EVENT3_O GPIO_AD_05 ALT2
UT
ENET_1G_COL GPIO_EMC_B2_10 ALT7
ENET_1G_CRS GPIO_EMC_B2_09 ALT7
ENET_1G_MDC GPIO_EMC_B2_19 ALT2
ENET_1G_MDC GPIO_EMC_B1_40 ALT7
ENET_1G_MDC GPIO_AD_16 ALT9
ENET_1G_MDC GPIO_AD_32 ALT9
ENET_1G_MDIO GPIO_EMC_B2_20 ALT2
ENET_1G_MDIO GPIO_EMC_B1_41 ALT7
ENET_1G_MDIO GPIO_AD_17 ALT9
ENET_1G_MDIO GPIO_AD_33 ALT9
ENET_1G_RX_DATA0 GPIO_DISP_B1_02 ALT1
ENET_1G_RX_DATA0 GPIO_EMC_B2_15 ALT2
ENET_1G_RX_DATA0 GPIO_SD_B2_02 ALT2
ENET_1G_RX_DATA1 GPIO_DISP_B1_03 ALT1
ENET_1G_RX_DATA1 GPIO_EMC_B2_16 ALT2
ENET_1G_RX_DATA1 GPIO_SD_B2_03 ALT2
ENET_1G_RX_DATA2 GPIO_DISP_B1_04 ALT1
ENET_1G_RX_DATA2 GPIO_SD_B2_04 ALT2
ENET_1G_RX_DATA2 GPIO_EMC_B2_08 ALT7
ENET_1G_RX_DATA3 GPIO_DISP_B1_05 ALT1
ENET_1G_RX_DATA3 GPIO_SD_B2_05 ALT2
ENET_1G_RX_DATA3 GPIO_EMC_B2_07 ALT7
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ENET_1G_REF_CLK GPIO_DISP_B1_11 ALT2
ENET_1G_REF_CLK GPIO_EMC_B2_19 ALT3
ENET_1G_REF_CLK GPIO_SD_B2_11 ALT3
ENET_1G_REF_CLK GPIO_DISP_B2_14 ALT4
ENET_1G_RX_CLK GPIO_DISP_B1_01 ALT1
ENET_1G_RX_CLK GPIO_SD_B2_01 ALT2
ENET_1G_RX_CLK GPIO_EMC_B2_05 ALT7
ENET_1G_RX_EN GPIO_DISP_B1_00 ALT1
ENET_1G_RX_EN GPIO_EMC_B2_17 ALT2
ENET_1G_RX_EN GPIO_SD_B2_00 ALT2
ENET_1G_RX_ER GPIO_EMC_B2_18 ALT2
ENET_1G_RX_ER GPIO_DISP_B1_01 ALT2
ENET_1G_TX_DATA0 GPIO_DISP_B1_09 ALT1
ENET_1G_TX_DATA0 GPIO_EMC_B2_11 ALT2
ENET_1G_TX_DATA0 GPIO_SD_B2_09 ALT2
ENET_1G_TX_DATA1 GPIO_DISP_B1_08 ALT1
ENET_1G_TX_DATA1 GPIO_EMC_B2_12 ALT2
ENET_1G_TX_DATA1 GPIO_SD_B2_08 ALT2
ENET_1G_TX_DATA2 GPIO_DISP_B1_07 ALT1
ENET_1G_TX_DATA2 GPIO_SD_B2_07 ALT2
ENET_1G_TX_DATA2 GPIO_EMC_B2_04 ALT7
ENET_1G_TX_DATA3 GPIO_DISP_B1_06 ALT1
ENET_1G_TX_DATA3 GPIO_SD_B2_06 ALT2
ENET_1G_TX_DATA3 GPIO_EMC_B2_03 ALT7
ENET_1G_TX_CLK_IO GPIO_DISP_B1_11 ALT1
ENET_1G_TX_CLK_IO GPIO_EMC_B2_14 ALT2
ENET_1G_TX_CLK_IO GPIO_SD_B2_11 ALT2
ENET_1G_TX_EN GPIO_DISP_B1_10 ALT1
ENET_1G_TX_EN GPIO_EMC_B2_13 ALT2
ENET_1G_TX_EN GPIO_SD_B2_10 ALT2
ENET_1G_TX_ER GPIO_DISP_B2_00 ALT3
ENET_1G_TX_ER GPIO_EMC_B2_06 ALT7
ENET QoS ENET_QOS_1588_EVENT0_ GPIO_DISP_B2_15 ALT8
AUX_IN
ENET_QOS_1588_EVENT0_ GPIO_DISP_B2_14 ALT8
IN
ENET_QOS_1588_EVENT0_ GPIO_DISP_B2_13 ALT8
OUT
ENET_QOS_1588_EVENT1_ GPIO_EMC_B2_02 ALT7
AUX_IN
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ENET_QOS_1588_EVENT1_ GPIO_EMC_B2_01 ALT7
IN
ENET_QOS_1588_EVENT1_ GPIO_EMC_B2_00 ALT7
OUT
ENET_QOS_1588_EVENT2_ GPIO_SD_B1_04 ALT9
AUX_IN
ENET_QOS_1588_EVENT2_ GPIO_AD_21 ALT9
IN
ENET_QOS_1588_EVENT2_ GPIO_AD_20 ALT9
OUT
ENET_QOS_1588_EVENT3_ GPIO_SD_B1_05 ALT9
AUX_IN
ENET_QOS_1588_EVENT3_ GPIO_AD_23 ALT9
IN
ENET_QOS_1588_EVENT3_ GPIO_AD_22 ALT9
OUT
ENET_QOS_COL GPIO_DISP_B2_12 ALT8
ENET_QOS_CRS GPIO_DISP_B2_11 ALT8
ENET_QOS_MDC GPIO_EMC_B2_19 ALT8
ENET_QOS_MDC GPIO_AD_26 ALT9
ENET_QOS_MDIO GPIO_EMC_B2_20 ALT8
ENET_QOS_MDIO GPIO_AD_27 ALT9
ENET_QOS_RX_DATA0 GPIO_DISP_B1_02 ALT8
ENET_QOS_RX_DATA0 GPIO_DISP_B2_06 ALT8
ENET_QOS_RX_DATA1 GPIO_DISP_B1_03 ALT8
ENET_QOS_RX_DATA1 GPIO_DISP_B2_07 ALT8
ENET_QOS_RX_DATA2 GPIO_DISP_B1_04 ALT8
ENET_QOS_RX_DATA3 GPIO_DISP_B1_05 ALT8
ENET_QOS_REF_CLK GPIO_EMC_B2_20 ALT3
ENET_QOS_REF_CLK GPIO_SD_B2_07 ALT9
ENET_QOS_REF_CLK GPIO_DISP_B1_11 ALT9
ENET_QOS_RX_CLK GPIO_DISP_B1_01 ALT8
ENET_QOS_RX_EN GPIO_DISP_B1_00 ALT8
ENET_QOS_RX_EN GPIO_DISP_B2_08 ALT8
ENET_QOS_RX_ER GPIO_DISP_B2_09 ALT8
ENET_QOS_RX_ER GPIO_DISP_B2_10 ALT8
ENET_QOS_RX_ER GPIO_DISP_B1_01 ALT9
ENET_QOS_TX_DATA0 GPIO_DISP_B1_09 ALT8
ENET_QOS_TX_DATA0 GPIO_DISP_B2_02 ALT8
ENET_QOS_TX_DATA1 GPIO_DISP_B1_08 ALT8
ENET_QOS_TX_DATA1 GPIO_DISP_B2_03 ALT8
ENET_QOS_TX_DATA2 GPIO_DISP_B1_07 ALT8
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
ENET_QOS_TX_DATA3 GPIO_DISP_B1_06 ALT8
ENET_QOS_TX_CLK GPIO_DISP_B1_11 ALT8
ENET_QOS_TX_CLK GPIO_DISP_B2_05 ALT8
ENET_QOS_TX_EN GPIO_DISP_B1_10 ALT8
ENET_QOS_TX_EN GPIO_DISP_B2_04 ALT8
ENET_QOS_TX_ER GPIO_DISP_B2_00 ALT8
EWM EWM_OUT_B GPIO_EMC_B2_18 ALT3
EWM_OUT_B GPIO_DISP_B2_01 ALT8
EWM_OUT_B GPIO_AD_12 ALT9
FLEXCAN1 FLEXCAN1_RX GPIO_AD_07 ALT1
FLEXCAN1_RX GPIO_DISP_B2_13 ALT2
FLEXCAN1_RX GPIO_DISP_B2_15 ALT6
FLEXCAN1_TX GPIO_AD_06 ALT1
FLEXCAN1_TX GPIO_DISP_B2_12 ALT2
FLEXCAN1_TX GPIO_DISP_B2_14 ALT6
FLEXCAN2 FLEXCAN2_RX GPIO_AD_01 ALT1
FLEXCAN2_RX GPIO_AD_31 ALT2
FLEXCAN2_TX GPIO_AD_00 ALT1
FLEXCAN2_TX GPIO_AD_30 ALT2
FLEXCAN3 FLEXCAN3_RX GPIO_LPSR_01 ALT0
FLEXCAN3_RX GPIO_LPSR_09 ALT1
FLEXCAN3_RX GPIO_LPSR_07 ALT6
FLEXCAN3_TX GPIO_LPSR_00 ALT0
FLEXCAN3_TX GPIO_LPSR_08 ALT1
FLEXCAN3_TX GPIO_LPSR_06 ALT6
FLEXIO1 FLEXIO1_D00 GPIO_EMC_B1_00 ALT8
FLEXIO1_D01 GPIO_EMC_B1_01 ALT8
FLEXIO1_D10 GPIO_EMC_B1_10 ALT8
FLEXIO1_D11 GPIO_EMC_B1_11 ALT8
FLEXIO1_D12 GPIO_EMC_B1_12 ALT8
FLEXIO1_D13 GPIO_EMC_B1_13 ALT8
FLEXIO1_D14 GPIO_EMC_B1_14 ALT8
FLEXIO1_D15 GPIO_EMC_B1_15 ALT8
FLEXIO1_D16 GPIO_EMC_B1_16 ALT8
FLEXIO1_D17 GPIO_EMC_B1_17 ALT8
FLEXIO1_D18 GPIO_EMC_B1_18 ALT8
FLEXIO1_D19 GPIO_EMC_B1_19 ALT8
FLEXIO1_D02 GPIO_EMC_B1_02 ALT8
FLEXIO1_D20 GPIO_EMC_B1_20 ALT8
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
FLEXIO1_D21 GPIO_EMC_B1_21 ALT8
FLEXIO1_D22 GPIO_EMC_B1_22 ALT8
FLEXIO1_D23 GPIO_EMC_B1_23 ALT8
FLEXIO1_D24 GPIO_EMC_B1_24 ALT8
FLEXIO1_D25 GPIO_EMC_B1_25 ALT8
FLEXIO1_D26 GPIO_EMC_B1_26 ALT8
FLEXIO1_D27 GPIO_EMC_B1_27 ALT8
FLEXIO1_D28 GPIO_EMC_B1_28 ALT8
FLEXIO1_D29 GPIO_EMC_B1_29 ALT8
FLEXIO1_D03 GPIO_EMC_B1_03 ALT8
FLEXIO1_D30 GPIO_EMC_B1_30 ALT8
FLEXIO1_D31 GPIO_EMC_B1_31 ALT8
FLEXIO1_D04 GPIO_EMC_B1_04 ALT8
FLEXIO1_D05 GPIO_EMC_B1_05 ALT8
FLEXIO1_D06 GPIO_EMC_B1_06 ALT8
FLEXIO1_D07 GPIO_EMC_B1_07 ALT8
FLEXIO1_D08 GPIO_EMC_B1_08 ALT8
FLEXIO1_D09 GPIO_EMC_B1_09 ALT8
FLEXIO 2 FLEXIO2_D00 GPIO_AD_00 ALT8
FLEXIO2_D01 GPIO_AD_01 ALT8
FLEXIO2_D10 GPIO_AD_10 ALT8
FLEXIO2_D11 GPIO_AD_11 ALT8
FLEXIO2_D12 GPIO_AD_12 ALT8
FLEXIO2_D13 GPIO_AD_13 ALT8
FLEXIO2_D14 GPIO_AD_14 ALT8
FLEXIO2_D15 GPIO_AD_15 ALT8
FLEXIO2_D16 GPIO_AD_16 ALT8
FLEXIO2_D17 GPIO_AD_17 ALT8
FLEXIO2_D18 GPIO_AD_18 ALT8
FLEXIO2_D19 GPIO_AD_19 ALT8
FLEXIO2_D02 GPIO_AD_02 ALT8
FLEXIO2_D20 GPIO_AD_20 ALT8
FLEXIO2_D21 GPIO_AD_21 ALT8
FLEXIO2_D22 GPIO_AD_22 ALT8
FLEXIO2_D23 GPIO_AD_23 ALT8
FLEXIO2_D24 GPIO_AD_24 ALT8
FLEXIO2_D25 GPIO_AD_25 ALT8
FLEXIO2_D26 GPIO_AD_26 ALT8
FLEXIO2_D27 GPIO_AD_27 ALT8
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
FLEXIO2_D28 GPIO_AD_28 ALT8
FLEXIO2_D29 GPIO_AD_29 ALT8
FLEXIO2_D3 GPIO_AD_03 ALT8
FLEXIO2_D30 GPIO_AD_30 ALT8
FLEXIO2_D31 GPIO_AD_31 ALT8
FLEXIO2_D04 GPIO_AD_04 ALT8
FLEXIO2_D05 GPIO_AD_05 ALT8
FLEXIO2_D06 GPIO_AD_06 ALT8
FLEXIO2_D07 GPIO_AD_07 ALT8
FLEXIO2_D08 GPIO_AD_08 ALT8
FLEXIO2_D09 GPIO_AD_09 ALT8
FLEXPWM1 FLEXPWM1_PWM0_A GPIO_EMC_B1_23 ALT1
FLEXPWM1_PWM0_A GPIO_AD_00 ALT4
FLEXPWM1_PWM1_A GPIO_EMC_B1_25 ALT1
FLEXPWM1_PWM1_A GPIO_AD_02 ALT4
FLEXPWM1_PWM2_A GPIO_EMC_B1_27 ALT1
FLEXPWM1_PWM2_A GPIO_AD_04 ALT4
FLEXPWM1_PWM3_A GPIO_EMC_B1_38 ALT1
FLEXPWM1_PWM0_B GPIO_EMC_B1_24 ALT1
FLEXPWM1_PWM0_B GPIO_AD_01 ALT4
FLEXPWM1_PWM1_B GPIO_EMC_B1_26 ALT1
FLEXPWM1_PWM1_B GPIO_AD_03 ALT4
FLEXPWM1_PWM2_B GPIO_EMC_B1_28 ALT1
FLEXPWM1_PWM2_B GPIO_AD_05 ALT4
FLEXPWM1_PWM3_B GPIO_EMC_B1_39 ALT1
FLEXPWM1_PWM0_X GPIO_AD_06 ALT11
FLEXPWM1_PWM1_X GPIO_AD_07 ALT11
FLEXPWM1_PWM2_X GPIO_AD_08 ALT11
FLEXPWM1_PWM3_X GPIO_AD_09 ALT11
FLEXPWM2 FLEXPWM2_PWM0_A GPIO_EMC_B1_06 ALT1
FLEXPWM2_PWM0_A GPIO_AD_24 ALT4
FLEXPWM2_PWM1_A GPIO_EMC_B1_08 ALT1
FLEXPWM2_PWM1_A GPIO_AD_26 ALT4
FLEXPWM2_PWM2_A GPIO_EMC_B1_10 ALT1
FLEXPWM2_PWM2_A GPIO_AD_28 ALT4
FLEXPWM2_PWM3_A GPIO_EMC_B1_19 ALT1
FLEXPWM2_PWM0_B GPIO_EMC_B1_07 ALT1
FLEXPWM2_PWM0_B GPIO_AD_25 ALT4
FLEXPWM2_PWM1_B GPIO_EMC_B1_09 ALT1
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
FLEXPWM2_PWM1_B GPIO_AD_27 ALT4
FLEXPWM2_PWM2_B GPIO_EMC_B1_11 ALT1
FLEXPWM2_PWM2_B GPIO_AD_29 ALT4
FLEXPWM2_PWM3_B GPIO_EMC_B1_20 ALT1
FLEXPWM2_PWM0_X GPIO_AD_10 ALT11
FLEXPWM2_PWM1_X GPIO_AD_11 ALT11
FLEXPWM2_PWM2_X GPIO_AD_12 ALT11
FLEXPWM2_PWM3_X GPIO_AD_13 ALT11
FLEXPWM3 FLEXPWM3_PWM0_A GPIO_EMC_B1_29 ALT1
FLEXPWM3_PWM0_A GPIO_EMC_B2_00 ALT11
FLEXPWM3_PWM1_A GPIO_EMC_B1_31 ALT1
FLEXPWM3_PWM1_A GPIO_EMC_B2_02 ALT11
FLEXPWM3_PWM2_A GPIO_EMC_B1_33 ALT1
FLEXPWM3_PWM2_A GPIO_EMC_B2_04 ALT11
FLEXPWM3_PWM3_A GPIO_EMC_B1_21 ALT1
FLEXPWM3_PWM3_A GPIO_EMC_B2_06 ALT11
FLEXPWM3_PWM0_B GPIO_EMC_B1_30 ALT1
FLEXPWM3_PWM0_B GPIO_EMC_B2_01 ALT11
FLEXPWM3_PWM1_B GPIO_EMC_B1_32 ALT1
FLEXPWM3_PWM1_B GPIO_EMC_B2_03 ALT11
FLEXPWM3_PWM2_B GPIO_EMC_B1_34 ALT1
FLEXPWM3_PWM2_B GPIO_EMC_B2_05 ALT11
FLEXPWM3_PWM3_B GPIO_EMC_B1_22 ALT1
FLEXPWM3_PWM3_B GPIO_EMC_B2_07 ALT11
FLEXPWM3_PWM0_X GPIO_AD_14 ALT11
FLEXPWM3_PWM1_X GPIO_AD_15 ALT11
FLEXPWM3_PWM2_X GPIO_AD_16 ALT11
FLEXPWM3_PWM3_X GPIO_AD_17 ALT11
FLEXPWM4 FLEXPWM4_PWM0_A GPIO_EMC_B1_00 ALT1
FLEXPWM4_PWM1_A GPIO_EMC_B1_02 ALT1
FLEXPWM4_PWM2_A GPIO_EMC_B1_04 ALT1
FLEXPWM4_PWM3_A GPIO_EMC_B1_17 ALT1
FLEXPWM4_PWM0_B GPIO_EMC_B1_01 ALT1
FLEXPWM4_PWM1_B GPIO_EMC_B1_03 ALT1
FLEXPWM4_PWM2_B GPIO_EMC_B1_05 ALT1
FLEXPWM4_PWM3_B GPIO_EMC_B1_18 ALT1
FLEXPWM4_PWM0_X GPIO_AD_18 ALT11
FLEXPWM4_PWM1_X GPIO_AD_19 ALT11
FLEXPWM4_PWM2_X GPIO_AD_20 ALT11
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
FLEXPWM4_PWM3_X GPIO_AD_21 ALT11
FLEXSPI1 A FLEXSPI1_A_DATA0 GPIO_SD_B2_08 ALT1
FLEXSPI1_A_DATA0 GPIO_AD_20 ALT3
FLEXSPI1_A_DATA1 GPIO_SD_B2_09 ALT1
FLEXSPI1_A_DATA1 GPIO_AD_21 ALT3
FLEXSPI1_A_DATA2 GPIO_SD_B2_10 ALT1
FLEXSPI1_A_DATA2 GPIO_AD_22 ALT3
FLEXSPI1_A_DATA3 GPIO_SD_B2_11 ALT1
FLEXSPI1_A_DATA3 GPIO_AD_23 ALT3
FLEXSPI1_A_DQS GPIO_SD_B2_05 ALT1
FLEXSPI1_A_DQS GPIO_AD_17 ALT3
FLEXSPI1_A_DQS GPIO_EMC_B2_18 ALT6
FLEXSPI1_A_SCLK GPIO_SD_B2_07 ALT1
FLEXSPI1_A_SCLK GPIO_AD_19 ALT3
FLEXSPI1_A_SS0_B GPIO_SD_B2_06 ALT1
FLEXSPI1_A_SS0_B GPIO_AD_18 ALT3
FLEXSPI1_A_SS1_B GPIO_SD_B2_04 ALT3
FLEXSPI1_A_SS1_B GPIO_SD_B1_02 ALT9
FLEXSPI1_B FLEXSPI1_B_DATA0 GPIO_SD_B2_03 ALT1
FLEXSPI1_B_DATA0 GPIO_AD_15 ALT3
FLEXSPI1_B_DATA1 GPIO_SD_B2_02 ALT1
FLEXSPI1_B_DATA1 GPIO_AD_14 ALT3
FLEXSPI1_B_DATA2 GPIO_SD_B2_01 ALT1
FLEXSPI1_B_DATA2 GPIO_AD_13 ALT3
FLEXSPI1_B_DATA3 GPIO_SD_B2_00 ALT1
FLEXSPI1_B_DATA3 GPIO_AD_12 ALT3
FLEXSPI1_B_DQS GPIO_SD_B1_05 ALT8
FLEXSPI1_B_SCLK GPIO_SD_B2_04 ALT1
FLEXSPI1_B_SCLK GPIO_AD_16 ALT3
FLEXSPI1_B_SS0_B GPIO_SD_B2_05 ALT3
FLEXSPI1_B_SS0_B GPIO_SD_B1_04 ALT8
FLEXSPI1_B_SS1_B GPIO_AD_35 ALT9
FLEXSPI1_B_SS1_B GPIO_SD_B1_03 ALT9
FLEXSPI2_A FLEXSPI2_A_DATA0 GPIO_EMC_B2_13 ALT4
FLEXSPI2_A_DATA0 GPIO_SD_B1_02 ALT6
FLEXSPI2_A_DATA1 GPIO_EMC_B2_14 ALT4
FLEXSPI2_A_DATA1 GPIO_SD_B1_03 ALT6
FLEXSPI2_A_DATA2 GPIO_EMC_B2_15 ALT4
FLEXSPI2_A_DATA2 GPIO_SD_B1_04 ALT6
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
FLEXSPI2_A_DATA3 GPIO_EMC_B2_16 ALT4
FLEXSPI2_A_DATA3 GPIO_SD_B1_05 ALT6
FLEXSPI2_A_DATA4 GPIO_EMC_B2_17 ALT4
FLEXSPI2_A_DATA5 GPIO_EMC_B2_18 ALT4
FLEXSPI2_A_DATA6 GPIO_EMC_B2_19 ALT4
FLEXSPI2_A_DATA7 GPIO_EMC_B2_20 ALT4
FLEXSPI2_A_DQS GPIO_EMC_B2_12 ALT4
FLEXSPI2_A_SCLK GPIO_EMC_B2_10 ALT4
FLEXSPI2_A_SCLK GPIO_SD_B1_01 ALT6
FLEXSPI2_A_SS0_B GPIO_EMC_B2_11 ALT4
FLEXSPI2_A_SS0_B GPIO_SD_B1_00 ALT6
FLEXSPI2_A_SS1_B GPIO_AD_01 ALT9
FLEXSPI2_B FLEXSPI2_B_DATA0 GPIO_EMC_B2_06 ALT4
FLEXSPI2_B_DATA1 GPIO_EMC_B2_05 ALT4
FLEXSPI2_B_DATA2 GPIO_EMC_B2_04 ALT4
FLEXSPI2_B_DATA3 GPIO_EMC_B2_03 ALT4
FLEXSPI2_B_DATA4 GPIO_EMC_B2_02 ALT4
FLEXSPI2_B_DATA5 GPIO_EMC_B2_01 ALT4
FLEXSPI2_B_DATA6 GPIO_EMC_B2_00 ALT4
FLEXSPI2_B_DATA7 GPIO_EMC_B1_41 ALT4
FLEXSPI2_B_DQS GPIO_EMC_B2_07 ALT4
FLEXSPI2_B_SCLK GPIO_EMC_B2_09 ALT4
FLEXSPI2_B_SS0_B GPIO_EMC_B2_08 ALT4
FLEXSPI2_B_SS1_B GPIO_AD_00 ALT9
GPIO1 GPIO1_IO00 GPIO_EMC_B1_00 ALT5
GPIO1_IO01 GPIO_EMC_B1_01 ALT5
GPIO1_IO02 GPIO_EMC_B1_02 ALT5
GPIO1_IO03 GPIO_EMC_B1_03 ALT5
GPIO1_IO04 GPIO_EMC_B1_04 ALT5
GPIO1_IO05 GPIO_EMC_B1_05 ALT5
GPIO1_IO06 GPIO_EMC_B1_06 ALT5
GPIO1_IO07 GPIO_EMC_B1_07 ALT5
GPIO1_IO08 GPIO_EMC_B1_08 ALT5
GPIO1_IO09 GPIO_EMC_B1_09 ALT5
GPIO1_IO10 GPIO_EMC_B1_10 ALT5
GPIO1_IO11 GPIO_EMC_B1_11 ALT5
GPIO1_IO12 GPIO_EMC_B1_12 ALT5
GPIO1_IO13 GPIO_EMC_B1_13 ALT5
GPIO1_IO14 GPIO_EMC_B1_14 ALT5
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO1_IO15 GPIO_EMC_B1_15 ALT5
GPIO1_IO16 GPIO_EMC_B1_16 ALT5
GPIO1_IO17 GPIO_EMC_B1_17 ALT5
GPIO1_IO18 GPIO_EMC_B1_18 ALT5
GPIO1_IO19 GPIO_EMC_B1_19 ALT5
GPIO1_IO20 GPIO_EMC_B1_20 ALT5
GPIO1_IO21 GPIO_EMC_B1_21 ALT5
GPIO1_IO22 GPIO_EMC_B1_22 ALT5
GPIO1_IO23 GPIO_EMC_B1_23 ALT5
GPIO1_IO24 GPIO_EMC_B1_24 ALT5
GPIO1_IO25 GPIO_EMC_B1_25 ALT5
GPIO1_IO26 GPIO_EMC_B1_26 ALT5
GPIO1_IO27 GPIO_EMC_B1_27 ALT5
GPIO1_IO28 GPIO_EMC_B1_28 ALT5
GPIO1_IO29 GPIO_EMC_B1_29 ALT5
GPIO1_IO30 GPIO_EMC_B1_30 ALT5
GPIO1_IO31 GPIO_EMC_B1_31 ALT5
GPIO_MUX21 GPIO_MUX2_IO00 GPIO_EMC_B1_32 ALT5
GPIO_MUX2_IO01 GPIO_EMC_B1_33 ALT5
GPIO_MUX2_IO02 GPIO_EMC_B1_34 ALT5
GPIO_MUX2_IO03 GPIO_EMC_B1_35 ALT5
GPIO_MUX2_IO04 GPIO_EMC_B1_36 ALT5
GPIO_MUX2_IO05 GPIO_EMC_B1_37 ALT5
GPIO_MUX2_IO06 GPIO_EMC_B1_38 ALT5
GPIO_MUX2_IO07 GPIO_EMC_B1_39 ALT5
GPIO_MUX2_IO08 GPIO_EMC_B1_40 ALT5
GPIO_MUX2_IO09 GPIO_EMC_B1_41 ALT5
GPIO_MUX2_IO10 GPIO_EMC_B2_00 ALT5
GPIO_MUX2_IO11 GPIO_EMC_B2_01 ALT5
GPIO_MUX2_IO12 GPIO_EMC_B2_02 ALT5
GPIO_MUX2_IO13 GPIO_EMC_B2_03 ALT5
GPIO_MUX2_IO14 GPIO_EMC_B2_04 ALT5
GPIO_MUX2_IO15 GPIO_EMC_B2_05 ALT5
GPIO_MUX2_IO16 GPIO_EMC_B2_06 ALT5
GPIO_MUX2_IO17 GPIO_EMC_B2_07 ALT5
GPIO_MUX2_IO18 GPIO_EMC_B2_08 ALT5
GPIO_MUX2_IO19 GPIO_EMC_B2_09 ALT5
GPIO_MUX2_IO20 GPIO_EMC_B2_10 ALT5
GPIO_MUX2_IO21 GPIO_EMC_B2_11 ALT5
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO_MUX2_IO22 GPIO_EMC_B2_12 ALT5
GPIO_MUX2_IO23 GPIO_EMC_B2_13 ALT5
GPIO_MUX2_IO24 GPIO_EMC_B2_14 ALT5
GPIO_MUX2_IO25 GPIO_EMC_B2_15 ALT5
GPIO_MUX2_IO26 GPIO_EMC_B2_16 ALT5
GPIO_MUX2_IO27 GPIO_EMC_B2_17 ALT5
GPIO_MUX2_IO28 GPIO_EMC_B2_18 ALT5
GPIO_MUX2_IO29 GPIO_EMC_B2_19 ALT5
GPIO_MUX2_IO30 GPIO_EMC_B2_20 ALT5
GPIO_MUX2_IO31 GPIO_AD_00 ALT5
GPIO_MUX32 GPIO_MUX3_IO00 GPIO_AD_01 ALT5
GPIO_MUX3_IO01 GPIO_AD_02 ALT5
GPIO_MUX3_IO02 GPIO_AD_03 ALT5
GPIO_MUX3_IO03 GPIO_AD_04 ALT5
GPIO_MUX3_IO04 GPIO_AD_05 ALT5
GPIO_MUX3_IO05 GPIO_AD_06 ALT5
GPIO_MUX3_IO06 GPIO_AD_07 ALT5
GPIO_MUX3_IO07 GPIO_AD_08 ALT5
GPIO_MUX3_IO08 GPIO_AD_09 ALT5
GPIO_MUX3_IO09 GPIO_AD_10 ALT5
GPIO_MUX3_IO10 GPIO_AD_11 ALT5
GPIO_MUX3_IO11 GPIO_AD_12 ALT5
GPIO_MUX3_IO12 GPIO_AD_13 ALT5
GPIO_MUX3_IO13 GPIO_AD_14 ALT5
GPIO_MUX3_IO14 GPIO_AD_15 ALT5
GPIO_MUX3_IO15 GPIO_AD_16 ALT5
GPIO_MUX3_IO16 GPIO_AD_17 ALT5
GPIO_MUX3_IO17 GPIO_AD_18 ALT5
GPIO_MUX3_IO18 GPIO_AD_19 ALT5
GPIO_MUX3_IO19 GPIO_AD_20 ALT5
GPIO_MUX3_IO20 GPIO_AD_21 ALT5
GPIO_MUX3_IO21 GPIO_AD_22 ALT5
GPIO_MUX3_IO22 GPIO_AD_23 ALT5
GPIO_MUX3_IO23 GPIO_AD_24 ALT5
GPIO_MUX3_IO24 GPIO_AD_25 ALT5
GPIO_MUX3_IO25 GPIO_AD_26 ALT5
GPIO_MUX3_IO26 GPIO_AD_27 ALT5
GPIO_MUX3_IO27 GPIO_AD_28 ALT5
GPIO_MUX3_IO28 GPIO_AD_29 ALT5
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO_MUX3_IO29 GPIO_AD_30 ALT5
GPIO_MUX3_IO30 GPIO_AD_31 ALT5
GPIO_MUX3_IO31 GPIO_AD_32 ALT5
GPIO4 GPIO4_IO00 GPIO_AD_33 ALT5
GPIO4_IO01 GPIO_AD_34 ALT5
GPIO4_IO02 GPIO_AD_35 ALT5
GPIO4_IO03 GPIO_SD_B1_00 ALT5
GPIO4_IO04 GPIO_SD_B1_01 ALT5
GPIO4_IO05 GPIO_SD_B1_02 ALT5
GPIO4_IO06 GPIO_SD_B1_03 ALT5
GPIO4_IO07 GPIO_SD_B1_04 ALT5
GPIO4_IO08 GPIO_SD_B1_05 ALT5
GPIO4_IO09 GPIO_SD_B2_00 ALT5
GPIO4_IO10 GPIO_SD_B2_01 ALT5
GPIO4_IO11 GPIO_SD_B2_02 ALT5
GPIO4_IO12 GPIO_SD_B2_03 ALT5
GPIO4_IO13 GPIO_SD_B2_04 ALT5
GPIO4_IO14 GPIO_SD_B2_05 ALT5
GPIO4_IO15 GPIO_SD_B2_06 ALT5
GPIO4_IO16 GPIO_SD_B2_07 ALT5
GPIO4_IO17 GPIO_SD_B2_08 ALT5
GPIO4_IO18 GPIO_SD_B2_09 ALT5
GPIO4_IO19 GPIO_SD_B2_10 ALT5
GPIO4_IO20 GPIO_SD_B2_11 ALT5
GPIO4_IO21 GPIO_DISP_B1_00 ALT5
GPIO4_IO22 GPIO_DISP_B1_01 ALT5
GPIO4_IO23 GPIO_DISP_B1_02 ALT5
GPIO4_IO24 GPIO_DISP_B1_03 ALT5
GPIO4_IO25 GPIO_DISP_B1_04 ALT5
GPIO4_IO26 GPIO_DISP_B1_05 ALT5
GPIO4_IO27 GPIO_DISP_B1_06 ALT5
GPIO4_IO28 GPIO_DISP_B1_07 ALT5
GPIO4_IO29 GPIO_DISP_B1_08 ALT5
GPIO4_IO30 GPIO_DISP_B1_09 ALT5
GPIO4_IO31 GPIO_DISP_B1_10 ALT5
GPIO5 GPIO5_IO00 GPIO_DISP_B1_11 ALT5
GPIO5_IO01 GPIO_DISP_B2_00 ALT5
GPIO5_IO02 GPIO_DISP_B2_01 ALT5
GPIO5_IO03 GPIO_DISP_B2_02 ALT5
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO5_IO04 GPIO_DISP_B2_03 ALT5
GPIO5_IO05 GPIO_DISP_B2_04 ALT5
GPIO5_IO06 GPIO_DISP_B2_05 ALT5
GPIO5_IO07 GPIO_DISP_B2_06 ALT5
GPIO5_IO08 GPIO_DISP_B2_07 ALT5
GPIO5_IO09 GPIO_DISP_B2_08 ALT5
GPIO5_IO10 GPIO_DISP_B2_09 ALT5
GPIO5_IO11 GPIO_DISP_B2_10 ALT5
GPIO5_IO12 GPIO_DISP_B2_11 ALT5
GPIO5_IO13 GPIO_DISP_B2_12 ALT5
GPIO5_IO14 GPIO_DISP_B2_13 ALT5
GPIO5_IO15 GPIO_DISP_B2_14 ALT5
GPIO5_IO16 GPIO_DISP_B2_15 ALT5
GPIO6 GPIO6_IO00 GPIO_LPSR_00 ALT5
GPIO6_IO01 GPIO_LPSR_01 ALT5
GPIO6_IO02 GPIO_LPSR_02 ALT5
GPIO6_IO03 GPIO_LPSR_03 ALT5
GPIO6_IO04 GPIO_LPSR_04 ALT5
GPIO6_IO05 GPIO_LPSR_05 ALT5
GPIO6_IO06 GPIO_LPSR_06 ALT5
GPIO6_IO07 GPIO_LPSR_07 ALT5
GPIO6_IO08 GPIO_LPSR_08 ALT5
GPIO6_IO09 GPIO_LPSR_09 ALT5
GPIO6_IO10 GPIO_LPSR_10 ALT5
GPIO6_IO11 GPIO_LPSR_11 ALT5
GPIO6_IO12 GPIO_LPSR_12 ALT5
GPIO6_IO13 GPIO_LPSR_13 ALT5
GPIO6_IO14 GPIO_LPSR_14 ALT5
GPIO6_IO15 GPIO_LPSR_15 ALT5
GPIO7 GPIO7_IO00 GPIO_EMC_B1_00 ALT10
GPIO7_IO01 GPIO_EMC_B1_01 ALT10
GPIO7_IO02 GPIO_EMC_B1_02 ALT10
GPIO7_IO03 GPIO_EMC_B1_03 ALT10
GPIO7_IO04 GPIO_EMC_B1_04 ALT10
GPIO7_IO05 GPIO_EMC_B1_05 ALT10
GPIO7_IO06 GPIO_EMC_B1_06 ALT10
GPIO7_IO07 GPIO_EMC_B1_07 ALT10
GPIO7_IO08 GPIO_EMC_B1_08 ALT10
GPIO7_IO09 GPIO_EMC_B1_09 ALT10
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO7_IO10 GPIO_EMC_B1_10 ALT10
GPIO7_IO11 GPIO_EMC_B1_11 ALT10
GPIO7_IO12 GPIO_EMC_B1_12 ALT10
GPIO7_IO13 GPIO_EMC_B1_13 ALT10
GPIO7_IO14 GPIO_EMC_B1_14 ALT10
GPIO7_IO15 GPIO_EMC_B1_15 ALT10
GPIO7_IO16 GPIO_EMC_B1_16 ALT10
GPIO7_IO17 GPIO_EMC_B1_17 ALT10
GPIO7_IO18 GPIO_EMC_B1_18 ALT10
GPIO7_IO19 GPIO_EMC_B1_19 ALT10
GPIO7_IO20 GPIO_EMC_B1_20 ALT10
GPIO7_IO21 GPIO_EMC_B1_21 ALT10
GPIO7_IO22 GPIO_EMC_B1_22 ALT10
GPIO7_IO23 GPIO_EMC_B1_23 ALT10
GPIO7_IO24 GPIO_EMC_B1_24 ALT10
GPIO7_IO25 GPIO_EMC_B1_25 ALT10
GPIO7_IO26 GPIO_EMC_B1_26 ALT10
GPIO7_IO27 GPIO_EMC_B1_27 ALT10
GPIO7_IO28 GPIO_EMC_B1_28 ALT10
GPIO7_IO29 GPIO_EMC_B1_29 ALT10
GPIO7_IO30 GPIO_EMC_B1_30 ALT10
GPIO7_IO31 GPIO_EMC_B1_31 ALT10
GPIO8 GPIO8_IO00 GPIO_EMC_B1_32 ALT10
GPIO8_IO01 GPIO_EMC_B1_33 ALT10
GPIO8_IO02 GPIO_EMC_B1_34 ALT10
GPIO8_IO03 GPIO_EMC_B1_35 ALT10
GPIO8_IO04 GPIO_EMC_B1_36 ALT10
GPIO8_IO05 GPIO_EMC_B1_37 ALT10
GPIO8_IO06 GPIO_EMC_B1_38 ALT10
GPIO8_IO07 GPIO_EMC_B1_39 ALT10
GPIO8_IO08 GPIO_EMC_B1_40 ALT10
GPIO8_IO09 GPIO_EMC_B1_41 ALT10
GPIO8_IO10 GPIO_EMC_B2_00 ALT10
GPIO8_IO11 GPIO_EMC_B2_01 ALT10
GPIO8_IO12 GPIO_EMC_B2_02 ALT10
GPIO8_IO13 GPIO_EMC_B2_03 ALT10
GPIO8_IO14 GPIO_EMC_B2_04 ALT10
GPIO8_IO15 GPIO_EMC_B2_05 ALT10
GPIO8_IO16 GPIO_EMC_B2_06 ALT10
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO8_IO17 GPIO_EMC_B2_07 ALT10
GPIO8_IO18 GPIO_EMC_B2_08 ALT10
GPIO8_IO19 GPIO_EMC_B2_09 ALT10
GPIO8_IO20 GPIO_EMC_B2_10 ALT10
GPIO8_IO21 GPIO_EMC_B2_11 ALT10
GPIO8_IO22 GPIO_EMC_B2_12 ALT10
GPIO8_IO23 GPIO_EMC_B2_13 ALT10
GPIO8_IO24 GPIO_EMC_B2_14 ALT10
GPIO8_IO25 GPIO_EMC_B2_15 ALT10
GPIO8_IO26 GPIO_EMC_B2_16 ALT10
GPIO8_IO27 GPIO_EMC_B2_17 ALT10
GPIO8_IO28 GPIO_EMC_B2_18 ALT10
GPIO8_IO29 GPIO_EMC_B2_19 ALT10
GPIO8_IO30 GPIO_EMC_B2_20 ALT10
GPIO8_IO31 GPIO_AD_00 ALT10
GPIO9 GPIO9_IO00 GPIO_AD_01 ALT10
GPIO9_IO01 GPIO_AD_02 ALT10
GPIO9_IO02 GPIO_AD_03 ALT10
GPIO9_IO03 GPIO_AD_04 ALT10
GPIO9_IO04 GPIO_AD_05 ALT10
GPIO9_IO05 GPIO_AD_06 ALT10
GPIO9_IO06 GPIO_AD_07 ALT10
GPIO9_IO07 GPIO_AD_08 ALT10
GPIO9_IO08 GPIO_AD_09 ALT10
GPIO9_IO09 GPIO_AD_10 ALT10
GPIO9_IO10 GPIO_AD_11 ALT10
GPIO9_IO11 GPIO_AD_12 ALT10
GPIO9_IO12 GPIO_AD_13 ALT10
GPIO9_IO13 GPIO_AD_14 ALT10
GPIO9_IO14 GPIO_AD_15 ALT10
GPIO9_IO15 GPIO_AD_16 ALT10
GPIO9_IO16 GPIO_AD_17 ALT10
GPIO9_IO17 GPIO_AD_18 ALT10
GPIO9_IO18 GPIO_AD_19 ALT10
GPIO9_IO19 GPIO_AD_20 ALT10
GPIO9_IO20 GPIO_AD_21 ALT10
GPIO9_IO21 GPIO_AD_22 ALT10
GPIO9_IO22 GPIO_AD_23 ALT10
GPIO9_IO23 GPIO_AD_24 ALT10
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO9_IO24 GPIO_AD_25 ALT10
GPIO9_IO25 GPIO_AD_26 ALT10
GPIO9_IO26 GPIO_AD_27 ALT10
GPIO9_IO27 GPIO_AD_28 ALT10
GPIO9_IO28 GPIO_AD_29 ALT10
GPIO9_IO29 GPIO_AD_30 ALT10
GPIO9_IO30 GPIO_AD_31 ALT10
GPIO9_IO31 GPIO_AD_32 ALT10
GPIO10 GPIO10_IO00 GPIO_AD_33 ALT10
GPIO10_IO01 GPIO_AD_34 ALT10
GPIO10_IO02 GPIO_AD_35 ALT10
GPIO10_IO03 GPIO_SD_B1_00 ALT10
GPIO10_IO04 GPIO_SD_B1_01 ALT10
GPIO10_IO05 GPIO_SD_B1_02 ALT10
GPIO10_IO06 GPIO_SD_B1_03 ALT10
GPIO10_IO07 GPIO_SD_B1_04 ALT10
GPIO10_IO08 GPIO_SD_B1_05 ALT10
GPIO10_IO09 GPIO_SD_B2_00 ALT10
GPIO10_IO10 GPIO_SD_B2_01 ALT10
GPIO10_IO11 GPIO_SD_B2_02 ALT10
GPIO10_IO12 GPIO_SD_B2_03 ALT10
GPIO10_IO13 GPIO_SD_B2_04 ALT10
GPIO10_IO14 GPIO_SD_B2_05 ALT10
GPIO10_IO15 GPIO_SD_B2_06 ALT10
GPIO10_IO16 GPIO_SD_B2_07 ALT10
GPIO10_IO17 GPIO_SD_B2_08 ALT10
GPIO10_IO18 GPIO_SD_B2_09 ALT10
GPIO10_IO19 GPIO_SD_B2_10 ALT10
GPIO10_IO20 GPIO_SD_B2_11 ALT10
GPIO10_IO21 GPIO_DISP_B1_00 ALT10
GPIO10_IO22 GPIO_DISP_B1_01 ALT10
GPIO10_IO23 GPIO_DISP_B1_02 ALT10
GPIO10_IO24 GPIO_DISP_B1_03 ALT10
GPIO10_IO25 GPIO_DISP_B1_04 ALT10
GPIO10_IO26 GPIO_DISP_B1_05 ALT10
GPIO10_IO27 GPIO_DISP_B1_06 ALT10
GPIO10_IO28 GPIO_DISP_B1_07 ALT10
GPIO10_IO29 GPIO_DISP_B1_08 ALT10
GPIO10_IO30 GPIO_DISP_B1_09 ALT10
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO10_IO31 GPIO_DISP_B1_10 ALT10
GPIO11 GPIO11_IO00 GPIO_DISP_B1_11 ALT10
GPIO11_IO01 GPIO_DISP_B2_00 ALT10
GPIO11_IO02 GPIO_DISP_B2_01 ALT10
GPIO11_IO03 GPIO_DISP_B2_02 ALT10
GPIO11_IO04 GPIO_DISP_B2_03 ALT10
GPIO11_IO05 GPIO_DISP_B2_04 ALT10
GPIO11_IO06 GPIO_DISP_B2_05 ALT10
GPIO11_IO07 GPIO_DISP_B2_06 ALT10
GPIO11_IO08 GPIO_DISP_B2_07 ALT10
GPIO11_IO09 GPIO_DISP_B2_08 ALT10
GPIO11_IO10 GPIO_DISP_B2_09 ALT10
GPIO11_IO11 GPIO_DISP_B2_10 ALT10
GPIO11_IO12 GPIO_DISP_B2_11 ALT10
GPIO11_IO13 GPIO_DISP_B2_12 ALT10
GPIO11_IO14 GPIO_DISP_B2_13 ALT10
GPIO11_IO15 GPIO_DISP_B2_14 ALT10
GPIO11_IO16 GPIO_DISP_B2_15 ALT10
GPIO12 GPIO12_IO00 GPIO_LPSR_00 ALT10
GPIO12_IO01 GPIO_LPSR_01 ALT10
GPIO12_IO02 GPIO_LPSR_02 ALT10
GPIO12_IO03 GPIO_LPSR_03 ALT10
GPIO12_IO04 GPIO_LPSR_04 ALT10
GPIO12_IO05 GPIO_LPSR_05 ALT10
GPIO12_IO06 GPIO_LPSR_06 ALT10
GPIO12_IO07 GPIO_LPSR_07 ALT10
GPIO12_IO08 GPIO_LPSR_08 ALT10
GPIO12_IO09 GPIO_LPSR_09 ALT10
GPIO12_IO10 GPIO_LPSR_10 ALT10
GPIO12_IO11 GPIO_LPSR_11 ALT10
GPIO12_IO12 GPIO_LPSR_12 ALT10
GPIO12_IO13 GPIO_LPSR_13 ALT10
GPIO12_IO14 GPIO_LPSR_14 ALT10
GPIO12_IO15 GPIO_LPSR_15 ALT10
GPIO133 GPIO13_IO00 WAKEUP ALT5
GPIO13_IO01 PMIC_ON_REQ ALT5
GPIO13_IO02 PMIC_STBY_REQ ALT5
GPIO13_IO03 GPIO_SNVS_00 ALT5
GPIO13_IO04 GPIO_SNVS_01 ALT5
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPIO13_IO05 GPIO_SNVS_02 ALT5
GPIO13_IO06 GPIO_SNVS_03 ALT5
GPIO13_IO07 GPIO_SNVS_04 ALT5
GPIO13_IO08 GPIO_SNVS_05 ALT5
GPIO13_IO09 GPIO_SNVS_06 ALT5
GPIO13_IO10 GPIO_SNVS_07 ALT5
GPIO13_IO11 GPIO_SNVS_08 ALT5
GPIO13_IO12 GPIO_SNVS_09 ALT5
GPT1 GPT1_CAPTURE1 GPIO_AD_12 ALT2
GPT1_CAPTURE2 GPIO_AD_13 ALT2
GPT1_CLK GPIO_AD_17 ALT2
GPT1_COMPARE1 GPIO_AD_14 ALT2
GPT1_COMPARE2 GPIO_AD_15 ALT2
GPT1_COMPARE3 GPIO_AD_16 ALT2
GPT2 GPT2_CAPTURE1 GPIO_AD_00 ALT3
GPT2_CAPTURE2 GPIO_AD_01 ALT3
GPT2_CLK GPIO_AD_05 ALT3
GPT2_COMPARE1 GPIO_AD_02 ALT3
GPT2_COMPARE2 GPIO_AD_03 ALT3
GPT2_COMPARE3 GPIO_AD_04 ALT3
GPT3 GPT3_CAPTURE1 GPIO_EMC_B2_06 ALT1
GPT3_CAPTURE1 GPIO_AD_06 ALT3
GPT3_CAPTURE2 GPIO_EMC_B2_07 ALT1
GPT3_CAPTURE2 GPIO_AD_07 ALT3
GPT3_CLK GPIO_EMC_B2_05 ALT1
GPT3_CLK GPIO_AD_11 ALT3
GPT3_COMPARE1 GPIO_EMC_B2_08 ALT1
GPT3_COMPARE1 GPIO_AD_08 ALT3
GPT3_COMPARE2 GPIO_EMC_B2_09 ALT1
GPT3_COMPARE2 GPIO_AD_09 ALT3
GPT3_COMPARE3 GPIO_EMC_B2_10 ALT1
GPT3_COMPARE3 GPIO_AD_10 ALT3
GPT4 GPT4_CAPTURE1 GPIO_SD_B1_00 ALT3
GPT4_CAPTURE2 GPIO_SD_B1_01 ALT3
GPT4_CLK GPIO_SD_B1_05 ALT3
GPT4_COMPARE1 GPIO_SD_B1_02 ALT3
GPT4_COMPARE2 GPIO_SD_B1_03 ALT3
GPT4_COMPARE3 GPIO_SD_B1_04 ALT3
GPT5 GPT5_CAPTURE1 GPIO_EMC_B1_09 ALT2
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
GPT5_CAPTURE2 GPIO_EMC_B1_10 ALT2
GPT5_CLK GPIO_EMC_B1_14 ALT2
GPT5_COMPARE1 GPIO_EMC_B1_11 ALT2
GPT5_COMPARE2 GPIO_EMC_B1_12 ALT2
GPT5_COMPARE3 GPIO_EMC_B1_13 ALT2
GPT6 GPT6_CAPTURE1 GPIO_SD_B2_06 ALT4
GPT6_CAPTURE2 GPIO_SD_B2_07 ALT4
GPT6_CLK GPIO_SD_B2_11 ALT4
GPT6_COMPARE1 GPIO_SD_B2_08 ALT4
GPT6_COMPARE2 GPIO_SD_B2_09 ALT4
GPT6_COMPARE3 GPIO_SD_B2_10 ALT4
JTAG JTAG_MUX_MOD GPIO_LPSR_13 ALT0
JTAG_MUX_TCK (SWD) GPIO_LPSR_14 ALT0
JTAG_MUX_TDI GPIO_LPSR_12 ALT0
JTAG_MUX_TDO GPIO_LPSR_11 ALT0
JTAG_MUX_TMS (SWD) GPIO_LPSR_15 ALT0
JTAG_MUX_TRSTB GPIO_LPSR_10 ALT0
KPP KPP_COL0 GPIO_AD_35 ALT6
KPP_COL1 GPIO_AD_33 ALT6
KPP_COL2 GPIO_AD_31 ALT6
KPP_COL3 GPIO_AD_29 ALT6
KPP_COL4 GPIO_AD_27 ALT6
KPP_COL5 GPIO_AD_25 ALT6
KPP_COL6 GPIO_AD_23 ALT6
KPP_COL6 GPIO_SD_B1_03 ALT8
KPP_COL7 GPIO_AD_21 ALT6
KPP_COL7 GPIO_SD_B1_01 ALT8
KPP_ROW0 GPIO_AD_34 ALT6
KPP_ROW1 GPIO_AD_32 ALT6
KPP_ROW2 GPIO_AD_30 ALT6
KPP_ROW3 GPIO_AD_28 ALT6
KPP_ROW4 GPIO_AD_26 ALT6
KPP_ROW5 GPIO_AD_24 ALT6
KPP_ROW6 GPIO_AD_22 ALT6
KPP_ROW6 GPIO_SD_B1_02 ALT8
KPP_ROW7 GPIO_AD_20 ALT6
KPP_ROW7 GPIO_SD_B1_00 ALT8
LPI2C1 LPI2C1_HREQ GPIO_AD_12 ALT1
LPI2C1_SCL GPIO_AD_32 ALT0
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
LPI2C1_SCL GPIO_AD_08 ALT1
LPI2C1_SCLS GPIO_AD_10 ALT1
LPI2C1_SDA GPIO_AD_33 ALT0
LPI2C1_SDA GPIO_AD_09 ALT1
LPI2C1_SDAS GPIO_AD_11 ALT1
LPI2C2 LPI2C2_SCL GPIO_EMC_B2_00 ALT9
LPI2C2_SCL GPIO_AD_18 ALT9
LPI2C2_SDA GPIO_EMC_B2_01 ALT9
LPI2C2_SDA GPIO_AD_19 ALT9
LPI2C3 LPI2C3_SCL GPIO_DISP_B1_02 ALT2
LPI2C3_SCL GPIO_DISP_B2_10 ALT6
LPI2C3_SDA GPIO_DISP_B1_03 ALT2
LPI2C3_SDA GPIO_DISP_B2_11 ALT6
LPI2C4 LPI2C4_SCL GPIO_DISP_B2_12 ALT6
LPI2C4_SCL GPIO_AD_24 ALT9
LPI2C4_SDA GPIO_DISP_B2_13 ALT6
LPI2C4_SDA GPIO_AD_25 ALT9
LPI2C5 LPI2C5_HREQ GPIO_LPSR_12 ALT6
LPI2C5_SCL GPIO_LPSR_05 ALT0
LPI2C5_SCL GPIO_LPSR_09 ALT6
LPI2C5_SCLS GPIO_LPSR_10 ALT6
LPI2C5_SDA GPIO_LPSR_04 ALT0
LPI2C5_SDA GPIO_LPSR_08 ALT6
LPI2C5_SDAS GPIO_LPSR_11 ALT6
LPI2C6 LPI2C6_SCL GPIO_LPSR_07 ALT0
LPI2C6_SCL GPIO_LPSR_11 ALT2
LPI2C6_SDA GPIO_LPSR_06 ALT0
LPI2C6_SDA GPIO_LPSR_10 ALT2
LPSPI1 LPSPI1_PCS0 GPIO_AD_29 ALT0
LPSPI1_PCS0 GPIO_EMC_B2_01 ALT8
LPSPI1_PCS1 GPIO_AD_18 ALT2
LPSPI1_PCS2 GPIO_AD_19 ALT2
LPSPI1_PCS3 GPIO_AD_20 ALT2
LPSPI1_SCK GPIO_AD_28 ALT0
LPSPI1_SCK GPIO_EMC_B2_00 ALT8
LPSPI1_SIN GPIO_AD_31 ALT0
LPSPI1_SIN GPIO_EMC_B2_03 ALT8
LPSPI1_SOUT GPIO_AD_30 ALT0
LPSPI1_SOUT GPIO_EMC_B2_02 ALT8
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
LPSPI2 LPSPI2_PCS0 GPIO_AD_25 ALT1
LPSPI2_PCS0 GPIO_SD_B2_08 ALT6
LPSPI2_PCS1 GPIO_AD_21 ALT2
LPSPI2_PCS1 GPIO_SD_B2_11 ALT6
LPSPI2_PCS2 GPIO_AD_22 ALT2
LPSPI2_PCS3 GPIO_AD_23 ALT2
LPSPI2_SCK GPIO_AD_24 ALT1
LPSPI2_SCK GPIO_SD_B2_07 ALT6
LPSPI2_SIN GPIO_AD_27 ALT1
LPSPI2_SIN GPIO_SD_B2_10 ALT6
LPSPI2_SOUT GPIO_AD_26 ALT1
LPSPI2_SOUT GPIO_SD_B2_09 ALT6
LPSPI3 LPSPI3_PCS0 GPIO_EMC_B2_05 ALT8
LPSPI3_PCS0 GPIO_DISP_B1_07 ALT9
LPSPI3_PCS1 GPIO_EMC_B2_08 ALT8
LPSPI3_PCS1 GPIO_DISP_B1_08 ALT9
LPSPI3_PCS2 GPIO_EMC_B2_09 ALT8
LPSPI3_PCS2 GPIO_DISP_B1_09 ALT9
LPSPI3_PCS3 GPIO_EMC_B2_10 ALT8
LPSPI3_PCS3 GPIO_DISP_B1_10 ALT9
LPSPI3_SCK GPIO_EMC_B2_04 ALT8
LPSPI3_SCK GPIO_DISP_B1_04 ALT9
LPSPI3_SIN GPIO_EMC_B2_07 ALT8
LPSPI3_SIN GPIO_DISP_B1_05 ALT9
LPSPI3_SOUT GPIO_EMC_B2_06 ALT8
LPSPI3_SOUT GPIO_DISP_B1_06 ALT9
LPSPI4 LPSPI4_PCS0 GPIO_SD_B2_01 ALT4
LPSPI4_PCS0 GPIO_DISP_B2_15 ALT9
LPSPI4_PCS1 GPIO_SD_B2_04 ALT4
LPSPI4_PCS2 GPIO_SD_B2_05 ALT4
LPSPI4_PCS3 GPIO_SD_B2_06 ALT3
LPSPI4_SCK GPIO_SD_B2_00 ALT4
LPSPI4_SCK GPIO_DISP_B2_12 ALT9
LPSPI4_SIN GPIO_SD_B2_03 ALT4
LPSPI4_SIN GPIO_DISP_B2_13 ALT9
LPSPI4_SOUT GPIO_SD_B2_02 ALT4
LPSPI4_SOUT GPIO_DISP_B2_14 ALT9
LPSPI5 LPSPI5_PCS0 GPIO_LPSR_03 ALT1
LPSPI5_PCS0 GPIO_LPSR_13 ALT8
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
LPSPI5_PCS1 GPIO_LPSR_06 ALT8
LPSPI5_PCS2 GPIO_LPSR_07 ALT8
LPSPI5_PCS3 GPIO_LPSR_08 ALT8
LPSPI5_SCK GPIO_LPSR_02 ALT1
LPSPI5_SCK GPIO_LPSR_12 ALT8
LPSPI5_SIN GPIO_LPSR_05 ALT1
LPSPI5_SIN GPIO_LPSR_15 ALT8
LPSPI5_SOUT GPIO_LPSR_04 ALT1
LPSPI5_SOUT GPIO_LPSR_14 ALT8
LPSPI6 LPSPI6_PCS0 GPIO_LPSR_09 ALT4
LPSPI6_PCS1 GPIO_LPSR_08 ALT4
LPSPI6_PCS2 GPIO_LPSR_07 ALT4
LPSPI6_PCS3 GPIO_LPSR_06 ALT4
LPSPI6_SCK GPIO_LPSR_10 ALT4
LPSPI6_SIN GPIO_LPSR_12 ALT4
LPSPI6_SOUT GPIO_LPSR_11 ALT4
LPUART1 LPUART1_CTS_B GPIO_AD_26 ALT0
LPUART1_RTS_B GPIO_AD_27 ALT0
LPUART1_RXD GPIO_AD_25 ALT0
LPUART1_RXD GPIO_DISP_B1_03 ALT9
LPUART1_RXD GPIO_DISP_B2_09 ALT9
LPUART1_TXD GPIO_AD_24 ALT0
LPUART1_TXD GPIO_DISP_B1_02 ALT9
LPUART1_TXD GPIO_DISP_B2_08 ALT9
LPUART2 LPUART2_CTS_B GPIO_DISP_B2_12 ALT3
LPUART2_RTS_B GPIO_DISP_B2_13 ALT3
LPUART2_RXD GPIO_DISP_B2_11 ALT2
LPUART2_TXD GPIO_DISP_B2_10 ALT2
LPUART3 LPUART3_CTS_B GPIO_SD_B2_07 ALT3
LPUART3_RTS_B GPIO_SD_B2_08 ALT3
LPUART3_RXD GPIO_AD_31 ALT4
LPUART3_TXD GPIO_AD_30 ALT4
LPUART4 LPUART4_CTS_B GPIO_DISP_B1_05 ALT2
LPUART4_RTS_B GPIO_DISP_B1_07 ALT2
LPUART4_RXD GPIO_DISP_B1_04 ALT2
LPUART4_TXD GPIO_DISP_B1_06 ALT2
LPUART5 LPUART5_CTS_B GPIO_SD_B2_09 ALT3
LPUART5_RTS_B GPIO_SD_B2_10 ALT3
LPUART5_RXD GPIO_AD_29 ALT1
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
LPUART5_TXD GPIO_AD_28 ALT1
LPUART6 LPUART6_CTS_B GPIO_EMC_B2_00 ALT3
LPUART6_RTS_B GPIO_EMC_B2_01 ALT3
LPUART6_RXD GPIO_EMC_B1_41 ALT3
LPUART6_TXD GPIO_EMC_B1_40 ALT3
LPUART7 LPUART7_CTS_B GPIO_AD_02 ALT1
LPUART7_RTS_B GPIO_AD_03 ALT1
LPUART7_RXD GPIO_DISP_B2_07 ALT2
LPUART7_RXD GPIO_AD_01 ALT6
LPUART7_TXD GPIO_DISP_B2_06 ALT2
LPUART7_TXD GPIO_AD_00 ALT6
LPUART8 LPUART8_CTS_B GPIO_AD_04 ALT1
LPUART8_RTS_B GPIO_AD_05 ALT1
LPUART8_RXD GPIO_DISP_B2_09 ALT2
LPUART8_RXD GPIO_AD_03 ALT6
LPUART8_TXD GPIO_DISP_B2_08 ALT2
LPUART8_TXD GPIO_AD_02 ALT6
LPUART9 LPUART9_CTS_B GPIO_SD_B2_02 ALT3
LPUART9_RTS_B GPIO_SD_B2_03 ALT3
LPUART9_RXD GPIO_SD_B2_01 ALT3
LPUART9_TXD GPIO_SD_B2_00 ALT3
LPUART10 LPUART10_CTS_B GPIO_AD_34 ALT8
LPUART10_RTS_B GPIO_AD_35 ALT8
LPUART10_RXD GPIO_AD_16 ALT1
LPUART10_RXD GPIO_AD_33 ALT8
LPUART10_TXD GPIO_AD_15 ALT1
LPUART10_TXD GPIO_AD_32 ALT8
LPUART11 LPUART11_CTS_B GPIO_LPSR_10 ALT1
LPUART11_RTS_B GPIO_LPSR_11 ALT1
LPUART11_RXD GPIO_LPSR_09 ALT0
LPUART11_RXD GPIO_LPSR_05 ALT6
LPUART11_TXD GPIO_LPSR_08 ALT0
LPUART11_TXD GPIO_LPSR_04 ALT6
LPUART12 LPUART12_CTS_B GPIO_LPSR_05 ALT3
LPUART12_RTS_B GPIO_LPSR_04 ALT3
LPUART12_RXD GPIO_LPSR_07 ALT3
LPUART12_RXD GPIO_LPSR_01 ALT6
LPUART12_RXD GPIO_LPSR_11 ALT8
LPUART12_TXD GPIO_LPSR_06 ALT3
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
LPUART12_TXD GPIO_LPSR_00 ALT6
LPUART12_TXD GPIO_LPSR_10 ALT8
MIPI DSI MIPI_DSI_DN0 MIPI_DSI_DN0 No muxing
MIPI_DSI_DP0 MIPI_DSI_DP0 No muxing
MIPI_DSI_DP1 MIPI_DSI_DP1 No muxing
MIPI_DSI_DN1 MIPI_DSI_DN1 No muxing
MIPI_DSI_CLKN MIPI_DSI_CLKN No muxing
MIPI_DSI_CLKP MIPI_DSI_CLKP No muxing
MIPI CSI2 MIPI_CSI_DP0 MIPI_CSI_DP0 No muxing
MIPI_CSI_DN0 MIPI_CSI_DN0 No muxing
MIPI_CSI_DP1 MIPI_CSI_DP1 No muxing
MIPI_CSI_DN1 MIPI_CSI_DN1 No muxing
MIPI_DSI_CLKN MIPI_DSI_CLKN No muxing
MIPI_DSI_CLKP MIPI_DSI_CLKP No muxing
MQS MQS_LEFT GPIO_LPSR_01 ALT2
MQS_LEFT GPIO_EMC_B1_41 ALT2
MQS_LEFT GPIO_DISP_B2_01 ALT2
MQS_LEFT GPIO_LPSR_03 ALT3
MQS_RIGHT GPIO_LPSR_00 ALT2
MQS_RIGHT GPIO_EMC_B1_40 ALT2
MQS_RIGHT GPIO_DISP_B2_00 ALT2
MQS_RIGHT GPIO_LPSR_02 ALT3
PDM PDM_DATA0 GPIO_LPSR_01 ALT1
PDM_DATA0 GPIO_LPSR_09 ALT3
PDM_DATA1 GPIO_LPSR_13 ALT1
PDM_DATA1 GPIO_LPSR_10 ALT3
PDM_DATA2 GPIO_LPSR_14 ALT1
PDM_DATA2 GPIO_LPSR_11 ALT3
PDM_DATA3 GPIO_LPSR_15 ALT1
PDM_DATA3 GPIO_LPSR_12 ALT3
PDM_CLK GPIO_LPSR_00 ALT1
PDM_CLK GPIO_LPSR_08 ALT3
PIT1 PIT1_TRIGGER0 GPIO_AD_13 ALT1
PIT1_TRIGGER0 GPIO_DISP_B2_15 ALT4
PIT1_TRIGGER0 GPIO_EMC_B2_05 ALT9
PIT1_TRIGGER1 GPIO_DISP_B2_04 ALT2
PIT1_TRIGGER1 GPIO_EMC_B2_06 ALT9
PIT1_TRIGGER2 GPIO_DISP_B2_03 ALT2
PIT1_TRIGGER2 GPIO_EMC_B2_07 ALT9
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
PIT1_TRIGGER3 GPIO_DISP_B2_02 ALT2
PIT1_TRIGGER3 GPIO_EMC_B2_08 ALT9
PIT2 PIT2_TRIGGER0 GPIO_LPSR_12 ALT1
PIT2_TRIGGER0 GPIO_LPSR_09 ALT2
PIT2_TRIGGER1 GPIO_LPSR_13 ALT2
PIT2_TRIGGER1 GPIO_LPSR_08 ALT7
PIT2_TRIGGER2 GPIO_LPSR_14 ALT2
PIT2_TRIGGER2 GPIO_LPSR_07 ALT7
PIT2_TRIGGER3 GPIO_LPSR_15 ALT2
PIT2_TRIGGER3 GPIO_LPSR_06 ALT7
PGMC PGMC_PMIC_READY GPIO_AD_32 ALT2
PGMC_PMIC_STBY_REQ PMIC_STBY_REQ ALT0
TMR1 TMR1_TIMER0 GPIO_EMC_B1_17 ALT2
TMR1_TIMER0 GPIO_DISP_B1_00 ALT3
TMR1_TIMER0 GPIO_EMC_B2_09 ALT9
TMR1_TIMER1 GPIO_EMC_B1_38 ALT2
TMR1_TIMER1 GPIO_DISP_B1_01 ALT3
TMR1_TIMER1 GPIO_EMC_B2_10 ALT9
TMR1_TIMER2 GPIO_DISP_B1_02 ALT3
TMR1_TIMER2 GPIO_EMC_B2_11 ALT9
TMR1_TIMER3 GPIO_EMC_B2_12 ALT9
TMR2 TMR2_TIMER0 GPIO_EMC_B1_18 ALT2
TMR2_TIMER0 GPIO_DISP_B1_03 ALT3
TMR2_TIMER0 GPIO_EMC_B2_13 ALT9
TMR2_TIMER1 GPIO_EMC_B1_39 ALT2
TMR2_TIMER1 GPIO_DISP_B1_04 ALT3
TMR2_TIMER1 GPIO_EMC_B2_14 ALT9
TMR2_TIMER2 GPIO_DISP_B1_05 ALT3
TMR2_TIMER2 GPIO_EMC_B2_15 ALT9
TMR2_TIMER3 GPIO_EMC_B2_16 ALT9
TMR3 TMR3_TIMER0 GPIO_EMC_B1_19 ALT2
TMR3_TIMER0 GPIO_DISP_B1_06 ALT3
TMR3_TIMER0 GPIO_EMC_B2_17 ALT9
TMR3_TIMER1 GPIO_EMC_B2_00 ALT2
TMR3_TIMER1 GPIO_DISP_B1_07 ALT3
TMR3_TIMER1 GPIO_EMC_B2_18 ALT9
TMR3_TIMER2 GPIO_DISP_B1_08 ALT3
TMR3_TIMER2 GPIO_EMC_B2_19 ALT9
TMR3_TIMER3 GPIO_EMC_B2_20 ALT9
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
TMR4 TMR4_TIMER0 GPIO_EMC_B1_20 ALT2
TMR4_TIMER0 GPIO_DISP_B1_09 ALT3
TMR4_TIMER0 GPIO_AD_04 ALT9
TMR4_TIMER1 GPIO_EMC_B2_01 ALT2
TMR4_TIMER1 GPIO_DISP_B1_10 ALT3
TMR4_TIMER1 GPIO_AD_05 ALT9
TMR4_TIMER2 GPIO_DISP_B1_11 ALT3
TMR4_TIMER2 GPIO_AD_06 ALT9
TMR4_TIMER3 GPIO_AD_07 ALT9
SAI1 SAI1_MCLK GPIO_AD_17 ALT0
SAI1_MCLK GPIO_DISP_B2_03 ALT4
SAI1_RX_BCLK GPIO_AD_19 ALT0
SAI1_RX_BCLK GPIO_DISP_B2_05 ALT4
SAI1_RX_DATA0 GPIO_AD_20 ALT0
SAI1_RX_DATA0 GPIO_DISP_B2_06 ALT4
SAI1_RX_SYNC GPIO_AD_18 ALT0
SAI1_RX_SYNC GPIO_DISP_B2_04 ALT4
SAI1_TX_BCLK GPIO_AD_22 ALT0
SAI1_TX_BCLK GPIO_DISP_B2_08 ALT4
SAI1_TX_DATA0 GPIO_AD_21 ALT0
SAI1_TX_DATA0 GPIO_DISP_B2_07 ALT4
SAI1_TX_DATA1 and GPIO_DISP_B2_02 ALT4
SAI1_RX_DATA3
SAI1_TX_DATA2 and GPIO_DISP_B2_01 ALT4
SAI1_RX_DATA2
SAI1_TX_DATA3 and GPIO_DISP_B2_00 ALT4
SAI1_RX_DATA1
SAI1_TX_SYNC GPIO_AD_23 ALT0
SAI1_TX_SYNC GPIO_DISP_B2_09 ALT4
SAI2 SAI2_MCLK GPIO_EMC_B2_04 ALT2
SAI2_RX_BCLK GPIO_EMC_B2_06 ALT2
SAI2_RX_DATA GPIO_EMC_B2_07 ALT2
SAI2_RX_SYNC GPIO_EMC_B2_05 ALT2
SAI2_TX_BCLK GPIO_EMC_B2_09 ALT2
SAI2_TX_DATA GPIO_EMC_B2_08 ALT2
SAI2_TX_SYNC GPIO_EMC_B2_10 ALT2
SAI3 SAI3_MCLK GPIO_EMC_B2_17 ALT3
SAI3_RX_BCLK GPIO_EMC_B2_12 ALT3
SAI3_RX_DATA GPIO_EMC_B2_13 ALT3
SAI3_RX_SYNC GPIO_EMC_B2_11 ALT3
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
SAI3_TX_BCLK GPIO_EMC_B2_15 ALT3
SAI3_TX_DATA GPIO_EMC_B2_14 ALT3
SAI3_TX_SYNC GPIO_EMC_B2_16 ALT3
SAI4 SAI4_MCLK GPIO_LPSR_05 ALT2
SAI4_MCLK GPIO_LPSR_00 ALT7
SAI4_RX_BCLK GPIO_LPSR_07 ALT2
SAI4_RX_BCLK GPIO_LPSR_14 ALT7
SAI4_RX_DATA GPIO_LPSR_06 ALT2
SAI4_RX_DATA GPIO_LPSR_13 ALT7
SAI4_RX_SYNC GPIO_LPSR_08 ALT2
SAI4_RX_SYNC GPIO_LPSR_15 ALT7
SAI4_TX_BCLK GPIO_LPSR_04 ALT2
SAI4_TX_BCLK GPIO_LPSR_12 ALT7
SAI4_TX_DATA GPIO_LPSR_02 ALT2
SAI4_TX_DATA GPIO_LPSR_09 ALT7
SAI4_TX_SYNC GPIO_LPSR_03 ALT2
SAI4_TX_SYNC GPIO_LPSR_10 ALT7
SEMC SEMC_ADDR00 GPIO_EMC_B1_09 ALT0
SEMC_ADDR01 GPIO_EMC_B1_10 ALT0
SEMC_ADDR02 GPIO_EMC_B1_11 ALT0
SEMC_ADDR03 GPIO_EMC_B1_12 ALT0
SEMC_ADDR04 GPIO_EMC_B1_13 ALT0
SEMC_ADDR05 GPIO_EMC_B1_14 ALT0
SEMC_ADDR06 GPIO_EMC_B1_15 ALT0
SEMC_ADDR07 GPIO_EMC_B1_16 ALT0
SEMC_ADDR08 GPIO_EMC_B1_17 ALT0
SEMC_ADDR09 GPIO_EMC_B1_18 ALT0
SEMC_ADDR10 GPIO_EMC_B1_23 ALT0
SEMC_ADDR11 GPIO_EMC_B1_19 ALT0
SEMC_ADDR12 GPIO_EMC_B1_20 ALT0
SEMC_BA0 GPIO_EMC_B1_21 ALT0
SEMC_BA1 GPIO_EMC_B1_22 ALT0
SEMC_CAS GPIO_EMC_B1_24 ALT0
SEMC_CKE GPIO_EMC_B1_27 ALT0
SEMC_CLK GPIO_EMC_B1_26 ALT0
SEMC_CLKX0 GPIO_EMC_B2_19 ALT0
SEMC_CLKX1 GPIO_EMC_B2_20 ALT0
SEMC_CS0 GPIO_EMC_B1_29 ALT0
SEMC_CSX0 GPIO_EMC_B1_41 ALT0
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
SEMC_CSX1 GPIO_AD_26 ALT2
SEMC_CSX2 GPIO_AD_27 ALT2
SEMC_CSX3 GPIO_AD_28 ALT2
SEMC_DATA00 GPIO_EMC_B1_00 ALT0
SEMC_DATA01 GPIO_EMC_B1_01 ALT0
SEMC_DATA10 GPIO_EMC_B1_32 ALT0
SEMC_DATA11 GPIO_EMC_B1_33 ALT0
SEMC_DATA12 GPIO_EMC_B1_34 ALT0
SEMC_DATA13 GPIO_EMC_B1_35 ALT0
SEMC_DATA14 GPIO_EMC_B1_36 ALT0
SEMC_DATA15 GPIO_EMC_B1_37 ALT0
SEMC_DATA16 GPIO_EMC_B2_00 ALT0
SEMC_DATA17 GPIO_EMC_B2_01 ALT0
SEMC_DATA18 GPIO_EMC_B2_02 ALT0
SEMC_DATA19 GPIO_EMC_B2_03 ALT0
SEMC_DATA02 GPIO_EMC_B1_02 ALT0
SEMC_DATA20 GPIO_EMC_B2_04 ALT0
SEMC_DATA21 GPIO_EMC_B2_05 ALT0
SEMC_DATA22 GPIO_EMC_B2_06 ALT0
SEMC_DATA23 GPIO_EMC_B2_07 ALT0
SEMC_DATA24 GPIO_EMC_B2_09 ALT0
SEMC_DATA25 GPIO_EMC_B2_10 ALT0
SEMC_DATA26 GPIO_EMC_B2_11 ALT0
SEMC_DATA27 GPIO_EMC_B2_12 ALT0
SEMC_DATA28 GPIO_EMC_B2_13 ALT0
SEMC_DATA29 GPIO_EMC_B2_14 ALT0
SEMC_DATA03 GPIO_EMC_B1_03 ALT0
SEMC_DATA30 GPIO_EMC_B2_15 ALT0
SEMC_DATA31 GPIO_EMC_B2_16 ALT0
SEMC_DATA04 GPIO_EMC_B1_04 ALT0
SEMC_DATA05 GPIO_EMC_B1_05 ALT0
SEMC_DATA06 GPIO_EMC_B1_06 ALT0
SEMC_DATA07 GPIO_EMC_B1_07 ALT0
SEMC_DATA08 GPIO_EMC_B1_30 ALT0
SEMC_DATA09 GPIO_EMC_B1_31 ALT0
SEMC_DM0 GPIO_EMC_B1_08 ALT0
SEMC_DM1 GPIO_EMC_B1_38 ALT0
SEMC_DM2 GPIO_EMC_B2_08 ALT0
SEMC_DM3 GPIO_EMC_B2_17 ALT0
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
SEMC_DQS GPIO_EMC_B1_39 ALT0
SEMC_DQS4 GPIO_EMC_B2_18 ALT0
SEMC_RAS GPIO_EMC_B1_25 ALT0
SEMC_RDY GPIO_EMC_B1_40 ALT0
SEMC_WE GPIO_EMC_B1_28 ALT0
SNVS LP4 SNVS_PMIC_ON_REQ PMIC_ON_REQ ALT0
SNVS_TAMPER1 GPIO_SNVS_00 ALT0
SNVS_TAMPER2 GPIO_SNVS_01 ALT0
SNVS_TAMPER3 GPIO_SNVS_02 ALT0
SNVS_TAMPER4 GPIO_SNVS_03 ALT0
SNVS_TAMPER5 GPIO_SNVS_04 ALT0
SNVS_TAMPER6 GPIO_SNVS_05 ALT0
SNVS_TAMPER7 GPIO_SNVS_06 ALT0
SNVS_TAMPER8 GPIO_SNVS_07 ALT0
SNVS_TAMPER9 GPIO_SNVS_08 ALT0
SNVS_TAMPER10 GPIO_SNVS_09 ALT0
SPDIF SPDIF_EXT_CLK GPIO_AD_14 ALT0
SPDIF_IN GPIO_AD_15 ALT0
SPDIF_IN GPIO_EMC_B2_11 ALT1
SPDIF_IN GPIO_DISP_B2_10 ALT9
SPDIF_LOCK GPIO_AD_12 ALT0
SPDIF_OUT GPIO_AD_16 ALT0
SPDIF_OUT GPIO_EMC_B2_12 ALT1
SPDIF_OUT GPIO_DISP_B2_11 ALT9
SPDIF_SR_CLK GPIO_AD_13 ALT0
SRC SRC_BOOT_MODE0 GPIO_LPSR_02 ALT0
SRC_BOOT_MODE1 GPIO_LPSR_03 ALT0
SRC_BT_CFG0 GPIO_DISP_B1_06 ALT6
SRC_BT_CFG1 GPIO_DISP_B1_07 ALT6
SRC_BT_CFG10 GPIO_DISP_B2_04 ALT6
SRC_BT_CFG11 GPIO_DISP_B2_05 ALT6
SRC_BT_CFG2 GPIO_DISP_B1_08 ALT6
SRC_BT_CFG3 GPIO_DISP_B1_09 ALT6
SRC_BT_CFG4 GPIO_DISP_B1_10 ALT6
SRC_BT_CFG5 GPIO_DISP_B1_11 ALT6
SRC_BT_CFG6 GPIO_DISP_B2_00 ALT6
SRC_BT_CFG7 GPIO_DISP_B2_01 ALT6
SRC_BT_CFG8 GPIO_DISP_B2_02 ALT6
SRC_BT_CFG9 GPIO_DISP_B2_03 ALT6
Table continues on the next page...
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Overview
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
SRC_POR_B POR_B ALT0
SRC_RESET_B ONOFF ALT0
USB OTG1 USB_OTG1_OC GPIO_AD_11 ALT0
GPIO_AD_35 ALT1
USB_OTG1_PWR GPIO_AD_10 ALT0
GPIO_AD_34 ALT1
USB_OTG1_ID GPIO_AD_09 ALT0
GPIO_AD_33 ALT1
USB_OTG1_DN USB1_DN No muxing
USB_OTG1_DP USB1_DP No muxing
USB_OTG1_VBUS USB1_VBUS No muxing
USB OTG2 USB_OTG2_OC GPIO_AD_06 ALT0
GPIO_AD_30 ALT1
USB_OTG2_PWR GPIO_AD_07 ALT0
GPIO_AD_31 ALT1
USB_OTG2_ID GPIO_AD_08 ALT0
GPIO_AD_32 ALT1
USB_OTG2_DN USB2_DN No muxing
USB_OTG2_VBUS USB2_VBUS No muxing
USB_OTG2_DP USB2_DP No muxing
USDHC1 USDHC1_CD_B GPIO_DISP_B1_08 ALT2
GPIO_AD_32 ALT4
USDHC1_CLK GPIO_SD_B1_01 ALT0
USDHC1_CMD GPIO_SD_B1_00 ALT0
USDHC1_DATA0 GPIO_SD_B1_02 ALT0
USDHC1_DATA1 GPIO_SD_B1_03 ALT0
USDHC1_DATA2 GPIO_SD_B1_04 ALT0
USDHC1_DATA3 GPIO_SD_B1_05 ALT0
USDHC1_RESET_B GPIO_DISP_B1_10 ALT2
GPIO_AD_35 ALT4
USDHC1_VSELECT GPIO_DISP_B2_01 ALT1
GPIO_AD_34 ALT4
USDHC1_WP GPIO_DISP_B1_09 ALT2
GPIO_AD_33 ALT4
USDHC2 USDHC2_CD_B GPIO_EMC_B2_01 ALT1
GPIO_AD_26 ALT11
USDHC2_CLK GPIO_SD_B2_04 ALT0
USDHC2_CMD GPIO_SD_B2_05 ALT0
USDHC2_DATA0 GPIO_SD_B2_03 ALT0
Table continues on the next page...
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
USDHC2_DATA1 GPIO_SD_B2_02 ALT0
USDHC2_DATA2 GPIO_SD_B2_01 ALT0
USDHC2_DATA3 GPIO_SD_B2_00 ALT0
USDHC2_DATA4 GPIO_SD_B2_08 ALT0
USDHC2_DATA5 GPIO_SD_B2_09 ALT0
USDHC2_DATA6 GPIO_SD_B2_10 ALT0
USDHC2_DATA7 GPIO_SD_B2_11 ALT0
USDHC2_RESET_B GPIO_SD_B2_06 ALT0
GPIO_EMC_B2_04 ALT1
GPIO_AD_29 ALT11
USDHC2_STROBE GPIO_SD_B2_07 ALT0
USDHC2_VSELECT GPIO_EMC_B2_03 ALT1
GPIO_AD_28 ALT11
USDHC2_WP GPIO_EMC_B2_02 ALT1
GPIO_AD_27 ALT11
VIDEO MUX (CSI) VIDEO_MUX_CSI_DATA00 GPIO_AD_24 ALT2
VIDEO_MUX_CSI_DATA01 GPIO_AD_25 ALT2
VIDEO_MUX_CSI_DATA10 GPIO_AD_11 ALT4
VIDEO_MUX_CSI_DATA11 GPIO_AD_10 ALT4
VIDEO_MUX_CSI_DATA12 GPIO_AD_09 ALT4
VIDEO_MUX_CSI_DATA13 GPIO_AD_08 ALT4
VIDEO_MUX_CSI_DATA14 GPIO_AD_07 ALT4
VIDEO_MUX_CSI_DATA15 GPIO_AD_06 ALT4
VIDEO_MUX_CSI_DATA16 GPIO_EMC_B2_09 ALT3
VIDEO_MUX_CSI_DATA17 GPIO_EMC_B2_08 ALT3
VIDEO_MUX_CSI_DATA18 GPIO_EMC_B2_07 ALT3
VIDEO_MUX_CSI_DATA19 GPIO_EMC_B2_06 ALT3
VIDEO_MUX_CSI_DATA02 GPIO_AD_23 ALT4
VIDEO_MUX_CSI_DATA20 GPIO_EMC_B2_05 ALT3
VIDEO_MUX_CSI_DATA21 GPIO_EMC_B2_04 ALT3
VIDEO_MUX_CSI_DATA22 GPIO_EMC_B2_03 ALT3
VIDEO_MUX_CSI_DATA23 GPIO_EMC_B2_02 ALT3
VIDEO_MUX_CSI_DATA03 GPIO_AD_22 ALT4
VIDEO_MUX_CSI_DATA04 GPIO_AD_21 ALT4
VIDEO_MUX_CSI_DATA05 GPIO_AD_20 ALT4
VIDEO_MUX_CSI_DATA06 GPIO_AD_19 ALT4
VIDEO_MUX_CSI_DATA07 GPIO_AD_18 ALT4
VIDEO_MUX_CSI_DATA08 GPIO_AD_17 ALT4
VIDEO_MUX_CSI_DATA09 GPIO_AD_16 ALT4
Table continues on the next page...
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
VIDEO_MUX_CSI_FIELD GPIO_EMC_B2_10 ALT3
VIDEO_MUX_CSI_HSYNC GPIO_AD_15 ALT4
VIDEO_MUX_CSI_MCLK GPIO_AD_13 ALT4
VIDEO_MUX_CSI_PIXCLK GPIO_AD_12 ALT4
VIDEO_MUX_CSI_VSYNC GPIO_AD_14 ALT4
VIDEO MUX DCIC(MIPI DSI) VIDEO_MUX_EXT_DCIC1 GPIO_DISP_B2_14 ALT3
GPIO_AD_02 ALT9
GPIO_AD_28 ALT9
VIDEO MUX DCIC (Parallel VIDEO_MUX_EXT_DCIC2 GPIO_DISP_B2_15 ALT3
LCDIF) GPIO_AD_03 ALT9
GPIO_AD_29 ALT9
VIDEO MUX (LCDIF) VIDEO_MUX_LCDIF_DOTCL GPIO_DISP_B1_00 ALT0
K
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_04 ALT0
0
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_05 ALT0
1
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_02 ALT0
0
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_03 ALT0
1
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_04 ALT0
2
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_05 ALT0
3
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_06 ALT0
4
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_07 ALT0
5
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_08 ALT0
6
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_09 ALT0
7
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_10 ALT0
8
VIDEO_MUX_LCDIF_DATA1 GPIO_DISP_B2_11 ALT0
9
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_06 ALT0
2
VIDEO_MUX_LCDIF_DATA2 GPIO_DISP_B2_12 ALT0
0
VIDEO_MUX_LCDIF_DATA2 GPIO_DISP_B2_13 ALT0
1
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
VIDEO_MUX_LCDIF_DATA2 GPIO_DISP_B2_14 ALT0
2
VIDEO_MUX_LCDIF_DATA2 GPIO_DISP_B2_15 ALT0
3
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_07 ALT0
3
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_08 ALT0
4
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_09 ALT0
5
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_10 ALT0
6
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B1_11 ALT0
7
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B2_00 ALT0
8
VIDEO_MUX_LCDIF_DATA0 GPIO_DISP_B2_01 ALT0
9
VIDEO_MUX_LCDIF_ENABL GPIO_DISP_B1_01 ALT0
E
VIDEO_MUX_LCDIF_HSYNC GPIO_DISP_B1_02 ALT0
VIDEO_MUX_LCDIF_VSYNC GPIO_DISP_B1_03 ALT0
WDOG1 WDOG1_ANY GPIO_EMC_B2_17 ALT8
WDOG1_ANY GPIO_AD_34 ALT9
WDOG1_B GPIO_DISP_B2_00 ALT1
WDOG1_B GPIO_DISP_B2_15 ALT2
WDOG1_B GPIO_AD_04 ALT6
WDOG1_B GPIO_EMC_B2_18 ALT8
WDOG1_RESET_B_DEB GPIO_DISP_B2_11 ALT3
WDOG1_RESET_B_DEB GPIO_AD_31 ALT9
WDOG2 WDOG2_B GPIO_DISP_B2_14 ALT2
WDOG2_B GPIO_DISP_B2_01 ALT3
WDOG2_B GPIO_AD_05 ALT6
WDOG2_RESET_B_DEB GPIO_DISP_B2_10 ALT3
WDOG2_RESET_B_DEB GPIO_AD_30 ALT9
XBAR XBAR_INOUT10 GPIO_EMC_B1_36 ALT1
XBAR_INOUT11 GPIO_EMC_B1_37 ALT1
XBAR_INOUT12 GPIO_EMC_B1_40 ALT1
XBAR_INOUT13 GPIO_EMC_B1_41 ALT1
XBAR_INOUT14 GPIO_EMC_B2_16 ALT1
XBAR_INOUT15 GPIO_EMC_B2_17 ALT1
XBAR_INOUT16 GPIO_EMC_B2_18 ALT1
Table continues on the next page...
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Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
XBAR_INOUT17 GPIO_AD_33 ALT2
XBAR_INOUT18 GPIO_AD_34 ALT2
XBAR_INOUT19 GPIO_AD_35 ALT2
XBAR_INOUT20 GPIO_SD_B1_00 ALT2
XBAR_INOUT20 GPIO_EMC_B2_00 ALT6
XBAR_INOUT21 GPIO_SD_B1_01 ALT2
XBAR_INOUT21 GPIO_EMC_B2_01 ALT6
XBAR_INOUT22 GPIO_SD_B1_02 ALT2
XBAR_INOUT22 GPIO_EMC_B2_02 ALT6
XBAR_INOUT23 GPIO_SD_B1_03 ALT2
XBAR_INOUT23 GPIO_EMC_B2_03 ALT6
XBAR_INOUT24 GPIO_SD_B1_04 ALT2
XBAR_INOUT24 GPIO_EMC_B2_04 ALT6
XBAR_INOUT25 GPIO_SD_B1_05 ALT2
XBAR_INOUT25 GPIO_EMC_B2_05 ALT6
XBAR_INOUT26 GPIO_DISP_B1_00 ALT4
XBAR_INOUT26 GPIO_EMC_B2_06 ALT6
XBAR_INOUT27 GPIO_DISP_B1_01 ALT4
XBAR_INOUT27 GPIO_EMC_B2_07 ALT6
XBAR_INOUT28 GPIO_DISP_B1_02 ALT4
XBAR_INOUT28 GPIO_EMC_B2_08 ALT6
XBAR_INOUT29 GPIO_DISP_B1_03 ALT4
XBAR_INOUT29 GPIO_EMC_B2_09 ALT6
XBAR_INOUT30 GPIO_DISP_B1_04 ALT4
XBAR_INOUT30 GPIO_EMC_B2_10 ALT6
XBAR_INOUT31 GPIO_DISP_B1_05 ALT4
XBAR_INOUT31 GPIO_EMC_B2_11 ALT6
XBAR_INOUT32 GPIO_DISP_B1_06 ALT4
XBAR_INOUT32 GPIO_EMC_B2_12 ALT6
XBAR_INOUT33 GPIO_DISP_B1_07 ALT4
XBAR_INOUT33 GPIO_EMC_B2_13 ALT6
XBAR_INOUT34 GPIO_DISP_B1_08 ALT4
XBAR_INOUT34 GPIO_EMC_B2_14 ALT6
XBAR_INOUT35 GPIO_DISP_B1_09 ALT4
XBAR_INOUT35 GPIO_EMC_B2_15 ALT6
XBAR_INOUT36 GPIO_DISP_B1_10 ALT4
XBAR_INOUT37 GPIO_DISP_B1_11 ALT4
XBAR_INOUT38 GPIO_DISP_B2_10 ALT4
XBAR_INOUT39 GPIO_DISP_B2_11 ALT4
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Chapter 11 External Signals and Pin Multiplexing
Table 11-1. Muxing Options (continued)
Instance Port Pad Mode
XBAR_INOUT04 GPIO_EMC_B1_12 ALT1
XBAR_INOUT40 GPIO_DISP_B2_12 ALT4
XBAR_INOUT05 GPIO_EMC_B1_13 ALT1
XBAR_INOUT06 GPIO_EMC_B1_14 ALT1
XBAR_INOUT07 GPIO_EMC_B1_15 ALT1
XBAR_INOUT08 GPIO_EMC_B1_16 ALT1
XBAR_INOUT09 GPIO_EMC_B1_35 ALT1
XTALOSC XTALI XTALI No muxing
XTALO XTALO No muxing
REF_CLK_32K GPIO_AD_13 ALT9
REF_CLK_24M GPIO_AD_14 ALT1
1. This GPIO instance contains a mux that selects between normal GPIO or CM7 fast GPIO. See IOMUXC_GPR_GPR40-41
for more details.
2. This GPIO instance contains a mux that selects between normal GPIO or CM7 fast GPIO. See IOMUXC_GPR_GPR42-43
for more details.
3. For GPIO13_IO3-GPIO13_IO12, GPIO functions are not available on devices that support tamper.
4. Tamper is only available on select part numbers. Refer to the Datasheet for details.
11.1.2 Pin Assignments
Table 11-2. Pin Assignments
Pin Name Pin Assignments Pad Settings
POR_B ALT0 - SRC_POR_B PUS - Weak PU
PUE - Pull Enable
DSE - High drive strength
SRE - Fast slew rate
ONOFF ALT0 - SRC_RESET_B PUS - Weak PU
PUE - Pull Enable
DSE - High drive strength
SRE - Fast slew rate
WAKEUP ALT5 - GPIO13_IO0 ODE - Disabled
ALT7 - NMI_GLUE_NMI PUS - Weak PU
PUE - Pull Enable
DSE - High drive strength
SRE - Fast slew rate
PMIC_ON_REQ ALT0 - SNVS_LP_PMIC_ON_REQ ODE - Disabled
ALT5 - GPIO13_IO1 PUS - Weak PU
PUE - Pull Disable
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
DSE - High drive strength
SRE - Fast slew rate
PMIC_STBY_REQ ALT0 - CCM_PMIC_VSTBY_REQ ODE - Disabled
ALT5 - GPIO13_IO2 PUS - Weak PU
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_001 ALT0 - SNVS_LP_TAMPER1 ODE - Disabled
ALT5 - GPIO13_IO3 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_01 ALT0 - SNVS_LP_TAMPER2 ODE - Disabled
ALT5 - GPIO13_IO4 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_02 ALT0 - SNVS_LP_TAMPER3 ODE - Disabled
ALT5 - GPIO13_IO5 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_03 ALT0 - SNVS_LP_TAMPER4 ODE - Disabled
ALT5 - GPIO13_IO6 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_04 ALT0 - SNVS_LP_TAMPER5 ODE - Disabled
ALT5 - GPIO13_IO7 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_05 ALT0 - SNVS_LP_TAMPER6 ODE - Disabled
ALT5 - GPIO13_IO8 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_06 ALT0 - SNVS_LP_TAMPER7 ODE - Disabled
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT5 - GPIO13_IO9 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_07 ALT0 - SNVS_LP_TAMPER8 ODE - Disabled
ALT5 - GPIO13_IO10 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_08 ALT0 - SNVS_LP_TAMPER9 ODE - Disabled
ALT5 - GPIO13_IO11 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_SNVS_09 ALT0 - SNVS_LP_TAMPER10 ODE - Disabled
ALT5 - GPIO13_IO12 PUS - Weak PD
PUE - Pull Disable
DSE - High drive strength
SRE - Fast slew rate
GPIO_LPSR_00 ALT0 - CAN3_TX ODE - Disabled
ALT1 - PDM_CLK PUS - Weak PD
ALT2 - MQS_RIGHT PUE - Pull Disable
ALT3 - CM4_EVENTO DSE - High drive strength
ALT5 - GPIO6_IO0 SRE - Fast slew rate
ALT6 - LPUART12_TX
ALT7 - SAI4_MCLK
ALT10 - GPIO12_IO0
GPIO_LPSR_01 ALT0 - CAN3_RX ODE - Disabled
ALT1 - PDM_DATA0 PUS - Weak PD
ALT2 - MQS_LEFT PUE - Pull Disable
ALT3 - CM4_EVENTI DSE - High drive strength
ALT5 - GPIO6_IO1 SRE - Fast slew rate
ALT6 - LPUART12_RX
ALT10 - GPIO12_IO1
GPIO_LPSR_02 ALT0 - SRC_BOOT_MODE0 ODE - Disabled
ALT1 - LPSPI5_SCK PUS - Weak PD
ALT2 - SAI4_TX_DATA PUE - Pull Disable
ALT3 - MQS_RIGHT DSE - High drive strength
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT5 - GPIO6_IO2 SRE - Fast slew rate
ALT10 - GPIO12_IO2
GPIO_LPSR_03 ALT0 - SRC_BOOT_MODE1 ODE - Disabled
ALT1 - LPSPI5_PCS0 PUS - Weak PD
ALT2 - SAI4_TX_SYNC PUE - Pull Disable
ALT3 - MQS_LEFT DSE - High drive strength
ALT5 - GPIO6_IO3 SRE - Fast slew rate
ALT10 - GPIO12_IO3
GPIO_LPSR_04 ALT0 - LPI2C5_SDA ODE - Disabled
ALT1 - LPSPI5_SDO PUS - Weak PD
ALT2 - SAI4_TX_BCLK PUE - Pull Disable
ALT3 - LPUART12_RTS_B DSE - High drive strength
ALT5 - GPIO6_IO4 SRE - Fast slew rate
ALT6 - LPUART11_TX
ALT10 - GPIO12_IO4
GPIO_LPSR_05 ALT0 - LPI2C5_SCL ODE - Disabled
ALT1 - LPSPI5_SDI PUS - Weak PD
ALT2 - SAI4_MCLK PUE - Pull Disable
ALT3 - LPUART12_CTS_B DSE - High drive strength
ALT5 - GPIO6_IO5 SRE - Fast slew rate
ALT6 - LPUART11_RX
ALT7 - NMI_GLUE_NMI
ALT10 - GPIO12_IO5
GPIO_LPSR_06 ALT0 - LPI2C6_SDA ODE - Disabled
ALT2 - SAI4_RX_DATA PUS - Weak PD
ALT3 - LPUART12_TX PUE - Pull Disable
ALT4 - LPSPI6_PCS3 DSE - High drive strength
ALT5 - GPIO6_IO6 SRE - Fast slew rate
ALT6 - CAN3_TX
ALT7 - PIT2_TRIGGER3
ALT8 - LPSPI5_PCS1
ALT10 - GPIO12_IO6
GPIO_LPSR_07 ALT0 - LPI2C6_SCL ODE - Disabled
ALT2 - SAI4_RX_BCLK PUS - Weak PD
ALT3 - LPUART12_RX PUE - Pull Disable
ALT4 - LPSPI6_PCS2 DSE - High drive strength
ALT5 - GPIO6_IO7 SRE - Fast slew rate
ALT6 - CAN3_RX
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT7 - PIT2_TRIGGER2
ALT8 - LPSPI5_PCS2
ALT10 - GPIO12_IO7
GPIO_LPSR_08 ALT0 - LPUART11_TX ODE - Disabled
ALT1 - CAN3_TX PUS - Weak PD
ALT2 - SAI4_RX_SYNC PUE - Pull Disable
ALT3 - PDM_CLK DSE - High drive strength
ALT4 - LPSPI6_PCS1 SRE - Fast slew rate
ALT5 - GPIO6_IO8
ALT6 - LPI2C5_SDA
ALT7 - PIT2_TRIGGER1
ALT8 - LPSPI5_PCS3
ALT10 - GPIO12_IO8
GPIO_LPSR_09 ALT0 - LPUART11_RX ODE - Disabled
ALT1 - CAN3_RX PUS - Weak PD
ALT2 - PIT2_TRIGGER0 PUE - Pull Disable
ALT3 - PDM_DATA0 DSE - High drive strength
ALT4 - LPSPI6_PCS0 SRE - Fast slew rate
ALT5 - GPIO6_IO9
ALT6 - LPI2C5_SCL
ALT7 - SAI4_TX_DATA
ALT10 - GPIO12_IO9
GPIO_LPSR_10 ALT0 - JTAG_MUX_TRSTB ODE - Disabled
ALT1 - LPUART11_CTS_B PUS - Weak PU
ALT2 - LPI2C6_SDA PUE - Pull Enable
ALT3 - PDM_DATA1 DSE - High drive strength
ALT4 - LPSPI6_SCK SRE - Fast slew rate
ALT5 - GPIO6_IO10
ALT6 - LPI2C5_SCLS
ALT7 - SAI4_TX_SYNC
ALT8 - LPUART12_TX
ALT10 - GPIO12_IO10
GPIO_LPSR_11 ALT0 - JTAG_MUX_TDO ODE - Disabled
ALT1 - LPUART11_RTS_B PUS - Weak PD
ALT2 - LPI2C6_SCL PUE - Pull Disable
ALT3 - PDM_DATA2 DSE - High drive strength
ALT4 - LPSPI6_SDO SRE - Fast slew rate
ALT5 - GPIO6_IO11
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT6 - LPI2C5_SDAS
ALT7 - CSSYS_TRACE_SWO
ALT8 - LPUART12_RX
ALT10 - GPIO12_IO11
GPIO_LPSR_12 ALT0 - JTAG_MUX_TDI ODE - Disabled
ALT1 - PIT2_TRIGGER0 PUS - Weak PU
ALT3 - PDM_DATA3 PUE - Pull Enable
ALT4 - LPSPI6_SDI DSE - High drive strength
ALT5 - GPIO6_IO12 SRE - Fast slew rate
ALT6 - LPI2C5_HREQ
ALT7 - SAI4_TX_BCLK
ALT8 - LPSPI5_SCK
ALT10 - GPIO12_IO12
GPIO_LPSR_13 ALT0 - JTAG_MUX_MOD ODE - Disabled
ALT1 - PDM_DATA1 PUS - Weak PD
ALT2 - PIT2_TRIGGER1 PUE - Pull Disable
ALT5 - GPIO6_IO13 DSE - High drive strength
ALT7 - SAI4_RX_DATA SRE - Fast slew rate
ALT8 - LPSPI5_PCS0
ALT10 - GPIO12_IO13
GPIO_LPSR_14 ALT0 - JTAG_MUX_TCK ODE - Disabled
ALT1 - PDM_DATA2 PUS - Weak PD
ALT2 - PIT2_TRIGGER2 PUE - Pull Enable
ALT5 - GPIO6_IO14 DSE - High drive strength
ALT7 - SAI4_RX_BCLK SRE - Fast slew rate
ALT8 - LPSPI5_SDO
ALT10 - GPIO12_IO14
GPIO_LPSR_15 ALT0 - JTAG_MUX_TMS ODE - Disabled
ALT1 - PDM_DATA3 PUS - Weak PU
ALT2 - PIT2_TRIGGER3 PUE - Pull Enable
ALT5 - GPIO6_IO15 DSE - High drive strength
ALT7 - SAI4_RX_SYNC SRE - Fast slew rate
ALT8 - LPSPI5_SDI
ALT10 - GPIO12_IO15
GPIO_EMC_B1_00 ALT0 - SEMC_DATA0 ODE - Disabled
ALT1 - FLEXPWM4_PWMA0 PULL - PD
ALT5 - GPIO1_IO0 PDRV - High drive strength
ALT7 - USBPHY1_TSTI_TX_LS_MODE
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - FLEXIO1_FLEXIO0
ALT10 - GPIO7_IO0
GPIO_EMC_B1_01 ALT0 - SEMC_DATA1 ODE - Disabled
ALT1 - FLEXPWM4_PWMB0 PULL - PD
ALT5 - GPIO1_IO1 PDRV - High drive strength
ALT7 - USBPHY1_TSTI_TX_HS_MODE
ALT8 - FLEXIO1_FLEXIO1
ALT10 - GPIO7_IO1
GPIO_EMC_B1_02 ALT0 - SEMC_DATA2 ODE - Disabled
ALT1 - FLEXPWM4_PWMA1 PULL - PD
ALT5 - GPIO1_IO2 PDRV - High drive strength
ALT7 - USBPHY1_TSTI_TX_DN
ALT8 - FLEXIO1_FLEXIO2
ALT10 - GPIO7_IO2
GPIO_EMC_B1_03 ALT0 - SEMC_DATA3 ODE - Disabled
ALT1 - FLEXPWM4_PWMB1 PULL - PD
ALT5 - GPIO1_IO3 PDRV - High drive strength
ALT7 - USBPHY1_TSTO_RX_SQUELCH
ALT8 - FLEXIO1_FLEXIO3
ALT10 - GPIO7_IO3
GPIO_EMC_B1_04 ALT0 - SEMC_DATA4 ODE - Disabled
ALT1 - FLEXPWM4_PWMA2 PULL - PD
ALT5 - GPIO1_IO4 PDRV - High drive strength
ALT7 -
USBPHY1_TSTO_RX_DISCON_DET
ALT8 - FLEXIO1_FLEXIO4
ALT10 - GPIO7_IO4
GPIO_EMC_B1_05 ALT0 - SEMC_DATA5 ODE - Disabled
ALT1 - FLEXPWM4_PWMB2 PULL - PD
ALT5 - GPIO1_IO5 PDRV - High drive strength
ALT7 - USBPHY1_TSTO_RX_HS_RXD
ALT8 - FLEXIO1_FLEXIO5
ALT10 - GPIO7_IO5
GPIO_EMC_B1_06 ALT0 - SEMC_DATA6 ODE - Disabled
ALT1 - FLEXPWM2_PWMA0 PULL - PD
ALT5 - GPIO1_IO6 PDRV - High drive strength
ALT7 - USBPHY2_TSTO_RX_FS_RXD
ALT8 - FLEXIO1_FLEXIO6
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT10 - GPIO7_IO6
GPIO_EMC_B1_07 ALT0 - SEMC_DATA7 ODE - Disabled
ALT1 - FLEXPWM2_PWMB0 PULL - PD
ALT5 - GPIO1_IO7 PDRV - High drive strength
ALT7 - USBPHY1_TSTO_RX_FS_RXD
ALT8 - FLEXIO1_FLEXIO7
ALT10 - GPIO7_IO7
GPIO_EMC_B1_08 ALT0 - SEMC_DM0 ODE - Disabled
ALT1 - FLEXPWM2_PWMA1 PULL - PD
ALT5 - GPIO1_IO8 PDRV - High drive strength
ALT7 - USBPHY1_TSTI_TX_DP
ALT8 - FLEXIO1_FLEXIO8
ALT10 - GPIO7_IO8
GPIO_EMC_B1_09 ALT0 - SEMC_ADDR0 ODE - Disabled
ALT1 - FLEXPWM2_PWMB1 PULL - PD
ALT2 - GPT5_CAPTURE1 PDRV - High drive strength
ALT5 - GPIO1_IO9
ALT7 - USBPHY1_TSTI_TX_EN
ALT8 - FLEXIO1_FLEXIO9
ALT10 - GPIO7_IO9
GPIO_EMC_B1_10 ALT0 - SEMC_ADDR1 ODE - Disabled
ALT1 - FLEXPWM2_PWMA2 PULL - PD
ALT2 - GPT5_CAPTURE2 PDRV - High drive strength
ALT5 - GPIO1_IO10
ALT7 - USBPHY1_TSTI_TX_HIZ
ALT8 - FLEXIO1_FLEXIO10
ALT10 - GPIO7_IO10
GPIO_EMC_B1_11 ALT0 - SEMC_ADDR2 ODE - Disabled
ALT1 - FLEXPWM2_PWMB2 PULL - PD
ALT2 - GPT5_COMPARE1 PDRV - High drive strength
ALT5 - GPIO1_IO11
ALT7 - USBPHY2_TSTO_RX_HS_RXD
ALT8 - FLEXIO1_FLEXIO11
ALT10 - GPIO7_IO11
GPIO_EMC_B1_12 ALT0 - SEMC_ADDR3 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT4 PULL - PD
ALT2 - GPT5_COMPARE2 PDRV - High drive strength
ALT5 - GPIO1_IO12
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT7 - USBPHY1_TSTO_PLL_CLK20DIV
ALT8 - FLEXIO1_FLEXIO12
ALT10 - GPIO7_IO12
GPIO_EMC_B1_13 ALT0 - SEMC_ADDR4 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT5 PULL - PD
ALT2 - GPT5_COMPARE3 PDRV - High drive strength
ALT5 - GPIO1_IO13
ALT7 - USBPHY2_TSTO_PLL_CLK20DIV
ALT8 - FLEXIO1_FLEXIO13
ALT10 - GPIO7_IO13
GPIO_EMC_B1_14 ALT0 - SEMC_ADDR5 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT6 PULL - PD
ALT2 - GPT5_CLK PDRV - High drive strength
ALT5 - GPIO1_IO14
ALT7 - USBPHY2_TSTO_RX_SQUELCH
ALT8 - FLEXIO1_FLEXIO14
ALT10 - GPIO7_IO14
GPIO_EMC_B1_15 ALT0 - SEMC_ADDR6 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT7 PULL - PD
ALT5 - GPIO1_IO15 PDRV - High drive strength
ALT7 -
USBPHY2_TSTO_RX_DISCON_DET
ALT8 - FLEXIO1_FLEXIO15
ALT10 - GPIO7_IO15
GPIO_EMC_B1_16 ALT0 - SEMC_ADDR7 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT8 PULL - PD
ALT5 - GPIO1_IO16 PDRV - High drive strength
ALT7 - ANATOP_WB_TSTO
ALT8 - FLEXIO1_FLEXIO16
ALT10 - GPIO7_IO16
GPIO_EMC_B1_17 ALT0 - SEMC_ADDR8 ODE - Disabled
ALT1 - FLEXPWM4_PWMA3 PULL - PD
ALT2 - QTIMER1_TIMER0 PDRV - High drive strength
ALT5 - GPIO1_IO17
ALT7 - ANATOP_WB_OK
ALT8 - FLEXIO1_FLEXIO17
ALT10 - GPIO7_IO17
GPIO_EMC_B1_18 ALT0 - SEMC_ADDR9 ODE - Disabled
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT1 - FLEXPWM4_PWMB3 PULL - PD
ALT2 - QTIMER2_TIMER0 PDRV - High drive strength
ALT5 - GPIO1_IO18
ALT8 - FLEXIO1_FLEXIO18
ALT10 - GPIO7_IO18
GPIO_EMC_B1_19 ALT0 - SEMC_ADDR11 ODE - Disabled
ALT1 - FLEXPWM2_PWMA3 PULL - PD
ALT2 - QTIMER3_TIMER0 PDRV - High drive strength
ALT5 - GPIO1_IO19
ALT8 - FLEXIO1_FLEXIO19
ALT10 - GPIO7_IO19
GPIO_EMC_B1_20 ALT0 - SEMC_ADDR12 ODE - Disabled
ALT1 - FLEXPWM2_PWMB3 PULL - PD
ALT2 - QTIMER4_TIMER0 PDRV - High drive strength
ALT5 - GPIO1_IO20
ALT8 - FLEXIO1_FLEXIO20
ALT10 - GPIO7_IO20
GPIO_EMC_B1_21 ALT0 - SEMC_BA0 ODE - Disabled
ALT1 - FLEXPWM3_PWMA3 PULL - PD
ALT5 - GPIO1_IO21 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO21
ALT10 - GPIO7_IO21
GPIO_EMC_B1_22 ALT0 - SEMC_BA1 ODE - Disabled
ALT1 - FLEXPWM3_PWMB3 PULL - PD
ALT5 - GPIO1_IO22 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO22
ALT10 - GPIO7_IO22
GPIO_EMC_B1_23 ALT0 - SEMC_ADDR10 ODE - Disabled
ALT1 - FLEXPWM1_PWMA0 PULL - PD
ALT5 - GPIO1_IO23 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO23
ALT10 - GPIO7_IO23
GPIO_EMC_B1_24 ALT0 - SEMC_CAS ODE - Disabled
ALT1 - FLEXPWM1_PWMB0 PULL - PD
ALT5 - GPIO1_IO24 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO24
ALT10 - GPIO7_IO24
GPIO_EMC_B1_25 ALT0 - SEMC_RAS ODE - Disabled
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT1 - FLEXPWM1_PWMA1 PULL - PD
ALT5 - GPIO1_IO25 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO25
ALT10 - GPIO7_IO25
GPIO_EMC_B1_26 ALT0 - SEMC_CLK ODE - Disabled
ALT1 - FLEXPWM1_PWMB1 PULL - PD
ALT5 - GPIO1_IO26 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO26
ALT10 - GPIO7_IO26
GPIO_EMC_B1_27 ALT0 - SEMC_CKE ODE - Disabled
ALT1 - FLEXPWM1_PWMA2 PULL - PD
ALT5 - GPIO1_IO27 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO27
ALT10 - GPIO7_IO27
GPIO_EMC_B1_28 ALT0 - SEMC_WE ODE - Disabled
ALT1 - FLEXPWM1_PWMB2 PULL - PD
ALT5 - GPIO1_IO28 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO28
ALT10 - GPIO7_IO28
GPIO_EMC_B1_29 ALT0 - SEMC_CS0 ODE - Disabled
ALT1 - FLEXPWM3_PWMA0 PULL - PD
ALT5 - GPIO1_IO29 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO29
ALT10 - GPIO7_IO29
GPIO_EMC_B1_30 ALT0 - SEMC_DATA8 ODE - Disabled
ALT1 - FLEXPWM3_PWMB0 PULL - PD
ALT5 - GPIO1_IO30 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO30
ALT10 - GPIO7_IO30
GPIO_EMC_B1_31 ALT0 - SEMC_DATA9 ODE - Disabled
ALT1 - FLEXPWM3_PWMA1 PULL - PD
ALT5 - GPIO1_IO31 PDRV - High drive strength
ALT8 - FLEXIO1_FLEXIO31
ALT10 - GPIO7_IO31
GPIO_EMC_B1_32 ALT0 - SEMC_DATA10 ODE - Disabled
ALT1 - FLEXPWM3_PWMB1 PULL - PD
ALT5 - GPIO_MUX2_IO0 PDRV - High drive strength
ALT10 - GPIO8_IO0
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
GPIO_EMC_B1_33 ALT0 - SEMC_DATA11 ODE - Disabled
ALT1 - FLEXPWM3_PWMA2 PULL - PD
ALT5 - GPIO_MUX2_IO1 PDRV - High drive strength
ALT10 - GPIO8_IO1
GPIO_EMC_B1_34 ALT0 - SEMC_DATA12 ODE - Disabled
ALT1 - FLEXPWM3_PWMB2 PULL - PD
ALT5 - GPIO_MUX2_IO2 PDRV - High drive strength
ALT10 - GPIO8_IO2
GPIO_EMC_B1_35 ALT0 - SEMC_DATA13 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT9 PULL - PD
ALT5 - GPIO_MUX2_IO3 PDRV - High drive strength
ALT10 - GPIO8_IO3
GPIO_EMC_B1_36 ALT0 - SEMC_DATA14 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT10 PULL - PD
ALT5 - GPIO_MUX2_IO4 PDRV - High drive strength
ALT10 - GPIO8_IO4
GPIO_EMC_B1_37 ALT0 - SEMC_DATA15 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT11 PULL - PD
ALT5 - GPIO_MUX2_IO5 PDRV - High drive strength
ALT7 - SRC_SYSTEM_RESET
ALT10 - GPIO8_IO5
GPIO_EMC_B1_38 ALT0 - SEMC_DM1 ODE - Disabled
ALT1 - FLEXPWM1_PWMA3 PULL - PD
ALT2 - QTIMER1_TIMER1 PDRV - High drive strength
ALT5 - GPIO_MUX2_IO6
ALT7 - SRC_EARLY_RESET
ALT10 - GPIO8_IO6
GPIO_EMC_B1_39 ALT0 - SEMC_DQS ODE - Disabled
ALT1 - FLEXPWM1_PWMB3 PULL - PD
ALT2 - QTIMER2_TIMER1 PDRV - High drive strength
ALT5 - GPIO_MUX2_IO7
ALT7 - SRC_WAKEUPMIX_RESET
ALT10 - GPIO8_IO7
GPIO_EMC_B1_40 ALT0 - SEMC_RDY ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT12 PULL - PD
ALT2 - MQS_RIGHT PDRV - High drive strength
ALT3 - LPUART6_TX
ALT5 - GPIO_MUX2_IO8
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT7 - ENET_1G_MDC
ALT9 - CCM_CLKO1
ALT10 - GPIO8_IO8
GPIO_EMC_B1_41 ALT0 - SEMC_CSX0 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT13 PULL - PD
ALT2 - MQS_LEFT PDRV - High drive strength
ALT3 - LPUART6_RX
ALT4 - FLEXSPI2_B_DATA7
ALT5 - GPIO_MUX2_IO9
ALT7 - ENET_1G_MDIO
ALT9 - CCM_CLKO2
ALT10 - GPIO8_IO9
GPIO_EMC_B2_00 ALT0 - SEMC_DATA16 ODE - Disabled
ALT1 - CCM_ENET_REF_CLK_25M PULL - PD
ALT2 - QTIMER3_TIMER1 PDRV - High drive strength
ALT3 - LPUART6_CTS_B
ALT4 - FLEXSPI2_B_DATA6
ALT5 - GPIO_MUX2_IO10
ALT6 - XBAR1_XBAR_INOUT20
ALT7 - ENET_QOS_1588_EVENT1_OUT
ALT8 - LPSPI1_SCK
ALT9 - LPI2C2_SCL
ALT10 - GPIO8_IO10
ALT11 - FLEXPWM3_PWMA0
GPIO_EMC_B2_01 ALT0 - SEMC_DATA17 ODE - Disabled
ALT1 - USDHC2_CD_B PULL - PD
ALT2 - QTIMER4_TIMER1 PDRV - High drive strength
ALT3 - LPUART6_RTS_B
ALT4 - FLEXSPI2_B_DATA5
ALT5 - GPIO_MUX2_IO11
ALT6 - XBAR1_XBAR_INOUT21
ALT7 - ENET_QOS_1588_EVENT1_IN
ALT8 - LPSPI1_PCS0
ALT9 - LPI2C2_SDA
ALT10 - GPIO8_IO11
ALT11 - FLEXPWM3_PWMB0
GPIO_EMC_B2_02 ALT0 - SEMC_DATA18 ODE - Disabled
ALT1 - USDHC2_WP PULL - PD
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT3 - VIDEO_MUX_CSI_DATA23 PDRV - High drive strength
ALT4 - FLEXSPI2_B_DATA4
ALT5 - GPIO_MUX2_IO12
ALT6 - XBAR1_XBAR_INOUT22
ALT7 -
ENET_QOS_1588_EVENT1_AUX_IN
ALT8 - LPSPI1_SDO
ALT10 - GPIO8_IO12
ALT11 - FLEXPWM3_PWMA1
GPIO_EMC_B2_03 ALT0 - SEMC_DATA19 ODE - Disabled
ALT1 - USDHC2_VSELECT PULL - PD
ALT3 - VIDEO_MUX_CSI_DATA22 PDRV - High drive strength
ALT4 - FLEXSPI2_B_DATA3
ALT5 - GPIO_MUX2_IO13
ALT6 - XBAR1_XBAR_INOUT23
ALT7 - ENET_1G_TDATA3
ALT8 - LPSPI1_SDI
ALT10 - GPIO8_IO13
ALT11 - FLEXPWM3_PWMB1
GPIO_EMC_B2_04 ALT0 - SEMC_DATA20 ODE - Disabled
ALT1 - USDHC2_RESET_B PULL - PD
ALT2 - SAI2_MCLK PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA21
ALT4 - FLEXSPI2_B_DATA2
ALT5 - GPIO_MUX2_IO14
ALT6 - XBAR1_XBAR_INOUT24
ALT7 - ENET_1G_TDATA2
ALT8 - LPSPI3_SCK
ALT10 - GPIO8_IO14
ALT11 - FLEXPWM3_PWMA2
GPIO_EMC_B2_05 ALT0 - SEMC_DATA21 ODE - Disabled
ALT1 - GPT3_CLK PULL - PD
ALT2 - SAI2_RX_SYNC PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA20
ALT4 - FLEXSPI2_B_DATA1
ALT5 - GPIO_MUX2_IO15
ALT6 - XBAR1_XBAR_INOUT25
ALT7 - ENET_1G_RX_CLK
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - LPSPI3_PCS0
ALT9 - PIT1_TRIGGER0
ALT10 - GPIO8_IO15
ALT11 - FLEXPWM3_PWMB2
GPIO_EMC_B2_06 ALT0 - SEMC_DATA22 ODE - Disabled
ALT1 - GPT3_CAPTURE1 PULL - PD
ALT2 - SAI2_RX_BCLK PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA19
ALT4 - FLEXSPI2_B_DATA0
ALT5 - GPIO_MUX2_IO16
ALT6 - XBAR1_XBAR_INOUT26
ALT7 - ENET_1G_TX_ER
ALT8 - LPSPI3_SDO
ALT9 - PIT1_TRIGGER1
ALT10 - GPIO8_IO16
ALT11 - FLEXPWM3_PWMA3
GPIO_EMC_B2_07 ALT0 - SEMC_DATA23 ODE - Disabled
ALT1 - GPT3_CAPTURE2 PULL - PD
ALT2 - SAI2_RX_DATA PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA18
ALT4 - FLEXSPI2_B_DQS
ALT5 - GPIO_MUX2_IO17
ALT6 - XBAR1_XBAR_INOUT27
ALT7 - ENET_1G_RDATA3
ALT8 - LPSPI3_SDI
ALT9 - PIT1_TRIGGER2
ALT10 - GPIO8_IO17
ALT11 - FLEXPWM3_PWMB3
GPIO_EMC_B2_08 ALT0 - SEMC_DM2 ODE - Disabled
ALT1 - GPT3_COMPARE1 PULL - PU
ALT2 - SAI2_TX_DATA PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA17
ALT4 - FLEXSPI2_B_SS0_B
ALT5 - GPIO_MUX2_IO18
ALT6 - XBAR1_XBAR_INOUT28
ALT7 - ENET_1G_RDATA2
ALT8 - LPSPI3_PCS1
ALT9 - PIT1_TRIGGER3
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT10 - GPIO8_IO18
GPIO_EMC_B2_09 ALT0 - SEMC_DATA24 ODE - Disabled
ALT1 - GPT3_COMPARE2 PULL - PD
ALT2 - SAI2_TX_BCLK PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_DATA16
ALT4 - FLEXSPI2_B_SCLK
ALT5 - GPIO_MUX2_IO19
ALT6 - XBAR1_XBAR_INOUT29
ALT7 - ENET_1G_CRS
ALT8 - LPSPI3_PCS2
ALT9 - QTIMER1_TIMER0
ALT10 - GPIO8_IO19
GPIO_EMC_B2_10 ALT0 - SEMC_DATA25 ODE - Disabled
ALT1 - GPT3_COMPARE3 PULL - PD
ALT2 - SAI2_TX_SYNC PDRV - High drive strength
ALT3 - VIDEO_MUX_CSI_FIELD
ALT4 - FLEXSPI2_A_SCLK
ALT5 - GPIO_MUX2_IO20
ALT6 - XBAR1_XBAR_INOUT30
ALT7 - ENET_1G_COL
ALT8 - LPSPI3_PCS3
ALT9 - QTIMER1_TIMER1
ALT10 - GPIO8_IO20
GPIO_EMC_B2_11 ALT0 - SEMC_DATA26 ODE - Disabled
ALT1 - SPDIF_IN PULL - PU
ALT2 - ENET_1G_TDATA0 PDRV - High drive strength
ALT3 - SAI3_RX_SYNC
ALT4 - FLEXSPI2_A_SS0_B
ALT5 - GPIO_MUX2_IO21
ALT6 - XBAR1_XBAR_INOUT31
ALT8 - SIM1_TRXD
ALT9 - QTIMER1_TIMER2
ALT10 - GPIO8_IO21
GPIO_EMC_B2_12 ALT0 - SEMC_DATA27 ODE - Disabled
ALT1 - SPDIF_OUT PULL - PD
ALT2 - ENET_1G_TDATA1 PDRV - High drive strength
ALT3 - SAI3_RX_BCLK
ALT4 - FLEXSPI2_A_DQS
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT5 - GPIO_MUX2_IO22
ALT6 - XBAR1_XBAR_INOUT32
ALT8 - SIM1_CLK
ALT9 - QTIMER1_TIMER3
ALT10 - GPIO8_IO22
GPIO_EMC_B2_13 ALT0 - SEMC_DATA28 ODE - Disabled
ALT2 - ENET_1G_TX_EN PULL - PD
ALT3 - SAI3_RX_DATA PDRV - High drive strength
ALT4 - FLEXSPI2_A_DATA0
ALT5 - GPIO_MUX2_IO23
ALT6 - XBAR1_XBAR_INOUT33
ALT8 - SIM1_RST_B
ALT9 - QTIMER2_TIMER0
ALT10 - GPIO8_IO23
GPIO_EMC_B2_14 ALT0 - SEMC_DATA29 ODE - Disabled
ALT2 - ENET_1G_TX_CLK_IO PULL - PD
ALT3 - SAI3_TX_DATA PDRV - High drive strength
ALT4 - FLEXSPI2_A_DATA1
ALT5 - GPIO_MUX2_IO24
ALT6 - XBAR1_XBAR_INOUT34
ALT8 - SIM1_SVEN
ALT9 - QTIMER2_TIMER1
ALT10 - GPIO8_IO24
GPIO_EMC_B2_15 ALT0 - SEMC_DATA30 ODE - Disabled
ALT2 - ENET_1G_RDATA0 PULL - PD
ALT3 - SAI3_TX_BCLK PDRV - High drive strength
ALT4 - FLEXSPI2_A_DATA2
ALT5 - GPIO_MUX2_IO25
ALT6 - XBAR1_XBAR_INOUT35
ALT8 - SIM1_PD
ALT9 - QTIMER2_TIMER2
ALT10 - GPIO8_IO25
GPIO_EMC_B2_16 ALT0 - SEMC_DATA31 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT14 PULL - PD
ALT2 - ENET_1G_RDATA1 PDRV - High drive strength
ALT3 - SAI3_TX_SYNC
ALT4 - FLEXSPI2_A_DATA3
ALT5 - GPIO_MUX2_IO26
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - SIM1_POWER_FAIL
ALT9 - QTIMER2_TIMER3
ALT10 - GPIO8_IO26
GPIO_EMC_B2_17 ALT0 - SEMC_DM3 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT15 PULL - PD
ALT2 - ENET_1G_RX_EN PDRV - High drive strength
ALT3 - SAI3_MCLK
ALT4 - FLEXSPI2_A_DATA4
ALT5 - GPIO_MUX2_IO27
ALT8 - WDOG1_WDOG_ANY
ALT9 - QTIMER3_TIMER0
ALT10 - GPIO8_IO27
GPIO_EMC_B2_18 ALT0 - SEMC_DQS4 ODE - Disabled
ALT1 - XBAR1_XBAR_INOUT16 PULL - PD
ALT2 - ENET_1G_RX_ER PDRV - High drive strength
ALT3 - EWM_EWM_OUT_B
ALT4 - FLEXSPI2_A_DATA5
ALT5 - GPIO_MUX2_IO28
ALT6 - FLEXSPI1_A_DQS
ALT8 - WDOG1_WDOG_B
ALT9 - QTIMER3_TIMER1
ALT10 - GPIO8_IO28
GPIO_EMC_B2_19 ALT0 - SEMC_CLKX0 ODE - Disabled
ALT1 - ENET_MDC PULL - PD
ALT2 - ENET_1G_MDC PDRV - High drive strength
ALT3 - ENET_1G_REF_CLK1
ALT4 - FLEXSPI2_A_DATA6
ALT5 - GPIO_MUX2_IO29
ALT8 - ENET_QOS_MDC
ALT9 - QTIMER3_TIMER2
ALT10 - GPIO8_IO29
GPIO_EMC_B2_20 ALT0 - SEMC_CLKX1 ODE - Disabled
ALT1 - ENET_MDIO PULL - PD
ALT2 - ENET_1G_MDIO PDRV - High drive strength
ALT3 - ENET_QOS_REF_CLK1
ALT4 - FLEXSPI2_A_DATA7
ALT5 - GPIO_MUX2_IO30
ALT8 - ENET_QOS_MDIO
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT9 - QTIMER3_TIMER3
ALT10 - GPIO8_IO30
GPIO_AD_00 ALT0 - SIM1_TRXD ODE - Disabled
ALT1 - CAN2_TX PUS - Weak PU
ALT2 - ENET_1G_1588_EVENT1_IN PUE - Pull Enable
ALT3 - GPT2_CAPTURE1 DSE - High drive strength
ALT4 - FLEXPWM1_PWMA0 SRE - Fast slew rate
ALT5 - GPIO_MUX2_IO31
ALT6 - LPUART7_TX
ALT8 - FLEXIO2_FLEXIO0
ALT9 - FLEXSPI2_B_SS1_B
ALT10 - GPIO8_IO31
ANALOG IO - ACMP1_1
GPIO_AD_01 ALT0 - SIM1_CLK ODE - Disabled
ALT1 - CAN2_RX PUS - Weak PU
ALT2 - ENET_1G_1588_EVENT1_OUT PUE - Pull Enable
ALT3 - GPT2_CAPTURE2 DSE - High drive strength
ALT4 - FLEXPWM1_PWMB0 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO0
ALT6 - LPUART7_RX
ALT8 - FLEXIO2_FLEXIO1
ALT9 - FLEXSPI2_A_SS1_B
ALT10 - GPIO9_IO0
ANALOG IO - ACMP1_2
GPIO_AD_02 ALT0 - SIM1_RST_B ODE - Disabled
ALT1 - LPUART7_CTS_B PUS - Weak PD
ALT2 - ENET_1G_1588_EVENT2_IN PUE - Pull Enable
ALT3 - GPT2_COMPARE1 DSE - High drive strength
ALT4 - FLEXPWM1_PWMA1 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO1
ALT6 - LPUART8_TX
ALT8 - FLEXIO2_FLEXIO2
ALT9 - VIDEO_MUX_EXT_DCIC1
ALT10 - GPIO9_IO1
ANALOG IO - ACMP1_3
GPIO_AD_03 ALT0 - SIM1_SVEN ODE - Disabled
ALT1 - LPUART7_RTS_B PUS - Weak PD
ALT2 - ENET_1G_1588_EVENT2_OUT PUE - Pull Enable
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT3 - GPT2_COMPARE2 DSE - High drive strength
ALT4 - FLEXPWM1_PWMB1 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO2
ALT6 - LPUART8_RX
ALT8 - FLEXIO2_FLEXIO3
ALT9 - VIDEO_MUX_EXT_DCIC2
ALT10 - GPIO9_IO2
ANALOG IO - ACMP1_4
GPIO_AD_04 ALT0 - SIM1_PD ODE - Disabled
ALT1 - LPUART8_CTS_B PUS - Weak PD
ALT2 - ENET_1G_1588_EVENT3_IN PUE - Pull Enable
ALT3 - GPT2_COMPARE3 DSE - High drive strength
ALT4 - FLEXPWM1_PWMA2 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO3
ALT6 - WDOG1_WDOG_B
ALT8 - FLEXIO2_FLEXIO4
ALT9 - QTIMER4_TIMER0
ALT10 - GPIO9_IO3
ANALOG IO - ACMP2_1
GPIO_AD_05 ALT0 - SIM1_POWER_FAIL ODE - Disabled
ALT1 - LPUART8_RTS_B PUS - Weak PD
ALT2 - ENET_1G_1588_EVENT3_OUT PUE - Pull Enable
ALT3 - GPT2_CLK DSE - High drive strength
ALT4 - FLEXPWM1_PWMB2 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO4
ALT6 - WDOG2_WDOG_B
ALT8 - FLEXIO2_FLEXIO5
ALT9 - QTIMER4_TIMER1
ALT10 - GPIO9_IO4
ANALOG IO - ACMP2_2
GPIO_AD_06 ALT0 - USB_OTG2_OC ODE - Disabled
ALT1 - CAN1_TX PUS - Weak PD
ALT2 - SIM2_TRXD PUE - Pull Enable
ALT3 - GPT3_CAPTURE1 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA15 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO5
ALT6 - ENET_1588_EVENT1_IN
ALT8 - FLEXIO2_FLEXIO6
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT9 - QTIMER4_TIMER2
ALT10 - GPIO9_IO5
ALT11 - FLEXPWM1_PWMX0
ANALOG IO - ADC1_A0
GPIO_AD_07 ALT0 - USB_OTG2_PWR ODE - Disabled
ALT1 - CAN1_RX PUS - Weak PD
ALT2 - SIM2_CLK PUE - Pull Enable
ALT3 - GPT3_CAPTURE2 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA14 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO6
ALT6 - ENET_1588_EVENT1_OUT
ALT8 - FLEXIO2_FLEXIO7
ALT9 - QTIMER4_TIMER3
ALT10 - GPIO9_IO6
ALT11 - FLEXPWM1_PWMX1
ANALOG IO - ADC1_B0
GPIO_AD_08 ALT0 - USBPHY2_OTG_ID ODE - Disabled
ALT1 - LPI2C1_SCL PUS - Weak PD
ALT2 - SIM2_RST_B PUE - Pull Enable
ALT3 - GPT3_COMPARE1 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA13 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO7
ALT6 - ENET_1588_EVENT2_IN
ALT8 - FLEXIO2_FLEXIO8
ALT10 - GPIO9_IO7
ALT11 - FLEXPWM1_PWMX2
ANALOG IO - ADC1_A1
GPIO_AD_09 ALT0 - USBPHY1_OTG_ID ODE - Disabled
ALT1 - LPI2C1_SDA PUS - Weak PD
ALT2 - SIM2_SVEN PUE - Pull Enable
ALT3 - GPT3_COMPARE2 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA12 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO8
ALT6 - ENET_1588_EVENT2_OUT
ALT8 - FLEXIO2_FLEXIO9
ALT10 - GPIO9_IO8
ALT11 - FLEXPWM1_PWMX3
ANALOG IO - ADC1_B1
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
GPIO_AD_10 ALT0 - USB_OTG1_PWR ODE - Disabled
ALT1 - LPI2C1_SCLS PUS - Weak PD
ALT2 - SIM2_PD PUE - Pull Enable
ALT3 - GPT3_COMPARE3 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA11 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO9
ALT6 - ENET_1588_EVENT3_IN
ALT8 - FLEXIO2_FLEXIO10
ALT10 - GPIO9_IO9
ALT11 - FLEXPWM2_PWMX0
ANALOG IO - ADC1_A2
GPIO_AD_11 ALT0 - USB_OTG1_OC ODE - Disabled
ALT1 - LPI2C1_SDAS PUS - Weak PD
ALT2 - SIM2_POWER_FAIL PUE - Pull Enable
ALT3 - GPT3_CLK DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA10 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO10
ALT6 - ENET_1588_EVENT3_OUT
ALT8 - FLEXIO2_FLEXIO11
ALT10 - GPIO9_IO10
ALT11 - FLEXPWM2_PWMX1
ANALOG IO - ADC1_B2
GPIO_AD_12 ALT0 - SPDIF_LOCK ODE - Disabled
ALT1 - LPI2C1_HREQ PUS - Weak PD
ALT2 - GPT1_CAPTURE1 PUE - Pull Enable
ALT3 - FLEXSPI1_B_DATA3 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_PIXCLK SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO11
ALT6 - ENET_TDATA3
ALT8 - FLEXIO2_FLEXIO12
ALT9 - EWM_EWM_OUT_B
ALT10 - GPIO9_IO11
ALT11 - FLEXPWM2_PWMX2
ANALOG IO - ADC12_A3
GPIO_AD_13 ALT0 - SPDIF_SR_CLK ODE - Disabled
ALT1 - PIT1_TRIGGER0 PUS - Weak PD
ALT2 - GPT1_CAPTURE2 PUE - Pull Enable
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT3 - FLEXSPI1_B_DATA2 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_MCLK SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO12
ALT6 - ENET_TDATA2
ALT8 - FLEXIO2_FLEXIO13
ALT9 - ANATOP_32K_OUT
ALT10 - GPIO9_IO12
ALT11 - FLEXPWM2_PWMX3
ANALOG IO - ADC12_B3
GPIO_AD_14 ALT0 - SPDIF_EXT_CLK ODE - Disabled
ALT1 - ANATOP_24M_OUT PUS - Weak PD
ALT2 - GPT1_COMPARE1 PUE - Pull Enable
ALT3 - FLEXSPI1_B_DATA1 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_VSYNC SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO13
ALT6 - ENET_RX_CLK
ALT8 - FLEXIO2_FLEXIO14
ALT9 - CCM_ENET_REF_CLK_25M
ALT10 - GPIO9_IO13
ALT11 - FLEXPWM3_PWMX0
ANALOG IO - ADC12_A4
GPIO_AD_15 ALT0 - SPDIF_IN ODE - Disabled
ALT1 - LPUART10_TX PUS - Weak PD
ALT2 - GPT1_COMPARE2 PUE - Pull Enable
ALT3 - FLEXSPI1_B_DATA0 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_HSYNC SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO14
ALT6 - ENET_TX_ER
ALT8 - FLEXIO2_FLEXIO15
ALT10 - GPIO9_IO14
ALT11 - FLEXPWM3_PWMX1
ANALOG IO - ADC12_B4
GPIO_AD_16 ALT0 - SPDIF_OUT ODE - Disabled
ALT1 - LPUART10_RX PUS - Weak PD
ALT2 - GPT1_COMPARE3 PUE - Pull Enable
ALT3 - FLEXSPI1_B_SCLK DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA9 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO15
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT6 - ENET_RDATA3
ALT8 - FLEXIO2_FLEXIO16
ALT9 - ENET_1G_MDC
ALT10 - GPIO9_IO15
ALT11 - FLEXPWM3_PWMX2
ANALOG IO - ADC12_A5
GPIO_AD_17 ALT0 - SAI1_MCLK ODE - Disabled
ALT1 - ACMP1_CMPO PUS - Weak PD
ALT2 - GPT1_CLK PUE - Pull Enable
ALT3 - FLEXSPI1_A_DQS DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA8 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO16
ALT6 - ENET_RDATA2
ALT8 - FLEXIO2_FLEXIO17
ALT9 - ENET_1G_MDIO
ALT10 - GPIO9_IO16
ALT11 - FLEXPWM3_PWMX3
ANALOG IO - ADC12_B5
GPIO_AD_18 ALT0 - SAI1_RX_SYNC ODE - Disabled
ALT1 - ACMP2_CMPO PUS - Weak PU
ALT2 - LPSPI1_PCS1 PUE - Pull Enable
ALT3 - FLEXSPI1_A_SS0_B DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA7 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO17
ALT6 - ENET_CRS
ALT8 - FLEXIO2_FLEXIO18
ALT9 - LPI2C2_SCL
ALT10 - GPIO9_IO17
ALT11 - FLEXPWM4_PWMX0
ANALOG IO - ADC2_A0
GPIO_AD_19 ALT0 - SAI1_RX_BCLK ODE - Disabled
ALT1 - ACMP3_CMPO PUS - Weak PD
ALT2 - LPSPI1_PCS2 PUE - Pull Enable
ALT3 - FLEXSPI1_A_SCLK DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA6 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO18
ALT6 - ENET_COL
ALT8 - FLEXIO2_FLEXIO19
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT9 - LPI2C2_SDA
ALT10 - GPIO9_IO18
ALT11 - FLEXPWM4_PWMX1
ANALOG IO - ADC2_B0
GPIO_AD_20 ALT0 - SAI1_RX_DATA0 ODE - Disabled
ALT1 - ACMP4_CMPO PUS - Weak PD
ALT2 - LPSPI1_PCS3 PUE - Pull Enable
ALT3 - FLEXSPI1_A_DATA0 DSE - High drive strength
ALT4 - VIDEO_MUX_CSI_DATA5 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO19
ALT6 - KPP_ROW7
ALT8 - FLEXIO2_FLEXIO20
ALT9 - ENET_QOS_1588_EVENT2_OUT
ALT10 - GPIO9_IO19
ALT11 - FLEXPWM4_PWMX2
ANALOG IO - ADC2_A1
GPIO_AD_21 ALT0 - SAI1_TX_DATA0 ODE - Disabled
ALT2 - LPSPI2_PCS1 PUS - Weak PD
ALT3 - FLEXSPI1_A_DATA1 PUE - Pull Enable
ALT4 - VIDEO_MUX_CSI_DATA4 DSE - High drive strength
ALT5 - GPIO_MUX3_IO20 SRE - Fast slew rate
ALT6 - KPP_COL7
ALT8 - FLEXIO2_FLEXIO21
ALT9 - ENET_QOS_1588_EVENT2_IN
ALT10 - GPIO9_IO20
ALT11 - FLEXPWM4_PWMX3
ANALOG IO - ADC2_B1
GPIO_AD_22 ALT0 - SAI1_TX_BCLK ODE - Disabled
ALT2 - LPSPI2_PCS2 PUS - Weak PD
ALT3 - FLEXSPI1_A_DATA2 PUE - Pull Enable
ALT4 - VIDEO_MUX_CSI_DATA3 DSE - High drive strength
ALT5 - GPIO_MUX3_IO21 SRE - Fast slew rate
ALT6 - KPP_ROW6
ALT8 - FLEXIO2_FLEXIO22
ALT9 - ENET_QOS_1588_EVENT3_OUT
ALT10 - GPIO9_IO21
ANALOG IO - ADC2_A2
GPIO_AD_23 ALT0 - SAI1_TX_SYNC ODE - Disabled
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT2 - LPSPI2_PCS3 PUS - Weak PD
ALT3 - FLEXSPI1_A_DATA3 PUE - Pull Enable
ALT4 - VIDEO_MUX_CSI_DATA2 DSE - High drive strength
ALT5 - GPIO_MUX3_IO22 SRE - Fast slew rate
ALT6 - KPP_COL6
ALT8 - FLEXIO2_FLEXIO23
ALT9 - ENET_QOS_1588_EVENT3_IN
ALT10 - GPIO9_IO22
ANALOG IO - ADC2_B2
GPIO_AD_24 ALT0 - LPUART1_TX ODE - Disabled
ALT1 - LPSPI2_SCK PUS - Weak PD
ALT2 - VIDEO_MUX_CSI_DATA0 PUE - Pull Enable
ALT3 - ENET_RX_EN DSE - High drive strength
ALT4 - FLEXPWM2_PWMA0 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO23
ALT6 - KPP_ROW5
ALT8 - FLEXIO2_FLEXIO24
ALT9 - LPI2C4_SCL
ALT10 - GPIO9_IO23
ANALOG IO - ADC2_A6
GPIO_AD_25 ALT0 - LPUART1_RX ODE - Disabled
ALT1 - LPSPI2_PCS0 PUS - Weak PD
ALT2 - VIDEO_MUX_CSI_DATA1 PUE - Pull Enable
ALT3 - ENET_RX_ER DSE - High drive strength
ALT4 - FLEXPWM2_PWMB0 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO24
ALT6 - KPP_COL5
ALT8 - FLEXIO2_FLEXIO25
ALT9 - LPI2C4_SDA
ALT10 - GPIO9_IO24
ANALOG IO - ADC2_B6
GPIO_AD_26 ALT0 - LPUART1_CTS_B ODE - Disabled
ALT1 - LPSPI2_SDO PUS - Weak PU
ALT2 - SEMC_CSX1 PUE - Pull Enable
ALT3 - ENET_RDATA0 DSE - High drive strength
ALT4 - FLEXPWM2_PWMA1 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO25
ALT6 - KPP_ROW4
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - FLEXIO2_FLEXIO26
ALT9 - ENET_QOS_MDC
ALT10 - GPIO9_IO25
ALT11 - USDHC2_CD_B
ANALOG IO - ACMP2_3
GPIO_AD_27 ALT0 - LPUART1_RTS_B ODE - Disabled
ALT1 - LPSPI2_SDI PUS - Weak PU
ALT2 - SEMC_CSX2 PUE - Pull Enable
ALT3 - ENET_RDATA1 DSE - High drive strength
ALT4 - FLEXPWM2_PWMB1 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO26
ALT6 - KPP_COL4
ALT8 - FLEXIO2_FLEXIO27
ALT9 - ENET_QOS_MDIO
ALT10 - GPIO9_IO26
ALT11 - USDHC2_WP
ANALOG IO - ACMP2_4
GPIO_AD_28 ALT0 - LPSPI1_SCK ODE - Disabled
ALT1 - LPUART5_TX PUS - Weak PD
ALT2 - SEMC_CSX3 PUE - Pull Enable
ALT3 - ENET_TX_EN DSE - High drive strength
ALT4 - FLEXPWM2_PWMA2 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO27
ALT6 - KPP_ROW3
ALT8 - FLEXIO2_FLEXIO28
ALT9 - VIDEO_MUX_EXT_DCIC1
ALT10 - GPIO9_IO27
ALT11 - USDHC2_VSELECT
ANALOG IO - ACMP3_1
GPIO_AD_29 ALT0 - LPSPI1_PCS0 ODE - Disabled
ALT1 - LPUART5_RX PUS - Weak PD
ALT2 - ENET_REF_CLK1 PUE - Pull Enable
ALT3 - ENET_TX_CLK DSE - High drive strength
ALT4 - FLEXPWM2_PWMB2 SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO28
ALT6 - KPP_COL3
ALT8 - FLEXIO2_FLEXIO29
ALT9 - VIDEO_MUX_EXT_DCIC2
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT10 - GPIO9_IO28
ALT11 - USDHC2_RESET_B
ANALOG IO - ACMP3_2
GPIO_AD_30 ALT0 - LPSPI1_SDO ODE - Disabled
ALT1 - USB_OTG2_OC PUS - Weak PD
ALT2 - CAN2_TX PUE - Pull Enable
ALT3 - ENET_TDATA0 DSE - High drive strength
ALT4 - LPUART3_TX SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO29
ALT6 - KPP_ROW2
ALT8 - FLEXIO2_FLEXIO30
ALT9 - WDOG2_WDOG_RESET_B_DEB
ALT10 - GPIO9_IO29
ANALOG IO - ACMP3_3
GPIO_AD_31 ALT0 - LPSPI1_SDI ODE - Disabled
ALT1 - USB_OTG2_PWR PUS - Weak PD
ALT2 - CAN2_RX PUE - Pull Enable
ALT3 - ENET_TDATA1 DSE - High drive strength
ALT4 - LPUART3_RX SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO30
ALT6 - KPP_COL2
ALT8 - FLEXIO2_FLEXIO31
ALT9 - WDOG1_WDOG_RESET_B_DEB
ALT10 - GPIO9_IO30
ANALOG IO - ACMP3_4
GPIO_AD_32 ALT0 - LPI2C1_SCL ODE - Disabled
ALT1 - USBPHY2_OTG_ID PUS - Weak PD
ALT2 - CCM_PMIC_RDY PUE - Pull Enable
ALT3 - ENET_MDC DSE - High drive strength
ALT4 - USDHC1_CD_B SRE - Fast slew rate
ALT5 - GPIO_MUX3_IO31
ALT6 - KPP_ROW1
ALT8 - LPUART10_TX
ALT9 - ENET_1G_MDC
ALT10 - GPIO9_IO31
ANALOG IO - ACMP4_1
GPIO_AD_33 ALT0 - LPI2C1_SDA ODE - Disabled
ALT1 - USBPHY1_OTG_ID PUS - Weak PD
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT2 - XBAR1_XBAR_INOUT17 PUE - Pull Enable
ALT3 - ENET_MDIO DSE - High drive strength
ALT4 - USDHC1_WP SRE - Fast slew rate
ALT5 - GPIO4_IO0
ALT6 - KPP_COL1
ALT8 - LPUART10_RX
ALT9 - ENET_1G_MDIO
ALT10 - GPIO10_IO0
ANALOG IO - ACMP4_2
GPIO_AD_34 ALT0 - ENET_1G_1588_EVENT0_IN ODE - Disabled
ALT1 - USB_OTG1_PWR PUS - Weak PD
ALT2 - XBAR1_XBAR_INOUT18 PUE - Pull Enable
ALT3 - ENET_1588_EVENT0_IN DSE - High drive strength
ALT4 - USDHC1_VSELECT SRE - Fast slew rate
ALT5 - GPIO4_IO1
ALT6 - KPP_ROW0
ALT8 - LPUART10_CTS_B
ALT9 - WDOG1_WDOG_ANY
ALT10 - GPIO10_IO1
ANALOG IO - ACMP4_3
GPIO_AD_35 ALT0 - ENET_1G_1588_EVENT0_OUT ODE - Disabled
ALT1 - USB_OTG1_OC PUS - Weak PU
ALT2 - XBAR1_XBAR_INOUT19 PUE - Pull Enable
ALT3 - ENET_1588_EVENT0_OUT DSE - High drive strength
ALT4 - USDHC1_RESET_B SRE - Fast slew rate
ALT5 - GPIO4_IO2
ALT6 - KPP_COL0
ALT8 - LPUART10_RTS_B
ALT9 - FLEXSPI1_B_SS1_B
ALT10 - GPIO10_IO2
ANALOG IO - ACMP4_4
GPIO_SD_B1_00 ALT0 - USDHC1_CMD ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT20 PULL - PU
ALT3 - GPT4_CAPTURE1 PDRV - High drive strength
ALT5 - GPIO4_IO3
ALT6 - FLEXSPI2_A_SS0_B
ALT8 - KPP_ROW7
ALT10 - GPIO10_IO3
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
GPIO_SD_B1_01 ALT0 - USDHC1_CLK ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT21 PULL - PD
ALT3 - GPT4_CAPTURE2 PDRV - High drive strength
ALT5 - GPIO4_IO4
ALT6 - FLEXSPI2_A_SCLK
ALT8 - KPP_COL7
ALT10 - GPIO10_IO4
GPIO_SD_B1_02 ALT0 - USDHC1_DATA0 ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT22 PULL - PU
ALT3 - GPT4_COMPARE1 PDRV - High drive strength
ALT5 - GPIO4_IO5
ALT6 - FLEXSPI2_A_DATA0
ALT8 - KPP_ROW6
ALT9 - FLEXSPI1_A_SS1_B
ALT10 - GPIO10_IO5
GPIO_SD_B1_03 ALT0 - USDHC1_DATA1 ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT23 PULL - PU
ALT3 - GPT4_COMPARE2 PDRV - High drive strength
ALT5 - GPIO4_IO6
ALT6 - FLEXSPI2_A_DATA1
ALT8 - KPP_COL6
ALT9 - FLEXSPI1_B_SS1_B
ALT10 - GPIO10_IO6
GPIO_SD_B1_04 ALT0 - USDHC1_DATA2 ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT24 PULL - PU
ALT3 - GPT4_COMPARE3 PDRV - High drive strength
ALT5 - GPIO4_IO7
ALT6 - FLEXSPI2_A_DATA2
ALT8 - FLEXSPI1_B_SS0_B
ALT9 -
ENET_QOS_1588_EVENT2_AUX_IN
ALT10 - GPIO10_IO7
GPIO_SD_B1_05 ALT0 - USDHC1_DATA3 ODE - Disabled
ALT2 - XBAR1_XBAR_INOUT25 PULL - PD
ALT3 - GPT4_CLK PDRV - High drive strength
ALT5 - GPIO4_IO8
ALT6 - FLEXSPI2_A_DATA3
ALT8 - FLEXSPI1_B_DQS
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT9 -
ENET_QOS_1588_EVENT3_AUX_IN
ALT10 - GPIO10_IO8
GPIO_SD_B2_00 ALT0 - USDHC2_DATA3 ODE - Disabled
ALT1 - FLEXSPI1_B_DATA3 PULL - PD
ALT2 - ENET_1G_RX_EN PDRV - High drive strength
ALT3 - LPUART9_TX
ALT4 - LPSPI4_SCK
ALT5 - GPIO4_IO9
ALT10 - GPIO10_IO9
GPIO_SD_B2_01 ALT0 - USDHC2_DATA2 ODE - Disabled
ALT1 - FLEXSPI1_B_DATA2 PULL - PD
ALT2 - ENET_1G_RX_CLK PDRV - High drive strength
ALT3 - LPUART9_RX
ALT4 - LPSPI4_PCS0
ALT5 - GPIO4_IO10
ALT10 - GPIO10_IO10
GPIO_SD_B2_02 ALT0 - USDHC2_DATA1 ODE - Disabled
ALT1 - FLEXSPI1_B_DATA1 PULL - PD
ALT2 - ENET_1G_RDATA0 PDRV - High drive strength
ALT3 - LPUART9_CTS_B
ALT4 - LPSPI4_SDO
ALT5 - GPIO4_IO11
ALT10 - GPIO10_IO11
GPIO_SD_B2_03 ALT0 - USDHC2_DATA0 ODE - Disabled
ALT1 - FLEXSPI1_B_DATA0 PULL - PD
ALT2 - ENET_1G_RDATA1 PDRV - High drive strength
ALT3 - LPUART9_RTS_B
ALT4 - LPSPI4_SDI
ALT5 - GPIO4_IO12
ALT10 - GPIO10_IO12
GPIO_SD_B2_04 ALT0 - USDHC2_CLK ODE - Disabled
ALT1 - FLEXSPI1_B_SCLK PULL - PU
ALT2 - ENET_1G_RDATA2 PDRV - High drive strength
ALT3 - FLEXSPI1_A_SS1_B
ALT4 - LPSPI4_PCS1
ALT5 - GPIO4_IO13
ALT10 - GPIO10_IO13
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
GPIO_SD_B2_05 ALT0 - USDHC2_CMD ODE - Disabled
ALT1 - FLEXSPI1_A_DQS PULL - PU
ALT2 - ENET_1G_RDATA3 PDRV - High drive strength
ALT3 - FLEXSPI1_B_SS0_B
ALT4 - LPSPI4_PCS2
ALT5 - GPIO4_IO14
ALT10 - GPIO10_IO14
GPIO_SD_B2_06 ALT0 - USDHC2_RESET_B ODE - Disabled
ALT1 - FLEXSPI1_A_SS0_B PULL - PU
ALT2 - ENET_1G_TDATA3 PDRV - High drive strength
ALT3 - LPSPI4_PCS3
ALT4 - GPT6_CAPTURE1
ALT5 - GPIO4_IO15
ALT10 - GPIO10_IO15
GPIO_SD_B2_07 ALT0 - USDHC2_STROBE ODE - Disabled
ALT1 - FLEXSPI1_A_SCLK PULL - PD
ALT2 - ENET_1G_TDATA2 PDRV - High drive strength
ALT3 - LPUART3_CTS_B
ALT4 - GPT6_CAPTURE2
ALT5 - GPIO4_IO16
ALT6 - LPSPI2_SCK
ALT8 - ENET_TX_ER
ALT9 - ENET_QOS_REF_CLK1
ALT10 - GPIO10_IO16
GPIO_SD_B2_08 ALT0 - USDHC2_DATA4 ODE - Disabled
ALT1 - FLEXSPI1_A_DATA0 PULL - PD
ALT2 - ENET_1G_TDATA1 PDRV - High drive strength
ALT3 - LPUART3_RTS_B
ALT4 - GPT6_COMPARE1
ALT5 - GPIO4_IO17
ALT6 - LPSPI2_PCS0
ALT10 - GPIO10_IO17
GPIO_SD_B2_09 ALT0 - USDHC2_DATA5 ODE - Disabled
ALT1 - FLEXSPI1_A_DATA1 PULL - PD
ALT2 - ENET_1G_TDATA0 PDRV - High drive strength
ALT3 - LPUART5_CTS_B
ALT4 - GPT6_COMPARE2
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT5 - GPIO4_IO18
ALT6 - LPSPI2_SDO
ALT10 - GPIO10_IO18
GPIO_SD_B2_10 ALT0 - USDHC2_DATA6 ODE - Disabled
ALT1 - FLEXSPI1_A_DATA2 PULL - PD
ALT2 - ENET_1G_TX_EN PDRV - High drive strength
ALT3 - LPUART5_RTS_B
ALT4 - GPT6_COMPARE3
ALT5 - GPIO4_IO19
ALT6 - LPSPI2_SDI
ALT10 - GPIO10_IO19
GPIO_SD_B2_11 ALT0 - USDHC2_DATA7 ODE - Disabled
ALT1 - FLEXSPI1_A_DATA3 PULL - PD
ALT2 - ENET_1G_TX_CLK_IO PDRV - High drive strength
ALT3 - ENET_1G_REF_CLK1
ALT4 - GPT6_CLK
ALT5 - GPIO4_IO20
ALT6 - LPSPI2_PCS1
ALT10 - GPIO10_IO20
GPIO_DISP_B1_00 ALT0 - VIDEO_MUX_LCDIF_CLK ODE - Disabled
ALT1 - ENET_1G_RX_EN PULL - PD
ALT3 - QTIMER1_TIMER0 PDRV - High drive strength
ALT4 - XBAR1_XBAR_INOUT26
ALT5 - GPIO4_IO21
ALT6 - SDIO_SLV_CMD
ALT8 - ENET_QOS_RX_EN
ALT10 - GPIO10_IO21
GPIO_DISP_B1_01 ALT0 - VIDEO_MUX_LCDIF_ENABLE ODE - Disabled
ALT1 - ENET_1G_RX_CLK PULL - PD
ALT2 - ENET_1G_RX_ER PDRV - High drive strength
ALT3 - QTIMER1_TIMER1
ALT4 - XBAR1_XBAR_INOUT27
ALT5 - GPIO4_IO22
ALT6 - SDIO_SLV_CLK
ALT8 - ENET_QOS_RX_CLK
ALT9 - ENET_QOS_RX_ER
ALT10 - GPIO10_IO22
GPIO_DISP_B1_02 ALT0 - VIDEO_MUX_LCDIF_HSYNC ODE - Disabled
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT1 - ENET_1G_RDATA0 PULL - PD
ALT2 - LPI2C3_SCL PDRV - High drive strength
ALT3 - QTIMER1_TIMER2
ALT4 - XBAR1_XBAR_INOUT28
ALT5 - GPIO4_IO23
ALT6 - SDIO_SLV_DATA0
ALT8 - ENET_QOS_RDATA0
ALT9 - LPUART1_TX
ALT10 - GPIO10_IO23
GPIO_DISP_B1_03 ALT0 - VIDEO_MUX_LCDIF_VSYNC ODE - Disabled
ALT1 - ENET_1G_RDATA1 PULL - PD
ALT2 - LPI2C3_SDA PDRV - High drive strength
ALT3 - QTIMER2_TIMER0
ALT4 - XBAR1_XBAR_INOUT29
ALT5 - GPIO4_IO24
ALT6 - SDIO_SLV_DATA1
ALT8 - ENET_QOS_RDATA1
ALT9 - LPUART1_RX
ALT10 - GPIO10_IO24
GPIO_DISP_B1_04 ALT0 - VIDEO_MUX_LCDIF_DATA0 ODE - Disabled
ALT1 - ENET_1G_RDATA2 PULL - PD
ALT2 - LPUART4_RX PDRV - High drive strength
ALT3 - QTIMER2_TIMER1
ALT4 - XBAR1_XBAR_INOUT30
ALT5 - GPIO4_IO25
ALT6 - SDIO_SLV_DATA2
ALT8 - ENET_QOS_RDATA2
ALT9 - LPSPI3_SCK
ALT10 - GPIO10_IO25
GPIO_DISP_B1_05 ALT0 - VIDEO_MUX_LCDIF_DATA1 ODE - Disabled
ALT1 - ENET_1G_RDATA3 PULL - PD
ALT2 - LPUART4_CTS_B PDRV - High drive strength
ALT3 - QTIMER2_TIMER2
ALT4 - XBAR1_XBAR_INOUT31
ALT5 - GPIO4_IO26
ALT6 - SDIO_SLV_DATA3
ALT8 - ENET_QOS_RDATA3
ALT9 - LPSPI3_SDI
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT10 - GPIO10_IO26
GPIO_DISP_B1_06 ALT0 - VIDEO_MUX_LCDIF_DATA2 ODE - Disabled
ALT1 - ENET_1G_TDATA3 PULL - No pull
ALT2 - LPUART4_TX PDRV - High drive strength
ALT3 - QTIMER3_TIMER0
ALT4 - XBAR1_XBAR_INOUT32
ALT5 - GPIO4_IO27
ALT6 - SRC_BT_CFG0
ALT8 - ENET_QOS_TDATA3
ALT9 - LPSPI3_SDO
ALT10 - GPIO10_IO27
GPIO_DISP_B1_07 ALT0 - VIDEO_MUX_LCDIF_DATA3 ODE - Disabled
ALT1 - ENET_1G_TDATA2 PULL - No pull
ALT2 - LPUART4_RTS_B PDRV - High drive strength
ALT3 - QTIMER3_TIMER1
ALT4 - XBAR1_XBAR_INOUT33
ALT5 - GPIO4_IO28
ALT6 - SRC_BT_CFG1
ALT8 - ENET_QOS_TDATA2
ALT9 - LPSPI3_PCS0
ALT10 - GPIO10_IO28
GPIO_DISP_B1_08 ALT0 - VIDEO_MUX_LCDIF_DATA4 ODE - Disabled
ALT1 - ENET_1G_TDATA1 PULL - No pull
ALT2 - USDHC1_CD_B PDRV - High drive strength
ALT3 - QTIMER3_TIMER2
ALT4 - XBAR1_XBAR_INOUT34
ALT5 - GPIO4_IO29
ALT6 - SRC_BT_CFG2
ALT8 - ENET_QOS_TDATA1
ALT9 - LPSPI3_PCS1
ALT10 - GPIO10_IO29
GPIO_DISP_B1_09 ALT0 - VIDEO_MUX_LCDIF_DATA5 ODE - Disabled
ALT1 - ENET_1G_TDATA0 PULL - No pull
ALT2 - USDHC1_WP PDRV - High drive strength
ALT3 - QTIMER4_TIMER0
ALT4 - XBAR1_XBAR_INOUT35
ALT5 - GPIO4_IO30
ALT6 - SRC_BT_CFG3
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - ENET_QOS_TDATA0
ALT9 - LPSPI3_PCS2
ALT10 - GPIO10_IO30
GPIO_DISP_B1_10 ALT0 - VIDEO_MUX_LCDIF_DATA6 ODE - Disabled
ALT1 - ENET_1G_TX_EN PULL - No pull
ALT2 - USDHC1_RESET_B PDRV - High drive strength
ALT3 - QTIMER4_TIMER1
ALT4 - XBAR1_XBAR_INOUT36
ALT5 - GPIO4_IO31
ALT6 - SRC_BT_CFG4
ALT8 - ENET_QOS_TX_EN
ALT9 - LPSPI3_PCS3
ALT10 - GPIO10_IO31
GPIO_DISP_B1_11 ALT0 - VIDEO_MUX_LCDIF_DATA7 ODE - Disabled
ALT1 - ENET_1G_TX_CLK_IO PULL - No pull
ALT2 - ENET_1G_REF_CLK1 PDRV - High drive strength
ALT3 - QTIMER4_TIMER2
ALT4 - XBAR1_XBAR_INOUT37
ALT5 - GPIO5_IO0
ALT6 - SRC_BT_CFG5
ALT8 - ENET_QOS_TX_CLK
ALT9 - ENET_QOS_REF_CLK1
ALT10 - GPIO11_IO0
GPIO_DISP_B2_00 ALT0 - VIDEO_MUX_LCDIF_DATA8 ODE - Disabled
ALT1 - WDOG1_WDOG_B PUS - Weak PD
ALT2 - MQS_RIGHT PUE - Pull Disable, Highz
ALT3 - ENET_1G_TX_ER DSE - High drive strength
ALT4 - SAI1_TX_DATA3 SRE - Fast slew rate
ALT5 - GPIO5_IO1
ALT6 - SRC_BT_CFG6
ALT8 - ENET_QOS_TX_ER
ALT10 - GPIO11_IO1
GPIO_DISP_B2_01 ALT0 - VIDEO_MUX_LCDIF_DATA9 ODE - Disabled
ALT1 - USDHC1_VSELECT PUS - Weak PD
ALT2 - MQS_LEFT PUE - Pull Disable, Highz
ALT3 - WDOG2_WDOG_B DSE - High drive strength
ALT4 - SAI1_TX_DATA2 SRE - Fast slew rate
ALT5 - GPIO5_IO2
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT6 - SRC_BT_CFG7
ALT8 - EWM_EWM_OUT_B
ALT9 - CCM_ENET_REF_CLK_25M
ALT10 - GPIO11_IO2
GPIO_DISP_B2_02 ALT0 - VIDEO_MUX_LCDIF_DATA10 ODE - Disabled
ALT1 - ENET_TDATA0 PUS - Weak PD
ALT2 - PIT1_TRIGGER3 PUE - Pull Disable, Highz
ALT3 - ARM_TRACE0 DSE - High drive strength
ALT4 - SAI1_TX_DATA1 SRE - Fast slew rate
ALT5 - GPIO5_IO3
ALT6 - SRC_BT_CFG8
ALT8 - ENET_QOS_TDATA0
ALT10 - GPIO11_IO3
GPIO_DISP_B2_03 ALT0 - VIDEO_MUX_LCDIF_DATA11 ODE - Disabled
ALT1 - ENET_TDATA1 PUS - Weak PD
ALT2 - PIT1_TRIGGER2 PUE - Pull Disable, Highz
ALT3 - ARM_TRACE1 DSE - High drive strength
ALT4 - SAI1_MCLK SRE - Fast slew rate
ALT5 - GPIO5_IO4
ALT6 - SRC_BT_CFG9
ALT8 - ENET_QOS_TDATA1
ALT10 - GPIO11_IO4
GPIO_DISP_B2_04 ALT0 - VIDEO_MUX_LCDIF_DATA12 ODE - Disabled
ALT1 - ENET_TX_EN PUS - Weak PD
ALT2 - PIT1_TRIGGER1 PUE - Pull Disable, Highz
ALT3 - ARM_TRACE2 DSE - High drive strength
ALT4 - SAI1_RX_SYNC SRE - Fast slew rate
ALT5 - GPIO5_IO5
ALT6 - SRC_BT_CFG10
ALT8 - ENET_QOS_TX_EN
ALT10 - GPIO11_IO5
GPIO_DISP_B2_05 ALT0 - VIDEO_MUX_LCDIF_DATA13 ODE - Disabled
ALT1 - ENET_TX_CLK PUS - Weak PD
ALT2 - ENET_REF_CLK1 PUE - Pull Disable, Highz
ALT3 - ARM_TRACE3 DSE - High drive strength
ALT4 - SAI1_RX_BCLK SRE - Fast slew rate
ALT5 - GPIO5_IO6
ALT6 - SRC_BT_CFG11
Table continues on the next page...
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Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT8 - ENET_QOS_TX_CLK
ALT10 - GPIO11_IO6
GPIO_DISP_B2_06 ALT0 - VIDEO_MUX_LCDIF_DATA14 ODE - Disabled
ALT1 - ENET_RDATA0 PUS - Weak PD
ALT2 - LPUART7_TX PUE - Pull Enable
ALT3 - ARM_TRACE_CLK DSE - High drive strength
ALT4 - SAI1_RX_DATA0 SRE - Fast slew rate
ALT5 - GPIO5_IO7
ALT8 - ENET_QOS_RDATA0
ALT10 - GPIO11_IO7
GPIO_DISP_B2_07 ALT0 - VIDEO_MUX_LCDIF_DATA15 ODE - Disabled
ALT1 - ENET_RDATA1 PUS - Weak PD
ALT2 - LPUART7_RX PUE - Pull Enable
ALT3 - ARM_TRACE_SWO DSE - High drive strength
ALT4 - SAI1_TX_DATA0 SRE - Fast slew rate
ALT5 - GPIO5_IO8
ALT8 - ENET_QOS_RDATA1
ALT10 - GPIO11_IO8
GPIO_DISP_B2_08 ALT0 - VIDEO_MUX_LCDIF_DATA16 ODE - Disabled
ALT1 - ENET_RX_EN PUS - Weak PD
ALT2 - LPUART8_TX PUE - Pull Enable
ALT3 - CM7_EVENTO DSE - High drive strength
ALT4 - SAI1_TX_BCLK SRE - Fast slew rate
ALT5 - GPIO5_IO9
ALT8 - ENET_QOS_RX_EN
ALT9 - LPUART1_TX
ALT10 - GPIO11_IO9
GPIO_DISP_B2_09 ALT0 - VIDEO_MUX_LCDIF_DATA17 ODE - Disabled
ALT1 - ENET_RX_ER PUS - Weak PD
ALT2 - LPUART8_RX PUE - Pull Enable
ALT3 - CM7_EVENTI DSE - High drive strength
ALT4 - SAI1_TX_SYNC SRE - Fast slew rate
ALT5 - GPIO5_IO10
ALT8 - ENET_QOS_RX_ER
ALT9 - LPUART1_RX
ALT10 - GPIO11_IO10
GPIO_DISP_B2_10 ALT0 - VIDEO_MUX_LCDIF_DATA18 ODE - Disabled
ALT1 - SIM2_TRXD PUS - Weak PD
Table continues on the next page...
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Chapter 11 External Signals and Pin Multiplexing
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
ALT2 - LPUART2_TX PUE - Pull Enable
ALT3 - WDOG2_WDOG_RESET_B_DEB DSE - High drive strength
ALT4 - XBAR1_XBAR_INOUT38 SRE - Fast slew rate
ALT5 - GPIO5_IO11
ALT6 - LPI2C3_SCL
ALT8 - ENET_QOS_RX_ER
ALT9 - SPDIF_IN
ALT10 - GPIO11_IO11
GPIO_DISP_B2_11 ALT0 - VIDEO_MUX_LCDIF_DATA19 ODE - Disabled
ALT1 - SIM2_CLK PUS - Weak PD
ALT2 - LPUART2_RX PUE - Pull Enable
ALT3 - WDOG1_WDOG_RESET_B_DEB DSE - High drive strength
ALT4 - XBAR1_XBAR_INOUT39 SRE - Fast slew rate
ALT5 - GPIO5_IO12
ALT6 - LPI2C3_SDA
ALT8 - ENET_QOS_CRS
ALT9 - SPDIF_OUT
ALT10 - GPIO11_IO12
GPIO_DISP_B2_12 ALT0 - VIDEO_MUX_LCDIF_DATA20 ODE - Disabled
ALT1 - SIM2_RST_B PUS - Weak PD
ALT2 - CAN1_TX PUE - Pull Enable
ALT3 - LPUART2_CTS_B DSE - High drive strength
ALT4 - XBAR1_XBAR_INOUT40 SRE - Fast slew rate
ALT5 - GPIO5_IO13
ALT6 - LPI2C4_SCL
ALT8 - ENET_QOS_COL
ALT9 - LPSPI4_SCK
ALT10 - GPIO11_IO13
GPIO_DISP_B2_13 ALT0 - VIDEO_MUX_LCDIF_DATA21 ODE - Disabled
ALT1 - SIM2_SVEN PUS - Weak PD
ALT2 - CAN1_RX PUE - Pull Enable
ALT3 - LPUART2_RTS_B DSE - High drive strength
ALT4 - ENET_REF_CLK1 SRE - Fast slew rate
ALT5 - GPIO5_IO14
ALT6 - LPI2C4_SDA
ALT8 - ENET_QOS_1588_EVENT0_OUT
ALT9 - LPSPI4_SDI
ALT10 - GPIO11_IO14
Table continues on the next page...
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Overview
Table 11-2. Pin Assignments (continued)
Pin Name Pin Assignments Pad Settings
GPIO_DISP_B2_14 ALT0 - VIDEO_MUX_LCDIF_DATA22 ODE - Disabled
ALT1 - SIM2_PD PUS - Weak PD
ALT2 - WDOG2_WDOG_B PUE - Pull Enable
ALT3 - VIDEO_MUX_EXT_DCIC1 DSE - High drive strength
ALT4 - ENET_1G_REF_CLK1 SRE - Fast slew rate
ALT5 - GPIO5_IO15
ALT6 - CAN1_TX
ALT8 - ENET_QOS_1588_EVENT0_IN
ALT9 - LPSPI4_SDO
ALT10 - GPIO11_IO15
GPIO_DISP_B2_15 ALT0 - VIDEO_MUX_LCDIF_DATA23 ODE - Disabled
ALT1 - SIM2_POWER_FAIL PUS - Weak PU
ALT2 - WDOG1_WDOG_B PUE - Pull Enable
ALT3 - VIDEO_MUX_EXT_DCIC2 DSE - High drive strength
ALT4 - PIT1_TRIGGER0 SRE - Fast slew rate
ALT5 - GPIO5_IO16
ALT6 - CAN1_RX
ALT8 -
ENET_QOS_1588_EVENT0_AUX_IN
ALT9 - LPSPI4_PCS0
ALT10 - GPIO11_IO16
1. For GPIO_SNVS_00-09, tamper or SNVS_GPIO is determine by selected part numbers. On those devices, the users
cannot select between Tamper and SNVS GPIO functionality.
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Chapter 12
IOMUX Controller (IOMUXC)
12.1 Chip-specific IOMUXC information
Table 12-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
NOTE
For GPIO_MUX2 and GPIO_MUX3 instances, the users can
select between normal GPIO or CM7 fast GPIO.
12.2 Overview
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC to share
one pad to several functional blocks. This sharing is done by multiplexing the pad's input
and output signals.
Every module requires a specific pad setting (such as pull up or keeper), and for each
pad, there are up to 12 muxing options (called ALT modes). The pad settings parameters
are controlled by the IOMUXC.
The IOMUX consists only of combinatorial logic combined from several basic IOMUX
cells. Each basic IOMUX cell handles only one pad signal's muxing.
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Overview
The figure below illustrates the IOMUX/IOMUXC connectivity in the system.
PAD Settings
PAD Settings
Registers
MUX Control
Registers
IOMUXC
. .
IOMUX IO Pad
Cells
. Cells
.
. .
IPMUX
HW
signal
moduleY
CFG
AIPS Reg
moduleX IOMUX IORING
Arm PLATFORM + AHBMAX module module module
#1 #2 #N
Figure 12-1. IOMUX SoC Level Block Diagram
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Chapter 12 IOMUX Controller (IOMUXC)
12.2.1 Block Diagram
The high level illustration of the IO cells is shown in Figure 12-3
12.2.2 Features
The IOMUXC features include:
• 32-bit software mux control registers (IOMUXC_SW_MUX_CTL_PAD_<PAD
NAME>) to configure 1 of 12 alternate (ALT) MUX_MODE fields of each pad or a
predefined group of pads and to enable the forcing of an input path of the pad(s)
(SION bit).
• 32-bit software pad control registers
(IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME>) to configure specific pad
settings of each pad, or a predefined group of pads.
• 32-bit general purpose registers - GPRxx, 32-bit registers according to SoC
requirements for any usage.
• 32-bit input select control registers to control the input path to a module when more
than one pad drives this module input.
Each SW MUX/PAD CTL IOMUXC register handles only one pad or one pad's group.
Only the minimum number of registers required by software are implemented by
hardware. For example, if only ALT0 and ALT1 modes are used on Pad x then only one
bit register will be generated as the MUX_MODE control field in the software mux
control register of Pad x.
The software mux control registers may allow the forcing of pads to become input (input
path enabled) regardless of the functional direction driven. This may be useful for
loopback and GPIO data capture.
12.3 Functional description
This section provides a complete functional description of the block.
The IOMUX consists of a number of basic iomux cell units. If only one functional mode
is required for a specific pad, would have been no need for IOMUX and the signals can
be connected directly from the module to the I/O. The IOMUX cell is required whenever
two or more functional modes are required for a specific pad or when one functional
mode and the one test mode are required.
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Functional description
IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
: PAD0
ALTn
ALT0
ALT1
<SOURCE>_SELECT_INPUT :
ALTn
Peripheral1 DATA_IN IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
:
PAD1
ALTn
ALT0
ALT1
:
ALTn
Figure 12-2. IOMUX Cell Block Diagram
12.3.1 ALT6 and ALT7 extended muxing modes
The ALT7 and ALT6 extended muxing modes allow any signal in the system (such as
fuse, pad input, JTAG, or software register) to override any software configuration and to
force the ALT6/ALT7 muxing mode.
It also allows an IOMUX software register to control a group of pads.
12.3.2 SW Loopback through SION bit
A limited option exists to override the default pad functionality and force the input path
to be active regardless of the value driven by the corresponding module. This can be done
by setting the SION (Software Input On) bit in the IOMUXC_SW_MUX_CTL register
(when available) to "1".
Uses include:
• LoopBack - Module x drives the pad and also receives pad value as an input.
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Chapter 12 IOMUX Controller (IOMUXC)
12.3.3 Daisy chain - multi pads driving same module input pin
In some cases, more than one pad may drive a single module input pin. Such cases
require the addition of one more level of IOMUXing; all of these input signals are
muxed, and a dedicated software controlled register controls the mux in order to select
the required input path.
A module port involved in "daisy chain" requires two software configuration commands,
one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
This means that a module port involved in "daisy chain" requires two software
configuration commands, one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
The daisy chain is illustrated in the figure below.
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Memory Map and register definition
IOMUX IORING
IOMUX Cells
To module D
To module F
A
To module X
ALT x select
To module G
To module X
Module X B
To module H
ALT x select
Daisy Chain
To module X
select
To module M
C
To module N
ALT x select
Figure 12-3. Daisy chain illustration
12.3.4 Clocks
The table found here describes the clock sources for IOMUXC. Please see Clock
Controller Module (CCM) chapter for clock setting, configuration and gating
information.
Table 12-2. IOMUXC Clocks
Clock Name Description
ipg_clk Peripheral clock
ipg_clk_s Peripheral access clock
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Chapter 12 IOMUX Controller (IOMUXC)
12.4 Memory Map and register definition
This section includes the IOMUXC module memory map and detailed descriptions of all
registers.
12.4.1 IOMUXC SNVS register descriptions
12.4.1.1 iomuxc_snvs memory map
IOMUXC_SNVS base address: 40C9_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_WAKEUP_DIG)
4 SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control 32 RW 0000_0000
Register (SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG)
8 SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control 32 RW 0000_0000
Register (SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG)
C SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG)
10 SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG)
14 SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG)
18 SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG)
1C SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG)
20 SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG)
24 SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG)
28 SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG)
2C SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG)
30 SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control 32 RW 0000_0005
Register (SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG)
34 SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_TEST_MODE_DIG)
38 SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_POR_B_DIG)
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
3C SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_ONOFF_DIG)
40 SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_WAKEUP_DIG)
44 SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control 32 RW 0000_000A
Register (SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG)
48 SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control 32 RW 0000_000A
Register (SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG)
4C SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG)
50 SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG)
54 SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG)
58 SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG)
5C SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG)
60 SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG)
64 SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG)
68 SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG)
6C SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG)
70 SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control 32 RW 0000_0002
Register (SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG)
12.4.1.2 SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_WAKEUP_DIG)
SW_MUX_CTL Register
12.4.1.2.1 Offset
Register Offset
SW_MUX_CTL_PAD_W 0h
AKEUP_DIG
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12.4.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.2.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad WAKEUP_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: WAKEUP_DIG.
101 - Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13
111 - Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE
12.4.1.3 SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG)
SW_MUX_CTL Register
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12.4.1.3.1 Offset
Register Offset
SW_MUX_CTL_PAD_P 4h
MIC_ON_REQ_DIG
12.4.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.1.3.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad PMIC_ON_REQ_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: PMIC_ON_REQ_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13
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12.4.1.4 SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX
Control Register
(SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG)
SW_MUX_CTL Register
12.4.1.4.1 Offset
Register Offset
SW_MUX_CTL_PAD_P 8h
MIC_STBY_REQ_DIG
12.4.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
W SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.1.4.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad PMIC_STBY_REQ_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: PMIC_STBY_REQ_DIG.
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Field Description
000 - Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM
101 - Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13
12.4.1.5 SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.5.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP Ch
IO_SNVS_00_DIG
12.4.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.5.3 Fields
Field Description
31-5 -
— Reserved
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_00_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_00_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13
12.4.1.6 SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.6.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 10h
IO_SNVS_01_DIG
12.4.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.1.6.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_01_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_01_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13
12.4.1.7 SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.7.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 14h
IO_SNVS_02_DIG
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12.4.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.7.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_02_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_02_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13
12.4.1.8 SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
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12.4.1.8.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 18h
IO_SNVS_03_DIG
12.4.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.8.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_03_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_03_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13
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12.4.1.9 SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.9.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 1Ch
IO_SNVS_04_DIG
12.4.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.9.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_04_DIG
3 -
— Reserved
Table continues on the next page...
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Field Description
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_04_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13
12.4.1.10 SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.10.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 20h
IO_SNVS_05_DIG
12.4.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.1.10.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_05_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_05_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13
12.4.1.11 SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.11.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 24h
IO_SNVS_06_DIG
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12.4.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.11.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_06_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_06_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13
12.4.1.12 SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
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12.4.1.12.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 28h
IO_SNVS_07_DIG
12.4.1.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.12.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_07_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_07_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13
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12.4.1.13 SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.13.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 2Ch
IO_SNVS_08_DIG
12.4.1.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.1.13.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_08_DIG
3 -
— Reserved
Table continues on the next page...
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Field Description
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_08_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13
12.4.1.14 SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG)
The functionality of this pin is determined by the part number. Tamper function is
available only on tamper-enabled parts, and GPIO is the only available function on parts
which do not support tamper. The MUX_MODE must be configured to select the
function in both cases. Refer to the Datasheet for details on part numbers.
12.4.1.14.1 Offset
Register Offset
SW_MUX_CTL_PAD_GP 30h
IO_SNVS_09_DIG
12.4.1.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.1.14.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SNVS_09_DIG
3 -
— Reserved
2-0 MUX Mode Select Field.
MUX_MODE Select 1 of 2 iomux modes to be used for pad: GPIO_SNVS_09_DIG.
000 - Select mux mode: ALT0 mux port: SNVS_TAMPER10 of instance: SNVS_LP
101 - Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13
12.4.1.15 SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_TEST_MODE_DIG)
SW_PAD_CTL Register
12.4.1.15.1 Offset
Register Offset
SW_PAD_CTL_PAD_TE 34h
ST_MODE_DIG
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12.4.1.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.1.15.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Reserved
—
5-4 Reserved
—
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: TEST_MODE_DIG
0 - Weak pull down
Table continues on the next page...
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NXP Semiconductors 475
Memory Map and register definition
Field Description
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: TEST_MODE_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: TEST_MODE_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: TEST_MODE_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.16 SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register
(SW_PAD_CTL_PAD_POR_B_DIG)
SW_PAD_CTL Register
12.4.1.16.1 Offset
Register Offset
SW_PAD_CTL_PAD_PO 38h
R_B_DIG
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.1.16.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Reserved
—
5-4 Reserved
—
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: POR_B_DIG
0 - Weak pull down
Table continues on the next page...
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Memory Map and register definition
Field Description
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: POR_B_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: POR_B_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: POR_B_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.17 SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register
(SW_PAD_CTL_PAD_ONOFF_DIG)
SW_PAD_CTL Register
12.4.1.17.1 Offset
Register Offset
SW_PAD_CTL_PAD_ON 3Ch
OFF_DIG
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12.4.1.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.1.17.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Reserved
—
5-4 Reserved
—
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: ONOFF_DIG
0 - Weak pull down
Table continues on the next page...
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NXP Semiconductors 479
Memory Map and register definition
Field Description
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: ONOFF_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: ONOFF_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: ONOFF_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.18 SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_WAKEUP_DIG)
SW_PAD_CTL Register
12.4.1.18.1 Offset
Register Offset
SW_PAD_CTL_PAD_WA 40h
KEUP_DIG
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.1.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.1.18.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: WAKEUP_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: WAKEUP_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: WAKEUP_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: WAKEUP_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: WAKEUP_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.19 SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG)
SW_PAD_CTL Register
12.4.1.19.1 Offset
Register Offset
SW_PAD_CTL_PAD_PM 44h
IC_ON_REQ_DIG
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12.4.1.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.1.19.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: PMIC_ON_REQ_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: PMIC_ON_REQ_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: PMIC_ON_REQ_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: PMIC_ON_REQ_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: PMIC_ON_REQ_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.20 SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD
Control Register
(SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG)
SW_PAD_CTL Register
12.4.1.20.1 Offset
Register Offset
SW_PAD_CTL_PAD_PM 48h
IC_STBY_REQ_DIG
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12.4.1.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.1.20.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: PMIC_STBY_REQ_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: PMIC_STBY_REQ_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: PMIC_STBY_REQ_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: PMIC_STBY_REQ_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: PMIC_STBY_REQ_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.21 SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG)
SW_PAD_CTL Register
12.4.1.21.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 4Ch
IO_SNVS_00_DIG
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12.4.1.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.21.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_00_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_00_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_00_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_00_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_00_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.22 SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG)
SW_PAD_CTL Register
12.4.1.22.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 50h
IO_SNVS_01_DIG
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12.4.1.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.22.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_01_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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NXP Semiconductors 489
Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_01_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_01_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_01_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_01_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.23 SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG)
SW_PAD_CTL Register
12.4.1.23.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 54h
IO_SNVS_02_DIG
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12.4.1.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.23.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_02_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_02_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_02_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_02_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_02_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.24 SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG)
SW_PAD_CTL Register
12.4.1.24.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 58h
IO_SNVS_03_DIG
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12.4.1.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.24.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_03_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_03_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_03_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_03_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_03_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.25 SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG)
SW_PAD_CTL Register
12.4.1.25.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 5Ch
IO_SNVS_04_DIG
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12.4.1.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.25.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_04_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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NXP Semiconductors 495
Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_04_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_04_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_04_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_04_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.26 SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG)
SW_PAD_CTL Register
12.4.1.26.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 60h
IO_SNVS_05_DIG
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12.4.1.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.26.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_05_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_05_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_05_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_05_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_05_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.27 SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG)
SW_PAD_CTL Register
12.4.1.27.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 64h
IO_SNVS_06_DIG
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12.4.1.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.27.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_06_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_06_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_06_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_06_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_06_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.28 SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG)
SW_PAD_CTL Register
12.4.1.28.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 68h
IO_SNVS_07_DIG
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12.4.1.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.28.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_07_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_07_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_07_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_07_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_07_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.29 SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG)
SW_PAD_CTL Register
12.4.1.29.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 6Ch
IO_SNVS_08_DIG
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12.4.1.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.29.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_08_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_08_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_08_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_08_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_08_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.1.30 SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG)
SW_PAD_CTL Register
12.4.1.30.1 Offset
Register Offset
SW_PAD_CTL_PAD_GP 70h
IO_SNVS_09_DIG
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12.4.1.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_SNV
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
S
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.1.30.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-7 -
— Reserved
6 Open Drain SNVS Field
ODE_SNVS Select one out of next values for pad: GPIO_SNVS_09_DIG
0 - Disabled
1 - Enabled
5-4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PUS Select one out of next values for pad: GPIO_SNVS_09_DIG
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_SNVS_09_DIG
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_SNVS_09_DIG
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_SNVS_09_DIG
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.2 IOMUXC LPSR GPR register descriptions
12.4.2.1 iomuxc_lpsr_gpr memory map
IOMUXC_LPSR_GPR base address: 40C0_C000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
68 GPR26 General Purpose Register (GPR26) 32 RW 0000_4000
84 GPR33 General Purpose Register (GPR33) 32 RW 0000_0000
88 GPR34 General Purpose Register (GPR34) 32 RW 0000_0E00
8C GPR35 General Purpose Register (GPR35) 32 RW 0000_0000
90 GPR36 General Purpose Register (GPR36) 32 RW 0000_0000
94 GPR37 General Purpose Register (GPR37) 32 RW 0000_0000
98 GPR38 General Purpose Register (GPR38) 32 RW 0000_0000
9C GPR39 General Purpose Register (GPR39) 32 RW 0000_0000
A0 GPR40 General Purpose Register (GPR40) 32 RO 0000_0000
A4 GPR41 General Purpose Register (GPR41) 32 RO 0000_0000
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12.4.2.2 GPR26 General Purpose Register (GPR26)
GPR Register
12.4.2.2.1 Offset
Register Offset
GPR26 68h
12.4.2.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CM7_INIT_VTOR
DWP_LOCK
FIELD_0
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CM7_INIT_VTOR
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.2.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change CM7_INIT_VTOR. When bit 0 is set, CM7 is
forbidden. When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
Table continues on the next page...
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Memory Map and register definition
Field Description
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-25 General purpose bits
FIELD_0 Reserved
24-0 Vector table offset register out of reset. See the ARM v7-M Architecture Reference Manual for more
information about the vector table offset register (VTOR).
CM7_INIT_VTO
R NOTE: When user uses HAB authenticated or encrypted boot function, NXP strongly suggest user to set
the default value (ROM entry address) into INIT_VTOR register and lock the default value.
12.4.2.3 GPR33 General Purpose Register (GPR33)
GPR Register
12.4.2.3.1 Offset
Register Offset
GPR33 84h
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12.4.2.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBPHY2_WAKEUP_IRQ_CLEAR
USBPHY1_WAKEUP_IRQ_CLEAR
M4_NMI_CLEAR
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.3.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change FIELD_0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-10 Reserved
Table continues on the next page...
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Memory Map and register definition
Field Description
—
9 Clear USBPHY1 wakeup interrupt holding register
USBPHY2_WA The wakeup interrupt from USBPHY1 will be held internally until this bit is set to 1. Not that this bit need
KEUP_IRQ_CL software to clear. Set it to 1 to clear the interrupt and following with writing it to 0 to complete the
EAR operation.
8 Clear USBPHY1 wakeup interrupt holding register
USBPHY1_WA The wakeup interrupt from USBPHY1 will be held internally until this bit is set to 1. Not that this bit need
KEUP_IRQ_CL software to clear. Set it to 1 to clear the interrupt and following with writing it to 0 to complete the
EAR operation.
7-1 Reserved
—
0 Clear CM4 NMI holding register
M4_NMI_CLEA The NMI input from IO will be held internally until this bit is set to 1. Note that this bit need software to
R clear. Set it to 1 to clear the interrupt and following with writing it to 0 to complete the operation.
12.4.2.4 GPR34 General Purpose Register (GPR34)
GPR Register
12.4.2.4.1 Offset
Register Offset
GPR34 88h
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12.4.2.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO_LPSR_HIGH_RANGE
GPIO_LPSR_LOW_RANGE
M4_GPC_SLEEP_SE
M4_NMI_MASK
M7_NMI_MASK
SEC_ERR_RE
Reserved
Reserved
Reserved
Reserved
W
SP
L
Reset 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0
12.4.2.4.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-12 Reserved
—
11 Security error response enable
Table continues on the next page...
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Memory Map and register definition
Field Description
SEC_ERR_RES This bitfield is the security error response enable for all security gaskets on both AHB and AXI buses. The
P RDC defines access policies and the security gaskets on the buses are responsible to verify the access
against these policies. This bit defines what kind of bus response is returned when the access violates
the policies.
0 - OKEY response
1 - SLVError (default)
10-9 Reserved
—
8-6 Reserved
—
5 CM4 sleep request selection
M4_GPC_SLEE This bit controls which kind of CM4 sleep request is sent to GPC to start sleep sequence.
P_SEL
0 - CM4 SLEEPDEEP is sent to GPC
1 - CM4 SLEEPING is sent to GPC
4 Mask CM4 NMI pin input
M4_NMI_MASK 0 - NMI input from IO to CM4 is not blocked
1 - NMI input from IO to CM4 is blocked
3 Mask CM7 NMI pin input
M7_NMI_MASK 0 - NMI input from IO to CM7 is not blocked
1 - NMI input from IO to CM7 is blocked
2 GPIO_LPSR IO bank supply voltage range selection
GPIO_LPSR_L
OW_RANGE GPIO_LPSR_HIGH_RANGE GPIO_LPSR_LOW_RANGE Mode
0 0 GPIO_LPSR_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_LPSR_xx IO will work in
low range mode with supply
voltage in 1.71v-1.98v
1 0 GPIO_LPSR_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
1 GPIO_LPSR IO bank supply voltage range selection
GPIO_LPSR_HI
GH_RANGE GPIO_LPSR_HIGH_RANGE GPIO_LPSR_LOW_RANGE Mode
0 0 GPIO_LPSR_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_LPSR_xx IO will work in
low range mode with supply
voltage in 1.71v-1.98v
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
1 0 GPIO_LPSR_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
0 Reserved
—
12.4.2.5 GPR35 General Purpose Register (GPR35)
GPR Register
12.4.2.5.1 Offset
Register Offset
GPR35 8Ch
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Memory Map and register definition
12.4.2.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EDMA_LPSR_STOP_REQ
FLEXSPI2_IPG_DOZE
FLEXSPI1_IPG_DOZE
FLEXIO2_IPG_DOZE
FLEXIO1_IPG_DOZE
ENET1G_IPG_DOZE
FLEXSPI2_STOP_RE
FLEXSPI1_STOP_RE
ENET1G_STOP_RE
ENET_IPG_DOZE
ENET_STOP_RE
DWP_LOCK
Reserved
DWP
W
Q
Q
Q
Q
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADC2_IPG_STOP_MODE
ADC1_IPG_STOP_MODE
EDMA_STOP_REQ
CAAM_STOP_REQ
CAN3_STOP_REQ
CAN2_STOP_REQ
CAN1_STOP_REQ
ADC2_STOP_REQ
ADC1_STOP_REQ
CAAM_IPG_DOZE
CAN3_IPG_DOZE
CAN2_IPG_DOZE
CAN1_IPG_DOZE
ADC2_IPG_DOZE
ADC1_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.5.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27 Reserved
—
Table continues on the next page...
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Field Description
26 FLEXSPI2 stop request
FLEXSPI2_STO 0 - Stop request off
P_REQ
1 - Stop request on
25 FLEXSPI2 doze mode
FLEXSPI2_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
24 FLEXSPI1 stop request
FLEXSPI1_STO 0 - Stop request off
P_REQ
1 - Stop request on
23 FLEXSPI1 doze mode
FLEXSPI1_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
22 FLEXIO2 doze mode
FLEXIO2_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
21 FLEXIO2 doze mode
FLEXIO1_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
20 ENET1G stop request
ENET1G_STOP 0 - Stop request off
_REQ
1 - Stop request on
19 ENET1G doze mode
ENET1G_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
18 ENET stop request
ENET_STOP_R 0 - Stop request off
EQ
1 - Stop request on
17 ENET doze mode
ENET_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
16 EDMA_LPSR stop request
EDMA_LPSR_S 0 - Stop request off
TOP_REQ
1 - Stop request on
15 EDMA stop request
EDMA_STOP_R 0 - Stop request off
EQ
1 - Stop request on
14 Reserved
—
13 CAN3 stop request
Table continues on the next page...
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Memory Map and register definition
Field Description
CAN3_STOP_R 0 - Stop request off
EQ
1 - Stop request on
12 CAN3 doze mode
CAN3_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
11 CAN2 stop request
CAN2_STOP_R 0 - Stop request off
EQ
1 - Stop request on
10 CAN2 doze mode
CAN2_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
9 CAN1 stop request
CAN1_STOP_R 0 - Stop request off
EQ
1 - Stop request on
8 CAN1 doze mode
CAN1_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
7 CAAM stop request
CAAM_STOP_R 0 - Stop request off
EQ
1 - Stop request on
6 CAN3 doze mode
CAAM_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
5 ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted.
ADC2_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 ADC2 stop request
ADC2_STOP_R 0 - Stop request off
EQ
1 - Stop request on
3 ADC2 doze mode
ADC2_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
2 ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted.
ADC1_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
1 ADC1 stop request
ADC1_STOP_R 0 - Stop request off
EQ
1 - Stop request on
0 ADC1 doze mode
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R
R
W
W
Bits
Bits
Reset
Reset
GPR36
LPI2C4_IPG_DOZE DWP_LOCK ZE
0
0
Field
15
31
12.4.2.6.2
12.4.2.6.1
LPI2C3_IPG_STOP_MODE
Register
0
0
GPR Register
14
30
NXP Semiconductors
LPI2C3_STOP_REQ DWP
0
0
13
29
Offset
90h
LPI2C3_IPG_DOZE
Diagram
0
0
12
28
1 - In doze mode
ADC1_IPG_DO 0 - Not in doze mode
LPI2C2_IPG_STOP_MODE Reserved
0
0
11
27
LPI2C2_STOP_REQ LPSPI1_IPG_STOP_MODE
0
0
10
26
LPI2C2_IPG_DOZE LPSPI1_STOP_REQ
0
0
25
LPI2C1_IPG_STOP_MODE LPSPI1_IPG_DOZE
0
0
24
LPI2C1_STOP_REQ LPI2C6_IPG_STOP_MODE
0
0
LPI2C1_IPG_DOZE LPI2C6_STOP_REQ 23
Description
0
0
22
Offset
GPT6_IPG_DOZE LPI2C6_IPG_DOZE
0
0
21
GPT5_IPG_DOZE LPI2C5_IPG_STOP_MODE
12.4.2.6 GPR36 General Purpose Register (GPR36)
0
0
20
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
GPT4_IPG_DOZE LPI2C5_STOP_REQ
0
0
19
GPT3_IPG_DOZE LPI2C5_IPG_DOZE
0
0
18
GPT2_IPG_DOZE LPI2C4_IPG_STOP_MODE
1
0
0
17
GPT1_IPG_DOZE LPI2C4_STOP_REQ
0
0
0
16
517
Chapter 12 IOMUX Controller (IOMUXC)
Memory Map and register definition
12.4.2.6.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27 Reserved
—
26 LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted.
LPSPI1_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 LPSPI1 stop request
LPSPI1_STOP_ 0 - Stop request off
REQ
1 - Stop request on
24 LPSPI1 doze mode
LPSPI1_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
23 LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted.
LPI2C6_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPI2C6 stop request
LPI2C6_STOP_ 0 - Stop request off
REQ
1 - Stop request on
21 LPI2C6 doze mode
LPI2C6_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
20 LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted.
LPI2C5_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPI2C5 stop request
0 - Stop request off
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPI2C5_STOP_ 1 - Stop request on
REQ
18 LPI2C5 doze mode
LPI2C5_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
17 LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted.
LPI2C4_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPI2C4 stop request
LPI2C4_STOP_ 0 - Stop request off
REQ
1 - Stop request on
15 LPI2C4 doze mode
LPI2C4_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
14 LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted.
LPI2C3_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPI2C3 stop request
LPI2C3_STOP_ 0 - Stop request off
REQ
1 - Stop request on
12 LPI2C3 doze mode
LPI2C3_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
11 LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted.
LPI2C2_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPI2C2 stop request
LPI2C2_STOP_ 0 - Stop request off
REQ
1 - Stop request on
9 LPI2C2 doze mode
LPI2C2_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
8 LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted.
LPI2C1_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPI2C1 stop request
LPI2C1_STOP_ 0 - Stop request off
REQ
1 - Stop request on
6 LPI2C1 doze mode
0 - Not in doze mode
Table continues on the next page...
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Memory Map and register definition
Field Description
LPI2C1_IPG_D 1 - In doze mode
OZE
5 GPT6 doze mode
GPT6_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
4 GPT5 doze mode
GPT5_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
3 GPT4 doze mode
GPT4_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
2 GPT3 doze mode
GPT3_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
1 GPT2 doze mode
GPT2_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
0 GPT1 doze mode
GPT1_IPG_DO 0 - Not in doze mode
ZE
1 - In doze mode
12.4.2.7 GPR37 General Purpose Register (GPR37)
GPR Register
12.4.2.7.1 Offset
Register Offset
GPR37 94h
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.2.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART4_IPG_STOP_MODE
LPUART3_IPG_STOP_MODE
LPUART2_IPG_STOP_MODE
LPUART1_IPG_STOP_MODE
LPUART4_STOP_REQ
LPUART3_STOP_REQ
LPUART2_STOP_REQ
LPUART1_STOP_REQ
LPUART4_IPG_DOZE
LPUART3_IPG_DOZE
LPUART2_IPG_DOZE
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPSPI6_IPG_STOP_MODE
LPSPI5_IPG_STOP_MODE
LPSPI4_IPG_STOP_MODE
LPSPI3_IPG_STOP_MODE
LPSPI2_IPG_STOP_MODE
LPUART1_IPG_DOZE
LPSPI6_STOP_REQ
LPSPI5_STOP_REQ
LPSPI4_STOP_REQ
LPSPI3_STOP_REQ
LPSPI2_STOP_REQ
LPSPI6_IPG_DOZE
LPSPI5_IPG_DOZE
LPSPI4_IPG_DOZE
LPSPI3_IPG_DOZE
LPSPI2_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.7.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
Table continues on the next page...
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Memory Map and register definition
Field Description
27 Reserved
—
26 LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted.
LPUART4_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 LPUART4 stop request
LPUART4_STO 0 - Stop request off
P_REQ
1 - Stop request on
24 LPUART4 doze mode
LPUART4_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
23 LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted.
LPUART3_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPUART3 stop request
LPUART3_STO 0 - Stop request off
P_REQ
1 - Stop request on
21 LPUART3 doze mode
LPUART3_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
20 LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted.
LPUART2_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPUART2 stop request
LPUART2_STO 0 - Stop request off
P_REQ
1 - Stop request on
18 LPUART2 doze mode
LPUART2_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
17 LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted.
LPUART1_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPUART1 stop request
LPUART1_STO 0 - Stop request off
P_REQ
1 - Stop request on
15 LPUART1 doze mode
LPUART1_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
14 LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted.
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPSPI6_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPSPI6 stop request
LPSPI6_STOP_ 0 - Stop request off
REQ
1 - Stop request on
12 LPSPI6 doze mode
LPSPI6_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
11 LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted.
LPSPI5_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPSPI5 stop request
LPSPI5_STOP_ 0 - Stop request off
REQ
1 - Stop request on
9 LPSPI5 doze mode
LPSPI5_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
8 LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted.
LPSPI4_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPSPI4 stop request
LPSPI4_STOP_ 0 - Stop request off
REQ
1 - Stop request on
6 LPSPI4 doze mode
LPSPI4_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
5 LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted.
LPSPI3_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 LPSPI3 stop request
LPSPI3_STOP_ 0 - Stop request off
REQ
1 - Stop request on
3 LPSPI3 doze mode
LPSPI3_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
2 LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted.
LPSPI2_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
1 LPSPI2 stop request
Table continues on the next page...
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Memory Map and register definition
Field Description
LPSPI2_STOP_ 0 - Stop request off
REQ
1 - Stop request on
0 LPSPI2 doze mode
LPSPI2_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
12.4.2.8 GPR38 General Purpose Register (GPR38)
GPR Register
12.4.2.8.1 Offset
Register Offset
GPR38 98h
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.2.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART12_IPG_STOP_MODE
LPUART11_IPG_STOP_MODE
LPUART10_IPG_STOP_MODE
LPUART12_STOP_REQ
LPUART11_STOP_REQ
LPUART10_STOP_REQ
MIC_IPG_STOP_MODE
LPUART12_IPG_DOZE
LPUART11_IPG_DOZE
MIC_STOP_REQ
MIC_IPG_DOZE
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPUART9_IPG_STOP_MODE
LPUART8_IPG_STOP_MODE
LPUART7_IPG_STOP_MODE
LPUART6_IPG_STOP_MODE
LPUART5_IPG_STOP_MODE
LPUART9_STOP_REQ
LPUART8_STOP_REQ
LPUART7_STOP_REQ
LPUART6_STOP_REQ
LPUART5_STOP_REQ
LPUART10_IPG_DOZE
LPUART9_IPG_DOZE
LPUART8_IPG_DOZE
LPUART7_IPG_DOZE
LPUART6_IPG_DOZE
LPUART5_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.8.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
Table continues on the next page...
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Memory Map and register definition
Field Description
11 - Both cores are forbidden
27 Reserved
—
26 MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted.
MIC_IPG_STOP 0 - This module is functional in Stop Mode
_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 MIC stop request
MIC_STOP_RE 0 - Stop request off
Q
1 - Stop request on
24 MIC doze mode
MIC_IPG_DOZE 0 - Not in doze mode
1 - In doze mode
23 LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted.
LPUART12_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPUART12 stop request
LPUART12_ST 0 - Stop request off
OP_REQ
1 - Stop request on
21 LPUART12 doze mode
LPUART12_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
20 LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted.
LPUART11_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPUART11 stop request
LPUART11_ST 0 - Stop request off
OP_REQ
1 - Stop request on
18 LPUART11 doze mode
LPUART11_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
17 LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted.
LPUART10_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPUART10 stop request
LPUART10_ST 0 - Stop request off
OP_REQ
1 - Stop request on
15 LPUART10 doze mode
LPUART10_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
14 LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted.
LPUART9_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPUART9 stop request
LPUART9_STO 0 - Stop request off
P_REQ
1 - Stop request on
12 LPUART9 doze mode
LPUART9_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
11 LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted.
LPUART8_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPUART8 stop request
LPUART8_STO 0 - Stop request off
P_REQ
1 - Stop request on
9 LPUART8 doze mode
LPUART8_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
8 LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted.
LPUART7_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPUART7 stop request
LPUART7_STO 0 - Stop request off
P_REQ
1 - Stop request on
6 LPUART7 doze mode
LPUART7_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
5 LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted.
LPUART6_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 LPUART6 stop request
LPUART6_STO 0 - Stop request off
P_REQ
1 - Stop request on
3 LPUART6 doze mode
LPUART6_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
2 LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted.
LPUART5_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
Table continues on the next page...
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Memory Map and register definition
Field Description
1 LPUART5 stop request
LPUART5_STO 0 - Stop request off
P_REQ
1 - Stop request on
0 LPUART5 doze mode
LPUART5_IPG_ 0 - Not in doze mode
DOZE
1 - In doze mode
12.4.2.9 GPR39 General Purpose Register (GPR39)
GPR Register
12.4.2.9.1 Offset
Register Offset
GPR39 9Ch
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.2.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLEXIO2_STOP_REQ_BUS
FLEXIO2_STOP_REQ_PE
DWP_LOCK
Reserved
DWP
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FLEXIO1_STOP_REQ_BUS
0
FLEXIO1_STOP_REQ_PE
SNVS_HP_IPG_DOZE
SNVS_HP_STOP_RE
WDOG2_IPG_DOZE
WDOG1_IPG_DOZE
SAI4_STOP_REQ
SAI3_STOP_REQ
SAI2_STOP_REQ
SAI1_STOP_REQ
PIT2_STOP_REQ
PIT1_STOP_REQ
SIM2_IPG_DOZE
SIM1_IPG_DOZE
SEMC_STOP_RE
W
Q
Q
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.9.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-18 Reserved
Table continues on the next page...
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Memory Map and register definition
Field Description
—
17 FLEXIO2 peripheral clock domain stop request
FLEXIO2_STOP 0 - Stop request off
_REQ_PER
1 - Stop request on
16 FLEXIO2 bus clock domain stop request
FLEXIO2_STOP 0 - Stop request off
_REQ_BUS
1 - Stop request on
15 FLEXIO1 peripheral clock domain stop request
FLEXIO1_STOP 0 - Stop request off
_REQ_PER
1 - Stop request on
14 FLEXIO1 bus clock domain stop request
FLEXIO1_STOP 0 - Stop request off
_REQ_BUS
1 - Stop request on
13 SAI4 stop request
SAI4_STOP_RE 0 - Stop request off
Q
1 - Stop request on
12 SAI3 stop request
SAI3_STOP_RE 0 - Stop request off
Q
1 - Stop request on
11 SAI2 stop request
SAI2_STOP_RE 0 - Stop request off
Q
1 - Stop request on
10 SAI1 stop request
SAI1_STOP_RE 0 - Stop request off
Q
1 - Stop request on
9 WDOG2 doze mode
WDOG2_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
8 WDOG1 doze mode
WDOG1_IPG_D 0 - Not in doze mode
OZE
1 - In doze mode
7 SNVS_HP stop request
SNVS_HP_STO 0 - Stop request off
P_REQ
1 - Stop request on
6 SNVS_HP doze mode
SNVS_HP_IPG 0 - Not in doze mode
_DOZE
1 - In doze mode
5 SIM2 doze mode
SIM2_IPG_DOZ 0 - Not in doze mode
E
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
1 - In doze mode
4 SIM1 doze mode
SIM1_IPG_DOZ 0 - Not in doze mode
E
1 - In doze mode
3 SEMC stop request
SEMC_STOP_R 0 - Stop request off
EQ
1 - Stop request on
2 PIT2 stop request
PIT2_STOP_RE 0 - Stop request off
Q
1 - Stop request on
1 PIT1 stop request
PIT1_STOP_RE 0 - Stop request off
Q
1 - Stop request on
0 Reserved
—
12.4.2.10 GPR40 General Purpose Register (GPR40)
GPR Register
12.4.2.10.1 Offset
Register Offset
GPR40 A0h
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Memory Map and register definition
12.4.2.10.2 Diagram
Bits 31
LPUART8_STOP_ACK 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART7_STOP_ACK
LPUART6_STOP_ACK
LPUART5_STOP_ACK
LPUART4_STOP_ACK
LPUART3_STOP_ACK
LPUART2_STOP_ACK
LPUART1_STOP_ACK
LPSPI6_STOP_ACK
LPSPI5_STOP_ACK
LPSPI4_STOP_ACK
LPSPI3_STOP_ACK
LPSPI2_STOP_ACK
LPSPI1_STOP_ACK
LPI2C6_STOP_ACK
LPI2C5_STOP_ACK
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EDMA_LPSR_STOP_ACK
FLEXSPI2_STOP_ACK
FLEXSPI1_STOP_ACK
ENET1G_STOP_ACK
LPI2C4_STOP_ACK
LPI2C3_STOP_ACK
LPI2C2_STOP_ACK
LPI2C1_STOP_ACK
ENET_STOP_ACK
EDMA_STOP_ACK
CAAM_STOP_ACK
CAN3_STOP_ACK
CAN2_STOP_ACK
CAN1_STOP_ACK
ADC2_STOP_ACK
ADC1_STOP_ACK
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.10.3 Fields
Field Description
31 LPUART8 stop acknowledge
LPUART8_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
30 LPUART7 stop acknowledge
LPUART7_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
29 LPUART6 stop acknowledge
LPUART6_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
28 LPUART5 stop acknowledge
LPUART5_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
27 LPUART4 stop acknowledge
LPUART4_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
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Field Description
26 LPUART3 stop acknowledge
LPUART3_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
25 LPUART2 stop acknowledge
LPUART2_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
24 LPUART1 stop acknowledge
LPUART1_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
23 LPSPI6 stop acknowledge
LPSPI6_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
22 LPSPI5 stop acknowledge
LPSPI5_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
21 LPSPI4 stop acknowledge
LPSPI4_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
20 LPSPI3 stop acknowledge
LPSPI3_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
19 LPSPI2 stop acknowledge
LPSPI2_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
18 LPSPI1 stop acknowledge
LPSPI1_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
17 LPI2C6 stop acknowledge
LPI2C6_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
16 LPI2C5 stop acknowledge
LPI2C5_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
15 LPI2C4 stop acknowledge
LPI2C4_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
14 LPI2C3 stop acknowledge
LPI2C3_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
13 LPI2C2 stop acknowledge
LPI2C2_STOP_ 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
ACK
12 LPI2C1 stop acknowledge
0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
Table continues on the next page...
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Memory Map and register definition
Field Description
LPI2C1_STOP_
ACK
11 FLEXSPI2 stop acknowledge
FLEXSPI2_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
10 FLEXSPI1 stop acknowledge
FLEXSPI1_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
9 ENET1G stop acknowledge
ENET1G_STOP 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
_ACK
8 ENET stop acknowledge
ENET_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
7 EDMA_LPSR stop acknowledge
EDMA_LPSR_S 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
TOP_ACK
6 EDMA stop acknowledge
EDMA_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
5 CAN3 stop acknowledge
CAN3_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
4 CAN2 stop acknowledge
CAN2_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
3 CAN1 stop acknowledge
CAN1_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
2 CAAM stop acknowledge
CAAM_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
1 ADC2 stop acknowledge
ADC2_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
0 ADC1 stop acknowledge
ADC1_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
12.4.2.11 GPR41 General Purpose Register (GPR41)
GPR Register
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12.4.2.11.1 Offset
Register Offset
GPR41 A4h
12.4.2.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLEXIO2_STOP_ACK_PER
ROM_READ_LOCKED
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEXIO1_STOP_ACK_PER
FLEXIO2_STOP_ACK_BUS
FLEXIO1_STOP_ACK_BUS
SNVS_HP_STOP_ACK
LPUART12_STOP_ACK
LPUART11_STOP_ACK
LPUART10_STOP_ACK
LPUART9_STOP_ACK
SEMC_STOP_ACK
SAI4_STOP_ACK
SAI3_STOP_ACK
SAI2_STOP_ACK
SAI1_STOP_ACK
PIT2_STOP_ACK
PIT1_STOP_ACK
MIC_STOP_ACK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.2.11.3 Fields
Field Description
31-25 Reserved
—
24 ROM read lock status bit
ROM_READ_L When is bit is 1, it indicates that the first 64KB of ROM code are locked and not readable anymore.
OCKED
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Memory Map and register definition
Field Description
23-17 Reserved
—
16 FLEXIO2 stop acknowledge of peripheral clock domain
FLEXIO2_STOP 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
_ACK_PER
15 FLEXIO2 stop acknowledge of bus clock domain
FLEXIO2_STOP 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
_ACK_BUS
14 FLEXIO1 stop acknowledge of peripheral clock domain
FLEXIO1_STOP 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
_ACK_PER
13 FLEXIO1 stop acknowledge of bus clock domain
FLEXIO1_STOP 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
_ACK_BUS
12 SAI4 stop acknowledge
SAI4_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
11 SAI3 stop acknowledge
SAI3_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
10 SAI2 stop acknowledge
SAI2_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
9 SAI1 stop acknowledge
SAI1_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
8 SNVS_HP stop acknowledge
SNVS_HP_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
7 SEMC stop acknowledge
SEMC_STOP_A 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
CK
6 PIT2 stop acknowledge
PIT2_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
5 PIT1 stop acknowledge
PIT1_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
4 MIC stop acknowledge
MIC_STOP_AC 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
K
3 LPUART12 stop acknowledge
LPUART12_ST 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
OP_ACK
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Field Description
2 LPUART11 stop acknowledge
LPUART11_ST 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
OP_ACK
1 LPUART10 stop acknowledge
LPUART10_ST 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
OP_ACK
0 LPUART9 stop acknowledge
LPUART9_STO 0: stop acknowledge is not asserted 1: stop acknowledge is asserted (the module is in Stop mode)
P_ACK
12.4.3 IOMUXC LPSR register descriptions
12.4.3.1 iomuxc_lpsr memory map
IOMUXC_LPSR base address: 40C0_8000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_00)
4 SW_MUX_CTL_PAD_GPIO_LPSR_01 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_01)
8 SW_MUX_CTL_PAD_GPIO_LPSR_02 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_02)
C SW_MUX_CTL_PAD_GPIO_LPSR_03 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_03)
10 SW_MUX_CTL_PAD_GPIO_LPSR_04 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_04)
14 SW_MUX_CTL_PAD_GPIO_LPSR_05 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_05)
18 SW_MUX_CTL_PAD_GPIO_LPSR_06 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_06)
1C SW_MUX_CTL_PAD_GPIO_LPSR_07 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_07)
20 SW_MUX_CTL_PAD_GPIO_LPSR_08 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_08)
24 SW_MUX_CTL_PAD_GPIO_LPSR_09 SW MUX Control Register 32 RW 0000_000A
(SW_MUX_CTL_PAD_GPIO_LPSR_09)
28 SW_MUX_CTL_PAD_GPIO_LPSR_10 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_10)
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
2C SW_MUX_CTL_PAD_GPIO_LPSR_11 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_11)
30 SW_MUX_CTL_PAD_GPIO_LPSR_12 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_12)
34 SW_MUX_CTL_PAD_GPIO_LPSR_13 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_13)
38 SW_MUX_CTL_PAD_GPIO_LPSR_14 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_14)
3C SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register 32 RW 0000_0000
(SW_MUX_CTL_PAD_GPIO_LPSR_15)
40 SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_00)
44 SW_PAD_CTL_PAD_GPIO_LPSR_01 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_01)
48 SW_PAD_CTL_PAD_GPIO_LPSR_02 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_02)
4C SW_PAD_CTL_PAD_GPIO_LPSR_03 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_03)
50 SW_PAD_CTL_PAD_GPIO_LPSR_04 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_04)
54 SW_PAD_CTL_PAD_GPIO_LPSR_05 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_05)
58 SW_PAD_CTL_PAD_GPIO_LPSR_06 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_06)
5C SW_PAD_CTL_PAD_GPIO_LPSR_07 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_07)
60 SW_PAD_CTL_PAD_GPIO_LPSR_08 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_08)
64 SW_PAD_CTL_PAD_GPIO_LPSR_09 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_09)
68 SW_PAD_CTL_PAD_GPIO_LPSR_10 SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_GPIO_LPSR_10)
6C SW_PAD_CTL_PAD_GPIO_LPSR_11 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_11)
70 SW_PAD_CTL_PAD_GPIO_LPSR_12 SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_GPIO_LPSR_12)
74 SW_PAD_CTL_PAD_GPIO_LPSR_13 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_LPSR_13)
78 SW_PAD_CTL_PAD_GPIO_LPSR_14 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_LPSR_14)
7C SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_GPIO_LPSR_15)
80 CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register (CAN3_ 32 RW 0000_0000
IPP_IND_CANRX_SELECT_INPUT)
84 LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT)
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
88 LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT)
8C LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT)
90 LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT)
94 LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY Register 32 RW 0000_0000
(LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0)
98 LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT)
9C LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT)
A0 LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY Register 32 RW 0000_0000
(LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT)
A4 LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY 32 RW 0000_0000
Register (LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT)
A8 LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY 32 RW 0000_0000
Register (LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT)
AC LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY 32 RW 0000_0000
Register (LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT)
B0 LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY 32 RW 0000_0000
Register (LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT)
B4 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 DAISY 32 RW 0000_0000
Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_
0)
B8 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 DAISY 32 RW 0000_0000
Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_
1)
BC MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 DAISY 32 RW 0000_0000
Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_
2)
C0 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 DAISY 32 RW 0000_0000
Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_
3)
C4 NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register (NMI_ 32 RW 0000_0000
GLUE_IPP_IND_NMI_SELECT_INPUT)
C8 SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register (SAI4 32 RW 0000_0000
_IPG_CLK_SAI_MCLK_SELECT_INPUT)
CC SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register 32 RW 0000_0000
(SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT)
D0 SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register 32 RW 0000_0000
(SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0)
D4 SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register 32 RW 0000_0000
(SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT)
D8 SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register 32 RW 0000_0000
(SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT)
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
DC SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register 32 RW 0000_0000
(SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
12.4.3.2 SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_00)
SW_MUX_CTL Register
12.4.3.2.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 0h
PIO_LPSR_00
12.4.3.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.2.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_LPSR_00.
0000 - Select mux mode: ALT0 mux port: FLEXCAN3_TX of instance: FLEXCAN3
0001 - Select mux mode: ALT1 mux port: MIC_CLK of instance: MIC
0010 - Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS
0011 - Select mux mode: ALT3 mux port: ARM_CM4_EVENTO of instance: CM4
0101 - Select mux mode: ALT5 mux port: GPIO6_IO00 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPUART12_TXD of instance: LPUART12
0111 - Select mux mode: ALT7 mux port: SAI4_MCLK of instance: SAI4
1010 - Select mux mode: ALT10 mux port: GPIO12_IO00 of instance: GPIO12
12.4.3.3 SW_MUX_CTL_PAD_GPIO_LPSR_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_01)
SW_MUX_CTL Register
12.4.3.3.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 4h
PIO_LPSR_01
12.4.3.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
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12.4.3.3.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_LPSR_01.
0000 - Select mux mode: ALT0 mux port: FLEXCAN3_RX of instance: FLEXCAN3
0001 - Select mux mode: ALT1 mux port: MIC_BITSTREAM0 of instance: MIC
0010 - Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS
0011 - Select mux mode: ALT3 mux port: ARM_CM4_EVENTI of instance: CM4
0101 - Select mux mode: ALT5 mux port: GPIO6_IO01 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPUART12_RXD of instance: LPUART12
1010 - Select mux mode: ALT10 mux port: GPIO12_IO01 of instance: GPIO12
12.4.3.4 SW_MUX_CTL_PAD_GPIO_LPSR_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_02)
SW_MUX_CTL Register
12.4.3.4.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 8h
PIO_LPSR_02
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12.4.3.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.4.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_LPSR_02.
0000 - Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: SRC
0001 - Select mux mode: ALT1 mux port: LPSPI5_SCK of instance: LPSPI5
0010 - Select mux mode: ALT2 mux port: SAI4_TX_DATA of instance: SAI4
0011 - Select mux mode: ALT3 mux port: MQS_RIGHT of instance: MQS
0101 - Select mux mode: ALT5 mux port: GPIO6_IO02 of instance: GPIO6
1010 - Select mux mode: ALT10 mux port: GPIO12_IO02 of instance: GPIO12
12.4.3.5 SW_MUX_CTL_PAD_GPIO_LPSR_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_03)
SW_MUX_CTL Register
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12.4.3.5.1 Offset
Register Offset
SW_MUX_CTL_PAD_G Ch
PIO_LPSR_03
12.4.3.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.5.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_LPSR_03.
0000 - Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: SRC
0001 - Select mux mode: ALT1 mux port: LPSPI5_PCS0 of instance: LPSPI5
0010 - Select mux mode: ALT2 mux port: SAI4_TX_SYNC of instance: SAI4
0011 - Select mux mode: ALT3 mux port: MQS_LEFT of instance: MQS
0101 - Select mux mode: ALT5 mux port: GPIO6_IO03 of instance: GPIO6
1010 - Select mux mode: ALT10 mux port: GPIO12_IO03 of instance: GPIO12
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12.4.3.6 SW_MUX_CTL_PAD_GPIO_LPSR_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_04)
SW_MUX_CTL Register
12.4.3.6.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 10h
PIO_LPSR_04
12.4.3.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.6.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_LPSR_04.
0000 - Select mux mode: ALT0 mux port: LPI2C5_SDA of instance: LPI2C5
0001 - Select mux mode: ALT1 mux port: LPSPI5_SOUT of instance: LPSPI5
0010 - Select mux mode: ALT2 mux port: SAI4_TX_BCLK of instance: SAI4
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Field Description
0011 - Select mux mode: ALT3 mux port: LPUART12_RTS_B of instance: LPUART12
0101 - Select mux mode: ALT5 mux port: GPIO6_IO04 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPUART11_TXD of instance: LPUART11
1010 - Select mux mode: ALT10 mux port: GPIO12_IO04 of instance: GPIO12
12.4.3.7 SW_MUX_CTL_PAD_GPIO_LPSR_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_05)
SW_MUX_CTL Register
12.4.3.7.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 14h
PIO_LPSR_05
12.4.3.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.7.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
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Field Description
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_LPSR_05.
0000 - Select mux mode: ALT0 mux port: LPI2C5_SCL of instance: LPI2C5
0001 - Select mux mode: ALT1 mux port: LPSPI5_SIN of instance: LPSPI5
0010 - Select mux mode: ALT2 mux port: SAI4_MCLK of instance: SAI4
0011 - Select mux mode: ALT3 mux port: LPUART12_CTS_B of instance: LPUART12
0101 - Select mux mode: ALT5 mux port: GPIO6_IO05 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPUART11_RXD of instance: LPUART11
0111 - Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue
1010 - Select mux mode: ALT10 mux port: GPIO12_IO05 of instance: GPIO12
12.4.3.8 SW_MUX_CTL_PAD_GPIO_LPSR_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_06)
SW_MUX_CTL Register
12.4.3.8.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 18h
PIO_LPSR_06
12.4.3.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
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12.4.3.8.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_LPSR_06.
0000 - Select mux mode: ALT0 mux port: LPI2C6_SDA of instance: LPI2C6
0010 - Select mux mode: ALT2 mux port: SAI4_RX_DATA of instance: SAI4
0011 - Select mux mode: ALT3 mux port: LPUART12_TXD of instance: LPUART12
0100 - Select mux mode: ALT4 mux port: LPSPI6_PCS3 of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO06 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: FLEXCAN3_TX of instance: FLEXCAN3
0111 - Select mux mode: ALT7 mux port: PIT2_TRIGGER3 of instance: PIT2
1000 - Select mux mode: ALT8 mux port: LPSPI5_PCS1 of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO06 of instance: GPIO12
12.4.3.9 SW_MUX_CTL_PAD_GPIO_LPSR_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_07)
SW_MUX_CTL Register
12.4.3.9.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1Ch
PIO_LPSR_07
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12.4.3.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.9.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_LPSR_07.
0000 - Select mux mode: ALT0 mux port: LPI2C6_SCL of instance: LPI2C6
0010 - Select mux mode: ALT2 mux port: SAI4_RX_BCLK of instance: SAI4
0011 - Select mux mode: ALT3 mux port: LPUART12_RXD of instance: LPUART12
0100 - Select mux mode: ALT4 mux port: LPSPI6_PCS2 of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO07 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: FLEXCAN3_RX of instance: FLEXCAN3
0111 - Select mux mode: ALT7 mux port: PIT2_TRIGGER2 of instance: PIT2
1000 - Select mux mode: ALT8 mux port: LPSPI5_PCS2 of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO07 of instance: GPIO12
12.4.3.10 SW_MUX_CTL_PAD_GPIO_LPSR_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_08)
SW_MUX_CTL Register
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12.4.3.10.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 20h
PIO_LPSR_08
12.4.3.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.10.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_LPSR_08.
0000 - Select mux mode: ALT0 mux port: LPUART11_TXD of instance: LPUART11
0001 - Select mux mode: ALT1 mux port: FLEXCAN3_TX of instance: FLEXCAN3
0010 - Select mux mode: ALT2 mux port: SAI4_RX_SYNC of instance: SAI4
0011 - Select mux mode: ALT3 mux port: MIC_CLK of instance: MIC
0100 - Select mux mode: ALT4 mux port: LPSPI6_PCS1 of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO08 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPI2C5_SDA of instance: LPI2C5
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Field Description
0111 - Select mux mode: ALT7 mux port: PIT2_TRIGGER1 of instance: PIT2
1000 - Select mux mode: ALT8 mux port: LPSPI5_PCS3 of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO08 of instance: GPIO12
12.4.3.11 SW_MUX_CTL_PAD_GPIO_LPSR_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_09)
SW_MUX_CTL Register
12.4.3.11.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 24h
PIO_LPSR_09
12.4.3.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
12.4.3.11.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_LPSR_09.
0000 - Select mux mode: ALT0 mux port: LPUART11_RXD of instance: LPUART11
0001 - Select mux mode: ALT1 mux port: FLEXCAN3_RX of instance: FLEXCAN3
0010 - Select mux mode: ALT2 mux port: PIT2_TRIGGER0 of instance: PIT2
0011 - Select mux mode: ALT3 mux port: MIC_BITSTREAM0 of instance: MIC
0100 - Select mux mode: ALT4 mux port: LPSPI6_PCS0 of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO09 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPI2C5_SCL of instance: LPI2C5
0111 - Select mux mode: ALT7 mux port: SAI4_TX_DATA of instance: SAI4
1010 - Select mux mode: ALT10 mux port: GPIO12_IO09 of instance: GPIO12
12.4.3.12 SW_MUX_CTL_PAD_GPIO_LPSR_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_10)
SW_MUX_CTL Register
12.4.3.12.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 28h
PIO_LPSR_10
12.4.3.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.3.12.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_LPSR_10.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX
0001 - Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11
0010 - Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6
0011 - Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC
0100 - Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO10 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5
0111 - Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4
1000 - Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12
1010 - Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12
12.4.3.13 SW_MUX_CTL_PAD_GPIO_LPSR_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_11)
SW_MUX_CTL Register
12.4.3.13.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 2Ch
PIO_LPSR_11
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12.4.3.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.13.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_LPSR_11.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_TDO of instance: JTAG_MUX
0001 - Select mux mode: ALT1 mux port: LPUART11_RTS_B of instance: LPUART11
0010 - Select mux mode: ALT2 mux port: LPI2C6_SCL of instance: LPI2C6
0011 - Select mux mode: ALT3 mux port: MIC_BITSTREAM2 of instance: MIC
0100 - Select mux mode: ALT4 mux port: LPSPI6_SOUT of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO11 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPI2C5_SDAS of instance: LPI2C5
0111 - Select mux mode: ALT7 mux port: ARM_TRACE_SWO of instance: ARM
1000 - Select mux mode: ALT8 mux port: LPUART12_RXD of instance: LPUART12
1010 - Select mux mode: ALT10 mux port: GPIO12_IO11 of instance: GPIO12
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12.4.3.14 SW_MUX_CTL_PAD_GPIO_LPSR_12 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_12)
SW_MUX_CTL Register
12.4.3.14.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 30h
PIO_LPSR_12
12.4.3.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.14.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_12
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_LPSR_12.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_TDI of instance: JTAG_MUX
0001 - Select mux mode: ALT1 mux port: PIT2_TRIGGER0 of instance: PIT2
0011 - Select mux mode: ALT3 mux port: MIC_BITSTREAM3 of instance: MIC
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Field Description
0100 - Select mux mode: ALT4 mux port: LPSPI6_SIN of instance: LPSPI6
0101 - Select mux mode: ALT5 mux port: GPIO6_IO12 of instance: GPIO6
0110 - Select mux mode: ALT6 mux port: LPI2C5_HREQ of instance: LPI2C5
0111 - Select mux mode: ALT7 mux port: SAI4_TX_BCLK of instance: SAI4
1000 - Select mux mode: ALT8 mux port: LPSPI5_SCK of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO12 of instance: GPIO12
12.4.3.15 SW_MUX_CTL_PAD_GPIO_LPSR_13 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_13)
SW_MUX_CTL Register
12.4.3.15.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 34h
PIO_LPSR_13
12.4.3.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.15.3 Fields
Field Description
31-5 -
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_13
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_LPSR_13.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: JTAG_MUX
0001 - Select mux mode: ALT1 mux port: MIC_BITSTREAM1 of instance: MIC
0010 - Select mux mode: ALT2 mux port: PIT2_TRIGGER1 of instance: PIT2
0101 - Select mux mode: ALT5 mux port: GPIO6_IO13 of instance: GPIO6
0111 - Select mux mode: ALT7 mux port: SAI4_RX_DATA of instance: SAI4
1000 - Select mux mode: ALT8 mux port: LPSPI5_PCS0 of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO13 of instance: GPIO12
12.4.3.16 SW_MUX_CTL_PAD_GPIO_LPSR_14 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_14)
SW_MUX_CTL Register
12.4.3.16.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 38h
PIO_LPSR_14
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12.4.3.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.16.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_14
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_LPSR_14.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: JTAG_MUX/SWD_CLK
0001 - Select mux mode: ALT1 mux port: MIC_BITSTREAM2 of instance: MIC
0010 - Select mux mode: ALT2 mux port: PIT2_TRIGGER2 of instance: PIT2
0101 - Select mux mode: ALT5 mux port: GPIO6_IO14 of instance: GPIO6
0111 - Select mux mode: ALT7 mux port: SAI4_RX_BCLK of instance: SAI4
1000 - Select mux mode: ALT8 mux port: LPSPI5_SOUT of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO14 of instance: GPIO12
12.4.3.17 SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_LPSR_15)
SW_MUX_CTL Register
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12.4.3.17.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 3Ch
PIO_LPSR_15
12.4.3.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.17.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_LPSR_15
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_LPSR_15.
0000 - Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: JTAG_MUX/SWD_DIO
0001 - Select mux mode: ALT1 mux port: MIC_BITSTREAM3 of instance: MIC
0010 - Select mux mode: ALT2 mux port: PIT2_TRIGGER3 of instance: PIT2
0101 - Select mux mode: ALT5 mux port: GPIO6_IO15 of instance: GPIO6
0111 - Select mux mode: ALT7 mux port: SAI4_RX_SYNC of instance: SAI4
1000 - Select mux mode: ALT8 mux port: LPSPI5_SIN of instance: LPSPI5
1010 - Select mux mode: ALT10 mux port: GPIO12_IO15 of instance: GPIO12
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12.4.3.18 SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_00)
SW_PAD_CTL Register
12.4.3.18.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 40h
PIO_LPSR_00
12.4.3.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.18.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP
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Field Description
These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_00
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_LPSR_00
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_00
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_00
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_00
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.19 SW_PAD_CTL_PAD_GPIO_LPSR_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_01)
SW_PAD_CTL Register
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NXP Semiconductors 561
Memory Map and register definition
12.4.3.19.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 44h
PIO_LPSR_01
12.4.3.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.19.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
Table continues on the next page...
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562 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_01
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_LPSR_01
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_01
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_01
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_01
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.20 SW_PAD_CTL_PAD_GPIO_LPSR_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_02)
SW_PAD_CTL Register
12.4.3.20.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 48h
PIO_LPSR_02
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Memory Map and register definition
12.4.3.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.20.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_02
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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564 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_02
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_02
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_02
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_02
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.21 SW_PAD_CTL_PAD_GPIO_LPSR_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_03)
SW_PAD_CTL Register
12.4.3.21.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 4Ch
PIO_LPSR_03
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NXP Semiconductors 565
Memory Map and register definition
12.4.3.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.21.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_03
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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566 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_03
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_03
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_03
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_03
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.22 SW_PAD_CTL_PAD_GPIO_LPSR_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_04)
SW_PAD_CTL Register
12.4.3.22.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 50h
PIO_LPSR_04
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Memory Map and register definition
12.4.3.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.22.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_04
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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568 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_04
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_04
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_04
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_04
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.23 SW_PAD_CTL_PAD_GPIO_LPSR_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_05)
SW_PAD_CTL Register
12.4.3.23.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 54h
PIO_LPSR_05
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NXP Semiconductors 569
Memory Map and register definition
12.4.3.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.23.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_05
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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570 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_05
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_05
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_05
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_05
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.24 SW_PAD_CTL_PAD_GPIO_LPSR_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_06)
SW_PAD_CTL Register
12.4.3.24.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 58h
PIO_LPSR_06
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Memory Map and register definition
12.4.3.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.24.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_06
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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572 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_06
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_06
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_06
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_06
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.25 SW_PAD_CTL_PAD_GPIO_LPSR_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_07)
SW_PAD_CTL Register
12.4.3.25.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 5Ch
PIO_LPSR_07
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NXP Semiconductors 573
Memory Map and register definition
12.4.3.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.25.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_07
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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574 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_07
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_07
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_07
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_07
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.26 SW_PAD_CTL_PAD_GPIO_LPSR_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_08)
SW_PAD_CTL Register
12.4.3.26.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 60h
PIO_LPSR_08
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NXP Semiconductors 575
Memory Map and register definition
12.4.3.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.26.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_08
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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576 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_08
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_08
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_08
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_08
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.27 SW_PAD_CTL_PAD_GPIO_LPSR_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_09)
SW_PAD_CTL Register
12.4.3.27.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 64h
PIO_LPSR_09
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NXP Semiconductors 577
Memory Map and register definition
12.4.3.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.27.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_09
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
578 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_09
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_09
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_09
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_09
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.28 SW_PAD_CTL_PAD_GPIO_LPSR_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_10)
SW_PAD_CTL Register
12.4.3.28.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 68h
PIO_LPSR_10
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Memory Map and register definition
12.4.3.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.3.28.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_10
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
580 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_10
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_10
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_10
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_10
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.29 SW_PAD_CTL_PAD_GPIO_LPSR_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_11)
SW_PAD_CTL Register
12.4.3.29.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 6Ch
PIO_LPSR_11
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NXP Semiconductors 581
Memory Map and register definition
12.4.3.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.29.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_11
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_11
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_11
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_11
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_11
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.30 SW_PAD_CTL_PAD_GPIO_LPSR_12 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_12)
SW_PAD_CTL Register
12.4.3.30.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 70h
PIO_LPSR_12
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Memory Map and register definition
12.4.3.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.3.30.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_12
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_12
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_12
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_12
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_12
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.31 SW_PAD_CTL_PAD_GPIO_LPSR_13 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_13)
SW_PAD_CTL Register
12.4.3.31.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 74h
PIO_LPSR_13
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Memory Map and register definition
12.4.3.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.3.31.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_13
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_13
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_13
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_13
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_13
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.32 SW_PAD_CTL_PAD_GPIO_LPSR_14 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_14)
SW_PAD_CTL Register
12.4.3.32.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 78h
PIO_LPSR_14
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12.4.3.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.3.32.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_14
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_14
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_14
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_14
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_14
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.33 SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_LPSR_15)
SW_PAD_CTL Register
12.4.3.33.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 7Ch
PIO_LPSR_15
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12.4.3.33.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODE_LPS
Reserved
Reserved
SR
DS
PU
PU
W
E
E
S
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.3.33.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-6 -
— Reserved
5 Open Drain LPSR Field
ODE_LPSR Select one out of next values for pad: GPIO_LPSR_15
0 - Disabled
1 - Enabled
4 Reserved
—
3 Pull Up / Down Config. Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PUS Select one out of next values for pad: GPIO_LPSR_15
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_LPSR_15
0 - Pull Disable
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_LPSR_15
0 - normal driver
1 - high driver
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_LPSR_15
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.3.34 CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register
(CAN3_IPP_IND_CANRX_SELECT_INPUT)
DAISY Register
12.4.3.34.1 Offset
Register Offset
CAN3_IPP_IND_CAN 80h
RX_SELECT_INPUT
12.4.3.34.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.3.34.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: can3, In Pin: ipp_ind_canrx
00 - Selecting Pad: GPIO_LPSR_01 for Mode: ALT0
01 - Selecting Pad: GPIO_LPSR_07 for Mode: ALT6
10 - Selecting Pad: GPIO_LPSR_09 for Mode: ALT1
12.4.3.35 LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY
Register (LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT)
DAISY Register
12.4.3.35.1 Offset
Register Offset
LPI2C5_IPP_IND_LPI2C 84h
_SCL_SELECT_INPUT
12.4.3.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.3.35.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c5, In Pin: ipp_ind_lpi2c_scl
0 - Selecting Pad: GPIO_LPSR_05 for Mode: ALT0
1 - Selecting Pad: GPIO_LPSR_09 for Mode: ALT6
12.4.3.36 LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY
Register (LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT)
DAISY Register
12.4.3.36.1 Offset
Register Offset
LPI2C5_IPP_IND_LPI2C 88h
_SDA_SELECT_INPUT
12.4.3.36.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.36.3 Fields
Field Description
31-1 -
Table continues on the next page...
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Field Description
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c5, In Pin: ipp_ind_lpi2c_sda
0 - Selecting Pad: GPIO_LPSR_04 for Mode: ALT0
1 - Selecting Pad: GPIO_LPSR_08 for Mode: ALT6
12.4.3.37 LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT DAISY
Register (LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT)
DAISY Register
12.4.3.37.1 Offset
Register Offset
LPI2C6_IPP_IND_LPI2C 8Ch
_SCL_SELECT_INPUT
12.4.3.37.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.37.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
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Field Description
DAISY Instance: lpi2c6, In Pin: ipp_ind_lpi2c_scl
0 - Selecting Pad: GPIO_LPSR_07 for Mode: ALT0
1 - Selecting Pad: GPIO_LPSR_11 for Mode: ALT2
12.4.3.38 LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT DAISY
Register (LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT)
DAISY Register
12.4.3.38.1 Offset
Register Offset
LPI2C6_IPP_IND_LPI2C 90h
_SDA_SELECT_INPUT
12.4.3.38.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.38.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c6, In Pin: ipp_ind_lpi2c_sda
0 - Selecting Pad: GPIO_LPSR_06 for Mode: ALT0
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Field Description
1 - Selecting Pad: GPIO_LPSR_10 for Mode: ALT2
12.4.3.39 LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 DAISY
Register (LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0)
DAISY Register
12.4.3.39.1 Offset
Register Offset
LPSPI5_IPP_IND_LPSPI 94h
_PCS_SELECT_INPUT_
0
12.4.3.39.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.39.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi5, In Pin: ipp_ind_lpspi_pcs[0]
0 - Selecting Pad: GPIO_LPSR_03 for Mode: ALT1
1 - Selecting Pad: GPIO_LPSR_13 for Mode: ALT8
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12.4.3.40 LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT DAISY
Register (LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT)
DAISY Register
12.4.3.40.1 Offset
Register Offset
LPSPI5_IPP_IND_LPSPI 98h
_SCK_SELECT_INPUT
12.4.3.40.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.40.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi5, In Pin: ipp_ind_lpspi_sck
0 - Selecting Pad: GPIO_LPSR_02 for Mode: ALT1
1 - Selecting Pad: GPIO_LPSR_12 for Mode: ALT8
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12.4.3.41 LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT DAISY
Register (LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT)
DAISY Register
12.4.3.41.1 Offset
Register Offset
LPSPI5_IPP_IND_LPSPI 9Ch
_SDI_SELECT_INPUT
12.4.3.41.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.41.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi5, In Pin: ipp_ind_lpspi_sdi
0 - Selecting Pad: GPIO_LPSR_05 for Mode: ALT1
1 - Selecting Pad: GPIO_LPSR_15 for Mode: ALT8
12.4.3.42 LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT DAISY
Register (LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT)
DAISY Register
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12.4.3.42.1 Offset
Register Offset
LPSPI5_IPP_IND_LPSPI A0h
_SDO_SELECT_INPUT
12.4.3.42.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.42.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi5, In Pin: ipp_ind_lpspi_sdo
0 - Selecting Pad: GPIO_LPSR_04 for Mode: ALT1
1 - Selecting Pad: GPIO_LPSR_14 for Mode: ALT8
12.4.3.43 LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY
Register (LPUART11_IPP_IND_LPUART_RXD_SELECT_I
NPUT)
DAISY Register
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12.4.3.43.1 Offset
Register Offset
LPUART11_IPP_IND_ A4h
LPUART_RXD_SELE
CT_INPUT
12.4.3.43.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.43.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart11, In Pin: ipp_ind_lpuart_rxd
0 - Selecting Pad: GPIO_LPSR_05 for Mode: ALT6
1 - Selecting Pad: GPIO_LPSR_09 for Mode: ALT0
12.4.3.44 LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY
Register (LPUART11_IPP_IND_LPUART_TXD_SELECT_I
NPUT)
DAISY Register
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12.4.3.44.1 Offset
Register Offset
LPUART11_IPP_IND_ A8h
LPUART_TXD_SELE
CT_INPUT
12.4.3.44.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.44.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart11, In Pin: ipp_ind_lpuart_txd
0 - Selecting Pad: GPIO_LPSR_04 for Mode: ALT6
1 - Selecting Pad: GPIO_LPSR_08 for Mode: ALT0
12.4.3.45 LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT DAISY
Register (LPUART12_IPP_IND_LPUART_RXD_SELECT_I
NPUT)
DAISY Register
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12.4.3.45.1 Offset
Register Offset
LPUART12_IPP_IND_ ACh
LPUART_RXD_SELE
CT_INPUT
12.4.3.45.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.45.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart12, In Pin: ipp_ind_lpuart_rxd
00 - Selecting Pad: GPIO_LPSR_01 for Mode: ALT6
01 - Selecting Pad: GPIO_LPSR_07 for Mode: ALT3
10 - Selecting Pad: GPIO_LPSR_11 for Mode: ALT8
12.4.3.46 LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT DAISY
Register (LPUART12_IPP_IND_LPUART_TXD_SELECT_I
NPUT)
DAISY Register
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12.4.3.46.1 Offset
Register Offset
LPUART12_IPP_IND_ B0h
LPUART_TXD_SELE
CT_INPUT
12.4.3.46.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.46.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart12, In Pin: ipp_ind_lpuart_txd
00 - Selecting Pad: GPIO_LPSR_00 for Mode: ALT6
01 - Selecting Pad: GPIO_LPSR_06 for Mode: ALT3
10 - Selecting Pad: GPIO_LPSR_10 for Mode: ALT8
12.4.3.47 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0
DAISY Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SE
LECT_INPUT_0)
DAISY Register
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12.4.3.47.1 Offset
Register Offset
MIC_IPP_IND_MIC_ B4h
PDM_BITSTREAM_SE
LECT_INPUT_0
12.4.3.47.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.47.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: mic, In Pin: ipp_ind_mic_pdm_bitstream[0]
0 - Selecting Pad: GPIO_LPSR_01 for Mode: ALT1
1 - Selecting Pad: GPIO_LPSR_09 for Mode: ALT3
12.4.3.48 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1
DAISY Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SE
LECT_INPUT_1)
DAISY Register
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12.4.3.48.1 Offset
Register Offset
MIC_IPP_IND_MIC_ B8h
PDM_BITSTREAM_SE
LECT_INPUT_1
12.4.3.48.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.48.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: mic, In Pin: ipp_ind_mic_pdm_bitstream[1]
0 - Selecting Pad: GPIO_LPSR_10 for Mode: ALT3
1 - Selecting Pad: GPIO_LPSR_13 for Mode: ALT1
12.4.3.49 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2
DAISY Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SE
LECT_INPUT_2)
DAISY Register
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12.4.3.49.1 Offset
Register Offset
MIC_IPP_IND_MIC_ BCh
PDM_BITSTREAM_SE
LECT_INPUT_2
12.4.3.49.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.49.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: mic, In Pin: ipp_ind_mic_pdm_bitstream[2]
0 - Selecting Pad: GPIO_LPSR_11 for Mode: ALT3
1 - Selecting Pad: GPIO_LPSR_14 for Mode: ALT1
12.4.3.50 MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3
DAISY Register (MIC_IPP_IND_MIC_PDM_BITSTREAM_SE
LECT_INPUT_3)
DAISY Register
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12.4.3.50.1 Offset
Register Offset
MIC_IPP_IND_MIC_ C0h
PDM_BITSTREAM_SE
LECT_INPUT_3
12.4.3.50.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.50.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: mic, In Pin: ipp_ind_mic_pdm_bitstream[3]
0 - Selecting Pad: GPIO_LPSR_12 for Mode: ALT3
1 - Selecting Pad: GPIO_LPSR_15 for Mode: ALT1
12.4.3.51 NMI_GLUE_IPP_IND_NMI_SELECT_INPUT DAISY Register
(NMI_GLUE_IPP_IND_NMI_SELECT_INPUT)
DAISY Register
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12.4.3.51.1 Offset
Register Offset
NMI_GLUE_IPP_IND_ C4h
NMI_SELECT_INPUT
12.4.3.51.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.51.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: nmi_glue, In Pin: ipp_ind_nmi
0 - Selecting Pad: GPIO_LPSR_05 for Mode: ALT7
1 - Selecting Pad: WAKEUP_DIG for Mode: ALT7
12.4.3.52 SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register
(SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT)
DAISY Register
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12.4.3.52.1 Offset
Register Offset
SAI4_IPG_CLK_SAI_ C8h
MCLK_SELECT_INPUT
12.4.3.52.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.52.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipg_clk_sai_mclk
0 - Selecting Pad: GPIO_LPSR_00 for Mode: ALT7
1 - Selecting Pad: GPIO_LPSR_05 for Mode: ALT2
12.4.3.53 SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY
Register (SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT)
DAISY Register
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12.4.3.53.1 Offset
Register Offset
SAI4_IPP_IND_SAI_RXB CCh
CLK_SELECT_INPUT
12.4.3.53.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.53.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipp_ind_sai_rxbclk
0 - Selecting Pad: GPIO_LPSR_07 for Mode: ALT2
1 - Selecting Pad: GPIO_LPSR_14 for Mode: ALT7
12.4.3.54 SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY
Register (SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0)
DAISY Register
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12.4.3.54.1 Offset
Register Offset
SAI4_IPP_IND_SAI_RXD D0h
ATA_SELECT_INPUT_0
12.4.3.54.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.54.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipp_ind_sai_rxdata[0]
0 - Selecting Pad: GPIO_LPSR_06 for Mode: ALT2
1 - Selecting Pad: GPIO_LPSR_13 for Mode: ALT7
12.4.3.55 SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY
Register (SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT)
DAISY Register
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12.4.3.55.1 Offset
Register Offset
SAI4_IPP_IND_SAI_RXS D4h
YNC_SELECT_INPUT
12.4.3.55.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.55.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipp_ind_sai_rxsync
0 - Selecting Pad: GPIO_LPSR_08 for Mode: ALT2
1 - Selecting Pad: GPIO_LPSR_15 for Mode: ALT7
12.4.3.56 SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY
Register (SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT)
DAISY Register
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12.4.3.56.1 Offset
Register Offset
SAI4_IPP_IND_SAI_TXB D8h
CLK_SELECT_INPUT
12.4.3.56.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.56.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipp_ind_sai_txbclk
0 - Selecting Pad: GPIO_LPSR_04 for Mode: ALT2
1 - Selecting Pad: GPIO_LPSR_12 for Mode: ALT7
12.4.3.57 SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY
Register (SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT)
DAISY Register
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12.4.3.57.1 Offset
Register Offset
SAI4_IPP_IND_SAI_TXS DCh
YNC_SELECT_INPUT
12.4.3.57.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.3.57.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai4, In Pin: ipp_ind_sai_txsync
0 - Selecting Pad: GPIO_LPSR_03 for Mode: ALT2
1 - Selecting Pad: GPIO_LPSR_10 for Mode: ALT7
12.4.4 IOMUXC GPR register descriptions
12.4.4.1 iomuxc_gpr memory map
IOMUXC_GPR base address: 400E_4000h
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 GPR0 General Purpose Register (GPR0) 32 RW 0000_0018
4 GPR1 General Purpose Register (GPR1) 32 RW 0000_0000
8 GPR2 General Purpose Register (GPR2) 32 RW 0000_0000
C GPR3 General Purpose Register (GPR3) 32 RW 0000_0000
10 GPR4 General Purpose Register (GPR4) 32 RW 0000_0000
14 GPR5 General Purpose Register (GPR5) 32 RW 0000_0000
18 GPR6 General Purpose Register (GPR6) 32 RW 0000_0000
1C GPR7 General Purpose Register (GPR7) 32 RW 0000_0000
20 GPR8 General Purpose Register (GPR8) 32 RW 0000_0000
24 GPR9 General Purpose Register (GPR9) 32 RW 0000_0000
28 GPR10 General Purpose Register (GPR10) 32 RW 0000_0000
2C GPR11 General Purpose Register (GPR11) 32 RW 0000_0000
30 GPR12 General Purpose Register (GPR12) 32 RW 0000_0000
34 GPR13 General Purpose Register (GPR13) 32 RW 0000_0000
38 GPR14 General Purpose Register (GPR14) 32 RW 0000_0000
3C GPR15 General Purpose Register (GPR15) 32 RW 0000_0000
40 GPR16 General Purpose Register (GPR16) 32 RW 0000_AA03
44 GPR17 General Purpose Register (GPR17) 32 RW 0000_0000
48 GPR18 General Purpose Register (GPR18) 32 RW 0000_0000
50 GPR20 General Purpose Register (GPR20) 32 RW 0000_0000
54 GPR21 General Purpose Register (GPR21) 32 RW 0000_0000
58 GPR22 General Purpose Register (GPR22) 32 RW 0000_0000
5C GPR23 General Purpose Register (GPR23) 32 RW 0000_0000
60 GPR24 General Purpose Register (GPR24) 32 RW 0000_0000
64 GPR25 General Purpose Register (GPR25) 32 RW 0000_0000
68 GPR26 General Purpose Register (GPR26) 32 RW 0000_0000
6C GPR27 General Purpose Register (GPR27) 32 RW 0000_0000
70 GPR28 General Purpose Register (GPR28) 32 RW 0000_0000
74 GPR29 General Purpose Register (GPR29) 32 RW 0000_0001
78 GPR30 General Purpose Register (GPR30) 32 RW 0000_0001
7C GPR31 General Purpose Register (GPR31) 32 RW 0000_0012
80 GPR32 General Purpose Register (GPR32) 32 RW 0000_0000
84 GPR33 General Purpose Register (GPR33) 32 RW 0000_0000
88 GPR34 General Purpose Register (GPR34) 32 RW 0000_0000
8C GPR35 General Purpose Register (GPR35) 32 RW 0000_0000
90 GPR36 General Purpose Register (GPR36) 32 RW 0000_0000
94 GPR37 General Purpose Register (GPR37) 32 RW 0000_0017
98 GPR38 General Purpose Register (GPR38) 32 RW 0000_0000
9C GPR39 General Purpose Register (GPR39) 32 RW 0000_0000
A0 GPR40 General Purpose Register (GPR40) 32 RW 0000_0000
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
A4 GPR41 General Purpose Register (GPR41) 32 RW 0000_0000
A8 GPR42 General Purpose Register (GPR42) 32 RW 0000_0000
AC GPR43 General Purpose Register (GPR43) 32 RW 0000_0000
B0 GPR44 General Purpose Register (GPR44) 32 RW 0000_0000
B4 GPR45 General Purpose Register (GPR45) 32 RW 0000_0000
B8 GPR46 General Purpose Register (GPR46) 32 RW 0000_0000
BC GPR47 General Purpose Register (GPR47) 32 RW 0000_0000
C0 GPR48 General Purpose Register (GPR48) 32 RW 0000_0000
C4 GPR49 General Purpose Register (GPR49) 32 RW 0000_0000
C8 GPR50 General Purpose Register (GPR50) 32 RW 0000_0000
CC GPR51 General Purpose Register (GPR51) 32 RW 0000_0000
D0 GPR52 General Purpose Register (GPR52) 32 RW 0000_0000
D4 GPR53 General Purpose Register (GPR53) 32 RW 0000_0000
D8 GPR54 General Purpose Register (GPR54) 32 RW 0000_0000
DC GPR55 General Purpose Register (GPR55) 32 RW 0000_0000
EC GPR59 General Purpose Register (GPR59) 32 RW 0000_0550
F8 GPR62 General Purpose Register (GPR62) 32 RW 0000_02DB
FC GPR63 General Purpose Register (GPR63) 32 RO 0000_0000
100 GPR64 General Purpose Register (GPR64) 32 RW 0000_4000
104 GPR65 General Purpose Register (GPR65) 32 RW 0000_4000
108 GPR66 General Purpose Register (GPR66) 32 RW 0000_4000
10C GPR67 General Purpose Register (GPR67) 32 RW 0000_4000
110 GPR68 General Purpose Register (GPR68) 32 RW 0000_4000
114 GPR69 General Purpose Register (GPR69) 32 RW 0000_0000
118 GPR70 General Purpose Register (GPR70) 32 RW 0000_0000
11C GPR71 General Purpose Register (GPR71) 32 RW 0000_0000
120 GPR72 General Purpose Register (GPR72) 32 RW 0000_0000
124 GPR73 General Purpose Register (GPR73) 32 RW 0000_0000
128 GPR74 General Purpose Register (GPR74) 32 RW 0000_0000
12C GPR75 General Purpose Register (GPR75) 32 RO 0000_0000
130 GPR76 General Purpose Register (GPR76) 32 RO 0000_0000
12.4.4.2 GPR0 General Purpose Register (GPR0)
GPR Register
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12.4.4.2.1 Offset
Register Offset
GPR0 0h
12.4.4.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI1_MCLK3_SEL
SAI1_MCLK2_SEL
SAI1_MCLK1_SEL
SAI1_MCLK_DIR
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0
12.4.4.2.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
Table continues on the next page...
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Memory Map and register definition
Field Description
—
15-9 Reserved
—
8 SAI1_MCLK signal direction control
SAI1_MCLK_DI 0: SAI1_MCLK is input signal
R
1: SAI1_MCLK is output signal
7-6 SAI1 MCLK3 source select
SAI1_MCLK3_S See the Audio subsystem clocking diagram in the Audio Overview Chapter for more information.
EL
00: SPDIF_CLK_ROOT
01: spdif_tx_clk2
10: spdif_srclk
11: spdif_outclock
5-3 SAI1 MCLK2 source select
SAI1_MCLK2_S See the Audio subsystem clocking diagram in the Audio Overview Chapter for more information.
EL
000 SAI1_CLK_ROOT
001: SAI2_CLK_ROOT
010: SAI3_CLK_ROOT
011: sai1_ipg_clk_sai_mclk
100: sai2_ipg_clk_sai_mclk
101: sai3_ipg_clk_sai_mclk
110: Reserved
111: Reserved
2-0 SAI1 MCLK1 source select
SAI1_MCLK1_S 000 SAI1_CLK_ROOT See the Audio subsystem clocking diagram in the Audio Overview Chapter for
EL more information.
001: SAI2_CLK_ROOT
010: SAI3_CLK_ROOT
011: sai1_ipg_clk_sai_mclk
100: sai2_ipg_clk_sai_mclk
101: sai3_ipg_clk_sai_mclk
110: Reserved
111: Reserved
12.4.4.3 GPR1 General Purpose Register (GPR1)
GPR Register
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12.4.4.3.1 Offset
Register Offset
GPR1 4h
12.4.4.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI2_MCLK3_SEL
SAI2_MCLK_DIR
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.3.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
Table continues on the next page...
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Memory Map and register definition
Field Description
—
15-9 Reserved
—
8 SAI2_MCLK signal direction control
SAI2_MCLK_DI 0: SAI2_MCLK is input signal
R
1: SAI2_MCLK is output signal
7-2 Reserved
—
1-0 SAI2 MCLK3 source select
SAI2_MCLK3_S See the Audio subsystem clocking diagram in the Audio Overview Chapter for more information.
EL
00: SPDIF_CLK_ROOT
01: spdif_tx_clk2
10: spdif_srclk
11: spdif_outclock
12.4.4.4 GPR2 General Purpose Register (GPR2)
GPR Register
12.4.4.4.1 Offset
Register Offset
GPR2 8h
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12.4.4.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI3_MCLK3_SEL
SAI4_MCLK_DIR
SAI3_MCLK_DIR
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.4.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-10 Reserved
—
9 SAI4_MCLK signal direction control
SAI4_MCLK_DI 0: SAI4_MCLK is input signal
R
1: SAI4_MCLK is output signal
Table continues on the next page...
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Memory Map and register definition
Field Description
8 SAI3_MCLK signal direction control
SAI3_MCLK_DI 0: SAI3_MCLK is input signal
R
1: SAI3_MCLK is output signal
7-2 Reserved
—
1-0 SAI3 MCLK3 source select
SAI3_MCLK3_S See the Audio subsystem clocking diagram in the Audio Overview Chapter for more information.
EL
00: SPDIF_CLK_ROOT
01: spdif_tx_clk2
10: spdif_srclk
11: spdif_outclock
12.4.4.5 GPR3 General Purpose Register (GPR3)
GPR Register
12.4.4.5.1 Offset
Register Offset
GPR3 Ch
12.4.4.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MQS_OVERSAMPLE
MQS_CLK_DIV
MQS_SW_RS
MQS_EN
Reserved
W
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.5.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-11 Reserved
—
10 Medium Quality Sound (MQS) Oversample
MQS_OVERSA Used to control the PWM oversampling rate compared with mclk.
MPLE
0: 32
1: 64
9 MQS enable
MQS_EN 0: Disable MQS
1: Enable MQS
8 MQS software reset
MQS_SW_RST 0: Exit software reset for MQS
1: Enable software reset for MQS
7-0 Divider ratio control for mclk from hmclk.
MQS_CLK_DIV mclk frequency = 1/(n+1) * hmclk frequency
00000000: mclk frequency = hmclk frequency
00000001: mclk frequency = 1/2 * hmclk frequency
00000010: mclk frequency = 1/3 * hmclk frequency
11111111: mclk frequency = 1/256 * hmclk frequency
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12.4.4.6 GPR4 General Purpose Register (GPR4)
GPR Register
12.4.4.6.1 Offset
Register Offset
GPR4 10h
12.4.4.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENET_EVENT0IN_SE
ENET_REF_CLK_DI
ENET_TX_CLK_SE
ENET_TIME_SE
Reserved
L
R
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.6.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
Table continues on the next page...
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Field Description
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-4 Reserved
—
3 ENET ENET_1588_EVENT0_IN source select
ENET_EVENT0I 0: ENET_1588_EVENT0_IN input is from pad
N_SEL
1: ENET_1588_EVENT0_IN input is from GPT2 COMPARE1 output
2 ENET master timer source select
ENET_TIME_S IEEE 1588 master counter value is used when IEEE 1588 circuitry for ENET is in slave mode.
EL
0: master counter value is from ENET1G module
1: master counter value is from ENET_QOS module
1 ENET_REF_CLK direction control
ENET_REF_CL This bitfield controls the direction of ENET_REF_CLK. ENET_REF_CLK is the 50MHz RMII clock. It
K_DIR should be set together with the corresponding IOMUXC SW_MUX_CTL_PAD_xx SION bit so that
ENET1_CLK_ROOT can provide 50MHz RMII clock to both ENET and board.
0: ENET_REF_CLK is input
1: ENET_REF_CLK is output driven by ENET1_CLK_ROOT
0 ENET TX_CLK select
ENET_TX_CLK This bit should always be set to 1 to use the 25MHz MII clock
_SEL
0: Not supported
1: ENET TX_CLK is from pad
12.4.4.7 GPR5 General Purpose Register (GPR5)
GPR Register
12.4.4.7.1 Offset
Register Offset
GPR5 14h
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12.4.4.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENET1G_EVENT0IN_SE
ENET1G_REF_CLK_DI
ENET1G_TX_CLK_SE
ENET1G_RGMII_EN
ENET1G_TIME_SE
Reserved
L
R
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.7.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-5 Reserved
—
4 ENET1G ENET_1588_EVENT0_IN source select
0: ENET_1588_EVENT0_IN input is from pad
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Field Description
ENET1G_EVEN 1 ENET_1588_EVENT0_IN input is from GPT2_COMPARE2 output
T0IN_SEL
3 ENET1G master timer source select
ENET1G_TIME IEEE 1588 master counter value is used when IEEE 1588 circuitry for ENET1G is in slave mode.
_SEL
0: master counter value is from ENET module
1: master counter value is from ENET_QOS module
2 ENET1G RGMII TX clock output enable
ENET1G_RGMII Set this bit to enable ENET1G RGMII TX clock output on TX_CLK_IO pad. It should be set in RGMII
_EN mode, and be cleared in MII mode as in MII mode TX_CLK_IO is input.
1 ENET1G_REF_CLK direction control
ENET1G_REF_ This bitfield controls the direction of ENET1G_REF_CLK. ENET1G_REF_CLK is the 50MHz RMII clock.
CLK_DIR It should be set together with the corresponding IOMUXC SW_MUX_CTL_PAD_xx SION bit so that
ENET1_CLK_ROOT can provide 50MHz RMII clock to both ENET and board.
0: ENET1G_REF_CLK is input
1: ENET1G_REF_CLK is output driven by ENET2_CLK_ROOT
0 ENET1G TX_CLK select
ENET1G_TX_C This bit should be set to 1 in MII mode to use the 25MHz TX clock. This bit should be set to 0 in RGMII
LK_SEL mode to use ENET2_CLK_ROOT as the 125MHZ TX clock.
0 ENET1G TX_CLK is driven by ENET2_CLK_ROOT
1: ENET1G TX_CLK is from pad
12.4.4.8 GPR6 General Purpose Register (GPR6)
GPR Register
12.4.4.8.1 Offset
Register Offset
GPR6 18h
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12.4.4.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENET_QOS_EVENT0IN_SE
ENET_QOS_CLKGEN_EN
ENET_QOS_REF_CLK_DI
ENET_QOS_RGMII_EN
ENET_QOS_TIME_SE
ENET_QOS_INTF_SE
Reserved
R
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.8.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-8 Reserved
—
7 ENET_QOS ENET_1588_EVENT0_IN source select
Table continues on the next page...
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Field Description
ENET_QOS_EV 0: ENET_1588_EVENT0_IN input is from pad
ENT0IN_SEL
1: ENET_1588_EVENT0_IN input is from GPT3_COMPARE1 output
6 ENET_QOS clock generator enable
ENET_QOS_CL The ENET_QOS clock generator provides ENET_QOS TX/RX clocks according to the PHY interface type
KGEN_EN and speed. Set this bit to enable the clock generator. It's required by all the three modes. In RGMII mode,
ENET_QOS_CLK_ROOT is the source of TX clock and will drive ENET_QOS TX_CLK pad given
ENET_QOS_RGMII_EN is set. In MII mode, the TX clock is input from TX_CLK. In RMII mode, the TX
clock is input from REF_CLK.
5-3 ENET_QOS PHY Interface Select
ENET_QOS_IN Selects the PHY interface of the MAC. This config is sampled only during ENET_QOS reset assertion,
TF_SEL and it is ignored after that. User can assert ENET_QOS reset via ENET_QOS software reset bit.
000: MII
001: RGMII
100: RMII
2 ENET_QOS master timer source select
ENET_QOS_TI IEEE 1588 master counter value is used when IEEE 1588 circuitry for ENET_QOS is in slave mode.
ME_SEL
0: master counter value is from ENET module
1 master counter value is from ENET_1G module
1 ENET_QOS RGMII TX clock output enable
ENET_QOS_R Set this bit to enable ENET_QOS RGMII TX clock output on TX_CLK pad. It should be set in RGMII
GMII_EN mode, and be cleared in MII mode as in MII mode TX_CLK is input.
0 ENET_QOS_REF_CLK direction control
ENET_QOS_RE This bitfield controls the direction of ENET_QOS_REF_CLK. ENET_QOS_REF_CLK is the 50MHz RMII
F_CLK_DIR clock. It should be set together with the corresponding IOMUXC SW_MUX_CTL_PAD_xx SION bit so
that ENET1_CLK_ROOT can provide 50MHz RMII clock to both ENET and board.
0: ENET_QOS_REF_CLK is input
1 ENET_QOS_REF_CLK is output driven by ENET_QOS_CLK_ROOT
12.4.4.9 GPR7 General Purpose Register (GPR7)
GPR Register
12.4.4.9.1 Offset
Register Offset
GPR7 1Ch
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12.4.4.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
GINT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.9.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 Global interrupt
GINT This is the global interrupt bit. It is connected to CM7/CM4 IRQ#53 and GPC.
0 Global interrupt request is not asserted
1: Global interrupt request is asserted.
Interrupt is issued to CM7/CM4 IRQ#53 and GPC
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12.4.4.10 GPR8 General Purpose Register (GPR8)
GPR Register
12.4.4.10.1 Offset
Register Offset
GPR8 20h
12.4.4.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDOG1_MASK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.10.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
Table continues on the next page...
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Memory Map and register definition
Field Description
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 WDOG1 timeout mask for WDOG_ANY
WDOG1_MASK WDOG_ANY pad is driven by WDOG1 timeout OR WDOG2 timeout. Set this bit will mask WDOG1
timeout from WDOG_ANY.
12.4.4.11 GPR9 General Purpose Register (GPR9)
GPR Register
12.4.4.11.1 Offset
Register Offset
GPR9 24h
12.4.4.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WDOG2_MASK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.11.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 WDOG2 timeout mask for WDOG_ANY
WDOG2_MASK WDOG_ANY pad is driven by WDOG1 timeout OR WDOG2 timeout. Set this bit will mask WDOG2
timeout from WDOG_ANY.
12.4.4.12 GPR10 General Purpose Register (GPR10)
GPR Register
12.4.4.12.1 Offset
Register Offset
GPR10 28h
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12.4.4.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.12.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.13 GPR11 General Purpose Register (GPR11)
GPR Register
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12.4.4.13.1 Offset
Register Offset
GPR11 2Ch
12.4.4.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.13.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
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12.4.4.14 GPR12 General Purpose Register (GPR12)
GPR Register
12.4.4.14.1 Offset
Register Offset
GPR12 30h
12.4.4.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QTIMER1_TMR_CNTS_FREEZE
QTIMER1_TRM3_INPUT_SEL
QTIMER1_TRM2_INPUT_SEL
QTIMER1_TRM1_INPUT_SEL
QTIMER1_TRM0_INPUT_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.14.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
Table continues on the next page...
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Field Description
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-12 Reserved
—
11 QTIMER1 TMR3 input select
QTIMER1_TRM 0: input from IOMUX;
3_INPUT_SEL
1: input from XBAR
10 QTIMER1 TMR2 input select
QTIMER1_TRM 0: input from IOMUX
2_INPUT_SEL
1: input from XBAR
9 QTIMER1 TMR1 input select
QTIMER1_TRM 0: input from IOMUX
1_INPUT_SEL
1: input from XBAR
8 QTIMER1 TMR0 input select
QTIMER1_TRM 0: input from IOMUX
0_INPUT_SEL
1: input from XBAR
7-1 Reserved
—
0 QTIMER1 timer counter freeze
QTIMER1_TMR Setting this bit resets counters and output pins of QTIMER1. It is not self-clearing.
_CNTS_FREEZ
0: Timer counter works normally
E
1 Reset counter and ouput flags
12.4.4.15 GPR13 General Purpose Register (GPR13)
GPR Register
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12.4.4.15.1 Offset
Register Offset
GPR13 34h
12.4.4.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QTIMER2_TMR_CNTS_FREEZE
QTIMER2_TRM3_INPUT_SEL
QTIMER2_TRM2_INPUT_SEL
QTIMER2_TRM1_INPUT_SEL
QTIMER2_TRM0_INPUT_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.15.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
Table continues on the next page...
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Field Description
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-12 Reserved
—
11 QTIMER2 TMR3 input select
QTIMER2_TRM 0: input from IOMUX
3_INPUT_SEL
1: input from XBAR
10 QTIMER2 TMR2 input select
QTIMER2_TRM 0: input from IOMUX
2_INPUT_SEL
1: input from XBAR
9 QTIMER2 TMR1 input select
QTIMER2_TRM 0: input from IOMUX
1_INPUT_SEL
1: input from XBAR
8 QTIMER2 TMR0 input select
QTIMER2_TRM 0: input from IOMUX
0_INPUT_SEL
1: input from XBAR
7-1 Reserved
—
0 QTIMER2 timer counter freeze
QTIMER2_TMR Setting this bit resets counters and output pins of QTIMER2. It is not self-clearing.
_CNTS_FREEZ
0: Timer counter works normally
E
1 Reset counter and ouput flags
12.4.4.16 GPR14 General Purpose Register (GPR14)
GPR Register
12.4.4.16.1 Offset
Register Offset
GPR14 38h
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12.4.4.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QTIMER3_TMR_CNTS_FREEZE
QTIMER3_TRM3_INPUT_SEL
QTIMER3_TRM2_INPUT_SEL
QTIMER3_TRM1_INPUT_SEL
QTIMER3_TRM0_INPUT_SEL
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.16.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-12 Reserved
—
Table continues on the next page...
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Field Description
11 QTIMER3 TMR3 input select
QTIMER3_TRM 0: input from IOMUX
3_INPUT_SEL
1: input from XBAR
10 QTIMER3 TMR2 input select
QTIMER3_TRM 0: input from IOMUX
2_INPUT_SEL
1: input from XBAR
9 QTIMER3 TMR1 input select
QTIMER3_TRM 0: input from IOMUX
1_INPUT_SEL
1: input from XBAR
8 QTIMER3 TMR0 input select
QTIMER3_TRM 0: input from IOMUX
0_INPUT_SEL
1: input from XBAR
7-1 Reserved
—
0 QTIMER3 timer counter freeze
QTIMER3_TMR Setting this bit resets counters and output pins of QTIMER3. It is not self-clearing.
_CNTS_FREEZ
0: Timer counter works normally
E
1 Reset counter and ouput flags
12.4.4.17 GPR15 General Purpose Register (GPR15)
GPR Register
12.4.4.17.1 Offset
Register Offset
GPR15 3Ch
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Memory Map and register definition
12.4.4.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QTIMER4_TMR_CNTS_FREEZE
QTIMER4_TRM3_INPUT_SEL
QTIMER4_TRM2_INPUT_SEL
QTIMER4_TRM1_INPUT_SEL
QTIMER4_TRM0_INPUT_SEL
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.17.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-12 Reserved
—
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
11 QTIMER4 TMR3 input select
QTIMER4_TRM 0: input from IOMUX
3_INPUT_SEL
1: input from XBAR
10 QTIMER4 TMR2 input select
QTIMER4_TRM 0: input from IOMUX
2_INPUT_SEL
1: input from XBAR
9 QTIMER4 TMR1 input select
QTIMER4_TRM 0: input from IOMUX
1_INPUT_SEL
1: input from XBAR
8 QTIMER4 TMR0 input select
QTIMER4_TRM 0: input from IOMUX
0_INPUT_SEL
1: input from XBAR
7-1 Reserved
—
0 QTIMER4 timer counter freeze
QTIMER4_TMR Setting this bit resets counters and output pins of QTIMER1. It is not self-clearing.
_CNTS_FREEZ
0: Timer counter works normally
E
1 Reset counter and ouput flags
12.4.4.18 GPR16 General Purpose Register (GPR16)
GPR Register
12.4.4.18.1 Offset
Register Offset
GPR16 40h
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Memory Map and register definition
12.4.4.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEXRAM_BANK_CFG_SEL
CM7_FORCE_HCLK_EN
M7_GPC_SLEEP_SE
Reserved
Reserved
Reserved
Reserved
W
L
Reset 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1
12.4.4.18.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-8 Reserved
—
7-6 Reserved
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
—
5 CM7 sleep request selection
M7_GPC_SLEE This bit controls which kind of CM7 sleep request is sent to GPC to start sleep sequence.
P_SEL
0: CM7 SLEEPDEEP is sent to GPC
1: CM7 SLEEPING is sent to GPC
4 Reserved
—
3 CM7 platform AHB clock enable
CM7_FORCE_H This bitfield determines whether or not the AHB clock is running when CM7 is sleeping. If the AHB clock
CLK_EN is not enabled with this bit, the TCM is not accessible.
0: AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible
1 AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible
2 FlexRAM bank config source select
FLEXRAM_BAN 0: use fuse value to configure
K_CFG_SEL
1: use FLEXRAM_BANK_CFG to configure
1-0 Reserved
—
12.4.4.19 GPR17 General Purpose Register (GPR17)
GPR Register
12.4.4.19.1 Offset
Register Offset
GPR17 44h
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Memory Map and register definition
12.4.4.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FLEXRAM_BANK_CFG_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.19.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 FlexRAM bank config value
FLEXRAM_BAN GPR_FLEXRAM_BANK_CFG[2n+1 : 2n], where n = 0, 1, ..., 7
K_CFG_LOW
00: RAM bank n is not used
01: RAM bank n is OCRAM
10: RAM bank n is DTCM
11: RAM bank n is ITCM
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12.4.4.20 GPR18 General Purpose Register (GPR18)
GPR Register
12.4.4.20.1 Offset
Register Offset
GPR18 48h
12.4.4.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FLEXRAM_BANK_CFG_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.20.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
Table continues on the next page...
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Memory Map and register definition
Field Description
27-16 Reserved
—
15-0 FlexRAM bank config value
FLEXRAM_BAN GPR_FLEXRAM_BANK_CFG[2n+1 : 2n], where n = 8, 9, ..., 15
K_CFG_HIGH
00: RAM bank n is not used
01: RAM bank n is OCRAM
10: RAM bank n is DTCM
11: RAM bank n is ITCM
12.4.4.21 GPR20 General Purpose Register (GPR20)
GPR Register
12.4.4.21.1 Offset
Register Offset
GPR20 50h
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12.4.4.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOMUXC_XBAR_DIR_SEL_31
IOMUXC_XBAR_DIR_SEL_30
IOMUXC_XBAR_DIR_SEL_29
IOMUXC_XBAR_DIR_SEL_28
IOMUXC_XBAR_DIR_SEL_27
IOMUXC_XBAR_DIR_SEL_26
IOMUXC_XBAR_DIR_SEL_25
IOMUXC_XBAR_DIR_SEL_24
IOMUXC_XBAR_DIR_SEL_23
IOMUXC_XBAR_DIR_SEL_22
IOMUXC_XBAR_DIR_SEL_21
IOMUXC_XBAR_DIR_SEL_20
DWP_LOCK
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IOMUXC_XBAR_DIR_SEL_19
IOMUXC_XBAR_DIR_SEL_18
IOMUXC_XBAR_DIR_SEL_17
IOMUXC_XBAR_DIR_SEL_16
IOMUXC_XBAR_DIR_SEL_15
IOMUXC_XBAR_DIR_SEL_14
IOMUXC_XBAR_DIR_SEL_13
IOMUXC_XBAR_DIR_SEL_12
IOMUXC_XBAR_DIR_SEL_11
IOMUXC_XBAR_DIR_SEL_10
IOMUXC_XBAR_DIR_SEL_9
IOMUXC_XBAR_DIR_SEL_8
IOMUXC_XBAR_DIR_SEL_7
IOMUXC_XBAR_DIR_SEL_6
IOMUXC_XBAR_DIR_SEL_5
IOMUXC_XBAR_DIR_SEL_4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.21.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
Table continues on the next page...
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Memory Map and register definition
Field Description
27 IOMUXC XBAR_INOUT31 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_31
1: XBAR_INOUT as output
26 IOMUXC XBAR_INOUT30 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_30
1: XBAR_INOUT as output
25 IOMUXC XBAR_INOUT29 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_29
1: XBAR_INOUT as output
24 IOMUXC XBAR_INOUT28 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_28
1: XBAR_INOUT as output
23 IOMUXC XBAR_INOUT27 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_27
1: XBAR_INOUT as output
22 IOMUXC XBAR_INOUT26 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_26
1: XBAR_INOUT as output
21 IOMUXC XBAR_INOUT25 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_25
1: XBAR_INOUT as output
20 IOMUXC XBAR_INOUT24 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_24
1: XBAR_INOUT as output
19 IOMUXC XBAR_INOUT23 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_23
1: XBAR_INOUT as output
18 IOMUXC XBAR_INOUT22 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_22
1: XBAR_INOUT as output
17 IOMUXC XBAR_INOUT21 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_21
1: XBAR_INOUT as output
16 IOMUXC XBAR_INOUT20 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_20
1: XBAR_INOUT as output
15 IOMUXC XBAR_INOUT19 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_19
1: XBAR_INOUT as output
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
14 IOMUXC XBAR_INOUT18 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_18
1: XBAR_INOUT as output
13 IOMUXC XBAR_INOUT17 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_17
1: XBAR_INOUT as output
12 IOMUXC XBAR_INOUT16 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_16
1: XBAR_INOUT as output
11 IOMUXC XBAR_INOUT15 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_15
1: XBAR_INOUT as output
10 IOMUXC XBAR_INOUT14 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_14
1: XBAR_INOUT as output
9 IOMUXC XBAR_INOUT13 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_13
1: XBAR_INOUT as output
8 IOMUXC XBAR_INOUT12 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_12
1: XBAR_INOUT as output
7 IOMUXC XBAR_INOUT11 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_11
1: XBAR_INOUT as output
6 IOMUXC XBAR_INOUT10 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_10
1: XBAR_INOUT as output
5 IOMUXC XBAR_INOUT9 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_9
1: XBAR_INOUT as output
4 IOMUXC XBAR_INOUT8 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_8
1: XBAR_INOUT as output
3 IOMUXC XBAR_INOUT7 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_7
1: XBAR_INOUT as output
2 IOMUXC XBAR_INOUT6 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_6
1: XBAR_INOUT as output
Table continues on the next page...
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Memory Map and register definition
Field Description
1 IOMUXC XBAR_INOUT5 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_5
1: XBAR_INOUT as output
0 IOMUXC XBAR_INOUT4 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_4
1: XBAR_INOUT as output
12.4.4.22 GPR21 General Purpose Register (GPR21)
GPR Register
12.4.4.22.1 Offset
Register Offset
GPR21 54h
12.4.4.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IOMUXC_XBAR_DIR_SEL_42
IOMUXC_XBAR_DIR_SEL_41
IOMUXC_XBAR_DIR_SEL_40
IOMUXC_XBAR_DIR_SEL_39
IOMUXC_XBAR_DIR_SEL_38
IOMUXC_XBAR_DIR_SEL_37
IOMUXC_XBAR_DIR_SEL_36
IOMUXC_XBAR_DIR_SEL_35
IOMUXC_XBAR_DIR_SEL_34
IOMUXC_XBAR_DIR_SEL_33
IOMUXC_XBAR_DIR_SEL_32
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.22.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-11 Reserved
—
10 IOMUXC XBAR_INOUT42 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_42
1: XBAR_INOUT as output
9 IOMUXC XBAR_INOUT41 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_41
1: XBAR_INOUT as output
8 IOMUXC XBAR_INOUT40 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_40
1: XBAR_INOUT as output
7 IOMUXC XBAR_INOUT39 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_39
1: XBAR_INOUT as output
6 IOMUXC XBAR_INOUT38 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_38
1: XBAR_INOUT as output
5 IOMUXC XBAR_INOUT37 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_37
1: XBAR_INOUT as output
4 IOMUXC XBAR_INOUT36 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_36
1: XBAR_INOUT as output
Table continues on the next page...
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Memory Map and register definition
Field Description
3 IOMUXC XBAR_INOUT35 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_35
1: XBAR_INOUT as output
2 IOMUXC XBAR_INOUT34 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_34
1: XBAR_INOUT as output
1 IOMUXC XBAR_INOUT33 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_33
1: XBAR_INOUT as output
0 IOMUXC XBAR_INOUT32 function direction select
IOMUXC_XBAR 0: XBAR_INOUT as input
_DIR_SEL_32
1: XBAR_INOUT as output
12.4.4.23 GPR22 General Purpose Register (GPR22)
GPR Register
12.4.4.23.1 Offset
Register Offset
GPR22 58h
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12.4.4.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT1
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.23.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 GPT1 1 MHz clock source select
REF_1M_CLK_ 0: GPT1 ipg_clk_highfreq driven by GPT1_CLK_ROOT
GPT1
1: GPT1 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
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12.4.4.24 GPR23 General Purpose Register (GPR23)
GPR Register
12.4.4.24.1 Offset
Register Offset
GPR23 5Ch
12.4.4.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT2
GPT2_CAPIN2_SEL
GPT2_CAPIN1_SEL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.24.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-3 Reserved
—
2 GPT2 input capture channel 2 source select
GPT2_CAPIN2_ 0: source from pad
SEL
1: source from ENET1G_1588_EVENT1_OUT
1 GPT2 input capture channel 1 source select
GPT2_CAPIN1_ 0 source from pad 1 source from ENET_1588_EVENT1_OUT
SEL
0 GPT2 1 MHz clock source select
REF_1M_CLK_ 0: GPT2 ipg_clk_highfreq driven by GPT2_CLK_ROOT
GPT2
1: GPT2 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
12.4.4.25 GPR24 General Purpose Register (GPR24)
GPR Register
12.4.4.25.1 Offset
Register Offset
GPR24 60h
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12.4.4.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT3
GPT3_CAPIN1_SEL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.25.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-2 Reserved
—
1 GPT3 input capture channel 1 source select
GPT3_CAPIN1_ 0: source from pad
SEL
1 source from ENET_QOS ptp_pps_o[1]
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 GPT3 1 MHz clock source select
REF_1M_CLK_ 0: GPT3 ipg_clk_highfreq driven by GPT3_CLK_ROOT
GPT3
1: GPT3 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
12.4.4.26 GPR25 General Purpose Register (GPR25)
GPR Register
12.4.4.26.1 Offset
Register Offset
GPR25 64h
12.4.4.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT4
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.26.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
Table continues on the next page...
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Memory Map and register definition
Field Description
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 GPT4 1 MHz clock source select
REF_1M_CLK_ 0: GPT4 ipg_clk_highfreq driven by GPT4_CLK_ROOT
GPT4
1: GPT4 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
12.4.4.27 GPR26 General Purpose Register (GPR26)
GPR Register
12.4.4.27.1 Offset
Register Offset
GPR26 68h
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12.4.4.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT5
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.27.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 GPT5 1 MHz clock source select
REF_1M_CLK_ 0: GPT5 ipg_clk_highfreq driven by GPT5_CLK_ROOT
GPT5
1: GPT5 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
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12.4.4.28 GPR27 General Purpose Register (GPR27)
GPR Register
12.4.4.28.1 Offset
Register Offset
GPR27 6Ch
12.4.4.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REF_1M_CLK_GPT6
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.28.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
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Field Description
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 GPT6 1 MHz clock source select
REF_1M_CLK_ 0: GPT6 ipg_clk_highfreq driven by GPT6_CLK_ROOT
GPT6
1: GPT6 ipg_clk_highfreq driven by 1 MHz clock derived from RCOSC_400M
12.4.4.29 GPR28 General Purpose Register (GPR28)
GPR Register
12.4.4.29.1 Offset
Register Offset
GPR28 70h
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12.4.4.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWCACHE_USDHC
ARCACHE_USDHC
CACHE_ENET1G
CACHE_ENET
CACHE_USB
Reserved
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.29.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-14 Reserved
—
13 USB block cacheable attribute value of AXI transactions
CACHE_USB If the current transaction is cacheable, the bus infrastructure (NIC) will reorganize the transaction to
optimize bus performance. The NIC will combine two 32-bit USB transactions into one 64-bit transaction.
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Field Description
0: Cacheable attribute is off for read/write transactions
1: Cacheable attribute is on for read/write transactions
12-8 Reserved
—
7 ENET block cacheable attribute value of AXI transactions
CACHE_ENET If the transaction is cacheable, the bus infrastructure (NIC) will reorganize the transaction to optimize bus
performance. The NIC will combine two 32-bit ENET transactions into one 64-bit transaction.
0: Cacheable attribute is off for read/write transactions
1: Cacheable attribute is on for read/write transactions
6 Reserved
—
5
CACHE_ENET1
G
4-2 Reserved
—
1 uSDHC block cacheable attribute value of AXI write transactions
AWCACHE_US If the current transaction is cacheable, the bus infrastructure (NIC) will reorganize the transaction to
DHC optimize bus performance. The NIC will combine two 32-bit uSDHC transactions into one 64-bit
transaction.
0: Cacheable attribute is off for write transactions
1: Cacheable attribute is on for write transactions
0 uSDHC block cacheable attribute value of AXI read transactions
ARCACHE_US If the current transaction is cacheable, the bus infrastructure (NIC) will reorganize the transaction to
DHC optimize bus performance. The NIC will combine two 32-bit uSDHC transactions into one 64-bit
transaction.
0: Cacheable attribute is off for read transactions
1: Cacheable attribute is on for read transactions
12.4.4.30 GPR29 General Purpose Register (GPR29)
GPR Register
12.4.4.30.1 Offset
Register Offset
GPR29 74h
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12.4.4.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBPHY1_IPG_CLK_ACTIVE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
12.4.4.30.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
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Field Description
0 USBPHY1 register access clock enable
USBPHY1_IPG Clearing this bit to 0 will stop USBPHY1 register access clock to save power.
_CLK_ACTIVE
12.4.4.31 GPR30 General Purpose Register (GPR30)
GPR Register
12.4.4.31.1 Offset
Register Offset
GPR30 78h
12.4.4.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBPHY2_IPG_CLK_ACTIVE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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12.4.4.31.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 USBPHY2 register access clock enable
USBPHY2_IPG Clearing this bit to 0 will stop USBPHY2 register access clock to save power.
_CLK_ACTIVE
12.4.4.32 GPR31 General Purpose Register (GPR31)
GPR Register.
12.4.4.32.1 Offset
Register Offset
GPR31 7Ch
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12.4.4.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMW2_WAIT_BVALID_CPL
OCRAM_M7_CLK_GATING
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
12.4.4.32.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-3 Reserved
—
2 OCRAM M7 clock gating enable
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Field Description
OCRAM_M7_C Set this bit to 1 to enable auto clock gating for OCRAM M7, which is the OCRAM of FlexRAM. When this
LK_GATING bit is high, and no access on OCRAM of FlexRAM, the OCRAM clock is gated off.
1 Reserved
—
0 OCRAM M7 RMW wait enable
RMW2_WAIT_B If this bit is set to 1, RMW will write back next data only after current write response is received. It only
VALID_CPL affects the speed of data transfer.
12.4.4.33 GPR32 General Purpose Register (GPR32)
GPR Register
12.4.4.33.1 Offset
Register Offset
GPR32 80h
12.4.4.33.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RMW1_WAIT_BVALID_CPL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.33.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 OCRAM1 RMW wait enable
RMW1_WAIT_B If this bit is set to 1, RMW will write back next data only after current write response is received. It only
VALID_CPL affects the speed of data transfer.
12.4.4.34 GPR33 General Purpose Register (GPR33)
GPR Register
12.4.4.34.1 Offset
Register Offset
GPR33 84h
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12.4.4.34.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RMW2_WAIT_BVALID_CPL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.34.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
—
0 OCRAM2 RMW wait enable
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Field Description
RMW2_WAIT_B If this bit is set to 1, RMW will write back next data only after current write response is received. It only
VALID_CPL affects the speed of data transfer.
12.4.4.35 GPR34 General Purpose Register (GPR34)
GPR Register
12.4.4.35.1 Offset
Register Offset
GPR34 88h
12.4.4.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XECC_FLEXSPI1_WAIT_BVALID_CPL
FLEXSPI1_OTFAD_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.35.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-2 Reserved
—
1 FlexSPI1 OTFAD enable
FLEXSPI1_OTF This bit enables the OTFAD operation when it's set to 1. It has the same effect as OTFAD_CR[GE] bit.
AD_EN
0 XECC_FLEXSPI1 RMW wait enable
XECC_FLEXSPI If this bit is set to 1, RMW will write back next data only after current write response is received. It only
1_WAIT_BVALI affects the speed of data transfer.
D_CPL
12.4.4.36 GPR35 General Purpose Register (GPR35)
GPR Register
12.4.4.36.1 Offset
Register Offset
GPR35 8Ch
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12.4.4.36.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XECC_FLEXSPI2_WAIT_BVALID_CPL
FLEXSPI2_OTFAD_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.36.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
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Field Description
15-2 Reserved
—
1 FlexSPI2 OTFAD enable
FLEXSPI2_OTF This bit enables the OTFAD operation when it's set to 1. It has the same effect as OTFAD_CR[GE] bit.
AD_EN
0 XECC_FLEXSPI2 RMW wait enable
XECC_FLEXSPI If this bit is set to 1, RMW will write back next data only after current write response is received. It only
2_WAIT_BVALI affects the speed of data transfer.
D_CPL
12.4.4.37 GPR36 General Purpose Register (GPR36)
GPR Register
12.4.4.37.1 Offset
Register Offset
GPR36 90h
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12.4.4.37.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XECC_SEMC_WAIT_BVALID_CPL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.37.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-1 Reserved
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Field Description
—
0 XECC_SEMC RMW wait enable
XECC_SEMC_ If this bit is set to 1, RMW will write back next data only after current write response is received. It only
WAIT_BVALID_ affects the speed of data transfer.
CPL
12.4.4.38 GPR37 General Purpose Register (GPR37)
GPR Register
12.4.4.38.1 Offset
Register Offset
GPR37 94h
12.4.4.38.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
M4_DBG_ACK_MASK
M7_DBG_ACK_MASK
EXC_MON
Reserved
Reserved
Reserved
NIDEN
DBG_E
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
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12.4.4.38.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-7 Reserved
—
6 CM4 debug halt mask
M4_DBG_ACK_ Once set to 1, peripheral won't be halted when CM4 is halted by debugger.
MASK
5 CM7 debug halt mask
M7_DBG_ACK_ Once set to 1, peripheral won't be halted when CM7 is halted by debugger.
MASK
4 Reserved
—
3 Exclusive monitor response select of illegal command
EXC_MON This bit sets the bus response value when CM7 or CM4 exclusive access fails.
0: OKAY response
1: SLVError response
2 Reserved
—
1 ARM invasive debug enable
DBG_EN Invasive debug is Arm concept. See the Arm v7-M Architecture Reference Manual for more information.
This bit applies to both CM7 and CM4.
0: Debug turned off
1: Debug enabled (default)
0 ARM non-secure (non-invasive) debug enable
NIDEN Non-invasive debug is Arm concept. See the Arm v7-M Architecture Reference Manual for more
information. This bit applies to both CM7 and CM4.
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Field Description
0: Debug turned off
1: Debug enabled (default)
12.4.4.39 GPR38 General Purpose Register (GPR38)
GPR Register
12.4.4.39.1 Offset
Register Offset
GPR38 98h
12.4.4.39.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.39.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
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Field Description
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.40 GPR39 General Purpose Register (GPR39)
GPR Register
12.4.4.40.1 Offset
Register Offset
GPR39 9Ch
12.4.4.40.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.40.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.41 GPR40 General Purpose Register (GPR40)
GPR Register
12.4.4.41.1 Offset
Register Offset
GPR40 A0h
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12.4.4.41.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_MUX2_GPIO_SEL_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.41.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
GPIO_MUX2_G This register controls GPIO_MUX2 to select GPIO2 or CM7_GPIO2. For bit n, 1b0 - GPIO2[n] is selected;
PIO_SEL_LOW 1b1 - CM7_GPIO2[n] is selected.
12.4.4.42 GPR41 General Purpose Register (GPR41)
GPR Register
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12.4.4.42.1 Offset
Register Offset
GPR41 A4h
12.4.4.42.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_MUX2_GPIO_SEL_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.42.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
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Field Description
GPIO_MUX2_G This register controls GPIO_MUX2 to select GPIO2 or fast CM7_GPIO2. For bit n, 1b0 - GPIO2[16+n] is
PIO_SEL_HIGH selected; 1b1 - CM7_GPIO2[16+n] is selected.
12.4.4.43 GPR42 General Purpose Register (GPR42)
GPR Register
12.4.4.43.1 Offset
Register Offset
GPR42 A8h
12.4.4.43.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_MUX3_GPIO_SEL_LOW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.43.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
Table continues on the next page...
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Field Description
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
GPIO_MUX3_G This register controls GPIO_MUX3 to select GPIO3 or fast CM7_GPIO3. For bit n, 1b0 - GPIO3[n] is
PIO_SEL_LOW selected; 1b1 - CM7_GPIO3[n] is selected.
12.4.4.44 GPR43 General Purpose Register (GPR43)
GPR Register
12.4.4.44.1 Offset
Register Offset
GPR43 ACh
12.4.4.44.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_MUX3_GPIO_SEL_HIGH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.44.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
GPIO_MUX3_G This register controls GPIO_MUX3 to select GPIO3 or CM7_GPIO3. For bit n, 1b0 - GPIO3[16+n] is
PIO_SEL_HIGH selected; 1b1 - CM7_GPIO3[16+n] is selected.
12.4.4.45 GPR44 General Purpose Register (GPR44)
GPR Register
12.4.4.45.1 Offset
Register Offset
GPR44 B0h
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12.4.4.45.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.45.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.46 GPR45 General Purpose Register (GPR45)
GPR Register
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12.4.4.46.1 Offset
Register Offset
GPR45 B4h
12.4.4.46.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.46.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
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12.4.4.47 GPR46 General Purpose Register (GPR46)
GPR Register
12.4.4.47.1 Offset
Register Offset
GPR46 B8h
12.4.4.47.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.47.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
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Field Description
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.48 GPR47 General Purpose Register (GPR47)
GPR Register
12.4.4.48.1 Offset
Register Offset
GPR47 BCh
12.4.4.48.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.48.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
Table continues on the next page...
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Field Description
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.49 GPR48 General Purpose Register (GPR48)
GPR Register
12.4.4.49.1 Offset
Register Offset
GPR48 C0h
12.4.4.49.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.4.49.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.50 GPR49 General Purpose Register (GPR49)
GPR Register
12.4.4.50.1 Offset
Register Offset
GPR49 C4h
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12.4.4.50.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.50.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-0 Reserved
—
12.4.4.51 GPR50 General Purpose Register (GPR50)
GPR Register
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12.4.4.51.1 Offset
Register Offset
GPR50 C8h
12.4.4.51.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved CAAM_IPS_MGR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.51.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-5 Reserved
—
Table continues on the next page...
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Field Description
4-0 CAAM manager processor identifier
CAAM_IPS_MG This register provides the value to CAAM module's caam_ips_manager[4:0] input signal.
R
12.4.4.52 GPR51 General Purpose Register (GPR51)
GPR Register
12.4.4.52.1 Offset
Register Offset
GPR51 CCh
12.4.4.52.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_NMI_CLEAR
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.52.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
Table continues on the next page...
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Field Description
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-1 Reserved
—
0 Clear CM7 NMI holding register
M7_NMI_CLEA The NMI input from IO wil be held internally until this bit is set to 1. Note that this bit need software write 0
R to clear.
12.4.4.53 GPR52 General Purpose Register (GPR52)
GPR Register
12.4.4.53.1 Offset
Register Offset
GPR52 D0h
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12.4.4.53.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.53.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-0 Reserved
—
12.4.4.54 GPR53 General Purpose Register (GPR53)
GPR Register
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12.4.4.54.1 Offset
Register Offset
GPR53 D4h
12.4.4.54.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.54.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-0 Reserved
—
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12.4.4.55 GPR54 General Purpose Register (GPR54)
GPR Register
12.4.4.55.1 Offset
Register Offset
GPR54 D8h
12.4.4.55.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.55.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
Table continues on the next page...
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Field Description
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-0 Reserved
—
12.4.4.56 GPR55 General Purpose Register (GPR55)
GPR Register
12.4.4.56.1 Offset
Register Offset
GPR55 DCh
12.4.4.56.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.56.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
Table continues on the next page...
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Field Description
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-20 Reserved
—
19-0 Reserved
—
12.4.4.57 GPR59 General Purpose Register (GPR59)
GPR Register
12.4.4.57.1 Offset
Register Offset
GPR59 ECh
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12.4.4.57.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIPI_CSI_S_PRG_RXHS_SETTL
DWP_LOCK
Reserved
DWP
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MIPI_CSI_S_PRG_RXHS_SETTL
MIPI_CSI_CONT_CLK_MODE
MIPI_CSI_SOFT_RST_N
MIPI_CSI_AUTO_PD_EN
MIPI_CSI_RX_ENABLE
MIPI_CSI_DDRCLK_EN
MIPI_CSI_RX_RCAL
MIPI_CSI_RXCDRP
MIPI_CSI_RXLPRP
MIPI_CSI_PD_RX
W
E
Reset 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0
12.4.4.57.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 17:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
Table continues on the next page...
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Field Description
10 - CM4 is forbidden
11 - Both cores are forbidden
27-18 Reserved
—
17-12 Bits used to program T_HS_SETTLE.
MIPI_CSI_S_PR HS-RX waits for Time-out T_HS_SETTLE in order to neglect transition effects.
G_RXHS_SETT
a. The equation is T_HS_SETTLE= (PRG_RXHS_SETTLE + 1) * (Tperiod of RxClkInEsc)
LE
b. Min value of T_HS_SETTLE = 85n + 6*UI, where UI is the time period of User Clock (clk_ui)
c. Max value of T_HS_SETTLE = 145ns + 10*UI
11-10 Programming bits that adjust the threshold voltage of LP-RX, default setting 2’b01
MIPI_CSI_RXLP
RP Bitfield Value High Threshold Voltage Low Threshold Voltage
2'b00 782mV 730mV
2'b01 (Default) 745mV 692mV
2'b10 708mV 655mV
2'b11 Invalid Invalid
9-8 Programming bits that adjust the threshold voltage of LP-CD, default setting 2’b01
MIPI_CSI_RXC 00 - 344mV
DRP
01 - 325mV (Default)
10 - 307mV
11 - Invalid
7-6 MIPI CSI PHY on-chip termination control bits
MIPI_CSI_RX_ On-chip termination control bits for manual calibration.
RCAL
00: 20% higher than mid range. Highest impedance setting
01 Mid range impedance setting.
10 15% lower than mid range
11 25% lower than mid range. Lowest impedance setting
5 Assert to enable MIPI CSI Receive Enable
MIPI_CSI_RX_E When deasserted, the RX controller will pause data reception at the next packet boundary. Since the
NABLE CSI-2 protocol does not allow the Receiver to pause data, when rx_enable is deasserted the RX
Controller still receives data from the RX DPHY but it does not forward the receive packets to the user
interface but instead discards the received data. When rx_enable is asserted, the RX controller will wait
for the start of the next packet before allowing data to be sent out over the user interface.
4 Power Down input for MIPI CSI PHY.
MIPI_CSI_PD_ When high, all blocks are powered down.
RX
3 When high, enables received DDR clock on CLK_DRXHS
MIPI_CSI_DDR
CLK_EN
2 Enables the slave clock lane feature to maintain HS reception state during continuous clock mode
operation, despite line glitches.
Table continues on the next page...
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Field Description
MIPI_CSI_CON 1: Feature enabled
T_CLK_MODE
0: Feature disabled
1 MIPI CSI APB clock domain and User interface clock domain software reset bit
MIPI_CSI_SOF Async reset for all logic in the pclk clock domain. Note this bit is active low and not self-clearing. By
T_RST_N default it holds the MIPI CSI in reset state.
0 - Assert reset
1 - De-assert reset
0 Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.
MIPI_CSI_AUT 1’b0: inactive lanes are powered up and driving LP11
O_PD_EN
1’b1: inactive lanes are powered down.
12.4.4.58 GPR62 General Purpose Register (GPR62)
GPR Register
12.4.4.58.1 Offset
Register Offset
GPR62 F8h
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12.4.4.58.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIPI_DSI_PCLK_SOFT_RESET_N
MIPI_DSI_DPI_SOFT_RESET_N
MIPI_DSI_BYTE_SOFT_RESET_
MIPI_DSI_ESC_SOFT_RESET_
DWP_LOCK
Reserved
DWP
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MIPI_DSI_TX_ULPS_ENABLE
MIPI_DSI_TX_RCAL
MIPI_DSI_CLK_TM
MIPI_DSI_D1_TM
MIPI_DSI_D0_TM
Reserved
Reset 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1
12.4.4.58.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
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Field Description
11 - Both cores are forbidden
27-20 Reserved
—
19 MIPI DSI Escape clock domain software reset bit
MIPI_DSI_ESC_ Note this bit is active low and not self-clearing. By default it holds the MIPI DSI in reset state
SOFT_RESET_
0 - Assert reset
N
1 - De-assert reset
18 MIPI DSI Pixel clock domain software reset bit
MIPI_DSI_DPI_ Note this bit is active low and not self-clearing. By default it holds the MIPI DSI in reset state.
SOFT_RESET_
0 - Assert reset
N
1 - De-assert reset
17 MIPI DSI Byte clock domain software reset bit
MIPI_DSI_BYTE Note this bit is active low and not self-clearing. By default it holds the MIPI DSI in reset state.
_SOFT_RESET
0 - Assert reset
_N
1 - De-assert reset
16 MIPI DSI APB clock domain software reset bit
MIPI_DSI_PCLK Note this bit is active low and not self-clearing. By default it holds the MIPI DSI in reset state.
_SOFT_RESET
0 - Assert reset
_N
1 - De-assert reset
15-14 Reserved
—
13-11 DSI transmit ULPS mode enable
MIPI_DSI_TX_U Each bit represents a data lane and the clock lane.
LPS_ENABLE
A ‘1’ enables the associated clock lane or data lane ULPS mode.
[0] – clock lane
[1] – data lane 0
[2] – data lane 1
10-9 MIPI DSI PHY on-chip termination control bits
MIPI_DSI_TX_R On-chip termination control bits for manual calibration of HS-TX.
CAL
00: 20% higher than mid-range (Highest impedance setting)
01: Mid-range impedance setting (default)
10: 15% lower than mid-range
11: 25% lower than mid-range (Lowest impedance setting)
8-6 MIPI DSI Data Lane 1 triming bits
MIPI_DSI_D1_T LPTX VOH voltage level trimming bus for Data Lane 1. Total of 8 trimming levels, voltage adjustment
M granularity is approximately 34mV. Default setting 3'b011. Voltage levels for each setting are listed
below(typical case, no mismatch):
3'b000=1086mV
3'b001=1120mV
3'b010=1155mV
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Field Description
3'b011=1190mV
3'b100=1224mV
3'b101=1258mV
3'b110=1293mV
3'b111=1327mV
5-3 MIPI DSI Data Lane 0 triming bits
MIPI_DSI_D0_T LPTX VOH voltage level trimming bus for Data Lane 0. Feature same as MIPI_DSI_D1_TM.
M
2-0 MIPI DSI Clock Lane triming bits
MIPI_DSI_CLK_ LPTX VOH voltage level trimming bus for Clock Lane. Feature same as MIPI_DSI_D1_TM.
TM
12.4.4.59 GPR63 General Purpose Register (GPR63)
GPR Register
12.4.4.59.1 Offset
Register Offset
GPR63 FCh
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12.4.4.59.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIPI_DSI_TX_ULPS_ACTIVE
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.59.3 Fields
Field Description
31-3 Reserved
—
2-0 DSI transmit ULPS mode active flag
MIPI_DSI_TX_U Each bit represents a data lane and the clock lane.
LPS_ACTIVE
A ‘1’ indicates the associated clock lane or data lane is in ULPS mode,
‘0’ indicates not in ULPS mode
[0] – clock lane
[1] – data lane 0
[2] – data lane 1
12.4.4.60 GPR64 General Purpose Register (GPR64)
GPR Register
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12.4.4.60.1 Offset
Register Offset
GPR64 100h
12.4.4.60.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_DISP1_COMPOK
GPIO_DISP1_NASRC
Reserved
DWP_LOCK
Reserved
R
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_DISP1_SUPLYDET_LATCH
GPIO_DISP1_SELECT_NASRC
GPIO_DISP1_REFGEN_SLEE
GPIO_DISP1_FASTFRZ_EN
GPIO_DISP1_RASRCN
GPIO_DISP1_RASRCP
GPIO_DISP1_COMPEN
GPIO_DISP1_COMPTQ
GPIO_DISP1_FREEZ
Reserved
E
P
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.60.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
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Field Description
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-25 Reserved
—
24-21 GPIO_DISP_B1 IO bank compensation codes
GPIO_DISP1_N 4-bit NMOS compensation codes or 4-bit PMOS compensation codes selected by
ASRC GPIO_DISP1_SELECT_NASRC.
20 GPIO_DISP_B1 IO bank compensation OK flag
GPIO_DISP1_C It can be high only in the Normal mode and when a new measured code is available.
OMPOK
19-15 Reserved
—
14 GPIO_DISP_B1 IO bank power supply mode latch enable
GPIO_DISP1_S Supply detector cell is used to detect the IO supply range and set IO to 3V3 supply mode or 1V8 supply
UPLYDET_LAT mode according to the detection. Setting this bit will latch the current detect result.
CH
13 GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable
GPIO_DISP1_R Reference voltage generator cell provides reference voltages to the IO bank. When this bit is high, it puts
EFGEN_SLEEP the reference voltage generator cell in sleep mode to reduce the static power consumption.
12 GPIO_DISP1_NASRC selection
GPIO_DISP1_S 0: Show the 4-bit PMOS compensation codes in GPIO_DISP1_NASRC field
ELECT_NASRC
1: Show the 4-bit NMOS compensation codes in GPIO_DISP1_NASRC field
11-8 GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core
GPIO_DISP1_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCN is high, high, low, low.
7-4 GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core
GPIO_DISP1_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCP is high, high, low, low.
3 Compensation code fast freeze
GPIO_DISP1_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, low, high, compensation cell Fast
ASTFRZ_EN Freeze mode is enabled. Fast Freeze mode is activated on signal rising edge. The compensation cell
delivers a refreshed compensation code, at a comparatively lesser delay after signal falling edge than the
delay of Freeze mode.
2 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_DISP1_C Normal Mode: In this mode, the macro cell constantly tracks the PVT condition of the chip and generates
OMPEN an 8-bit digital code. This 8-bit code is referred to as f(PVT) and it represents current PVT state. In
Normal mode, the internal reference current generators are active and power consumption is higher than
that in all the other modes.
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Field Description
Freeze mode: This mode is used where the current consumption is to be kept low. In this mode, all the
internal blocks are switched off to reduce the static power consumption. Internal latches keep the code,
which is calculated before the cell enters the Freeze mode.
Fast Freeze mode: This mode is used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during Burst mode. This ensures
signal integrity and eliminates the jitter caused due to modification in IO driver strength. In this mode, the
current consumption is comparable to consumption in the Normal mode.
Read Mode: In this mode, it is possible to force the digital codes from the chip core logic. The bandgap,
measurement block, and comparator blocks are switched off to reduce static power consumption to
minimum value.
Fixed Code mode: The digital code is forced to a fixed value, obtained at typical PVT conditions and
represents typical bit patterns. The bandgap, measurement, and other blocks are switched off to reduce
static power consumption to minimum value.
COMPEN COMPTQ FREEZE FASTFRZ_EN Mode
0 0 0 0 Normal Mode
0 0 1 0 Freeze Mode
0 0 0 1 Fast Freeze Mode
1 1 0 0 Read Mode
0 1 0 0 Fixed Code Mode
1 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_DISP1_C
OMPTQ
0 Compensation code freeze
GPIO_DISP1_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, high, low, compensation cell Freeze
REEZE mode is enabled. On the rising edge of FREEZE, it freezes the compensation code at its running value.
The compensation cell delivers refreshed compensation code at a delay after FREEZE falling edge.
12.4.4.61 GPR65 General Purpose Register (GPR65)
GPR Register
12.4.4.61.1 Offset
Register Offset
GPR65 104h
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12.4.4.61.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_EMC1_COMPOK
GPIO_EMC1_NASRC
Reserved
DWP_LOCK
Reserved
R DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_EMC1_SUPLYDET_LATCH
GPIO_EMC1_SELECT_NASRC
GPIO_EMC1_REFGEN_SLEE
GPIO_EMC1_FASTFRZ_EN
GPIO_EMC1_RASRCN
GPIO_EMC1_RASRCP
GPIO_EMC1_COMPEN
GPIO_EMC1_COMPTQ
GPIO_EMC1_FREEZ
Reserved
E
P
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.61.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
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Field Description
11 - Both cores are forbidden
27-25 Reserved
—
24-21 GPIO_EMC_B1 IO bank compensation codes
GPIO_EMC1_N 4-bit NMOS compensation codes or 4-bit PMOS compensation codes selected by
ASRC GPIO_EMC1_SELECT_NASRC.
20 GPIO_EMC_B1 IO bank compensation OK flag
GPIO_EMC1_C It can be high only in the Normal mode and when a new measured code is available.
OMPOK
19-15 Reserved
—
14 GPIO_EMC_B1 IO bank power supply mode latch enable
GPIO_EMC1_S Supply detector cell is used to detect the IO supply range and set IO to 3V3 supply mode or 1V8 supply
UPLYDET_LAT mode according to the detection. Setting this bit will latch the current detect result.
CH
13 GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable
GPIO_EMC1_R Reference voltage generator cell provides reference voltages to the IO bank. When this bit is high, it puts
EFGEN_SLEEP the reference voltage generator cell in sleep mode to reduce the static power consumption.
12 GPIO_EMC1_NASRC selection
GPIO_EMC1_S 0: Show the 4-bit PMOS compensation codes in GPIO_EMC1_NASRC field
ELECT_NASRC
1: Show the 4-bit NMOS compensation codes in GPIO_EMC1_NASRC field
11-8 GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core
GPIO_EMC1_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCN is high, high, low, low.
7-4 GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core
GPIO_EMC1_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCP is high, high, low, low.
3 Compensation code fast freeze
GPIO_EMC1_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, low, high, compensation cell Fast
ASTFRZ_EN Freeze mode is enabled. Fast Freeze mode is activated on signal rising edge. The compensation cell
delivers a refreshed compensation code, at a comparatively lesser delay after signal falling edge than the
delay of Freeze mode.
2 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_EMC1_C Normal Mode: In this mode, the macro cell constantly tracks the PVT condition of the chip and generates
OMPEN an 8-bit digital code. This 8-bit code is referred to as f(PVT) and it represents current PVT state. In
Normal mode, the internal reference current generators are active and power consumption is higher than
that in all the other modes.
Freeze mode: This mode is used where the current consumption is to be kept low. In this mode, all the
internal blocks are switched off to reduce the static power consumption. Internal latches keep the code,
which is calculated before the cell enters the Freeze mode.
Fast Freeze mode: This mode is used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during Burst mode. This ensures
signal integrity and eliminates the jitter caused due to modification in IO driver strength. In this mode, the
current consumption is comparable to consumption in the Normal mode.
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Field Description
Read Mode: In this mode, it is possible to force the digital codes from the chip core logic. The bandgap,
measurement block, and comparator blocks are switched off to reduce static power consumption to
minimum value.
Fixed Code mode: The digital code is forced to a fixed value, obtained at typical PVT conditions and
represents typical bit patterns. The bandgap, measurement, and other blocks are switched off to reduce
static power consumption to minimum value.
COMPEN COMPTQ FREEZE FASTFRZ_EN Mode
0 0 0 0 Normal Mode
0 0 1 0 Freeze Mode
0 0 0 1 Fast Freeze Mode
1 1 0 0 Read Mode
0 1 0 0 Fixed Code Mode
1 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_EMC1_C
OMPTQ
0 Compensation code freeze
GPIO_EMC1_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, high, low, compensation cell Freeze
REEZE mode is enabled. On the rising edge of FREEZE, it freezes the compensation code at its running value.
The compensation cell delivers refreshed compensation code at a delay after FREEZE falling edge.
12.4.4.62 GPR66 General Purpose Register (GPR66)
GPR Register
12.4.4.62.1 Offset
Register Offset
GPR66 108h
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12.4.4.62.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_EMC2_COMPOK
GPIO_EMC2_NASRC
Reserved
DWP_LOCK
Reserved
R DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_EMC2_SUPLYDET_LATCH
GPIO_EMC2_SELECT_NASRC
GPIO_EMC2_REFGEN_SLEE
GPIO_EMC2_FASTFRZ_EN
GPIO_EMC2_RASRCN
GPIO_EMC2_RASRCP
GPIO_EMC2_COMPEN
GPIO_EMC2_COMPTQ
GPIO_EMC2_FREEZ
Reserved
E
P
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.62.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
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Field Description
11 - Both cores are forbidden
27-25 Reserved
—
24-21 GPIO_EMC_B2 IO bank compensation codes
GPIO_EMC2_N 4-bit NMOS compensation codes or 4-bit PMOS compensation codes selected by
ASRC GPIO_EMC2_SELECT_NASRC.
20 GPIO_EMC_B2 IO bank compensation OK flag
GPIO_EMC2_C It can be high only in the Normal mode and when a new measured code is available.
OMPOK
19-15 Reserved
—
14 GPIO_EMC_B2 IO bank power supply mode latch enable
GPIO_EMC2_S Supply detector cell is used to detect the IO supply range and set IO to 3V3 supply mode or 1V8 supply
UPLYDET_LAT mode according to the detection. Setting this bit will latch the current detect result.
CH
13 GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable
GPIO_EMC2_R Reference voltage generator cell provides reference voltages to the IO bank. When this bit is high, it puts
EFGEN_SLEEP the reference voltage generator cell in sleep mode to reduce the static power consumption.
12 GPIO_EMC2_NASRC selection
GPIO_EMC2_S 0: Show the 4-bit PMOS compensation codes in GPIO_EMC2_NASRC field
ELECT_NASRC
1: Show the 4-bit NMOS compensation codes in GPIO_EMC2_NASRC field
11-8 GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core
GPIO_EMC2_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCN is high, high, low, low.
7-4 GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core
GPIO_EMC2_R These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
ASRCP is high, high, low, low.
3 Compensation code fast freeze
GPIO_EMC2_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, low, high, compensation cell Fast
ASTFRZ_EN Freeze mode is enabled. Fast Freeze mode is activated on signal rising edge. The compensation cell
delivers a refreshed compensation code, at a comparatively lesser delay after signal falling edge than the
delay of Freeze mode.
2 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_EMC2_C Normal Mode: In this mode, the macro cell constantly tracks the PVT condition of the chip and generates
OMPEN an 8-bit digital code. This 8-bit code is referred to as f(PVT) and it represents current PVT state. In
Normal mode, the internal reference current generators are active and power consumption is higher than
that in all the other modes.
Freeze mode: This mode is used where the current consumption is to be kept low. In this mode, all the
internal blocks are switched off to reduce the static power consumption. Internal latches keep the code,
which is calculated before the cell enters the Freeze mode.
Fast Freeze mode: This mode is used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during Burst mode. This ensures
signal integrity and eliminates the jitter caused due to modification in IO driver strength. In this mode, the
current consumption is comparable to consumption in the Normal mode.
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Field Description
Read Mode: In this mode, it is possible to force the digital codes from the chip core logic. The bandgap,
measurement block, and comparator blocks are switched off to reduce static power consumption to
minimum value.
Fixed Code mode: The digital code is forced to a fixed value, obtained at typical PVT conditions and
represents typical bit patterns. The bandgap, measurement, and other blocks are switched off to reduce
static power consumption to minimum value.
COMPEN COMPTQ FREEZE FASTFRZ_EN Mode
0 0 0 0 Normal Mode
0 0 1 0 Freeze Mode
0 0 0 1 Fast Freeze Mode
1 1 0 0 Read Mode
0 1 0 0 Fixed Code Mode
1 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_EMC2_C
OMPTQ
0 Compensation code freeze
GPIO_EMC2_F When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, high, low, compensation cell Freeze
REEZE mode is enabled. On the rising edge of FREEZE, it freezes the compensation code at its running value.
The compensation cell delivers refreshed compensation code at a delay after FREEZE falling edge.
12.4.4.63 GPR67 General Purpose Register (GPR67)
GPR Register
12.4.4.63.1 Offset
Register Offset
GPR67 10Ch
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12.4.4.63.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_SD1_COMPOK
GPIO_SD1_NASRC
Reserved
DWP_LOCK
Reserved
R DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_SD1_SUPLYDET_LATCH
GPIO_SD1_SELECT_NASRC
GPIO_SD1_REFGEN_SLEE
GPIO_SD1_FASTFRZ_EN
GPIO_SD1_RASRCN
GPIO_SD1_RASRCP
GPIO_SD1_COMPEN
GPIO_SD1_COMPTQ
GPIO_SD1_FREEZ
Reserved
E
P
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.63.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
Table continues on the next page...
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Memory Map and register definition
Field Description
27-25 Reserved
—
24-21 GPIO_SD_B1 IO bank compensation codes
GPIO_SD1_NA 4-bit NMOS compensation codes or 4-bit PMOS compensation codes selected by
SRC GPIO_SD1_SELECT_NASRC.
20 GPIO_SD_B1 IO bank compensation OK flag
GPIO_SD1_CO It can be high only in the Normal mode and when a new measured code is available.
MPOK
19-15 Reserved
—
14 GPIO_SD_B1 IO bank power supply mode latch enable
GPIO_SD1_SU Supply detector cell is used to detect the IO supply range and set IO to 3V3 supply mode or 1V8 supply
PLYDET_LATC mode according to the detection. Setting this bit will latch the current detect result.
H
13 GPIO_SD_B1 IO bank reference voltage generator cell sleep enable
GPIO_SD1_RE Reference voltage generator cell provides reference voltages to the IO bank. When this bit is high, it puts
FGEN_SLEEP the reference voltage generator cell in sleep mode to reduce the static power consumption.
12 GPIO_SD1_NASRC selection
GPIO_SD1_SEL 0: Show the 4-bit PMOS compensation codes in GPIO_SD1_NASRC field
ECT_NASRC
1: Show the 4-bit NMOS compensation codes in GPIO_SD1_NASRC field
11-8 GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core
GPIO_SD1_RA These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
SRCN is high, high, low, low.
7-4 GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core
GPIO_SD1_RA These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
SRCP is high, high, low, low.
3 Compensation code fast freeze
GPIO_SD1_FA When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, low, high, compensation cell Fast
STFRZ_EN Freeze mode is enabled. Fast Freeze mode is activated on signal rising edge. The compensation cell
delivers a refreshed compensation code, at a comparatively lesser delay after signal falling edge than the
delay of Freeze mode.
2 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_SD1_CO Normal Mode: In this mode, the macro cell constantly tracks the PVT condition of the chip and generates
MPEN an 8-bit digital code. This 8-bit code is referred to as f(PVT) and it represents current PVT state. In
Normal mode, the internal reference current generators are active and power consumption is higher than
that in all the other modes.
Freeze mode: This mode is used where the current consumption is to be kept low. In this mode, all the
internal blocks are switched off to reduce the static power consumption. Internal latches keep the code,
which is calculated before the cell enters the Freeze mode.
Fast Freeze mode: This mode is used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during Burst mode. This ensures
signal integrity and eliminates the jitter caused due to modification in IO driver strength. In this mode, the
current consumption is comparable to consumption in the Normal mode.
Read Mode: In this mode, it is possible to force the digital codes from the chip core logic. The bandgap,
measurement block, and comparator blocks are switched off to reduce static power consumption to
minimum value.
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
Fixed Code mode: The digital code is forced to a fixed value, obtained at typical PVT conditions and
represents typical bit patterns. The bandgap, measurement, and other blocks are switched off to reduce
static power consumption to minimum value.
COMPEN COMPTQ FREEZE FASTFRZ_EN Mode
0 0 0 0 Normal Mode
0 0 1 0 Freeze Mode
0 0 0 1 Fast Freeze Mode
1 1 0 0 Read Mode
0 1 0 0 Fixed Code Mode
1 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_SD1_CO
MPTQ
0 Compensation code freeze
GPIO_SD1_FR When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, high, low, compensation cell Freeze
EEZE mode is enabled. On the rising edge of FREEZE, it freezes the compensation code at its running value.
The compensation cell delivers refreshed compensation code at a delay after FREEZE falling edge.
12.4.4.64 GPR68 General Purpose Register (GPR68)
GPR Register
12.4.4.64.1 Offset
Register Offset
GPR68 110h
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12.4.4.64.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPIO_SD2_COMPOK
GPIO_SD2_NASRC
Reserved
DWP_LOCK
Reserved
R DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_SD2_SUPLYDET_LATCH
GPIO_SD2_SELECT_NASRC
GPIO_SD2_REFGEN_SLEE
GPIO_SD2_FASTFRZ_EN
GPIO_SD2_RASRCN
GPIO_SD2_RASRCP
GPIO_SD2_COMPEN
GPIO_SD2_COMPTQ
GPIO_SD2_FREEZ
Reserved
E
P
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.64.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 19:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
27-25 Reserved
—
24-21 GPIO_SD_B2 IO bank compensation codes
GPIO_SD2_NA 4-bit NMOS compensation codes or 4-bit PMOS compensation codes selected by
SRC GPIO_SD2_SELECT_NASRC.
20 GPIO_SD_B2 IO bank compensation OK flag
GPIO_SD2_CO It can be high only in the Normal mode and when a new measured code is available.
MPOK
19-15 Reserved
—
14 GPIO_SD_B2 IO bank power supply mode latch enable
GPIO_SD2_SU Supply detector cell is used to detect the IO supply range and set IO to 3V3 supply mode or 1V8 supply
PLYDET_LATC mode according to the detection. Setting this bit will latch the current detect result.
H
13 GPIO_SD_B2 IO bank reference voltage generator cell sleep enable
GPIO_SD2_RE Reference voltage generator cell provides reference voltages to the IO bank. When this bit is high, it puts
FGEN_SLEEP the reference voltage generator cell in sleep mode to reduce the static power consumption.
12 GPIO_SD2_NASRC selection
GPIO_SD2_SEL 0: Show the 4-bit PMOS compensation codes in GPIO_SD2_NASRC field
ECT_NASRC
1: Show the 4-bit NMOS compensation codes in GPIO_SD2_NASRC field
11-8 GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core
GPIO_SD2_RA These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
SRCN is high, high, low, low.
7-4 GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core
GPIO_SD2_RA These codes are used in compensation Read mode when COMPEN, COMPTQ, FREEZE, FASTFRZ_EN
SRCP is high, high, low, low.
3 Compensation code fast freeze
GPIO_SD2_FA When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, low, high, compensation cell Fast
STFRZ_EN Freeze mode is enabled. Fast Freeze mode is activated on signal rising edge. The compensation cell
delivers a refreshed compensation code, at a comparatively lesser delay after signal falling edge than the
delay of Freeze mode.
2 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_SD2_CO Normal Mode: In this mode, the macro cell constantly tracks the PVT condition of the chip and generates
MPEN an 8-bit digital code. This 8-bit code is referred to as f(PVT) and it represents current PVT state. In
Normal mode, the internal reference current generators are active and power consumption is higher than
that in all the other modes.
Freeze mode: This mode is used where the current consumption is to be kept low. In this mode, all the
internal blocks are switched off to reduce the static power consumption. Internal latches keep the code,
which is calculated before the cell enters the Freeze mode.
Fast Freeze mode: This mode is used to freeze the digital compensation codes, when the data is
transferred from the compensated IOs on a chip to an external device during Burst mode. This ensures
signal integrity and eliminates the jitter caused due to modification in IO driver strength. In this mode, the
current consumption is comparable to consumption in the Normal mode.
Read Mode: In this mode, it is possible to force the digital codes from the chip core logic. The bandgap,
measurement block, and comparator blocks are switched off to reduce static power consumption to
minimum value.
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Memory Map and register definition
Field Description
Fixed Code mode: The digital code is forced to a fixed value, obtained at typical PVT conditions and
represents typical bit patterns. The bandgap, measurement, and other blocks are switched off to reduce
static power consumption to minimum value.
COMPEN COMPTQ FREEZE FASTFRZ_EN Mode
0 0 0 0 Normal Mode
0 0 1 0 Freeze Mode
0 0 0 1 Fast Freeze Mode
1 1 0 0 Read Mode
0 1 0 0 Fixed Code Mode
1 COMPEN and COMPTQ control the operating modes of the compensation cell
GPIO_SD2_CO
MPTQ
0 Compensation code freeze
GPIO_SD2_FR When COMPEN, COMPTQ, FREEZE, FASTFRZ_EN is low, low, high, low, compensation cell Freeze
EEZE mode is enabled. On the rising edge of FREEZE, it freezes the compensation code at its running value.
The compensation cell delivers refreshed compensation code at a delay after FREEZE falling edge.
12.4.4.65 GPR69 General Purpose Register (GPR69)
GPR Register
12.4.4.65.1 Offset
Register Offset
GPR69 114h
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.4.65.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIO_DISP2_HIGH_RANGE
GPIO_DISP2_LOW_RANGE
GPIO_AD1_HIGH_RANGE
GPIO_AD0_HIGH_RANGE
SUPLYDET_DISP1_SLEE
GPIO_AD1_LOW_RANGE
GPIO_AD0_LOW_RANGE
SUPLYDET_EMC2_SLEE
SUPLYDET_EMC1_SLEE
SUPLYDET_SD2_SLEE
SUPLYDET_SD1_SLEE
Reserved
Reserved
Reserved
Reserved
W
P
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.65.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 15:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-16 Reserved
—
15-14 Reserved
—
13 GPIO_SD_B2 IO bank supply voltage detector sleep mode enable
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Memory Map and register definition
Field Description
SUPLYDET_SD Supply detector cell is used to detect the IO supply range. When this bit is high, it puts the cell in sleep
2_SLEEP mode to reduce the static power consumption. The detect result can be latched by setting
SUPLYDET_LATCH bit before putting the cell in sleep mode.
12 GPIO_SD_B1 IO bank supply voltage detector sleep mode enable
SUPLYDET_SD Supply detector cell is used to detect the IO supply range. When this bit is high, it puts the cell in sleep
1_SLEEP mode to reduce the static power consumption. The detect result can be latched by setting
SUPLYDET_LATCH bit before putting the cell in sleep mode.
11 GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable
SUPLYDET_EM Supply detector cell is used to detect the IO supply range. When this bit is high, it puts the cell in sleep
C2_SLEEP mode to reduce the static power consumption. The detect result can be latched by setting
SUPLYDET_LATCH bit before putting the cell in sleep mode.
10 GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable
SUPLYDET_EM Supply detector cell is used to detect the IO supply range. When this bit is high, it puts the cell in sleep
C1_SLEEP mode to reduce the static power consumption. The detect result can be latched by setting
SUPLYDET_LATCH bit before putting the cell in sleep mode.
9 GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable
SUPLYDET_DI Supply detector cell is used to detect the IO supply range. When this bit is high, it puts the supply
SP1_SLEEP detector cell in sleep mode to reduce the static power consumption. The detect result can be latched by
setting SUPLYDET_LATCH bit before putting the cell in sleep mode.
8 GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
GPIO_AD1_LO
W_RANGE GPIO_AD1_HIGH_RANGE GPIO_AD1_LOW_RANGE Mode
0 0 GPIO_AD1_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_AD1_xx IO will work in low
range mode with supply voltage
in 1.71v-1.98v
1 0 GPIO_AD1_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
7 GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
GPIO_AD1_HIG
H_RANGE GPIO_AD0_HIGH_RANGE GPIO_AD0_LOW_RANGE Mode
0 0 GPIO_AD1_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_AD1_xx IO will work in low
range mode with supply voltage
in 1.71v-1.98v
1 0 GPIO_AD1_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
6 Reserved
—
5 GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
GPIO_AD0_LO
W_RANGE GPIO_AD0_HIGH_RANGE GPIO_AD0_LOW_RANGE Mode
0 0 GPIO_AD0_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_AD0_xx IO will work in low
range mode with supply voltage
in 1.71v-1.98v
1 0 GPIO_AD0_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
4 GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
GPIO_AD0_HIG
H_RANGE GPIO_AD0_HIGH_RANGE GPIO_AD0_LOW_RANGE Mode
0 0 GPIO_AD0_xx IO will work in
continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_AD0_xx IO will work in low
range mode with supply voltage
in 1.71v-1.98v
1 0 GPIO_AD0_xx IO will work in
high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
3 Reserved
—
2 GPIO_DISP_B2 IO bank supply voltage range selection
GPIO_DISP2_L
OW_RANGE GPIO_DISP_B2_HIGH_RANGE GPIO_DISP_B2_LOW_RANGE Mode
0 0 GPIO_DISP_B2_xx IO will work
in continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_DISP_B2_xx IO will work
in low range mode with supply
voltage in 1.71v-1.98v
1 0 GPIO_DISP_B2_xx IO will work
in high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
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Memory Map and register definition
Field Description
1 GPIO_DISP_B2 IO bank supply voltage range selection
GPIO_DISP2_H
IGH_RANGE GPIO_DISP_B2_HIGH_RANGE GPIO_DISP_B2_LOW_RANGE Mode
0 0 GPIO_DISP_B2_xx IO will work
in continuous range mode with
supply voltage in 1.71v-3.6v
0 1 GPIO_DISP_B2_xx IO will work
in low range mode with supply
voltage in 1.71v-1.98v
1 0 GPIO_DISP_B2_xx IO will work
in high range mode with supply
voltage in 3v-3.6v
1 1 Not allowed
0 Reserved
—
12.4.4.66 GPR70 General Purpose Register (GPR70)
GPR Register
12.4.4.66.1 Offset
Register Offset
GPR70 118h
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12.4.4.66.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EDMA_LPSR_STOP_REQ
FLEXSPI2_IPG_DOZE
FLEXSPI1_IPG_DOZE
FLEXIO2_IPG_DOZE
FLEXIO1_IPG_DOZE
ENET1G_IPG_DOZE
FLEXSPI2_STOP_RE
FLEXSPI1_STOP_RE
ENET1G_STOP_RE
ENET_IPG_DOZE
ENET_STOP_RE
DWP_LOCK
Reserved
DWP
W
Q
Q
Q
Q
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADC2_IPG_STOP_MODE
ADC1_IPG_STOP_MODE
EDMA_STOP_REQ
CAAM_STOP_REQ
CAN3_STOP_REQ
CAN2_STOP_REQ
CAN1_STOP_REQ
ADC2_STOP_REQ
ADC1_STOP_REQ
CAAM_IPG_DOZE
CAN3_IPG_DOZE
CAN2_IPG_DOZE
CAN1_IPG_DOZE
ADC2_IPG_DOZE
ADC1_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.66.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27 Reserved
—
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Memory Map and register definition
Field Description
26 FLEXSPI2 stop request
FLEXSPI2_STO 0: stop request off
P_REQ
1: stop request on
25 FLEXSPI2 doze mode
FLEXSPI2_IPG 0: not in doze mode
_DOZE
1: in doze mode
24 FLEXSPI1 stop request
FLEXSPI1_STO 0: stop request off
P_REQ
1: stop request on
23 FLEXSPI1 doze mode
FLEXSPI1_IPG 0: not in doze mode
_DOZE
1: in doze mode
22 FLEXIO2 doze mode
FLEXIO2_IPG_ 0: not in doze mode
DOZE
1: in doze mode
21 FLEXIO2 doze mode
FLEXIO1_IPG_ 0: not in doze mode
DOZE
1: in doze mode
20 ENET1G stop request
ENET1G_STOP 0: stop request off
_REQ
1: stop request on
19 ENET1G doze mode
ENET1G_IPG_ 0: not in doze mode
DOZE
1: in doze mode
18 ENET stop request
ENET_STOP_R 0: stop request off
EQ
1: stop request on
17 ENET doze mode
ENET_IPG_DO 0: not in doze mode
ZE
1: in doze mode
16 EDMA_LPSR stop request
EDMA_LPSR_S 0: stop request off
TOP_REQ
1: stop request on
15 EDMA stop request
EDMA_STOP_R 0: stop request off
EQ
1: stop request on
14 Reserved
—
13 CAN3 stop request
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
CAN3_STOP_R 0: stop request off
EQ
1: stop request on
12 CAN3 doze mode
CAN3_IPG_DO 0: not in doze mode
ZE
1: in doze mode
11 CAN2 stop request
CAN2_STOP_R 0: stop request off
EQ
1: stop request on
10 CAN2 doze mode
CAN2_IPG_DO 0: not in doze mode
ZE
1: in doze mode
9 CAN1 stop request
CAN1_STOP_R 0: stop request off
EQ
1: stop request on
8 CAN1 doze mode
CAN1_IPG_DO 0: not in doze mode
ZE
1: in doze mode
7 CAAM stop request
CAAM_STOP_R 0: stop request off
EQ
1: stop request on
6 CAN3 doze mode
CAAM_IPG_DO 0: not in doze mode
ZE
1: in doze mode
5 ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted.
ADC2_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 ADC2 stop request
ADC2_STOP_R 0: stop request off
EQ
1: stop request on
3 ADC2 doze mode
ADC2_IPG_DO 0: not in doze mode
ZE
1: in doze mode
2 ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted.
ADC1_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
1 ADC1 stop request
ADC1_STOP_R 0: stop request off
EQ
1: stop request on
0 ADC1 doze mode
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732
R
R
W
W
Bits
Bits
Reset
Reset
GPR71
LPI2C4_IPG_DOZE DWP_LOCK ZE
0
0
Field
15
31
12.4.4.67.2
12.4.4.67.1
LPI2C3_IPG_STOP_MODE
Register
0
0
GPR Register
14
30
LPI2C3_STOP_REQ DWP
0
0
13
29
Offset
LPI2C3_IPG_DOZE
11Ch
0
0
12
28
1: in doze mode
Diagram
Memory Map and register definition
ADC1_IPG_DO 0: not in doze mode
LPI2C2_IPG_STOP_MODE Reserved
0
0
11
27
LPI2C2_STOP_REQ LPSPI1_IPG_STOP_MODE
0
0
10
26
LPI2C2_IPG_DOZE LPSPI1_STOP_REQ
0
0
25
LPI2C1_IPG_STOP_MODE LPSPI1_IPG_DOZE
0
0
24
LPI2C1_STOP_REQ LPI2C6_IPG_STOP_MODE
0
0
LPI2C1_IPG_DOZE LPI2C6_STOP_REQ 23
Description
0
0
22
Offset
GPT6_IPG_DOZE LPI2C6_IPG_DOZE
0
0
21
GPT5_IPG_DOZE LPI2C5_IPG_STOP_MODE
0
0
20
12.4.4.67 GPR71 General Purpose Register (GPR71)
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GPT4_IPG_DOZE LPI2C5_STOP_REQ
0
0
19
GPT3_IPG_DOZE LPI2C5_IPG_DOZE
0
0
18
GPT2_IPG_DOZE LPI2C4_IPG_STOP_MODE
1
0
0
17
GPT1_IPG_DOZE LPI2C4_STOP_REQ
0
0
0
16
NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.4.67.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27 Reserved
—
26 LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted.
LPSPI1_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 LPSPI1 stop request
LPSPI1_STOP_ 0: stop request off
REQ
1: stop request on
24 LPSPI1 doze mode
LPSPI1_IPG_D 0: not in doze mode
OZE
1: in doze mode
23 LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted.
LPI2C6_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPI2C6 stop request
LPI2C6_STOP_ 0: stop request off
REQ
1: stop request on
21 LPI2C6 doze mode
LPI2C6_IPG_D 0: not in doze mode
OZE
1: in doze mode
20 LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted.
LPI2C5_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPI2C5 stop request
0: stop request off
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Memory Map and register definition
Field Description
LPI2C5_STOP_ 1: stop request on
REQ
18 LPI2C5 doze mode
LPI2C5_IPG_D 0: not in doze mode
OZE
1: in doze mode
17 LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted.
LPI2C4_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPI2C4 stop request
LPI2C4_STOP_ 0: stop request off
REQ
1: stop request on
15 LPI2C4 doze mode
LPI2C4_IPG_D 0: not in doze mode
OZE
1: in doze mode
14 LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted.
LPI2C3_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPI2C3 stop request
LPI2C3_STOP_ 0: stop request off
REQ
1: stop request on
12 LPI2C3 doze mode
LPI2C3_IPG_D 0: not in doze mode
OZE
1: in doze mode
11 LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted.
LPI2C2_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPI2C2 stop request
LPI2C2_STOP_ 0: stop request off
REQ
1: stop request on
9 LPI2C2 doze mode
LPI2C2_IPG_D 0: not in doze mode
OZE
1: in doze mode
8 LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted.
LPI2C1_IPG_ST 0 - This module is functional in Stop Mode
OP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPI2C1 stop request
LPI2C1_STOP_ 0: stop request off
REQ
1: stop request on
6 LPI2C1 doze mode
0: not in doze mode
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPI2C1_IPG_D 1: in doze mode
OZE
5 GPT6 doze mode
GPT6_IPG_DO 0: not in doze mode
ZE
1: in doze mode
4 GPT5 doze mode
GPT5_IPG_DO 0: not in doze mode
ZE
1: in doze mode
3 GPT4 doze mode
GPT4_IPG_DO 0: not in doze mode
ZE
1: in doze mode
2 GPT3 doze mode
GPT3_IPG_DO 0: not in doze mode
ZE
1: in doze mode
1 GPT2 doze mode
GPT2_IPG_DO 0: not in doze mode
ZE
1: in doze mode
0 GPT1 doze mode
GPT1_IPG_DO 0: not in doze mode
ZE
1: in doze mode
12.4.4.68 GPR72 General Purpose Register (GPR72)
GPR Register
12.4.4.68.1 Offset
Register Offset
GPR72 120h
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Memory Map and register definition
12.4.4.68.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART4_IPG_STOP_MODE
LPUART3_IPG_STOP_MODE
LPUART2_IPG_STOP_MODE
LPUART1_IPG_STOP_MODE
LPUART4_STOP_REQ
LPUART3_STOP_REQ
LPUART2_STOP_REQ
LPUART1_STOP_REQ
LPUART4_IPG_DOZE
LPUART3_IPG_DOZE
LPUART2_IPG_DOZE
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPSPI6_IPG_STOP_MODE
LPSPI5_IPG_STOP_MODE
LPSPI4_IPG_STOP_MODE
LPSPI3_IPG_STOP_MODE
LPSPI2_IPG_STOP_MODE
LPUART1_IPG_DOZE
LPSPI6_STOP_REQ
LPSPI5_STOP_REQ
LPSPI4_STOP_REQ
LPSPI3_STOP_REQ
LPSPI2_STOP_REQ
LPSPI6_IPG_DOZE
LPSPI5_IPG_DOZE
LPSPI4_IPG_DOZE
LPSPI3_IPG_DOZE
LPSPI2_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.68.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
27 Reserved
—
26 LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted.
LPUART4_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 LPUART4 stop request
LPUART4_STO 0: stop request off
P_REQ
1: stop request on
24 LPUART4 doze mode
LPUART4_IPG_ 0: not in doze mode
DOZE
1: in doze mode
23 LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted.
LPUART3_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPUART3 stop request
LPUART3_STO 0: stop request off
P_REQ
1: stop request on
21 LPUART3 doze mode
LPUART3_IPG_ 0: not in doze mode
DOZE
1: in doze mode
20 LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted.
LPUART2_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPUART2 stop request
LPUART2_STO 0: stop request off
P_REQ
1: stop request on
18 LPUART2 doze mode
LPUART2_IPG_ 0: not in doze mode
DOZE
1: in doze mode
17 LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted.
LPUART1_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPUART1 stop request
LPUART1_STO 0: stop request off
P_REQ
1: stop request on
15 LPUART1 doze mode
LPUART1_IPG_ 0: not in doze mode
DOZE
1: in doze mode
14 LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted.
Table continues on the next page...
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Memory Map and register definition
Field Description
LPSPI6_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPSPI6 stop request
LPSPI6_STOP_ 0: stop request off
REQ
1: stop request on
12 LPSPI6 doze mode
LPSPI6_IPG_D 0: not in doze mode
OZE
1: in doze mode
11 LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted.
LPSPI5_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPSPI5 stop request
LPSPI5_STOP_ 0: stop request off
REQ
1: stop request on
9 LPSPI5 doze mode
LPSPI5_IPG_D 0: not in doze mode
OZE
1: in doze mode
8 LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted.
LPSPI4_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPSPI4 stop request
LPSPI4_STOP_ 0: stop request off
REQ
1: stop request on
6 LPSPI4 doze mode
LPSPI4_IPG_D 0: not in doze mode
OZE
1: in doze mode
5 LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted.
LPSPI3_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 LPSPI3 stop request
LPSPI3_STOP_ 0: stop request off
REQ
1: stop request on
3 LPSPI3 doze mode
LPSPI3_IPG_D 0: not in doze mode
OZE
1: in doze mode
2 LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted.
LPSPI2_IPG_S 0 - This module is functional in Stop Mode
TOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
1 LPSPI2 stop request
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPSPI2_STOP_ 0: stop request off
REQ
1: stop request on
0 LPSPI2 doze mode
LPSPI2_IPG_D 0: not in doze mode
OZE
1: in doze mode
12.4.4.69 GPR73 General Purpose Register (GPR73)
GPR Register
12.4.4.69.1 Offset
Register Offset
GPR73 124h
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Memory Map and register definition
12.4.4.69.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART12_IPG_STOP_MODE
LPUART11_IPG_STOP_MODE
LPUART10_IPG_STOP_MODE
LPUART12_STOP_REQ
LPUART11_STOP_REQ
LPUART10_STOP_REQ
MIC_IPG_STOP_MODE
LPUART12_IPG_DOZE
LPUART11_IPG_DOZE
MIC_STOP_REQ
MIC_IPG_DOZE
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LPUART9_IPG_STOP_MODE
LPUART8_IPG_STOP_MODE
LPUART7_IPG_STOP_MODE
LPUART6_IPG_STOP_MODE
LPUART5_IPG_STOP_MODE
LPUART9_STOP_REQ
LPUART8_STOP_REQ
LPUART7_STOP_REQ
LPUART6_STOP_REQ
LPUART5_STOP_REQ
LPUART10_IPG_DOZE
LPUART9_IPG_DOZE
LPUART8_IPG_DOZE
LPUART7_IPG_DOZE
LPUART6_IPG_DOZE
LPUART5_IPG_DOZE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.69.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
11 - Both cores are forbidden
27 Reserved
—
26 MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted.
MIC_IPG_STOP 0 - This module is functional in Stop Mode
_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
25 MIC stop request
MIC_STOP_RE 0: stop request off
Q
1: stop request on
24 MIC doze mode
MIC_IPG_DOZE 0: not in doze mode
1: in doze mode
23 LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted.
LPUART12_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
22 LPUART12 stop request
LPUART12_ST 0: stop request off
OP_REQ
1: stop request on
21 LPUART12 doze mode
LPUART12_IPG 0: not in doze mode
_DOZE
1: in doze mode
20 LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted.
LPUART11_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
19 LPUART11 stop request
LPUART11_ST 0: stop request off
OP_REQ
1: stop request on
18 LPUART11 doze mode
LPUART11_IPG 0: not in doze mode
_DOZE
1: in doze mode
17 LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted.
LPUART10_IPG 0 - This module is functional in Stop Mode
_STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
16 LPUART10 stop request
LPUART10_ST 0: stop request off
OP_REQ
1: stop request on
15 LPUART10 doze mode
LPUART10_IPG 0: not in doze mode
_DOZE
1: in doze mode
Table continues on the next page...
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Memory Map and register definition
Field Description
14 LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted.
LPUART9_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
13 LPUART9 stop request
LPUART9_STO 0: stop request off
P_REQ
1: stop request on
12 LPUART9 doze mode
LPUART9_IPG_ 0: not in doze mode
DOZE
1: in doze mode
11 LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted.
LPUART8_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
10 LPUART8 stop request
LPUART8_STO 0: stop request off
P_REQ
1: stop request on
9 LPUART8 doze mode
LPUART8_IPG_ 0: not in doze mode
DOZE
1: in doze mode
8 LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted.
LPUART7_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
7 LPUART7 stop request
LPUART7_STO 0: stop request off
P_REQ
1: stop request on
6 LPUART7 doze mode
LPUART7_IPG_ 0: not in doze mode
DOZE
1: in doze mode
5 LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted.
LPUART6_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
4 LPUART6 stop request
LPUART6_STO 0: stop request off
P_REQ
1: stop request on
3 LPUART6 doze mode
LPUART6_IPG_ 0: not in doze mode
DOZE
1: in doze mode
2 LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted.
LPUART5_IPG_ 0 - This module is functional in Stop Mode
STOP_MODE
1 - This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
1 LPUART5 stop request
LPUART5_STO 0: stop request off
P_REQ
1: stop request on
0 LPUART5 doze mode
LPUART5_IPG_ 0: not in doze mode
DOZE
1: in doze mode
12.4.4.70 GPR74 General Purpose Register (GPR74)
GPR Register
12.4.4.70.1 Offset
Register Offset
GPR74 128h
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12.4.4.70.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLEXIO2_STOP_REQ_BUS
FLEXIO2_STOP_REQ_PE
DWP_LOCK
Reserved
DWP
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FLEXIO1_STOP_REQ_BUS
0
FLEXIO1_STOP_REQ_PE
SNVS_HP_IPG_DOZE
SNVS_HP_STOP_RE
WDOG2_IPG_DOZE
WDOG1_IPG_DOZE
SAI4_STOP_REQ
SAI3_STOP_REQ
SAI2_STOP_REQ
SAI1_STOP_REQ
PIT2_STOP_REQ
PIT1_STOP_REQ
SIM2_IPG_DOZE
SIM1_IPG_DOZE
SEMC_STOP_RE
W
Q
Q
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.70.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 27:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-18 Reserved
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
—
17 FLEXIO2 peripheral clock domain stop request
FLEXIO2_STOP 0: stop request off
_REQ_PER
1: stop request on
16 FLEXIO2 bus clock domain stop request
FLEXIO2_STOP 0: stop request off
_REQ_BUS
1: stop request on
15 FLEXIO1 peripheral clock domain stop request
FLEXIO1_STOP 0: stop request off
_REQ_PER
1: stop request on
14 FLEXIO1 bus clock domain stop request
FLEXIO1_STOP 0: stop request off
_REQ_BUS
1: stop request on
13 SAI4 stop request
SAI4_STOP_RE 0: stop request off
Q
1: stop request on
12 SAI3 stop request
SAI3_STOP_RE 0: stop request off
Q
1: stop request on
11 SAI2 stop request
SAI2_STOP_RE 0: stop request off
Q
1: stop request on
10 SAI1 stop request
SAI1_STOP_RE 0: stop request off
Q
1: stop request on
9 WDOG2 doze mode
WDOG2_IPG_D 0: not in doze mode
OZE
1: in doze mode
8 WDOG1 doze mode
WDOG1_IPG_D 0: not in doze mode
OZE
1: in doze mode
7 SNVS_HP stop request
SNVS_HP_STO 0: stop request off
P_REQ
1: stop request on
6 SNVS_HP doze mode
SNVS_HP_IPG 0: not in doze mode
_DOZE
1: in doze mode
5 SIM2 doze mode
SIM2_IPG_DOZ 0: not in doze mode
E
Table continues on the next page...
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Memory Map and register definition
Field Description
1: in doze mode
4 SIM1 doze mode
SIM1_IPG_DOZ 0: not in doze mode
E
1: in doze mode
3 SEMC stop request
SEMC_STOP_R 0: stop request off
EQ
1: stop request on
2 PIT2 stop request
PIT2_STOP_RE 0: stop request off
Q
1: stop request on
1 PIT1 stop request
PIT1_STOP_RE 0: stop request off
Q
1: stop request on
0 Reserved
—
12.4.4.71 GPR75 General Purpose Register (GPR75)
GPR Register
12.4.4.71.1 Offset
Register Offset
GPR75 12Ch
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.4.71.2 Diagram
Bits 31
LPUART8_STOP_ACK 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPUART7_STOP_ACK
LPUART6_STOP_ACK
LPUART5_STOP_ACK
LPUART4_STOP_ACK
LPUART3_STOP_ACK
LPUART2_STOP_ACK
LPUART1_STOP_ACK
LPSPI6_STOP_ACK
LPSPI5_STOP_ACK
LPSPI4_STOP_ACK
LPSPI3_STOP_ACK
LPSPI2_STOP_ACK
LPSPI1_STOP_ACK
LPI2C6_STOP_ACK
LPI2C5_STOP_ACK
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EDMA_LPSR_STOP_ACK
FLEXSPI2_STOP_ACK
FLEXSPI1_STOP_ACK
ENET1G_STOP_ACK
LPI2C4_STOP_ACK
LPI2C3_STOP_ACK
LPI2C2_STOP_ACK
LPI2C1_STOP_ACK
ENET_STOP_ACK
EDMA_STOP_ACK
CAAM_STOP_ACK
CAN3_STOP_ACK
CAN2_STOP_ACK
CAN1_STOP_ACK
ADC2_STOP_ACK
ADC1_STOP_ACK
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.71.3 Fields
Field Description
31 LPUART8 stop acknowledge
LPUART8_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
30 LPUART7 stop acknowledge
LPUART7_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
29 LPUART6 stop acknowledge
LPUART6_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
28 LPUART5 stop acknowledge
LPUART5_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
27 LPUART4 stop acknowledge
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Memory Map and register definition
Field Description
LPUART4_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
26 LPUART3 stop acknowledge
LPUART3_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
25 LPUART2 stop acknowledge
LPUART2_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
24 LPUART1 stop acknowledge
LPUART1_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
23 LPSPI6 stop acknowledge
LPSPI6_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
22 LPSPI5 stop acknowledge
LPSPI5_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
21 LPSPI4 stop acknowledge
LPSPI4_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
20 LPSPI3 stop acknowledge
LPSPI3_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
19 LPSPI2 stop acknowledge
LPSPI2_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
18 LPSPI1 stop acknowledge
LPSPI1_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
17 LPI2C6 stop acknowledge
LPI2C6_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
16 LPI2C5 stop acknowledge
LPI2C5_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
15 LPI2C4 stop acknowledge
LPI2C4_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
14 LPI2C3 stop acknowledge
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPI2C3_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
13 LPI2C2 stop acknowledge
LPI2C2_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
12 LPI2C1 stop acknowledge
LPI2C1_STOP_ 0: stop acknowledge is not asserted
ACK
1: stop acknowledge is asserted (the module is in Stop mode)
11 FLEXSPI2 stop acknowledge
FLEXSPI2_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
10 FLEXSPI1 stop acknowledge
FLEXSPI1_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
9 ENET1G stop acknowledge
ENET1G_STOP 0: stop acknowledge is not asserted
_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
8 ENET stop acknowledge
ENET_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
7 EDMA_LPSR stop acknowledge
EDMA_LPSR_S 0: stop acknowledge is not asserted
TOP_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
6 EDMA stop acknowledge
EDMA_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
5 CAN3 stop acknowledge
CAN3_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
4 CAN2 stop acknowledge
CAN2_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
3 CAN1 stop acknowledge
CAN1_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
2 CAAM stop acknowledge
CAAM_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
1 ADC2 stop acknowledge
Table continues on the next page...
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Memory Map and register definition
Field Description
ADC2_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
0 ADC1 stop acknowledge
ADC1_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
12.4.4.72 GPR76 General Purpose Register (GPR76)
GPR Register
12.4.4.72.1 Offset
Register Offset
GPR76 130h
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.4.72.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLEXIO2_STOP_ACK_PER
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEXIO1_STOP_ACK_PER
FLEXIO2_STOP_ACK_BUS
FLEXIO1_STOP_ACK_BUS
SNVS_HP_STOP_ACK
LPUART12_STOP_ACK
LPUART11_STOP_ACK
LPUART10_STOP_ACK
LPUART9_STOP_ACK
SEMC_STOP_ACK
SAI4_STOP_ACK
SAI3_STOP_ACK
SAI2_STOP_ACK
SAI1_STOP_ACK
PIT2_STOP_ACK
PIT1_STOP_ACK
MIC_STOP_ACK
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.4.72.3 Fields
Field Description
31-17 Reserved
—
16 FLEXIO2 stop acknowledge of peripheral clock domain
FLEXIO2_STOP 0: stop acknowledge is not asserted
_ACK_PER
1: stop acknowledge is asserted (the module is in Stop mode)
15 FLEXIO2 stop acknowledge of bus clock domain
FLEXIO2_STOP 0: stop acknowledge is not asserted
_ACK_BUS
1: stop acknowledge is asserted (the module is in Stop mode)
14 FLEXIO1 stop acknowledge of peripheral clock domain
FLEXIO1_STOP 0: stop acknowledge is not asserted
_ACK_PER
1: stop acknowledge is asserted (the module is in Stop mode)
13 FLEXIO1 stop acknowledge of bus clock domain
Table continues on the next page...
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Memory Map and register definition
Field Description
FLEXIO1_STOP 0: stop acknowledge is not asserted
_ACK_BUS
1: stop acknowledge is asserted (the module is in Stop mode)
12 SAI4 stop acknowledge
SAI4_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
11 SAI3 stop acknowledge
SAI3_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
10 SAI2 stop acknowledge
SAI2_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
9 SAI1 stop acknowledge
SAI1_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
8 SNVS_HP stop acknowledge
SNVS_HP_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
7 SEMC stop acknowledge
SEMC_STOP_A 0: stop acknowledge is not asserted
CK
1: stop acknowledge is asserted (the module is in Stop mode)
6 PIT2 stop acknowledge
PIT2_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
5 PIT1 stop acknowledge
PIT1_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
4 MIC stop acknowledge
MIC_STOP_AC 0: stop acknowledge is not asserted
K
1: stop acknowledge is asserted (the module is in Stop mode)
3 LPUART12 stop acknowledge
LPUART12_ST 0: stop acknowledge is not asserted
OP_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
2 LPUART11 stop acknowledge
LPUART11_ST 0: stop acknowledge is not asserted
OP_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
1 LPUART10 stop acknowledge
LPUART10_ST 0: stop acknowledge is not asserted
OP_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
0 LPUART9 stop acknowledge
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
LPUART9_STO 0: stop acknowledge is not asserted
P_ACK
1: stop acknowledge is asserted (the module is in Stop mode)
12.4.5 IOMUXC register descriptions
12.4.5.1 iomuxc memory map
IOMUXC base address: 400E_8000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
10 SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_00)
14 SW_MUX_CTL_PAD_GPIO_EMC_B1_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_01)
18 SW_MUX_CTL_PAD_GPIO_EMC_B1_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_02)
1C SW_MUX_CTL_PAD_GPIO_EMC_B1_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_03)
20 SW_MUX_CTL_PAD_GPIO_EMC_B1_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_04)
24 SW_MUX_CTL_PAD_GPIO_EMC_B1_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_05)
28 SW_MUX_CTL_PAD_GPIO_EMC_B1_06 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_06)
2C SW_MUX_CTL_PAD_GPIO_EMC_B1_07 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_07)
30 SW_MUX_CTL_PAD_GPIO_EMC_B1_08 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_08)
34 SW_MUX_CTL_PAD_GPIO_EMC_B1_09 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_09)
38 SW_MUX_CTL_PAD_GPIO_EMC_B1_10 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_10)
3C SW_MUX_CTL_PAD_GPIO_EMC_B1_11 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_11)
40 SW_MUX_CTL_PAD_GPIO_EMC_B1_12 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_12)
44 SW_MUX_CTL_PAD_GPIO_EMC_B1_13 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_13)
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
48 SW_MUX_CTL_PAD_GPIO_EMC_B1_14 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_14)
4C SW_MUX_CTL_PAD_GPIO_EMC_B1_15 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_15)
50 SW_MUX_CTL_PAD_GPIO_EMC_B1_16 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_16)
54 SW_MUX_CTL_PAD_GPIO_EMC_B1_17 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_17)
58 SW_MUX_CTL_PAD_GPIO_EMC_B1_18 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_18)
5C SW_MUX_CTL_PAD_GPIO_EMC_B1_19 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_19)
60 SW_MUX_CTL_PAD_GPIO_EMC_B1_20 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_20)
64 SW_MUX_CTL_PAD_GPIO_EMC_B1_21 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_21)
68 SW_MUX_CTL_PAD_GPIO_EMC_B1_22 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_22)
6C SW_MUX_CTL_PAD_GPIO_EMC_B1_23 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_23)
70 SW_MUX_CTL_PAD_GPIO_EMC_B1_24 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_24)
74 SW_MUX_CTL_PAD_GPIO_EMC_B1_25 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_25)
78 SW_MUX_CTL_PAD_GPIO_EMC_B1_26 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_26)
7C SW_MUX_CTL_PAD_GPIO_EMC_B1_27 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_27)
80 SW_MUX_CTL_PAD_GPIO_EMC_B1_28 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_28)
84 SW_MUX_CTL_PAD_GPIO_EMC_B1_29 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_29)
88 SW_MUX_CTL_PAD_GPIO_EMC_B1_30 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_30)
8C SW_MUX_CTL_PAD_GPIO_EMC_B1_31 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_31)
90 SW_MUX_CTL_PAD_GPIO_EMC_B1_32 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_32)
94 SW_MUX_CTL_PAD_GPIO_EMC_B1_33 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_33)
98 SW_MUX_CTL_PAD_GPIO_EMC_B1_34 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_34)
9C SW_MUX_CTL_PAD_GPIO_EMC_B1_35 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_35)
A0 SW_MUX_CTL_PAD_GPIO_EMC_B1_36 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_36)
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
A4 SW_MUX_CTL_PAD_GPIO_EMC_B1_37 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_37)
A8 SW_MUX_CTL_PAD_GPIO_EMC_B1_38 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_38)
AC SW_MUX_CTL_PAD_GPIO_EMC_B1_39 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_39)
B0 SW_MUX_CTL_PAD_GPIO_EMC_B1_40 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_40)
B4 SW_MUX_CTL_PAD_GPIO_EMC_B1_41 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B1_41)
B8 SW_MUX_CTL_PAD_GPIO_EMC_B2_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_00)
BC SW_MUX_CTL_PAD_GPIO_EMC_B2_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_01)
C0 SW_MUX_CTL_PAD_GPIO_EMC_B2_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_02)
C4 SW_MUX_CTL_PAD_GPIO_EMC_B2_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_03)
C8 SW_MUX_CTL_PAD_GPIO_EMC_B2_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_04)
CC SW_MUX_CTL_PAD_GPIO_EMC_B2_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_05)
D0 SW_MUX_CTL_PAD_GPIO_EMC_B2_06 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_06)
D4 SW_MUX_CTL_PAD_GPIO_EMC_B2_07 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_07)
D8 SW_MUX_CTL_PAD_GPIO_EMC_B2_08 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_08)
DC SW_MUX_CTL_PAD_GPIO_EMC_B2_09 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_09)
E0 SW_MUX_CTL_PAD_GPIO_EMC_B2_10 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_10)
E4 SW_MUX_CTL_PAD_GPIO_EMC_B2_11 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_11)
E8 SW_MUX_CTL_PAD_GPIO_EMC_B2_12 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_12)
EC SW_MUX_CTL_PAD_GPIO_EMC_B2_13 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_13)
F0 SW_MUX_CTL_PAD_GPIO_EMC_B2_14 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_14)
F4 SW_MUX_CTL_PAD_GPIO_EMC_B2_15 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_15)
F8 SW_MUX_CTL_PAD_GPIO_EMC_B2_16 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_16)
FC SW_MUX_CTL_PAD_GPIO_EMC_B2_17 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_17)
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
100 SW_MUX_CTL_PAD_GPIO_EMC_B2_18 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_18)
104 SW_MUX_CTL_PAD_GPIO_EMC_B2_19 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_19)
108 SW_MUX_CTL_PAD_GPIO_EMC_B2_20 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_EMC_B2_20)
10C SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_00)
110 SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_01)
114 SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_02)
118 SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_03)
11C SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_04)
120 SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_05)
124 SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_06)
128 SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_07)
12C SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_08)
130 SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_09)
134 SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_10)
138 SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_11)
13C SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_12)
140 SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_13)
144 SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_14)
148 SW_MUX_CTL_PAD_GPIO_AD_15 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_15)
14C SW_MUX_CTL_PAD_GPIO_AD_16 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_16)
150 SW_MUX_CTL_PAD_GPIO_AD_17 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_17)
154 SW_MUX_CTL_PAD_GPIO_AD_18 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_18)
158 SW_MUX_CTL_PAD_GPIO_AD_19 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_19)
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
15C SW_MUX_CTL_PAD_GPIO_AD_20 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_20)
160 SW_MUX_CTL_PAD_GPIO_AD_21 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_21)
164 SW_MUX_CTL_PAD_GPIO_AD_22 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_22)
168 SW_MUX_CTL_PAD_GPIO_AD_23 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_23)
16C SW_MUX_CTL_PAD_GPIO_AD_24 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_24)
170 SW_MUX_CTL_PAD_GPIO_AD_25 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_25)
174 SW_MUX_CTL_PAD_GPIO_AD_26 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_26)
178 SW_MUX_CTL_PAD_GPIO_AD_27 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_27)
17C SW_MUX_CTL_PAD_GPIO_AD_28 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_28)
180 SW_MUX_CTL_PAD_GPIO_AD_29 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_29)
184 SW_MUX_CTL_PAD_GPIO_AD_30 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_30)
188 SW_MUX_CTL_PAD_GPIO_AD_31 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_31)
18C SW_MUX_CTL_PAD_GPIO_AD_32 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_32)
190 SW_MUX_CTL_PAD_GPIO_AD_33 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_33)
194 SW_MUX_CTL_PAD_GPIO_AD_34 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_34)
198 SW_MUX_CTL_PAD_GPIO_AD_35 SW MUX Control Register (SW_ 32 RW 0000_0005
MUX_CTL_PAD_GPIO_AD_35)
19C SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_00)
1A0 SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_01)
1A4 SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_02)
1A8 SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_03)
1AC SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_04)
1B0 SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B1_05)
1B4 SW_MUX_CTL_PAD_GPIO_SD_B2_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_00)
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1B8 SW_MUX_CTL_PAD_GPIO_SD_B2_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_01)
1BC SW_MUX_CTL_PAD_GPIO_SD_B2_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_02)
1C0 SW_MUX_CTL_PAD_GPIO_SD_B2_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_03)
1C4 SW_MUX_CTL_PAD_GPIO_SD_B2_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_04)
1C8 SW_MUX_CTL_PAD_GPIO_SD_B2_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_05)
1CC SW_MUX_CTL_PAD_GPIO_SD_B2_06 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_06)
1D0 SW_MUX_CTL_PAD_GPIO_SD_B2_07 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_07)
1D4 SW_MUX_CTL_PAD_GPIO_SD_B2_08 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_08)
1D8 SW_MUX_CTL_PAD_GPIO_SD_B2_09 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_09)
1DC SW_MUX_CTL_PAD_GPIO_SD_B2_10 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_10)
1E0 SW_MUX_CTL_PAD_GPIO_SD_B2_11 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_SD_B2_11)
1E4 SW_MUX_CTL_PAD_GPIO_DISP_B1_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_00)
1E8 SW_MUX_CTL_PAD_GPIO_DISP_B1_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_01)
1EC SW_MUX_CTL_PAD_GPIO_DISP_B1_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_02)
1F0 SW_MUX_CTL_PAD_GPIO_DISP_B1_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_03)
1F4 SW_MUX_CTL_PAD_GPIO_DISP_B1_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_04)
1F8 SW_MUX_CTL_PAD_GPIO_DISP_B1_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_05)
1FC SW_MUX_CTL_PAD_GPIO_DISP_B1_06 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_06)
200 SW_MUX_CTL_PAD_GPIO_DISP_B1_07 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_07)
204 SW_MUX_CTL_PAD_GPIO_DISP_B1_08 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_08)
208 SW_MUX_CTL_PAD_GPIO_DISP_B1_09 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_09)
20C SW_MUX_CTL_PAD_GPIO_DISP_B1_10 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_10)
210 SW_MUX_CTL_PAD_GPIO_DISP_B1_11 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B1_11)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
758 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
214 SW_MUX_CTL_PAD_GPIO_DISP_B2_00 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_00)
218 SW_MUX_CTL_PAD_GPIO_DISP_B2_01 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_01)
21C SW_MUX_CTL_PAD_GPIO_DISP_B2_02 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_02)
220 SW_MUX_CTL_PAD_GPIO_DISP_B2_03 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_03)
224 SW_MUX_CTL_PAD_GPIO_DISP_B2_04 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_04)
228 SW_MUX_CTL_PAD_GPIO_DISP_B2_05 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_05)
22C SW_MUX_CTL_PAD_GPIO_DISP_B2_06 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_06)
230 SW_MUX_CTL_PAD_GPIO_DISP_B2_07 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_07)
234 SW_MUX_CTL_PAD_GPIO_DISP_B2_08 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_08)
238 SW_MUX_CTL_PAD_GPIO_DISP_B2_09 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_09)
23C SW_MUX_CTL_PAD_GPIO_DISP_B2_10 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_10)
240 SW_MUX_CTL_PAD_GPIO_DISP_B2_11 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_11)
244 SW_MUX_CTL_PAD_GPIO_DISP_B2_12 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_12)
248 SW_MUX_CTL_PAD_GPIO_DISP_B2_13 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_13)
24C SW_MUX_CTL_PAD_GPIO_DISP_B2_14 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_14)
250 SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register 32 RW 0000_0005
(SW_MUX_CTL_PAD_GPIO_DISP_B2_15)
254 SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_00)
258 SW_PAD_CTL_PAD_GPIO_EMC_B1_01 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_01)
25C SW_PAD_CTL_PAD_GPIO_EMC_B1_02 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_02)
260 SW_PAD_CTL_PAD_GPIO_EMC_B1_03 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_03)
264 SW_PAD_CTL_PAD_GPIO_EMC_B1_04 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_04)
268 SW_PAD_CTL_PAD_GPIO_EMC_B1_05 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_05)
26C SW_PAD_CTL_PAD_GPIO_EMC_B1_06 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_06)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 759
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
270 SW_PAD_CTL_PAD_GPIO_EMC_B1_07 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_07)
274 SW_PAD_CTL_PAD_GPIO_EMC_B1_08 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_08)
278 SW_PAD_CTL_PAD_GPIO_EMC_B1_09 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_09)
27C SW_PAD_CTL_PAD_GPIO_EMC_B1_10 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_10)
280 SW_PAD_CTL_PAD_GPIO_EMC_B1_11 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_11)
284 SW_PAD_CTL_PAD_GPIO_EMC_B1_12 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_12)
288 SW_PAD_CTL_PAD_GPIO_EMC_B1_13 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_13)
28C SW_PAD_CTL_PAD_GPIO_EMC_B1_14 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_14)
290 SW_PAD_CTL_PAD_GPIO_EMC_B1_15 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_15)
294 SW_PAD_CTL_PAD_GPIO_EMC_B1_16 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_16)
298 SW_PAD_CTL_PAD_GPIO_EMC_B1_17 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_17)
29C SW_PAD_CTL_PAD_GPIO_EMC_B1_18 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_18)
2A0 SW_PAD_CTL_PAD_GPIO_EMC_B1_19 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_19)
2A4 SW_PAD_CTL_PAD_GPIO_EMC_B1_20 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_20)
2A8 SW_PAD_CTL_PAD_GPIO_EMC_B1_21 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_21)
2AC SW_PAD_CTL_PAD_GPIO_EMC_B1_22 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_22)
2B0 SW_PAD_CTL_PAD_GPIO_EMC_B1_23 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_23)
2B4 SW_PAD_CTL_PAD_GPIO_EMC_B1_24 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_24)
2B8 SW_PAD_CTL_PAD_GPIO_EMC_B1_25 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_25)
2BC SW_PAD_CTL_PAD_GPIO_EMC_B1_26 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_26)
2C0 SW_PAD_CTL_PAD_GPIO_EMC_B1_27 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_27)
2C4 SW_PAD_CTL_PAD_GPIO_EMC_B1_28 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_28)
2C8 SW_PAD_CTL_PAD_GPIO_EMC_B1_29 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_29)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
760 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
2CC SW_PAD_CTL_PAD_GPIO_EMC_B1_30 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_30)
2D0 SW_PAD_CTL_PAD_GPIO_EMC_B1_31 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_31)
2D4 SW_PAD_CTL_PAD_GPIO_EMC_B1_32 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_32)
2D8 SW_PAD_CTL_PAD_GPIO_EMC_B1_33 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_33)
2DC SW_PAD_CTL_PAD_GPIO_EMC_B1_34 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_34)
2E0 SW_PAD_CTL_PAD_GPIO_EMC_B1_35 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_35)
2E4 SW_PAD_CTL_PAD_GPIO_EMC_B1_36 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_36)
2E8 SW_PAD_CTL_PAD_GPIO_EMC_B1_37 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_37)
2EC SW_PAD_CTL_PAD_GPIO_EMC_B1_38 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_38)
2F0 SW_PAD_CTL_PAD_GPIO_EMC_B1_39 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_39)
2F4 SW_PAD_CTL_PAD_GPIO_EMC_B1_40 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_40)
2F8 SW_PAD_CTL_PAD_GPIO_EMC_B1_41 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B1_41)
2FC SW_PAD_CTL_PAD_GPIO_EMC_B2_00 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_00)
300 SW_PAD_CTL_PAD_GPIO_EMC_B2_01 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_01)
304 SW_PAD_CTL_PAD_GPIO_EMC_B2_02 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_02)
308 SW_PAD_CTL_PAD_GPIO_EMC_B2_03 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_03)
30C SW_PAD_CTL_PAD_GPIO_EMC_B2_04 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_04)
310 SW_PAD_CTL_PAD_GPIO_EMC_B2_05 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_05)
314 SW_PAD_CTL_PAD_GPIO_EMC_B2_06 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_06)
318 SW_PAD_CTL_PAD_GPIO_EMC_B2_07 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_07)
31C SW_PAD_CTL_PAD_GPIO_EMC_B2_08 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_EMC_B2_08)
320 SW_PAD_CTL_PAD_GPIO_EMC_B2_09 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_09)
324 SW_PAD_CTL_PAD_GPIO_EMC_B2_10 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_10)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 761
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
328 SW_PAD_CTL_PAD_GPIO_EMC_B2_11 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_EMC_B2_11)
32C SW_PAD_CTL_PAD_GPIO_EMC_B2_12 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_12)
330 SW_PAD_CTL_PAD_GPIO_EMC_B2_13 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_13)
334 SW_PAD_CTL_PAD_GPIO_EMC_B2_14 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_14)
338 SW_PAD_CTL_PAD_GPIO_EMC_B2_15 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_15)
33C SW_PAD_CTL_PAD_GPIO_EMC_B2_16 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_16)
340 SW_PAD_CTL_PAD_GPIO_EMC_B2_17 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_17)
344 SW_PAD_CTL_PAD_GPIO_EMC_B2_18 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_18)
348 SW_PAD_CTL_PAD_GPIO_EMC_B2_19 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_19)
34C SW_PAD_CTL_PAD_GPIO_EMC_B2_20 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_EMC_B2_20)
350 SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_00)
354 SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_01)
358 SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_02)
35C SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_03)
360 SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_04)
364 SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_05)
368 SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_06)
36C SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_07)
370 SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_08)
374 SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_09)
378 SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_10)
37C SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_11)
380 SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_12)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
762 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
384 SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_13)
388 SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_14)
38C SW_PAD_CTL_PAD_GPIO_AD_15 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_15)
390 SW_PAD_CTL_PAD_GPIO_AD_16 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_16)
394 SW_PAD_CTL_PAD_GPIO_AD_17 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_17)
398 SW_PAD_CTL_PAD_GPIO_AD_18 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_18)
39C SW_PAD_CTL_PAD_GPIO_AD_19 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_19)
3A0 SW_PAD_CTL_PAD_GPIO_AD_20 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_20)
3A4 SW_PAD_CTL_PAD_GPIO_AD_21 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_21)
3A8 SW_PAD_CTL_PAD_GPIO_AD_22 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_22)
3AC SW_PAD_CTL_PAD_GPIO_AD_23 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_23)
3B0 SW_PAD_CTL_PAD_GPIO_AD_24 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_24)
3B4 SW_PAD_CTL_PAD_GPIO_AD_25 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_25)
3B8 SW_PAD_CTL_PAD_GPIO_AD_26 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_26)
3BC SW_PAD_CTL_PAD_GPIO_AD_27 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_27)
3C0 SW_PAD_CTL_PAD_GPIO_AD_28 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_28)
3C4 SW_PAD_CTL_PAD_GPIO_AD_29 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_29)
3C8 SW_PAD_CTL_PAD_GPIO_AD_30 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_30)
3CC SW_PAD_CTL_PAD_GPIO_AD_31 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_31)
3D0 SW_PAD_CTL_PAD_GPIO_AD_32 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_32)
3D4 SW_PAD_CTL_PAD_GPIO_AD_33 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_33)
3D8 SW_PAD_CTL_PAD_GPIO_AD_34 SW PAD Control Register (SW_ 32 RW 0000_0006
PAD_CTL_PAD_GPIO_AD_34)
3DC SW_PAD_CTL_PAD_GPIO_AD_35 SW PAD Control Register (SW_ 32 RW 0000_000E
PAD_CTL_PAD_GPIO_AD_35)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 763
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
3E0 SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B1_00)
3E4 SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B1_01)
3E8 SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B1_02)
3EC SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B1_03)
3F0 SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B1_04)
3F4 SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B1_05)
3F8 SW_PAD_CTL_PAD_GPIO_SD_B2_00 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_00)
3FC SW_PAD_CTL_PAD_GPIO_SD_B2_01 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_01)
400 SW_PAD_CTL_PAD_GPIO_SD_B2_02 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_02)
404 SW_PAD_CTL_PAD_GPIO_SD_B2_03 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_03)
408 SW_PAD_CTL_PAD_GPIO_SD_B2_04 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B2_04)
40C SW_PAD_CTL_PAD_GPIO_SD_B2_05 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B2_05)
410 SW_PAD_CTL_PAD_GPIO_SD_B2_06 SW PAD Control Register 32 RW 0000_0004
(SW_PAD_CTL_PAD_GPIO_SD_B2_06)
414 SW_PAD_CTL_PAD_GPIO_SD_B2_07 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_07)
418 SW_PAD_CTL_PAD_GPIO_SD_B2_08 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_08)
41C SW_PAD_CTL_PAD_GPIO_SD_B2_09 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_09)
420 SW_PAD_CTL_PAD_GPIO_SD_B2_10 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_10)
424 SW_PAD_CTL_PAD_GPIO_SD_B2_11 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_SD_B2_11)
428 SW_PAD_CTL_PAD_GPIO_DISP_B1_00 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_00)
42C SW_PAD_CTL_PAD_GPIO_DISP_B1_01 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_01)
430 SW_PAD_CTL_PAD_GPIO_DISP_B1_02 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_02)
434 SW_PAD_CTL_PAD_GPIO_DISP_B1_03 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_03)
438 SW_PAD_CTL_PAD_GPIO_DISP_B1_04 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_04)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
764 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
43C SW_PAD_CTL_PAD_GPIO_DISP_B1_05 SW PAD Control Register 32 RW 0000_0008
(SW_PAD_CTL_PAD_GPIO_DISP_B1_05)
440 SW_PAD_CTL_PAD_GPIO_DISP_B1_06 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_06)
444 SW_PAD_CTL_PAD_GPIO_DISP_B1_07 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_07)
448 SW_PAD_CTL_PAD_GPIO_DISP_B1_08 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_08)
44C SW_PAD_CTL_PAD_GPIO_DISP_B1_09 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_09)
450 SW_PAD_CTL_PAD_GPIO_DISP_B1_10 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_10)
454 SW_PAD_CTL_PAD_GPIO_DISP_B1_11 SW PAD Control Register 32 RW 0000_000C
(SW_PAD_CTL_PAD_GPIO_DISP_B1_11)
458 SW_PAD_CTL_PAD_GPIO_DISP_B2_00 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_00)
45C SW_PAD_CTL_PAD_GPIO_DISP_B2_01 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_01)
460 SW_PAD_CTL_PAD_GPIO_DISP_B2_02 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_02)
464 SW_PAD_CTL_PAD_GPIO_DISP_B2_03 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_03)
468 SW_PAD_CTL_PAD_GPIO_DISP_B2_04 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_04)
46C SW_PAD_CTL_PAD_GPIO_DISP_B2_05 SW PAD Control Register 32 RW 0000_0002
(SW_PAD_CTL_PAD_GPIO_DISP_B2_05)
470 SW_PAD_CTL_PAD_GPIO_DISP_B2_06 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_06)
474 SW_PAD_CTL_PAD_GPIO_DISP_B2_07 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_07)
478 SW_PAD_CTL_PAD_GPIO_DISP_B2_08 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_08)
47C SW_PAD_CTL_PAD_GPIO_DISP_B2_09 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_09)
480 SW_PAD_CTL_PAD_GPIO_DISP_B2_10 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_10)
484 SW_PAD_CTL_PAD_GPIO_DISP_B2_11 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_11)
488 SW_PAD_CTL_PAD_GPIO_DISP_B2_12 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_12)
48C SW_PAD_CTL_PAD_GPIO_DISP_B2_13 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_13)
490 SW_PAD_CTL_PAD_GPIO_DISP_B2_14 SW PAD Control Register 32 RW 0000_0006
(SW_PAD_CTL_PAD_GPIO_DISP_B2_14)
494 SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register 32 RW 0000_000E
(SW_PAD_CTL_PAD_GPIO_DISP_B2_15)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 765
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
498 FLEXCAN1_RX_SELECT_INPUT DAISY Register (FLEXCAN1_RX_ 32 RW 0000_0000
SELECT_INPUT)
49C FLEXCAN2_RX_SELECT_INPUT DAISY Register (FLEXCAN2_RX_ 32 RW 0000_0000
SELECT_INPUT)
4A0 CCM_ENET_QOS_REF_CLK_SELECT_INPUT DAISY Register 32 RW 0000_0000
(CCM_ENET_QOS_REF_CLK_SELECT_INPUT)
4A4 CCM_ENET_QOS_TX_CLK_SELECT_INPUT DAISY Register 32 RW 0000_0000
(CCM_ENET_QOS_TX_CLK_SELECT_INPUT)
4A8 ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
IPG_CLK_RMII_SELECT_INPUT)
4AC ENET_MAC0_MDIO_SELECT_INPUT DAISY Register (ENET_MAC 32 RW 0000_0000
0_MDIO_SELECT_INPUT)
4B0 ENET_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register (ENET_ 32 RW 0000_0000
MAC0_RXDATA_SELECT_INPUT_0)
4B4 ENET_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register (ENET_ 32 RW 0000_0000
MAC0_RXDATA_SELECT_INPUT_1)
4B8 ENET_MAC0_RXEN_SELECT_INPUT DAISY Register (ENET_MAC 32 RW 0000_0000
0_RXEN_SELECT_INPUT)
4BC ENET_MAC0_RXERR_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
MAC0_RXERR_SELECT_INPUT)
4C0 ENET_MAC0_TXCLK_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
MAC0_TXCLK_SELECT_INPUT)
4C4 ENET_1G_IPG_CLK_RMII_SELECT_INPUT DAISY Register (ENET 32 RW 0000_0000
_1G_IPG_CLK_RMII_SELECT_INPUT)
4C8 ENET_1G_MAC0_MDIO_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
1G_MAC0_MDIO_SELECT_INPUT)
4CC ENET_1G_MAC0_RXCLK_SELECT_INPUT DAISY Register (ENET 32 RW 0000_0000
_1G_MAC0_RXCLK_SELECT_INPUT)
4D0 ENET_1G_MAC0_RXDATA_0_SELECT_INPUT DAISY Register 32 RW 0000_0000
(ENET_1G_MAC0_RXDATA_0_SELECT_INPUT)
4D4 ENET_1G_MAC0_RXDATA_1_SELECT_INPUT DAISY Register 32 RW 0000_0000
(ENET_1G_MAC0_RXDATA_1_SELECT_INPUT)
4D8 ENET_1G_MAC0_RXDATA_2_SELECT_INPUT DAISY Register 32 RW 0000_0000
(ENET_1G_MAC0_RXDATA_2_SELECT_INPUT)
4DC ENET_1G_MAC0_RXDATA_3_SELECT_INPUT DAISY Register 32 RW 0000_0000
(ENET_1G_MAC0_RXDATA_3_SELECT_INPUT)
4E0 ENET_1G_MAC0_RXEN_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
1G_MAC0_RXEN_SELECT_INPUT)
4E4 ENET_1G_MAC0_RXERR_SELECT_INPUT DAISY Register (ENET 32 RW 0000_0000
_1G_MAC0_RXERR_SELECT_INPUT)
4E8 ENET_1G_MAC0_TXCLK_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
1G_MAC0_TXCLK_SELECT_INPUT)
4EC ENET_QOS_GMII_MDI_I_SELECT_INPUT DAISY Register (ENET_ 32 RW 0000_0000
QOS_GMII_MDI_I_SELECT_INPUT)
4F0 ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 DAISY Register 32 RW 0000_0000
(ENET_QOS_PHY_RXD_I_SELECT_INPUT_0)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
766 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4F4 ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 DAISY Register 32 RW 0000_0000
(ENET_QOS_PHY_RXD_I_SELECT_INPUT_1)
4F8 ENET_QOS_PHY_RXDV_I_SELECT_INPUT DAISY Register (ENET 32 RW 0000_0000
_QOS_PHY_RXDV_I_SELECT_INPUT)
4FC ENET_QOS_PHY_RXER_I_SELECT_INPUT DAISY Register (ENET 32 RW 0000_0000
_QOS_PHY_RXER_I_SELECT_INPUT)
500 FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMA_SELECT_INPUT_0)
504 FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMA_SELECT_INPUT_1)
508 FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMA_SELECT_INPUT_2)
50C FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMB_SELECT_INPUT_0)
510 FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMB_SELECT_INPUT_1)
514 FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM1_PWMB_SELECT_INPUT_2)
518 FLEXPWM2_PWMA_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMA_SELECT_INPUT_0)
51C FLEXPWM2_PWMA_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMA_SELECT_INPUT_1)
520 FLEXPWM2_PWMA_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMA_SELECT_INPUT_2)
524 FLEXPWM2_PWMB_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMB_SELECT_INPUT_0)
528 FLEXPWM2_PWMB_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMB_SELECT_INPUT_1)
52C FLEXPWM2_PWMB_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM2_PWMB_SELECT_INPUT_2)
530 FLEXPWM3_PWMA_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMA_SELECT_INPUT_0)
534 FLEXPWM3_PWMA_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMA_SELECT_INPUT_1)
538 FLEXPWM3_PWMA_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMA_SELECT_INPUT_2)
53C FLEXPWM3_PWMA_SELECT_INPUT_3 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMA_SELECT_INPUT_3)
540 FLEXPWM3_PWMB_SELECT_INPUT_0 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMB_SELECT_INPUT_0)
544 FLEXPWM3_PWMB_SELECT_INPUT_1 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMB_SELECT_INPUT_1)
548 FLEXPWM3_PWMB_SELECT_INPUT_2 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMB_SELECT_INPUT_2)
54C FLEXPWM3_PWMB_SELECT_INPUT_3 DAISY Register (FLEX 32 RW 0000_0000
PWM3_PWMB_SELECT_INPUT_3)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 767
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
550 FLEXSPI1_I_DQS_FA_SELECT_INPUT DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_DQS_FA_SELECT_INPUT)
554 FLEXSPI1_I_IO_FA_SELECT_INPUT_0 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_0)
558 FLEXSPI1_I_IO_FA_SELECT_INPUT_1 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_1)
55C FLEXSPI1_I_IO_FA_SELECT_INPUT_2 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_2)
560 FLEXSPI1_I_IO_FA_SELECT_INPUT_3 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_3)
564 FLEXSPI1_I_IO_FB_SELECT_INPUT_0 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FB_SELECT_INPUT_0)
568 FLEXSPI1_I_IO_FB_SELECT_INPUT_1 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FB_SELECT_INPUT_1)
56C FLEXSPI1_I_IO_FB_SELECT_INPUT_2 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FB_SELECT_INPUT_2)
570 FLEXSPI1_I_IO_FB_SELECT_INPUT_3 DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_IO_FB_SELECT_INPUT_3)
574 FLEXSPI1_I_SCK_FA_SELECT_INPUT DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_SCK_FA_SELECT_INPUT)
578 FLEXSPI1_I_SCK_FB_SELECT_INPUT DAISY Register (FLEXSPI1 32 RW 0000_0000
_I_SCK_FB_SELECT_INPUT)
57C FLEXSPI2_I_IO_FA_SELECT_INPUT_0 DAISY Register (FLEXSPI2 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_0)
580 FLEXSPI2_I_IO_FA_SELECT_INPUT_1 DAISY Register (FLEXSPI2 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_1)
584 FLEXSPI2_I_IO_FA_SELECT_INPUT_2 DAISY Register (FLEXSPI2 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_2)
588 FLEXSPI2_I_IO_FA_SELECT_INPUT_3 DAISY Register (FLEXSPI2 32 RW 0000_0000
_I_IO_FA_SELECT_INPUT_3)
58C FLEXSPI2_I_SCK_FA_SELECT_INPUT DAISY Register (FLEXSPI2 32 RW 0000_0000
_I_SCK_FA_SELECT_INPUT)
590 GPT3_CAPIN1_SELECT_INPUT DAISY Register (GPT3_CAPIN1_ 32 RW 0000_0000
SELECT_INPUT)
594 GPT3_CAPIN2_SELECT_INPUT DAISY Register (GPT3_CAPIN2_ 32 RW 0000_0000
SELECT_INPUT)
598 GPT3_CLKIN_SELECT_INPUT DAISY Register (GPT3_CLKIN_S 32 RW 0000_0000
ELECT_INPUT)
59C KPP_COL_SELECT_INPUT_6 DAISY Register (KPP_COL_SELE 32 RW 0000_0000
CT_INPUT_6)
5A0 KPP_COL_SELECT_INPUT_7 DAISY Register (KPP_COL_SELE 32 RW 0000_0000
CT_INPUT_7)
5A4 KPP_ROW_SELECT_INPUT_6 DAISY Register (KPP_ROW_SELE 32 RW 0000_0000
CT_INPUT_6)
5A8 KPP_ROW_SELECT_INPUT_7 DAISY Register (KPP_ROW_SELE 32 RW 0000_0000
CT_INPUT_7)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
768 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
5AC LPI2C1_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2C1_L 32 RW 0000_0000
PI2C_SCL_SELECT_INPUT)
5B0 LPI2C1_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2C1_L 32 RW 0000_0000
PI2C_SDA_SELECT_INPUT)
5B4 LPI2C2_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2C2_L 32 RW 0000_0000
PI2C_SCL_SELECT_INPUT)
5B8 LPI2C2_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2C2_L 32 RW 0000_0000
PI2C_SDA_SELECT_INPUT)
5BC LPI2C3_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2C3_L 32 RW 0000_0000
PI2C_SCL_SELECT_INPUT)
5C0 LPI2C3_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2C3_L 32 RW 0000_0000
PI2C_SDA_SELECT_INPUT)
5C4 LPI2C4_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2C4_L 32 RW 0000_0000
PI2C_SCL_SELECT_INPUT)
5C8 LPI2C4_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2C4_L 32 RW 0000_0000
PI2C_SDA_SELECT_INPUT)
5CC LPSPI1_LPSPI_PCS_SELECT_INPUT_0 DAISY Register (LPSPI1_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_0)
5D0 LPSPI1_LPSPI_SCK_SELECT_INPUT DAISY Register (LPSPI1_L 32 RW 0000_0000
PSPI_SCK_SELECT_INPUT)
5D4 LPSPI1_LPSPI_SDI_SELECT_INPUT DAISY Register (LPSPI1_L 32 RW 0000_0000
PSPI_SDI_SELECT_INPUT)
5D8 LPSPI1_LPSPI_SDO_SELECT_INPUT DAISY Register (LPSPI1_L 32 RW 0000_0000
PSPI_SDO_SELECT_INPUT)
5DC LPSPI2_LPSPI_PCS_SELECT_INPUT_0 DAISY Register (LPSPI2_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_0)
5E0 LPSPI2_LPSPI_PCS_SELECT_INPUT_1 DAISY Register (LPSPI2_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_1)
5E4 LPSPI2_LPSPI_SCK_SELECT_INPUT DAISY Register (LPSPI2_L 32 RW 0000_0000
PSPI_SCK_SELECT_INPUT)
5E8 LPSPI2_LPSPI_SDI_SELECT_INPUT DAISY Register (LPSPI2_L 32 RW 0000_0000
PSPI_SDI_SELECT_INPUT)
5EC LPSPI2_LPSPI_SDO_SELECT_INPUT DAISY Register (LPSPI2_L 32 RW 0000_0000
PSPI_SDO_SELECT_INPUT)
5F0 LPSPI3_LPSPI_PCS_SELECT_INPUT_0 DAISY Register (LPSPI3_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_0)
5F4 LPSPI3_LPSPI_PCS_SELECT_INPUT_1 DAISY Register (LPSPI3_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_1)
5F8 LPSPI3_LPSPI_PCS_SELECT_INPUT_2 DAISY Register (LPSPI3_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_2)
5FC LPSPI3_LPSPI_PCS_SELECT_INPUT_3 DAISY Register (LPSPI3_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_3)
600 LPSPI3_LPSPI_SCK_SELECT_INPUT DAISY Register (LPSPI3_L 32 RW 0000_0000
PSPI_SCK_SELECT_INPUT)
604 LPSPI3_LPSPI_SDI_SELECT_INPUT DAISY Register (LPSPI3_L 32 RW 0000_0000
PSPI_SDI_SELECT_INPUT)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 769
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
608 LPSPI3_LPSPI_SDO_SELECT_INPUT DAISY Register (LPSPI3_L 32 RW 0000_0000
PSPI_SDO_SELECT_INPUT)
60C LPSPI4_LPSPI_PCS_SELECT_INPUT_0 DAISY Register (LPSPI4_ 32 RW 0000_0000
LPSPI_PCS_SELECT_INPUT_0)
610 LPSPI4_LPSPI_SCK_SELECT_INPUT DAISY Register (LPSPI4_L 32 RW 0000_0000
PSPI_SCK_SELECT_INPUT)
614 LPSPI4_LPSPI_SDI_SELECT_INPUT DAISY Register (LPSPI4_L 32 RW 0000_0000
PSPI_SDI_SELECT_INPUT)
618 LPSPI4_LPSPI_SDO_SELECT_INPUT DAISY Register (LPSPI4_L 32 RW 0000_0000
PSPI_SDO_SELECT_INPUT)
61C LPUART1_LPUART_RXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT1_LPUART_RXD_SELECT_INPUT)
620 LPUART1_LPUART_TXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT1_LPUART_TXD_SELECT_INPUT)
624 LPUART10_LPUART_RXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT10_LPUART_RXD_SELECT_INPUT)
628 LPUART10_LPUART_TXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT10_LPUART_TXD_SELECT_INPUT)
62C LPUART7_LPUART_RXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT7_LPUART_RXD_SELECT_INPUT)
630 LPUART7_LPUART_TXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT7_LPUART_TXD_SELECT_INPUT)
634 LPUART8_LPUART_RXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT8_LPUART_RXD_SELECT_INPUT)
638 LPUART8_LPUART_TXD_SELECT_INPUT DAISY Register (LPUA 32 RW 0000_0000
RT8_LPUART_TXD_SELECT_INPUT)
63C QTIMER1_TMR0_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER1_TMR0_INPUT_SELECT_INPUT)
640 QTIMER1_TMR1_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER1_TMR1_INPUT_SELECT_INPUT)
644 QTIMER1_TMR2_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER1_TMR2_INPUT_SELECT_INPUT)
648 QTIMER2_TMR0_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER2_TMR0_INPUT_SELECT_INPUT)
64C QTIMER2_TMR1_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER2_TMR1_INPUT_SELECT_INPUT)
650 QTIMER2_TMR2_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER2_TMR2_INPUT_SELECT_INPUT)
654 QTIMER3_TMR0_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER3_TMR0_INPUT_SELECT_INPUT)
658 QTIMER3_TMR1_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER3_TMR1_INPUT_SELECT_INPUT)
65C QTIMER3_TMR2_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER3_TMR2_INPUT_SELECT_INPUT)
660 QTIMER4_TMR0_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER4_TMR0_INPUT_SELECT_INPUT)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
770 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
664 QTIMER4_TMR1_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER4_TMR1_INPUT_SELECT_INPUT)
668 QTIMER4_TMR2_INPUT_SELECT_INPUT DAISY Register (QTIM 32 RW 0000_0000
ER4_TMR2_INPUT_SELECT_INPUT)
66C SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY Register (SAI1 32 RW 0000_0000
_IPG_CLK_SAI_MCLK_SELECT_INPUT)
670 SAI1_SAI_RXBCLK_SELECT_INPUT DAISY Register (SAI1_SAI_ 32 RW 0000_0000
RXBCLK_SELECT_INPUT)
674 SAI1_SAI_RXDATA_SELECT_INPUT_0 DAISY Register (SAI1_SAI_ 32 RW 0000_0000
RXDATA_SELECT_INPUT_0)
678 SAI1_SAI_RXSYNC_SELECT_INPUT DAISY Register (SAI1_SAI_ 32 RW 0000_0000
RXSYNC_SELECT_INPUT)
67C SAI1_SAI_TXBCLK_SELECT_INPUT DAISY Register (SAI1_SAI_ 32 RW 0000_0000
TXBCLK_SELECT_INPUT)
680 SAI1_SAI_TXSYNC_SELECT_INPUT DAISY Register (SAI1_SAI_ 32 RW 0000_0000
TXSYNC_SELECT_INPUT)
69C EMVSIM1_SIO_SELECT_INPUT DAISY Register (EMVSIM1_SIO_ 32 RW 0000_0000
SELECT_INPUT)
6A0 EMVSIM1_IPP_SIMPD_SELECT_INPUT DAISY Register (EMVS 32 RW 0000_0000
IM1_IPP_SIMPD_SELECT_INPUT)
6A4 EMVSIM1_POWER_FAIL_SELECT_INPUT DAISY Register (EMVS 32 RW 0000_0000
IM1_POWER_FAIL_SELECT_INPUT)
6A8 EMVSIM2_SIO_SELECT_INPUT DAISY Register (EMVSIM2_SIO_ 32 RW 0000_0000
SELECT_INPUT)
6AC EMVSIM2_IPP_SIMPD_SELECT_INPUT DAISY Register (EMVS 32 RW 0000_0000
IM2_IPP_SIMPD_SELECT_INPUT)
6B0 EMVSIM2_POWER_FAIL_SELECT_INPUT DAISY Register (EMVS 32 RW 0000_0000
IM2_POWER_FAIL_SELECT_INPUT)
6B4 SPDIF_SPDIF_IN1_SELECT_INPUT DAISY Register (SPDIF_SP 32 RW 0000_0000
DIF_IN1_SELECT_INPUT)
6B8 USB_OTG2_OC_SELECT_INPUT DAISY Register (USB_OTG2_ 32 RW 0000_0000
OC_SELECT_INPUT)
6BC USB_OTG_OC_SELECT_INPUT DAISY Register (USB_OTG_OC_S 32 RW 0000_0000
ELECT_INPUT)
6C0 USBPHY1_USB_ID_SELECT_INPUT DAISY Register (USBPHY1_ 32 RW 0000_0000
USB_ID_SELECT_INPUT)
6C4 USBPHY2_USB_ID_SELECT_INPUT DAISY Register (USBPHY2_ 32 RW 0000_0000
USB_ID_SELECT_INPUT)
6C8 USDHC1_IPP_CARD_DET_SELECT_INPUT DAISY Register 32 RW 0000_0000
(USDHC1_IPP_CARD_DET_SELECT_INPUT)
6CC USDHC1_IPP_WP_ON_SELECT_INPUT DAISY Register (USDH 32 RW 0000_0000
C1_IPP_WP_ON_SELECT_INPUT)
6D0 USDHC2_IPP_CARD_DET_SELECT_INPUT DAISY Register 32 RW 0000_0000
(USDHC2_IPP_CARD_DET_SELECT_INPUT)
6D4 USDHC2_IPP_WP_ON_SELECT_INPUT DAISY Register (USDH 32 RW 0000_0000
C2_IPP_WP_ON_SELECT_INPUT)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 771
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
6D8 XBAR1_IN_SELECT_INPUT_20 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_20)
6DC XBAR1_IN_SELECT_INPUT_21 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_21)
6E0 XBAR1_IN_SELECT_INPUT_22 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_22)
6E4 XBAR1_IN_SELECT_INPUT_23 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_23)
6E8 XBAR1_IN_SELECT_INPUT_24 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_24)
6EC XBAR1_IN_SELECT_INPUT_25 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_25)
6F0 XBAR1_IN_SELECT_INPUT_26 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_26)
6F4 XBAR1_IN_SELECT_INPUT_27 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_27)
6F8 XBAR1_IN_SELECT_INPUT_28 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_28)
6FC XBAR1_IN_SELECT_INPUT_29 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_29)
700 XBAR1_IN_SELECT_INPUT_30 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_30)
704 XBAR1_IN_SELECT_INPUT_31 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_31)
708 XBAR1_IN_SELECT_INPUT_32 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_32)
70C XBAR1_IN_SELECT_INPUT_33 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_33)
710 XBAR1_IN_SELECT_INPUT_34 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_34)
714 XBAR1_IN_SELECT_INPUT_35 DAISY Register (XBAR1_IN_SEL 32 RW 0000_0000
ECT_INPUT_35)
12.4.5.2 SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_00)
SW_MUX_CTL Register
12.4.5.2.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 10h
PIO_EMC_B1_00
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12.4.5.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.2.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_00.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_A of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO00 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D00 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO00 of instance: GPIO7
12.4.5.3 SW_MUX_CTL_PAD_GPIO_EMC_B1_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_01)
SW_MUX_CTL Register
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12.4.5.3.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 14h
PIO_EMC_B1_01
12.4.5.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.3.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_01.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA01 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM0_B of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO01 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D01 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO01 of instance: GPIO7
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12.4.5.4 SW_MUX_CTL_PAD_GPIO_EMC_B1_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_02)
SW_MUX_CTL Register
12.4.5.4.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 18h
PIO_EMC_B1_02
12.4.5.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.4.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_02.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA02 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_A of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO02 of instance: GPIO1_
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Field Description
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D02 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO02 of instance: GPIO7
12.4.5.5 SW_MUX_CTL_PAD_GPIO_EMC_B1_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_03)
SW_MUX_CTL Register
12.4.5.5.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1Ch
PIO_EMC_B1_03
12.4.5.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.5.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
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Field Description
1 - Force input path of pad GPIO_EMC_B1_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_03.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA03 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM1_B of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO03 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D03 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO03 of instance: GPIO7
12.4.5.6 SW_MUX_CTL_PAD_GPIO_EMC_B1_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_04)
SW_MUX_CTL Register
12.4.5.6.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 20h
PIO_EMC_B1_04
12.4.5.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.6.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_04.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_A of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO04 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D04 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO04 of instance: GPIO7
12.4.5.7 SW_MUX_CTL_PAD_GPIO_EMC_B1_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_05)
SW_MUX_CTL Register
12.4.5.7.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 24h
PIO_EMC_B1_05
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12.4.5.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.7.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_05.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM2_B of instance: FLEXPWM4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO05 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D05 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO05 of instance: GPIO7
12.4.5.8 SW_MUX_CTL_PAD_GPIO_EMC_B1_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_06)
SW_MUX_CTL Register
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12.4.5.8.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 28h
PIO_EMC_B1_06
12.4.5.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.8.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_06.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_A of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO1__IO06 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D06 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO06 of instance: GPIO7
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12.4.5.9 SW_MUX_CTL_PAD_GPIO_EMC_B1_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_07)
SW_MUX_CTL Register
12.4.5.9.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 2Ch
PIO_EMC_B1_07
12.4.5.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.9.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_07.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM0_B of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO1__IO07 of instance: GPIO1_
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Field Description
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D07 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO07 of instance: GPIO7
12.4.5.10 SW_MUX_CTL_PAD_GPIO_EMC_B1_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_08)
SW_MUX_CTL Register
12.4.5.10.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 30h
PIO_EMC_B1_08
12.4.5.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.10.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
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Field Description
1 - Force input path of pad GPIO_EMC_B1_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_08.
0000 - Select mux mode: ALT0 mux port: SEMC_DM00 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_A of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO1__IO08 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D08 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO08 of instance: GPIO7
12.4.5.11 SW_MUX_CTL_PAD_GPIO_EMC_B1_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_09)
SW_MUX_CTL Register
12.4.5.11.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 34h
PIO_EMC_B1_09
12.4.5.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.11.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_09.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM1_B of instance: FLEXPWM2
0010 - Select mux mode: ALT2 mux port: GPT5_CAPTURE1 of instance: GPT5
0101 - Select mux mode: ALT5 mux port: GPIO1__IO09 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D09 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO09 of instance: GPIO7
12.4.5.12 SW_MUX_CTL_PAD_GPIO_EMC_B1_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_10)
SW_MUX_CTL Register
12.4.5.12.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 38h
PIO_EMC_B1_10
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12.4.5.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.12.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_10.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_A of instance: FLEXPWM2
0010 - Select mux mode: ALT2 mux port: GPT5_CAPTURE2 of instance: GPT5
0101 - Select mux mode: ALT5 mux port: GPIO1__IO10 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D10 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO10 of instance: GPIO7
12.4.5.13 SW_MUX_CTL_PAD_GPIO_EMC_B1_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_11)
SW_MUX_CTL Register
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12.4.5.13.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 3Ch
PIO_EMC_B1_11
12.4.5.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.13.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_11.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM2_B of instance: FLEXPWM2
0010 - Select mux mode: ALT2 mux port: GPT5_COMPARE1 of instance: GPT5
0101 - Select mux mode: ALT5 mux port: GPIO1__IO11 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D11 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO11 of instance: GPIO7
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12.4.5.14 SW_MUX_CTL_PAD_GPIO_EMC_B1_12 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_12)
SW_MUX_CTL Register
12.4.5.14.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 40h
PIO_EMC_B1_12
12.4.5.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.14.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_12
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_12.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT04 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: GPT5_COMPARE2 of instance: GPT5
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Field Description
0101 - Select mux mode: ALT5 mux port: GPIO1__IO12 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D12 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO12 of instance: GPIO7
12.4.5.15 SW_MUX_CTL_PAD_GPIO_EMC_B1_13 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_13)
SW_MUX_CTL Register
12.4.5.15.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 44h
PIO_EMC_B1_13
12.4.5.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.15.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_13
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_13.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT05 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: GPT5_COMPARE3 of instance: GPT5
0101 - Select mux mode: ALT5 mux port: GPIO1__IO13 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D13 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO13 of instance: GPIO7
12.4.5.16 SW_MUX_CTL_PAD_GPIO_EMC_B1_14 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_14)
SW_MUX_CTL Register
12.4.5.16.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 48h
PIO_EMC_B1_14
12.4.5.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.16.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_14
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_14.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT06 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: GPT5_CLK of instance: GPT5
0101 - Select mux mode: ALT5 mux port: GPIO1__IO14 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D14 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO14 of instance: GPIO7
12.4.5.17 SW_MUX_CTL_PAD_GPIO_EMC_B1_15 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_15)
SW_MUX_CTL Register
12.4.5.17.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 4Ch
PIO_EMC_B1_15
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12.4.5.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.17.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_15
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_15.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT07 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO15 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D15 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO15 of instance: GPIO7
12.4.5.18 SW_MUX_CTL_PAD_GPIO_EMC_B1_16 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_16)
SW_MUX_CTL Register
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12.4.5.18.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 50h
PIO_EMC_B1_16
12.4.5.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.18.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_16
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_16.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT08 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO16 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D16 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO16 of instance: GPIO7
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12.4.5.19 SW_MUX_CTL_PAD_GPIO_EMC_B1_17 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_17)
SW_MUX_CTL Register
12.4.5.19.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 54h
PIO_EMC_B1_17
12.4.5.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.19.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_17
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 7 iomux modes to be used for pad: GPIO_EMC_B1_17.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_A of instance: FLEXPWM4
0010 - Select mux mode: ALT2 mux port: TMR1_TIMER0 of instance: TMR1
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Field Description
0101 - Select mux mode: ALT5 mux port: GPIO1__IO17 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D17 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO17 of instance: GPIO7
12.4.5.20 SW_MUX_CTL_PAD_GPIO_EMC_B1_18 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_18)
SW_MUX_CTL Register
12.4.5.20.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 58h
PIO_EMC_B1_18
12.4.5.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.20.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_18
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_18.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM4_PWM3_B of instance: FLEXPWM4
0010 - Select mux mode: ALT2 mux port: TMR2_TIMER0 of instance: TMR2
0101 - Select mux mode: ALT5 mux port: GPIO1__IO18 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D18 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO18 of instance: GPIO7
12.4.5.21 SW_MUX_CTL_PAD_GPIO_EMC_B1_19 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_19)
SW_MUX_CTL Register
12.4.5.21.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 5Ch
PIO_EMC_B1_19
12.4.5.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.21.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_19
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_19.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_A of instance: FLEXPWM2
0010 - Select mux mode: ALT2 mux port: TMR3_TIMER0 of instance: TMR3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO19 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D19 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO19 of instance: GPIO7
12.4.5.22 SW_MUX_CTL_PAD_GPIO_EMC_B1_20 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_20)
SW_MUX_CTL Register
12.4.5.22.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 60h
PIO_EMC_B1_20
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12.4.5.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.22.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_20
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_20.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM2_PWM3_B of instance: FLEXPWM2
0010 - Select mux mode: ALT2 mux port: TMR4_TIMER0 of instance: TMR4
0101 - Select mux mode: ALT5 mux port: GPIO1__IO20 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D20 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO20 of instance: GPIO7
12.4.5.23 SW_MUX_CTL_PAD_GPIO_EMC_B1_21 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_21)
SW_MUX_CTL Register
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12.4.5.23.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 64h
PIO_EMC_B1_21
12.4.5.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.23.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_21
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_21.
0000 - Select mux mode: ALT0 mux port: SEMC_BA0 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO21 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D21 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO21 of instance: GPIO7
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12.4.5.24 SW_MUX_CTL_PAD_GPIO_EMC_B1_22 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_22)
SW_MUX_CTL Register
12.4.5.24.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 68h
PIO_EMC_B1_22
12.4.5.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.24.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_22
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_22.
0000 - Select mux mode: ALT0 mux port: SEMC_BA1 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM3_B of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO22 of instance: GPIO1_
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Field Description
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D22 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO22 of instance: GPIO7
12.4.5.25 SW_MUX_CTL_PAD_GPIO_EMC_B1_23 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_23)
SW_MUX_CTL Register
12.4.5.25.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 6Ch
PIO_EMC_B1_23
12.4.5.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.25.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
1 - Force input path of pad GPIO_EMC_B1_23
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_23.
0000 - Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO23 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D23 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO23 of instance: GPIO7
12.4.5.26 SW_MUX_CTL_PAD_GPIO_EMC_B1_24 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_24)
SW_MUX_CTL Register
12.4.5.26.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 70h
PIO_EMC_B1_24
12.4.5.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.26.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_24
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_24.
0000 - Select mux mode: ALT0 mux port: SEMC_CAS of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO24 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D24 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO24 of instance: GPIO7
12.4.5.27 SW_MUX_CTL_PAD_GPIO_EMC_B1_25 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_25)
SW_MUX_CTL Register
12.4.5.27.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 74h
PIO_EMC_B1_25
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12.4.5.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.27.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_25
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_25.
0000 - Select mux mode: ALT0 mux port: SEMC_RAS of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO25 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D25 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO25 of instance: GPIO7
12.4.5.28 SW_MUX_CTL_PAD_GPIO_EMC_B1_26 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_26)
SW_MUX_CTL Register
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12.4.5.28.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 78h
PIO_EMC_B1_26
12.4.5.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.28.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_26
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_26.
0000 - Select mux mode: ALT0 mux port: SEMC_CLK of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO26 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D26 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO26 of instance: GPIO7
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12.4.5.29 SW_MUX_CTL_PAD_GPIO_EMC_B1_27 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_27)
SW_MUX_CTL Register
12.4.5.29.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 7Ch
PIO_EMC_B1_27
12.4.5.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.29.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_27
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_27.
0000 - Select mux mode: ALT0 mux port: SEMC_CKE of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO27 of instance: GPIO1_
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Field Description
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D27 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO27 of instance: GPIO7
12.4.5.30 SW_MUX_CTL_PAD_GPIO_EMC_B1_28 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_28)
SW_MUX_CTL Register
12.4.5.30.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 80h
PIO_EMC_B1_28
12.4.5.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.30.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
Table continues on the next page...
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Field Description
1 - Force input path of pad GPIO_EMC_B1_28
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_28.
0000 - Select mux mode: ALT0 mux port: SEMC_WE of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO1__IO28 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D28 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO28 of instance: GPIO7
12.4.5.31 SW_MUX_CTL_PAD_GPIO_EMC_B1_29 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_29)
SW_MUX_CTL Register
12.4.5.31.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 84h
PIO_EMC_B1_29
12.4.5.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.31.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_29
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_29.
0000 - Select mux mode: ALT0 mux port: SEMC_CS0 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO29 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D29 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO29 of instance: GPIO7
12.4.5.32 SW_MUX_CTL_PAD_GPIO_EMC_B1_30 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_30)
SW_MUX_CTL Register
12.4.5.32.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 88h
PIO_EMC_B1_30
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12.4.5.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.32.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_30
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_30.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA08 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM0_B of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO30 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D30 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO30 of instance: GPIO7
12.4.5.33 SW_MUX_CTL_PAD_GPIO_EMC_B1_31 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_31)
SW_MUX_CTL Register
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12.4.5.33.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 8Ch
PIO_EMC_B1_31
12.4.5.33.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.33.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_31
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_31.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_A of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO1__IO31 of instance: GPIO1_
1000 - Select mux mode: ALT8 mux port: FLEXIO1_D31 of instance: FLEXIO1
1010 - Select mux mode: ALT10 mux port: GPIO7_IO31 of instance: GPIO7
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12.4.5.34 SW_MUX_CTL_PAD_GPIO_EMC_B1_32 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_32)
SW_MUX_CTL Register
12.4.5.34.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 90h
PIO_EMC_B1_32
12.4.5.34.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.34.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_32
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 4 iomux modes to be used for pad: GPIO_EMC_B1_32.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM1_B of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO00 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO00 of instance: GPIO8
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12.4.5.35 SW_MUX_CTL_PAD_GPIO_EMC_B1_33 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_33)
SW_MUX_CTL Register
12.4.5.35.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 94h
PIO_EMC_B1_33
12.4.5.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.35.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_33
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 4 iomux modes to be used for pad: GPIO_EMC_B1_33.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: SEMC
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Field Description
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_A of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO01 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO01 of instance: GPIO8
12.4.5.36 SW_MUX_CTL_PAD_GPIO_EMC_B1_34 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_34)
SW_MUX_CTL Register
12.4.5.36.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 98h
PIO_EMC_B1_34
12.4.5.36.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.36.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_34
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 4 iomux modes to be used for pad: GPIO_EMC_B1_34.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA12 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM3_PWM2_B of instance: FLEXPWM3
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO02 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO02 of instance: GPIO8
12.4.5.37 SW_MUX_CTL_PAD_GPIO_EMC_B1_35 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_35)
SW_MUX_CTL Register
12.4.5.37.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 9Ch
PIO_EMC_B1_35
12.4.5.37.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.37.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_35
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 4 iomux modes to be used for pad: GPIO_EMC_B1_35.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT09 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO03 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO03 of instance: GPIO8
12.4.5.38 SW_MUX_CTL_PAD_GPIO_EMC_B1_36 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_36)
SW_MUX_CTL Register
12.4.5.38.1 Offset
Register Offset
SW_MUX_CTL_PAD_G A0h
PIO_EMC_B1_36
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12.4.5.38.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.38.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_36
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 4 iomux modes to be used for pad: GPIO_EMC_B1_36.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA14 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO04 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO04 of instance: GPIO8
12.4.5.39 SW_MUX_CTL_PAD_GPIO_EMC_B1_37 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_37)
SW_MUX_CTL Register
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12.4.5.39.1 Offset
Register Offset
SW_MUX_CTL_PAD_G A4h
PIO_EMC_B1_37
12.4.5.39.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.39.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_37
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 5 iomux modes to be used for pad: GPIO_EMC_B1_37.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA15 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO05 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO05 of instance: GPIO8
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12.4.5.40 SW_MUX_CTL_PAD_GPIO_EMC_B1_38 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_38)
SW_MUX_CTL Register
12.4.5.40.1 Offset
Register Offset
SW_MUX_CTL_PAD_G A8h
PIO_EMC_B1_38
12.4.5.40.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.40.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_38
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_38.
0000 - Select mux mode: ALT0 mux port: SEMC_DM01 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_A of instance: FLEXPWM1
0010 - Select mux mode: ALT2 mux port: TMR1_TIMER1 of instance: TMR1
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Field Description
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO06 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO06 of instance: GPIO8
12.4.5.41 SW_MUX_CTL_PAD_GPIO_EMC_B1_39 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_39)
SW_MUX_CTL Register
12.4.5.41.1 Offset
Register Offset
SW_MUX_CTL_PAD_G ACh
PIO_EMC_B1_39
12.4.5.41.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.41.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
Table continues on the next page...
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Field Description
1 - Force input path of pad GPIO_EMC_B1_39
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 6 iomux modes to be used for pad: GPIO_EMC_B1_39.
0000 - Select mux mode: ALT0 mux port: SEMC_DQS of instance: SEMC
0001 - Select mux mode: ALT1 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1
0010 - Select mux mode: ALT2 mux port: TMR2_TIMER1 of instance: TMR2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO07 of instance: GPIO_MUX2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO07 of instance: GPIO8
12.4.5.42 SW_MUX_CTL_PAD_GPIO_EMC_B1_40 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_40)
SW_MUX_CTL Register
12.4.5.42.1 Offset
Register Offset
SW_MUX_CTL_PAD_G B0h
PIO_EMC_B1_40
12.4.5.42.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.42.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_40
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_EMC_B1_40.
0000 - Select mux mode: ALT0 mux port: SEMC_RDY of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS
0011 - Select mux mode: ALT3 mux port: LPUART6_TXD of instance: LPUART6
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO08 of instance: GPIO_MUX2
0111 - Select mux mode: ALT7 mux port: ENET_1G_MDC of instance: ENET_1G
1001 - Select mux mode: ALT9 mux port: CCM_CLKO1 of instance: CCM
1010 - Select mux mode: ALT10 mux port: GPIO8_IO08 of instance: GPIO8
12.4.5.43 SW_MUX_CTL_PAD_GPIO_EMC_B1_41 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B1_41)
SW_MUX_CTL Register
12.4.5.43.1 Offset
Register Offset
SW_MUX_CTL_PAD_G B4h
PIO_EMC_B1_41
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12.4.5.43.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.43.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B1_41
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_EMC_B1_41.
0000 - Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS
0011 - Select mux mode: ALT3 mux port: LPUART6_RXD of instance: LPUART6
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA07 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO09 of instance: GPIO_MUX2
0111 - Select mux mode: ALT7 mux port: ENET_1G_MDIO of instance: ENET_1G
1001 - Select mux mode: ALT9 mux port: CCM_CLKO2 of instance: CCM
1010 - Select mux mode: ALT10 mux port: GPIO8_IO09 of instance: GPIO8
12.4.5.44 SW_MUX_CTL_PAD_GPIO_EMC_B2_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_00)
SW_MUX_CTL Register
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12.4.5.44.1 Offset
Register Offset
SW_MUX_CTL_PAD_G B8h
PIO_EMC_B2_00
12.4.5.44.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.44.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_00.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA16 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
0010 - Select mux mode: ALT2 mux port: TMR3_TIMER1 of instance: TMR3
0011 - Select mux mode: ALT3 mux port: LPUART6_CTS_B of instance: LPUART6
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA06 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO10 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT20 of instance: XBAR1
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Field Description
0111 - Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_OUT of instance: ENET_QOS
1000 - Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: LPSPI1
1001 - Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO10 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3
12.4.5.45 SW_MUX_CTL_PAD_GPIO_EMC_B2_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_01)
SW_MUX_CTL Register
12.4.5.45.1 Offset
Register Offset
SW_MUX_CTL_PAD_G BCh
PIO_EMC_B2_01
12.4.5.45.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.45.3 Fields
Field Description
31-5 -
— Reserved
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Field Description
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_01.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA17 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: USDHC2_CD_B of instance: USDHC2
0010 - Select mux mode: ALT2 mux port: TMR4_TIMER1 of instance: TMR4
0011 - Select mux mode: ALT3 mux port: LPUART6_RTS_B of instance: LPUART6
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA05 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO11 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT21 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_IN of instance: ENET_QOS
1000 - Select mux mode: ALT8 mux port: LPSPI1_PCS0 of instance: LPSPI1
1001 - Select mux mode: ALT9 mux port: LPI2C2_SDA of instance: LPI2C2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO11 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_B of instance: FLEXPWM3
12.4.5.46 SW_MUX_CTL_PAD_GPIO_EMC_B2_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_02)
SW_MUX_CTL Register
12.4.5.46.1 Offset
Register Offset
SW_MUX_CTL_PAD_G C0h
PIO_EMC_B2_02
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12.4.5.46.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.46.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_02.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA18 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: USDHC2_WP of instance: USDHC2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA23 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA04 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO12 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT22 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_AUX_IN of instance: ENET_QOS
1000 - Select mux mode: ALT8 mux port: LPSPI1_SOUT of instance: LPSPI1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO12 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_A of instance: FLEXPWM3
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12.4.5.47 SW_MUX_CTL_PAD_GPIO_EMC_B2_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_03)
SW_MUX_CTL Register
12.4.5.47.1 Offset
Register Offset
SW_MUX_CTL_PAD_G C4h
PIO_EMC_B2_03
12.4.5.47.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.47.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_03.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA19 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: USDHC2_VSELECT of instance: USDHC2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA22 of instance: VIDEO_MUX
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Field Description
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA03 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO13 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT23 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI1_SIN of instance: LPSPI1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO13 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_B of instance: FLEXPWM3
12.4.5.48 SW_MUX_CTL_PAD_GPIO_EMC_B2_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_04)
SW_MUX_CTL Register
12.4.5.48.1 Offset
Register Offset
SW_MUX_CTL_PAD_G C8h
PIO_EMC_B2_04
12.4.5.48.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.48.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_04.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA20 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: USDHC2_RESET_B of instance: USDHC2
0010 - Select mux mode: ALT2 mux port: SAI2_MCLK of instance: SAI2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA21 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA02 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO14 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT24 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_SCK of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO8_IO14 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_A of instance: FLEXPWM3
12.4.5.49 SW_MUX_CTL_PAD_GPIO_EMC_B2_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_05)
SW_MUX_CTL Register
12.4.5.49.1 Offset
Register Offset
SW_MUX_CTL_PAD_G CCh
PIO_EMC_B2_05
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12.4.5.49.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.49.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_05.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA21 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_CLK of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: SAI2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA20 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA01 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO15 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT25 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_RX_CLK of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_PCS0 of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: PIT1_TRIGGER0 of instance: PIT1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO15 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_B of instance: FLEXPWM3
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12.4.5.50 SW_MUX_CTL_PAD_GPIO_EMC_B2_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_06)
SW_MUX_CTL Register
12.4.5.50.1 Offset
Register Offset
SW_MUX_CTL_PAD_G D0h
PIO_EMC_B2_06
12.4.5.50.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.50.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_06.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA22 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_CAPTURE1 of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: SAI2
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Field Description
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA19 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA00 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO16 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT26 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_TX_ER of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_SOUT of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: PIT1_TRIGGER1 of instance: PIT1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO16 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_A of instance: FLEXPWM3
12.4.5.51 SW_MUX_CTL_PAD_GPIO_EMC_B2_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_07)
SW_MUX_CTL Register
12.4.5.51.1 Offset
Register Offset
SW_MUX_CTL_PAD_G D4h
PIO_EMC_B2_07
12.4.5.51.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.51.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_07.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA23 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_CAPTURE2 of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: SAI2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA18 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_DQS of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO17 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT27 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_SIN of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: PIT1_TRIGGER2 of instance: PIT1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO17 of instance: GPIO8
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_B of instance: FLEXPWM3
12.4.5.52 SW_MUX_CTL_PAD_GPIO_EMC_B2_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_08)
SW_MUX_CTL Register
12.4.5.52.1 Offset
Register Offset
SW_MUX_CTL_PAD_G D8h
PIO_EMC_B2_08
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12.4.5.52.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.52.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_08.
0000 - Select mux mode: ALT0 mux port: SEMC_DM02 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_COMPARE1 of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: SAI2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA17 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_SS0_B of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO18 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT28 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_PCS1 of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: PIT1_TRIGGER3 of instance: PIT1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO18 of instance: GPIO8
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12.4.5.53 SW_MUX_CTL_PAD_GPIO_EMC_B2_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_09)
SW_MUX_CTL Register
12.4.5.53.1 Offset
Register Offset
SW_MUX_CTL_PAD_G DCh
PIO_EMC_B2_09
12.4.5.53.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.53.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_09.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA24 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_COMPARE2 of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: SAI2
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Field Description
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_DATA16 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_B_SCLK of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO19 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT29 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_CRS of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_PCS2 of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: TMR1_TIMER0 of instance: TMR1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO19 of instance: GPIO8
12.4.5.54 SW_MUX_CTL_PAD_GPIO_EMC_B2_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_10)
SW_MUX_CTL Register
12.4.5.54.1 Offset
Register Offset
SW_MUX_CTL_PAD_G E0h
PIO_EMC_B2_10
12.4.5.54.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.54.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_10.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA25 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: GPT3_COMPARE3 of instance: GPT3
0010 - Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: SAI2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_CSI_FIELD of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_SCLK of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO20 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT30 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: ENET_1G_COL of instance: ENET_1G
1000 - Select mux mode: ALT8 mux port: LPSPI3_PCS3 of instance: LPSPI3
1001 - Select mux mode: ALT9 mux port: TMR1_TIMER1 of instance: TMR1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO20 of instance: GPIO8
12.4.5.55 SW_MUX_CTL_PAD_GPIO_EMC_B2_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_11)
SW_MUX_CTL Register
12.4.5.55.1 Offset
Register Offset
SW_MUX_CTL_PAD_G E4h
PIO_EMC_B2_11
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12.4.5.55.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.55.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_11.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA26 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: SPDIF_IN of instance: SPDIF
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_SS0_B of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO21 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT31 of instance: XBAR1
1000 - Select mux mode: ALT8 mux port: EMVSIM1_IO of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR1_TIMER2 of instance: TMR1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO21 of instance: GPIO8
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12.4.5.56 SW_MUX_CTL_PAD_GPIO_EMC_B2_12 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_12)
SW_MUX_CTL Register
12.4.5.56.1 Offset
Register Offset
SW_MUX_CTL_PAD_G E8h
PIO_EMC_B2_12
12.4.5.56.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.56.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_12
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_12.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA27 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: SPDIF_OUT of instance: SPDIF
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G
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Field Description
0011 - Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DQS of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO22 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT32 of instance: XBAR1
1000 - Select mux mode: ALT8 mux port: EMVSIM1_CLK of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR1_TIMER3 of instance: TMR1
1010 - Select mux mode: ALT10 mux port: GPIO8_IO22 of instance: GPIO8
12.4.5.57 SW_MUX_CTL_PAD_GPIO_EMC_B2_13 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_13)
SW_MUX_CTL Register
12.4.5.57.1 Offset
Register Offset
SW_MUX_CTL_PAD_G ECh
PIO_EMC_B2_13
12.4.5.57.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.57.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_13
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_13.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA28 of instance: SEMC
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_EN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA00 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO23 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT33 of instance: XBAR1
1000 - Select mux mode: ALT8 mux port: EMVSIM1_RST of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR2_TIMER0 of instance: TMR2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO23 of instance: GPIO8
12.4.5.58 SW_MUX_CTL_PAD_GPIO_EMC_B2_14 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_14)
SW_MUX_CTL Register
12.4.5.58.1 Offset
Register Offset
SW_MUX_CTL_PAD_G F0h
PIO_EMC_B2_14
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12.4.5.58.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.58.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_14
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_14.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA29 of instance: SEMC
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA01 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO24 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT34 of instance: XBAR1
0111 - Select mux mode: ALT7 mux port: SFA_ipp_do_atx_clk_under_test of instance: sfa
1000 - Select mux mode: ALT8 mux port: EMVSIM1_SVEN of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR2_TIMER1 of instance: TMR2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO24 of instance: GPIO8
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12.4.5.59 SW_MUX_CTL_PAD_GPIO_EMC_B2_15 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_15)
SW_MUX_CTL Register
12.4.5.59.1 Offset
Register Offset
SW_MUX_CTL_PAD_G F4h
PIO_EMC_B2_15
12.4.5.59.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.59.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_15
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_15.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA30 of instance: SEMC
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: SAI3
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Field Description
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA02 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO25 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: XBAR1_INOUT35 of instance: XBAR1
1000 - Select mux mode: ALT8 mux port: EMVSIM1_PD of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR2_TIMER2 of instance: TMR2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO25 of instance: GPIO8
12.4.5.60 SW_MUX_CTL_PAD_GPIO_EMC_B2_16 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_16)
SW_MUX_CTL Register
12.4.5.60.1 Offset
Register Offset
SW_MUX_CTL_PAD_G F8h
PIO_EMC_B2_16
12.4.5.60.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.60.3 Fields
Field Description
31-5 -
Table continues on the next page...
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_16
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_16.
0000 - Select mux mode: ALT0 mux port: SEMC_DATA31 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA03 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO26 of instance: GPIO_MUX2
1000 - Select mux mode: ALT8 mux port: EMVSIM1_POWER_FAIL of instance: EMVSIM1
1001 - Select mux mode: ALT9 mux port: TMR2_TIMER3 of instance: TMR2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO26 of instance: GPIO8
12.4.5.61 SW_MUX_CTL_PAD_GPIO_EMC_B2_17 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_17)
SW_MUX_CTL Register
12.4.5.61.1 Offset
Register Offset
SW_MUX_CTL_PAD_G FCh
PIO_EMC_B2_17
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12.4.5.61.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.61.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_17
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_17.
0000 - Select mux mode: ALT0 mux port: SEMC_DM03 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_EN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: SAI3_MCLK of instance: SAI3
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA04 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO27 of instance: GPIO_MUX2
1000 - Select mux mode: ALT8 mux port: WDOG1_ANY of instance: WDOG1
1001 - Select mux mode: ALT9 mux port: TMR3_TIMER0 of instance: TMR3
1010 - Select mux mode: ALT10 mux port: GPIO8_IO27 of instance: GPIO8
12.4.5.62 SW_MUX_CTL_PAD_GPIO_EMC_B2_18 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_18)
SW_MUX_CTL Register
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12.4.5.62.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 100h
PIO_EMC_B2_18
12.4.5.62.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.62.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_18
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_EMC_B2_18.
0000 - Select mux mode: ALT0 mux port: SEMC_DQS4 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: XBAR1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_ER of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: EWM_OUT_B of instance: EWM
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA05 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO28 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1
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Field Description
1000 - Select mux mode: ALT8 mux port: WDOG1_B of instance: WDOG1
1001 - Select mux mode: ALT9 mux port: TMR3_TIMER1 of instance: TMR3
1010 - Select mux mode: ALT10 mux port: GPIO8_IO28 of instance: GPIO8
12.4.5.63 SW_MUX_CTL_PAD_GPIO_EMC_B2_19 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_19)
SW_MUX_CTL Register
12.4.5.63.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 104h
PIO_EMC_B2_19
12.4.5.63.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.63.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
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Field Description
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_19
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_19.
0000 - Select mux mode: ALT0 mux port: SEMC_CLKX00 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: ENET_MDC of instance: ENET
0010 - Select mux mode: ALT2 mux port: ENET_1G_MDC of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: ENET_1G_REF_CLK of instance: ENET_1G
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA06 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO29 of instance: GPIO_MUX2
1000 - Select mux mode: ALT8 mux port: ENET_QOS_MDC of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: TMR3_TIMER2 of instance: TMR3
1010 - Select mux mode: ALT10 mux port: GPIO8_IO29 of instance: GPIO8
12.4.5.64 SW_MUX_CTL_PAD_GPIO_EMC_B2_20 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_EMC_B2_20)
SW_MUX_CTL Register
12.4.5.64.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 108h
PIO_EMC_B2_20
12.4.5.64.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.64.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_EMC_B2_20
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_EMC_B2_20.
0000 - Select mux mode: ALT0 mux port: SEMC_CLKX01 of instance: SEMC
0001 - Select mux mode: ALT1 mux port: ENET_MDIO of instance: ENET
0010 - Select mux mode: ALT2 mux port: ENET_1G_MDIO of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS
0100 - Select mux mode: ALT4 mux port: FLEXSPI2_A_DATA07 of instance: FLEXSPI2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO30 of instance: GPIO_MUX2
1000 - Select mux mode: ALT8 mux port: ENET_QOS_MDIO of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: TMR3_TIMER3 of instance: TMR3
1010 - Select mux mode: ALT10 mux port: GPIO8_IO30 of instance: GPIO8
12.4.5.65 SW_MUX_CTL_PAD_GPIO_AD_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_00)
SW_MUX_CTL Register
12.4.5.65.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 10Ch
PIO_AD_00
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12.4.5.65.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.65.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_00.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_IO of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: FLEXCAN2_TX of instance: FLEXCAN2
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT1_IN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: GPT2_CAPTURE1 of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM0_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX2_IO31 of instance: GPIO_MUX2
0110 - Select mux mode: ALT6 mux port: LPUART7_TXD of instance: LPUART7
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D00 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: FLEXSPI2_B_SS1_B of instance: FLEXSPI2
1010 - Select mux mode: ALT10 mux port: GPIO8_IO31 of instance: GPIO8
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12.4.5.66 SW_MUX_CTL_PAD_GPIO_AD_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_01)
SW_MUX_CTL Register
12.4.5.66.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 110h
PIO_AD_01
12.4.5.66.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.66.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_01.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_CLK of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: FLEXCAN2_RX of instance: FLEXCAN2
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT1_OUT of instance: ENET_1G
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Field Description
0011 - Select mux mode: ALT3 mux port: GPT2_CAPTURE2 of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM0_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO00 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: LPUART7_RXD of instance: LPUART7
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D01 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: FLEXSPI2_A_SS1_B of instance: FLEXSPI2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO00 of instance: GPIO9
12.4.5.67 SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_02)
SW_MUX_CTL Register
12.4.5.67.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 114h
PIO_AD_02
12.4.5.67.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.67.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_02.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_RST of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: LPUART7_CTS_B of instance: LPUART7
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT2_IN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: GPT2_COMPARE1 of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM1_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO01 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: LPUART8_TXD of instance: LPUART8
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D02 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX
1010 - Select mux mode: ALT10 mux port: GPIO9_IO01 of instance: GPIO9
12.4.5.68 SW_MUX_CTL_PAD_GPIO_AD_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_03)
SW_MUX_CTL Register
12.4.5.68.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 118h
PIO_AD_03
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12.4.5.68.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.68.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_03.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_SVEN of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: LPUART7_RTS_B of instance: LPUART7
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT2_OUT of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: GPT2_COMPARE2 of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM1_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO02 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: LPUART8_RXD of instance: LPUART8
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D03 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX
1010 - Select mux mode: ALT10 mux port: GPIO9_IO02 of instance: GPIO9
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12.4.5.69 SW_MUX_CTL_PAD_GPIO_AD_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_04)
SW_MUX_CTL Register
12.4.5.69.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 11Ch
PIO_AD_04
12.4.5.69.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.69.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_04.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_PD of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: LPUART8_CTS_B of instance: LPUART8
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT3_IN of instance: ENET_1G
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Field Description
0011 - Select mux mode: ALT3 mux port: GPT2_COMPARE3 of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM2_A of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO03 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: WDOG1_B of instance: WDOG1
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D04 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: TMR4_TIMER0 of instance: TMR4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO03 of instance: GPIO9
12.4.5.70 SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_05)
SW_MUX_CTL Register
12.4.5.70.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 120h
PIO_AD_05
12.4.5.70.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.70.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_05.
0000 - Select mux mode: ALT0 mux port: EMVSIM1_POWER_FAIL of instance: EMVSIM1
0001 - Select mux mode: ALT1 mux port: LPUART8_RTS_B of instance: LPUART8
0010 - Select mux mode: ALT2 mux port: ENET_1G_1588_EVENT3_OUT of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: GPT2_CLK of instance: GPT2
0100 - Select mux mode: ALT4 mux port: FLEXPWM1_PWM2_B of instance: FLEXPWM1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO04 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: WDOG2_B of instance: WDOG2
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D05 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: TMR4_TIMER1 of instance: TMR4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO04 of instance: GPIO9
12.4.5.71 SW_MUX_CTL_PAD_GPIO_AD_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_06)
SW_MUX_CTL Register
12.4.5.71.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 124h
PIO_AD_06
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12.4.5.71.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.71.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_06.
0000 - Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: USB
0001 - Select mux mode: ALT1 mux port: FLEXCAN1_TX of instance: FLEXCAN1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_IO of instance: EMVSIM2
0011 - Select mux mode: ALT3 mux port: GPT3_CAPTURE1 of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA15 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO05 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D06 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: TMR4_TIMER2 of instance: TMR4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO05 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM1_PWM0_X of instance: FLEXPWM1
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12.4.5.72 SW_MUX_CTL_PAD_GPIO_AD_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_07)
SW_MUX_CTL Register
12.4.5.72.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 128h
PIO_AD_07
12.4.5.72.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.72.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_07.
0000 - Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: USB
0001 - Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: FLEXCAN1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_CLK of instance: EMVSIM2
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Field Description
0011 - Select mux mode: ALT3 mux port: GPT3_CAPTURE2 of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA14 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO06 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D07 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: TMR4_TIMER3 of instance: TMR4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO06 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM1_PWM1_X of instance: FLEXPWM1
12.4.5.73 SW_MUX_CTL_PAD_GPIO_AD_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_08)
SW_MUX_CTL Register
12.4.5.73.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 12Ch
PIO_AD_08
12.4.5.73.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.73.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_08.
0000 - Select mux mode: ALT0 mux port: USBPHY2_OTG_ID of instance: USBPHY2
0001 - Select mux mode: ALT1 mux port: LPI2C1_SCL of instance: LPI2C1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_RST of instance: EMVSIM2
0011 - Select mux mode: ALT3 mux port: GPT3_COMPARE1 of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA13 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO07 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT2_IN of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D08 of instance: FLEXIO2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO07 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM1_PWM2_X of instance: FLEXPWM1
12.4.5.74 SW_MUX_CTL_PAD_GPIO_AD_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_09)
SW_MUX_CTL Register
12.4.5.74.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 130h
PIO_AD_09
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12.4.5.74.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.74.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_09.
0000 - Select mux mode: ALT0 mux port: USBPHY1_OTG_ID of instance: USBPHY1
0001 - Select mux mode: ALT1 mux port: LPI2C1_SDA of instance: LPI2C1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_SVEN of instance: EMVSIM2
0011 - Select mux mode: ALT3 mux port: GPT3_COMPARE2 of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA12 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO08 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT2_OUT of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D09 of instance: FLEXIO2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO08 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM1_PWM3_X of instance: FLEXPWM1
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12.4.5.75 SW_MUX_CTL_PAD_GPIO_AD_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_10)
SW_MUX_CTL Register
12.4.5.75.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 134h
PIO_AD_10
12.4.5.75.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.75.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_10.
0000 - Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: USB
0001 - Select mux mode: ALT1 mux port: LPI2C1_SCLS of instance: LPI2C1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_PD of instance: EMVSIM2
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Field Description
0011 - Select mux mode: ALT3 mux port: GPT3_COMPARE3 of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA11 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO09 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT3_IN of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D10 of instance: FLEXIO2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO09 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM2_PWM0_X of instance: FLEXPWM2
12.4.5.76 SW_MUX_CTL_PAD_GPIO_AD_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_11)
SW_MUX_CTL Register
12.4.5.76.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 138h
PIO_AD_11
12.4.5.76.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.76.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_11.
0000 - Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: USB
0001 - Select mux mode: ALT1 mux port: LPI2C1_SDAS of instance: LPI2C1
0010 - Select mux mode: ALT2 mux port: EMVSIM2_POWER_FAIL of instance: EMVSIM2
0011 - Select mux mode: ALT3 mux port: GPT3_CLK of instance: GPT3
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA10 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO10 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_1588_EVENT3_OUT of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D11 of instance: FLEXIO2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO10 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM2_PWM1_X of instance: FLEXPWM2
12.4.5.77 SW_MUX_CTL_PAD_GPIO_AD_12 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_12)
SW_MUX_CTL Register
12.4.5.77.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 13Ch
PIO_AD_12
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12.4.5.77.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.77.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_12
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_12.
0000 - Select mux mode: ALT0 mux port: SPDIF_LOCK of instance: SPDIF
0001 - Select mux mode: ALT1 mux port: LPI2C1_HREQ of instance: LPI2C1
0010 - Select mux mode: ALT2 mux port: GPT1_CAPTURE1 of instance: GPT1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA03 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_PIXCLK of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO11 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_TX_DATA03 of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D12 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: EWM_OUT_B of instance: EWM
1010 - Select mux mode: ALT10 mux port: GPIO9_IO11 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM2_PWM2_X of instance: FLEXPWM2
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12.4.5.78 SW_MUX_CTL_PAD_GPIO_AD_13 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_13)
SW_MUX_CTL Register
12.4.5.78.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 140h
PIO_AD_13
12.4.5.78.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.78.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_13
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_13.
0000 - Select mux mode: ALT0 mux port: SPDIF_SR_CLK of instance: SPDIF
0001 - Select mux mode: ALT1 mux port: PIT1_TRIGGER0 of instance: PIT1
0010 - Select mux mode: ALT2 mux port: GPT1_CAPTURE2 of instance: GPT1
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Field Description
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA02 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_MCLK of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO12 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_TX_DATA02 of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D13 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: REF_CLK_32K of instance: XTAL OSC
1010 - Select mux mode: ALT10 mux port: GPIO9_IO12 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM2_PWM3_X of instance: FLEXPWM2
12.4.5.79 SW_MUX_CTL_PAD_GPIO_AD_14 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_14)
SW_MUX_CTL Register
12.4.5.79.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 144h
PIO_AD_14
12.4.5.79.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.79.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_14
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_14.
0000 - Select mux mode: ALT0 mux port: SPDIF_EXT_CLK of instance: SPDIF
0001 - Select mux mode: ALT1 mux port: REF_CLK_24M of instance: XTAL OSC
0010 - Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: GPT1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA01 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_VSYNC of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO13 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_RX_CLK of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D14 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
1010 - Select mux mode: ALT10 mux port: GPIO9_IO13 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_X of instance: FLEXPWM3
12.4.5.80 SW_MUX_CTL_PAD_GPIO_AD_15 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_15)
SW_MUX_CTL Register
12.4.5.80.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 148h
PIO_AD_15
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12.4.5.80.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.80.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_15
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_15.
0000 - Select mux mode: ALT0 mux port: SPDIF_IN of instance: SPDIF
0001 - Select mux mode: ALT1 mux port: LPUART10_TXD of instance: LPUART10
0010 - Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: GPT1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_DATA00 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_HSYNC of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO14 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_TX_ER of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D15 of instance: FLEXIO2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO14 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM1_X of instance: FLEXPWM3
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12.4.5.81 SW_MUX_CTL_PAD_GPIO_AD_16 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_16)
SW_MUX_CTL Register
12.4.5.81.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 14Ch
PIO_AD_16
12.4.5.81.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.81.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_16
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_16.
0000 - Select mux mode: ALT0 mux port: SPDIF_OUT of instance: SPDIF
0001 - Select mux mode: ALT1 mux port: LPUART10_RXD of instance: LPUART10
0010 - Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: GPT1
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Field Description
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_SCLK of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA09 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO15 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_RX_DATA03 of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D16 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_1G_MDC of instance: ENET_1G
1010 - Select mux mode: ALT10 mux port: GPIO9_IO15 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM2_X of instance: FLEXPWM3
12.4.5.82 SW_MUX_CTL_PAD_GPIO_AD_17 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_17)
SW_MUX_CTL Register
12.4.5.82.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 150h
PIO_AD_17
12.4.5.82.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.82.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_17
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_17.
0000 - Select mux mode: ALT0 mux port: SAI1_MCLK of instance: SAI1
0001 - Select mux mode: ALT1 mux port: ACMP1_OUT of instance: ACMP1
0010 - Select mux mode: ALT2 mux port: GPT1_CLK of instance: GPT1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA08 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO16 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_RX_DATA02 of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D17 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_1G_MDIO of instance: ENET_1G
1010 - Select mux mode: ALT10 mux port: GPIO9_IO16 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM3_PWM3_X of instance: FLEXPWM3
12.4.5.83 SW_MUX_CTL_PAD_GPIO_AD_18 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_18)
SW_MUX_CTL Register
12.4.5.83.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 154h
PIO_AD_18
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12.4.5.83.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.83.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_18
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_18.
0000 - Select mux mode: ALT0 mux port: SAI1_RX_SYNC of instance: SAI1
0001 - Select mux mode: ALT1 mux port: ACMP2_OUT of instance: ACMP2
0010 - Select mux mode: ALT2 mux port: LPSPI1_PCS1 of instance: LPSPI1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_SS0_B of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA07 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO17 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_CRS of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D18 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO17 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM4_PWM0_X of instance: FLEXPWM4
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12.4.5.84 SW_MUX_CTL_PAD_GPIO_AD_19 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_19)
SW_MUX_CTL Register
12.4.5.84.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 158h
PIO_AD_19
12.4.5.84.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.84.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_19
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_19.
0000 - Select mux mode: ALT0 mux port: SAI1_RX_BCLK of instance: SAI1
0001 - Select mux mode: ALT1 mux port: ACMP3_OUT of instance: ACMP3
0010 - Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: LPSPI1
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Field Description
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_SCLK of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA06 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO18 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: ENET_COL of instance: ENET
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D19 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: LPI2C2_SDA of instance: LPI2C2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO18 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM4_PWM1_X of instance: FLEXPWM4
12.4.5.85 SW_MUX_CTL_PAD_GPIO_AD_20 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_20)
SW_MUX_CTL Register
12.4.5.85.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 15Ch
PIO_AD_20
12.4.5.85.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.85.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_20
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_20.
0000 - Select mux mode: ALT0 mux port: SAI1_RX_DATA00 of instance: SAI1
0001 - Select mux mode: ALT1 mux port: ACMP4_OUT of instance: ACMP4
0010 - Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: LPSPI1
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA00 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA05 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO19 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW07 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D20 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_OUT of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO19 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM4_PWM2_X of instance: FLEXPWM4
12.4.5.86 SW_MUX_CTL_PAD_GPIO_AD_21 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_21)
SW_MUX_CTL Register
12.4.5.86.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 160h
PIO_AD_21
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12.4.5.86.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.86.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_21
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_21.
0000 - Select mux mode: ALT0 mux port: SAI1_TX_DATA00 of instance: SAI1
0010 - Select mux mode: ALT2 mux port: LPSPI2_PCS1 of instance: LPSPI2
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA01 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA04 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO20 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL07 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D21 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_IN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO20 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: FLEXPWM4_PWM3_X of instance: FLEXPWM4
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12.4.5.87 SW_MUX_CTL_PAD_GPIO_AD_22 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_22)
SW_MUX_CTL Register
12.4.5.87.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 164h
PIO_AD_22
12.4.5.87.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.87.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_22
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_AD_22.
0000 - Select mux mode: ALT0 mux port: SAI1_TX_BCLK of instance: SAI1
0010 - Select mux mode: ALT2 mux port: LPSPI2_PCS2 of instance: LPSPI2
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA02 of instance: FLEXSPI1
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Field Description
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA03 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO21 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW06 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D22 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_OUT of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO21 of instance: GPIO9
12.4.5.88 SW_MUX_CTL_PAD_GPIO_AD_23 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_23)
SW_MUX_CTL Register
12.4.5.88.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 168h
PIO_AD_23
12.4.5.88.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.88.3 Fields
Field Description
31-5 -
Table continues on the next page...
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_23
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_AD_23.
0000 - Select mux mode: ALT0 mux port: SAI1_TX_SYNC of instance: SAI1
0010 - Select mux mode: ALT2 mux port: LPSPI2_PCS3 of instance: LPSPI2
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_DATA03 of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: VIDEO_MUX_CSI_DATA02 of instance: VIDEO_MUX
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO22 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL06 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D23 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_IN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO22 of instance: GPIO9
12.4.5.89 SW_MUX_CTL_PAD_GPIO_AD_24 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_24)
SW_MUX_CTL Register
12.4.5.89.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 16Ch
PIO_AD_24
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12.4.5.89.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.89.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_24
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_24.
0000 - Select mux mode: ALT0 mux port: LPUART1_TXD of instance: LPUART1
0001 - Select mux mode: ALT1 mux port: LPSPI2_SCK of instance: LPSPI2
0010 - Select mux mode: ALT2 mux port: VIDEO_MUX_CSI_DATA00 of instance: VIDEO_MUX
0011 - Select mux mode: ALT3 mux port: ENET_RX_EN of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM0_A of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO23 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW05 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D24 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: LPI2C4_SCL of instance: LPI2C4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO23 of instance: GPIO9
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12.4.5.90 SW_MUX_CTL_PAD_GPIO_AD_25 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_25)
SW_MUX_CTL Register
12.4.5.90.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 170h
PIO_AD_25
12.4.5.90.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.90.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_25
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_25.
0000 - Select mux mode: ALT0 mux port: LPUART1_RXD of instance: LPUART1
0001 - Select mux mode: ALT1 mux port: LPSPI2_PCS0 of instance: LPSPI2
0010 - Select mux mode: ALT2 mux port: VIDEO_MUX_CSI_DATA01 of instance: VIDEO_MUX
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Field Description
0011 - Select mux mode: ALT3 mux port: ENET_RX_ER of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM0_B of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO24 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL05 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D25 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: LPI2C4_SDA of instance: LPI2C4
1010 - Select mux mode: ALT10 mux port: GPIO9_IO24 of instance: GPIO9
12.4.5.91 SW_MUX_CTL_PAD_GPIO_AD_26 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_26)
SW_MUX_CTL Register
12.4.5.91.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 174h
PIO_AD_26
12.4.5.91.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.91.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_26
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_26.
0000 - Select mux mode: ALT0 mux port: LPUART1_CTS_B of instance: LPUART1
0001 - Select mux mode: ALT1 mux port: LPSPI2_SOUT of instance: LPSPI2
0010 - Select mux mode: ALT2 mux port: SEMC_CSX01 of instance: SEMC
0011 - Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM1_A of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO25 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW04 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D26 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_MDC of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO25 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: USDHC2_CD_B of instance: USDHC2
12.4.5.92 SW_MUX_CTL_PAD_GPIO_AD_27 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_27)
SW_MUX_CTL Register
12.4.5.92.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 178h
PIO_AD_27
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12.4.5.92.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.92.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_27
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_27.
0000 - Select mux mode: ALT0 mux port: LPUART1_RTS_B of instance: LPUART1
0001 - Select mux mode: ALT1 mux port: LPSPI2_SIN of instance: LPSPI2
0010 - Select mux mode: ALT2 mux port: SEMC_CSX02 of instance: SEMC
0011 - Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM1_B of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO26 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL04 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D27 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: ENET_QOS_MDIO of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO9_IO26 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: USDHC2_WP of instance: USDHC2
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12.4.5.93 SW_MUX_CTL_PAD_GPIO_AD_28 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_28)
SW_MUX_CTL Register
12.4.5.93.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 17Ch
PIO_AD_28
12.4.5.93.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.93.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_28
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_28.
0000 - Select mux mode: ALT0 mux port: LPSPI1_SCK of instance: LPSPI1
0001 - Select mux mode: ALT1 mux port: LPUART5_TXD of instance: LPUART5
0010 - Select mux mode: ALT2 mux port: SEMC_CSX03 of instance: SEMC
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Field Description
0011 - Select mux mode: ALT3 mux port: ENET_TX_EN of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM2_A of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO27 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW03 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D28 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX
1010 - Select mux mode: ALT10 mux port: GPIO9_IO27 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: USDHC2_VSELECT of instance: USDHC2
12.4.5.94 SW_MUX_CTL_PAD_GPIO_AD_29 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_29)
SW_MUX_CTL Register
12.4.5.94.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 180h
PIO_AD_29
12.4.5.94.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.94.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_29
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_AD_29.
0000 - Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1
0001 - Select mux mode: ALT1 mux port: LPUART5_RXD of instance: LPUART5
0010 - Select mux mode: ALT2 mux port: ENET_REF_CLK of instance: ENET
0011 - Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: ENET
0100 - Select mux mode: ALT4 mux port: FLEXPWM2_PWM2_B of instance: FLEXPWM2
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO28 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL03 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D29 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX
1010 - Select mux mode: ALT10 mux port: GPIO9_IO28 of instance: GPIO9
1011 - Select mux mode: ALT11 mux port: USDHC2_RESET_B of instance: USDHC2
12.4.5.95 SW_MUX_CTL_PAD_GPIO_AD_30 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_30)
SW_MUX_CTL Register
12.4.5.95.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 184h
PIO_AD_30
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12.4.5.95.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.95.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_30
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_30.
0000 - Select mux mode: ALT0 mux port: LPSPI1_SOUT of instance: LPSPI1
0001 - Select mux mode: ALT1 mux port: USB_OTG2_OC of instance: USB
0010 - Select mux mode: ALT2 mux port: FLEXCAN2_TX of instance: FLEXCAN2
0011 - Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: ENET
0100 - Select mux mode: ALT4 mux port: LPUART3_TXD of instance: LPUART3
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO29 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW02 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D30 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: WDOG2_RESET_B_DEB of instance: WDOG2
1010 - Select mux mode: ALT10 mux port: GPIO9_IO29 of instance: GPIO9
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12.4.5.96 SW_MUX_CTL_PAD_GPIO_AD_31 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_31)
SW_MUX_CTL Register
12.4.5.96.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 188h
PIO_AD_31
12.4.5.96.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.96.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_31
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_31.
0000 - Select mux mode: ALT0 mux port: LPSPI1_SIN of instance: LPSPI1
0001 - Select mux mode: ALT1 mux port: USB_OTG2_PWR of instance: USB
0010 - Select mux mode: ALT2 mux port: FLEXCAN2_RX of instance: FLEXCAN2
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Field Description
0011 - Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: ENET
0100 - Select mux mode: ALT4 mux port: LPUART3_RXD of instance: LPUART3
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO30 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_COL02 of instance: KPP
1000 - Select mux mode: ALT8 mux port: FLEXIO2_D31 of instance: FLEXIO2
1001 - Select mux mode: ALT9 mux port: WDOG1_RESET_B_DEB of instance: WDOG1
1010 - Select mux mode: ALT10 mux port: GPIO9_IO30 of instance: GPIO9
12.4.5.97 SW_MUX_CTL_PAD_GPIO_AD_32 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_32)
SW_MUX_CTL Register
12.4.5.97.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 18Ch
PIO_AD_32
12.4.5.97.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.97.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_32
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_32.
0000 - Select mux mode: ALT0 mux port: LPI2C1_SCL of instance: LPI2C1
0001 - Select mux mode: ALT1 mux port: USBPHY2_OTG_ID of instance: USBPHY2
0010 - Select mux mode: ALT2 mux port: PGMC_PMIC_RDY of instance: pgmc
0011 - Select mux mode: ALT3 mux port: ENET_MDC of instance: ENET
0100 - Select mux mode: ALT4 mux port: USDHC1_CD_B of instance: USDHC1
0101 - Select mux mode: ALT5 mux port: GPIO_MUX3_IO31 of instance: GPIO_MUX3
0110 - Select mux mode: ALT6 mux port: KPP_ROW01 of instance: KPP
1000 - Select mux mode: ALT8 mux port: LPUART10_TXD of instance: LPUART10
1001 - Select mux mode: ALT9 mux port: ENET_1G_MDC of instance: ENET_1G
1010 - Select mux mode: ALT10 mux port: GPIO9_IO31 of instance: GPIO9
12.4.5.98 SW_MUX_CTL_PAD_GPIO_AD_33 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_33)
SW_MUX_CTL Register
12.4.5.98.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 190h
PIO_AD_33
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12.4.5.98.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.98.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_33
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_33.
0000 - Select mux mode: ALT0 mux port: LPI2C1_SDA of instance: LPI2C1
0001 - Select mux mode: ALT1 mux port: USBPHY1_OTG_ID of instance: USBPHY1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT17 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: ENET_MDIO of instance: ENET
0100 - Select mux mode: ALT4 mux port: USDHC1_WP of instance: USDHC1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO00 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: KPP_COL01 of instance: KPP
1000 - Select mux mode: ALT8 mux port: LPUART10_RXD of instance: LPUART10
1001 - Select mux mode: ALT9 mux port: ENET_1G_MDIO of instance: ENET_1G
1010 - Select mux mode: ALT10 mux port: GPIO10_IO00 of instance: GPIO10
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12.4.5.99 SW_MUX_CTL_PAD_GPIO_AD_34 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_34)
SW_MUX_CTL Register
12.4.5.99.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 194h
PIO_AD_34
12.4.5.99.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.99.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_34
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_34.
0000 - Select mux mode: ALT0 mux port: ENET_1G_1588_EVENT0_IN of instance: ENET_1G
0001 - Select mux mode: ALT1 mux port: USB_OTG1_PWR of instance: USB
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT18 of instance: XBAR1
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Field Description
0011 - Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: ENET
0100 - Select mux mode: ALT4 mux port: USDHC1_VSELECT of instance: USDHC1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO01 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: KPP_ROW00 of instance: KPP
1000 - Select mux mode: ALT8 mux port: LPUART10_CTS_B of instance: LPUART10
1001 - Select mux mode: ALT9 mux port: WDOG1_ANY of instance: WDOG1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO01 of instance: GPIO10
12.4.5.100 SW_MUX_CTL_PAD_GPIO_AD_35 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_AD_35)
SW_MUX_CTL Register
12.4.5.100.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 198h
PIO_AD_35
12.4.5.100.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.100.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_AD_35
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_AD_35.
0000 - Select mux mode: ALT0 mux port: ENET_1G_1588_EVENT0_OUT of instance: ENET_1G
0001 - Select mux mode: ALT1 mux port: USB_OTG1_OC of instance: USB
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT19 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: ENET
0100 - Select mux mode: ALT4 mux port: USDHC1_RESET_B of instance: USDHC1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO02 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: KPP_COL00 of instance: KPP
1000 - Select mux mode: ALT8 mux port: LPUART10_RTS_B of instance: LPUART10
1001 - Select mux mode: ALT9 mux port: FLEXSPI1_B_SS1_B of instance: FLEXSPI1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO02 of instance: GPIO10
12.4.5.101 SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_00)
SW_MUX_CTL Register
12.4.5.101.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 19Ch
PIO_SD_B1_00
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12.4.5.101.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.101.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_SD_B1_00.
0000 - Select mux mode: ALT0 mux port: USDHC1_CMD of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT20 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_CAPTURE1 of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO03 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_SS0_B of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: KPP_ROW07 of instance: KPP
1010 - Select mux mode: ALT10 mux port: GPIO10_IO03 of instance: GPIO10
12.4.5.102 SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_01)
SW_MUX_CTL Register
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12.4.5.102.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1A0h
PIO_SD_B1_01
12.4.5.102.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.102.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_SD_B1_01.
0000 - Select mux mode: ALT0 mux port: USDHC1_CLK of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT21 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_CAPTURE2 of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO04 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_SCLK of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: KPP_COL07 of instance: KPP
1010 - Select mux mode: ALT10 mux port: GPIO10_IO04 of instance: GPIO10
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12.4.5.103 SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_02)
SW_MUX_CTL Register
12.4.5.103.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1A4h
PIO_SD_B1_02
12.4.5.103.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.103.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B1_02.
0000 - Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: USDHC1
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Field Description
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT22 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_COMPARE1 of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO05 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA00 of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: KPP_ROW06 of instance: KPP
1001 - Select mux mode: ALT9 mux port: FLEXSPI1_A_SS1_B of instance: FLEXSPI1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO05 of instance: GPIO10
12.4.5.104 SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_03)
SW_MUX_CTL Register
12.4.5.104.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1A8h
PIO_SD_B1_03
12.4.5.104.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.104.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B1_03.
0000 - Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT23 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_COMPARE2 of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO06 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA01 of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: KPP_COL06 of instance: KPP
1001 - Select mux mode: ALT9 mux port: FLEXSPI1_B_SS1_B of instance: FLEXSPI1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO06 of instance: GPIO10
12.4.5.105 SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_04)
SW_MUX_CTL Register
12.4.5.105.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1ACh
PIO_SD_B1_04
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12.4.5.105.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.105.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B1_04.
0000 - Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT24 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_COMPARE3 of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO07 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA02 of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: FLEXSPI1_B_SS0_B of instance: FLEXSPI1
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT2_AUX_IN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO10_IO07 of instance: GPIO10
12.4.5.106 SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B1_05)
SW_MUX_CTL Register
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12.4.5.106.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1B0h
PIO_SD_B1_05
12.4.5.106.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.106.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B1_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B1_05.
0000 - Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: XBAR1_INOUT25 of instance: XBAR1
0011 - Select mux mode: ALT3 mux port: GPT4_CLK of instance: GPT4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO08 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: FLEXSPI2_A_DATA03 of instance: FLEXSPI2
1000 - Select mux mode: ALT8 mux port: FLEXSPI1_B_DQS of instance: FLEXSPI1
1001 - Select mux mode: ALT9 mux port: ENET_QOS_1588_EVENT3_AUX_IN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO10_IO08 of instance: GPIO10
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12.4.5.107 SW_MUX_CTL_PAD_GPIO_SD_B2_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_00)
SW_MUX_CTL Register
12.4.5.107.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1B4h
PIO_SD_B2_00
12.4.5.107.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.107.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_00.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: USDHC2
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Field Description
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA03 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_EN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART9_TXD of instance: LPUART9
0100 - Select mux mode: ALT4 mux port: LPSPI4_SCK of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO09 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO09 of instance: GPIO10
12.4.5.108 SW_MUX_CTL_PAD_GPIO_SD_B2_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_01)
SW_MUX_CTL Register
12.4.5.108.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1B8h
PIO_SD_B2_01
12.4.5.108.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.108.3 Fields
Field Description
31-5 -
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_01.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA02 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_CLK of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART9_RXD of instance: LPUART9
0100 - Select mux mode: ALT4 mux port: LPSPI4_PCS0 of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO10 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO10 of instance: GPIO10
12.4.5.109 SW_MUX_CTL_PAD_GPIO_SD_B2_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_02)
SW_MUX_CTL Register
12.4.5.109.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1BCh
PIO_SD_B2_02
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12.4.5.109.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.109.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_02.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA01 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART9_CTS_B of instance: LPUART9
0100 - Select mux mode: ALT4 mux port: LPSPI4_SOUT of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO11 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO11 of instance: GPIO10
12.4.5.110 SW_MUX_CTL_PAD_GPIO_SD_B2_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_03)
SW_MUX_CTL Register
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12.4.5.110.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1C0h
PIO_SD_B2_03
12.4.5.110.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.110.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_03.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_B_DATA00 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART9_RTS_B of instance: LPUART9
0100 - Select mux mode: ALT4 mux port: LPSPI4_SIN of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO12 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO12 of instance: GPIO10
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12.4.5.111 SW_MUX_CTL_PAD_GPIO_SD_B2_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_04)
SW_MUX_CTL Register
12.4.5.111.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1C4h
PIO_SD_B2_04
12.4.5.111.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.111.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_04.
0000 - Select mux mode: ALT0 mux port: USDHC2_CLK of instance: USDHC2
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Field Description
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_B_SCLK of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_A_SS1_B of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: LPSPI4_PCS1 of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO13 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO13 of instance: GPIO10
12.4.5.112 SW_MUX_CTL_PAD_GPIO_SD_B2_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_05)
SW_MUX_CTL Register
12.4.5.112.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1C8h
PIO_SD_B2_05
12.4.5.112.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.112.3 Fields
Field Description
31-5 -
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_05.
0000 - Select mux mode: ALT0 mux port: USDHC2_CMD of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_DQS of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: FLEXSPI1_B_SS0_B of instance: FLEXSPI1
0100 - Select mux mode: ALT4 mux port: LPSPI4_PCS2 of instance: LPSPI4
0101 - Select mux mode: ALT5 mux port: GPIO4__IO14 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO14 of instance: GPIO10
12.4.5.113 SW_MUX_CTL_PAD_GPIO_SD_B2_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_06)
SW_MUX_CTL Register
12.4.5.113.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1CCh
PIO_SD_B2_06
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12.4.5.113.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.113.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 8 iomux modes to be used for pad: GPIO_SD_B2_06.
0000 - Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_SS0_B of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPSPI4_PCS3 of instance: LPSPI4
0100 - Select mux mode: ALT4 mux port: GPT6_CAPTURE1 of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO15 of instance: GPIO4_
1010 - Select mux mode: ALT10 mux port: GPIO10_IO15 of instance: GPIO10
12.4.5.114 SW_MUX_CTL_PAD_GPIO_SD_B2_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_07)
SW_MUX_CTL Register
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12.4.5.114.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1D0h
PIO_SD_B2_07
12.4.5.114.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.114.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_SD_B2_07.
0000 - Select mux mode: ALT0 mux port: USDHC2_STROBE of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_SCLK of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART3_CTS_B of instance: LPUART3
0100 - Select mux mode: ALT4 mux port: GPT6_CAPTURE2 of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO16 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: LPSPI2_SCK of instance: LPSPI2
1000 - Select mux mode: ALT8 mux port: ENET_TX_ER of instance: ENET
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Field Description
1001 - Select mux mode: ALT9 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO10_IO16 of instance: GPIO10
12.4.5.115 SW_MUX_CTL_PAD_GPIO_SD_B2_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_08)
SW_MUX_CTL Register
12.4.5.115.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1D4h
PIO_SD_B2_08
12.4.5.115.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.115.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
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Field Description
1 - Force input path of pad GPIO_SD_B2_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B2_08.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA00 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART3_RTS_B of instance: LPUART3
0100 - Select mux mode: ALT4 mux port: GPT6_COMPARE1 of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO17 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: LPSPI2_PCS0 of instance: LPSPI2
1010 - Select mux mode: ALT10 mux port: GPIO10_IO17 of instance: GPIO10
12.4.5.116 SW_MUX_CTL_PAD_GPIO_SD_B2_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_09)
SW_MUX_CTL Register
12.4.5.116.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1D8h
PIO_SD_B2_09
12.4.5.116.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.116.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B2_09.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA01 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART5_CTS_B of instance: LPUART5
0100 - Select mux mode: ALT4 mux port: GPT6_COMPARE2 of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO18 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: LPSPI2_SOUT of instance: LPSPI2
1010 - Select mux mode: ALT10 mux port: GPIO10_IO18 of instance: GPIO10
12.4.5.117 SW_MUX_CTL_PAD_GPIO_SD_B2_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_10)
SW_MUX_CTL Register
12.4.5.117.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1DCh
PIO_SD_B2_10
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12.4.5.117.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.117.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B2_10.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA02 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_EN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: LPUART5_RTS_B of instance: LPUART5
0100 - Select mux mode: ALT4 mux port: GPT6_COMPARE3 of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO19 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: LPSPI2_SIN of instance: LPSPI2
1010 - Select mux mode: ALT10 mux port: GPIO10_IO19 of instance: GPIO10
12.4.5.118 SW_MUX_CTL_PAD_GPIO_SD_B2_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_SD_B2_11)
SW_MUX_CTL Register
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12.4.5.118.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1E0h
PIO_SD_B2_11
12.4.5.118.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.118.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_SD_B2_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_SD_B2_11.
0000 - Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: USDHC2
0001 - Select mux mode: ALT1 mux port: FLEXSPI1_A_DATA03 of instance: FLEXSPI1
0010 - Select mux mode: ALT2 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: ENET_1G_REF_CLK of instance: ENET_1G
0100 - Select mux mode: ALT4 mux port: GPT6_CLK of instance: GPT6
0101 - Select mux mode: ALT5 mux port: GPIO4__IO20 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: LPSPI2_PCS1 of instance: LPSPI2
1010 - Select mux mode: ALT10 mux port: GPIO10_IO20 of instance: GPIO10
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12.4.5.119 SW_MUX_CTL_PAD_GPIO_DISP_B1_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_00)
SW_MUX_CTL Register
12.4.5.119.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1E4h
PIO_DISP_B1_00
12.4.5.119.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.119.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_DISP_B1_00.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_CLK of instance: VIDEO_MUX
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Field Description
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_EN of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: TMR1_TIMER0 of instance: TMR1
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT26 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO21 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_EN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO10_IO21 of instance: GPIO10
12.4.5.120 SW_MUX_CTL_PAD_GPIO_DISP_B1_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_01)
SW_MUX_CTL Register
12.4.5.120.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1E8h
PIO_DISP_B1_01
12.4.5.120.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.120.3 Fields
Field Description
31-5 -
Table continues on the next page...
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Field Description
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_01.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_ENABLE of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_CLK of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: ENET_1G_RX_ER of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: TMR1_TIMER1 of instance: TMR1
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT27 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO22 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_CLK of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: ENET_QOS_RX_ER of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO10_IO22 of instance: GPIO10
12.4.5.121 SW_MUX_CTL_PAD_GPIO_DISP_B1_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_02)
SW_MUX_CTL Register
12.4.5.121.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1ECh
PIO_DISP_B1_02
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12.4.5.121.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.121.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_02.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_HSYNC of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_DATA00 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: LPI2C3
0011 - Select mux mode: ALT3 mux port: TMR1_TIMER2 of instance: TMR1
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT28 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO23 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA00 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPUART1_TXD of instance: LPUART1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO23 of instance: GPIO10
12.4.5.122 SW_MUX_CTL_PAD_GPIO_DISP_B1_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_03)
SW_MUX_CTL Register
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12.4.5.122.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1F0h
PIO_DISP_B1_03
12.4.5.122.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.122.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_03.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_VSYNC of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_DATA01 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: LPI2C3
0011 - Select mux mode: ALT3 mux port: TMR2_TIMER0 of instance: TMR2
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT29 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO24 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA01 of instance: ENET_QOS
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Field Description
1001 - Select mux mode: ALT9 mux port: LPUART1_RXD of instance: LPUART1
1010 - Select mux mode: ALT10 mux port: GPIO10_IO24 of instance: GPIO10
12.4.5.123 SW_MUX_CTL_PAD_GPIO_DISP_B1_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_04)
SW_MUX_CTL Register
12.4.5.123.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1F4h
PIO_DISP_B1_04
12.4.5.123.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.123.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
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Field Description
1 - Force input path of pad GPIO_DISP_B1_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_04.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA00 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_DATA02 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPUART4_RXD of instance: LPUART4
0011 - Select mux mode: ALT3 mux port: TMR2_TIMER1 of instance: TMR2
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT30 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO25 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA02 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_SCK of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO25 of instance: GPIO10
12.4.5.124 SW_MUX_CTL_PAD_GPIO_DISP_B1_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_05)
SW_MUX_CTL Register
12.4.5.124.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1F8h
PIO_DISP_B1_05
12.4.5.124.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.124.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_05.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA01 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_RX_DATA03 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: LPUART4
0011 - Select mux mode: ALT3 mux port: TMR2_TIMER2 of instance: TMR2
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT31 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO26 of instance: GPIO4_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA03 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_SIN of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO26 of instance: GPIO10
12.4.5.125 SW_MUX_CTL_PAD_GPIO_DISP_B1_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_06)
SW_MUX_CTL Register
12.4.5.125.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 1FCh
PIO_DISP_B1_06
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12.4.5.125.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.125.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_06.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA02 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_DATA03 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPUART4_TXD of instance: LPUART4
0011 - Select mux mode: ALT3 mux port: TMR3_TIMER0 of instance: TMR3
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT32 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO27 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG00 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA03 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_SOUT of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO27 of instance: GPIO10
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12.4.5.126 SW_MUX_CTL_PAD_GPIO_DISP_B1_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_07)
SW_MUX_CTL Register
12.4.5.126.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 200h
PIO_DISP_B1_07
12.4.5.126.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.126.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_07.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA03 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_DATA02 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: LPUART4
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Field Description
0011 - Select mux mode: ALT3 mux port: TMR3_TIMER1 of instance: TMR3
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT33 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO28 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG01 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA02 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_PCS0 of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO28 of instance: GPIO10
12.4.5.127 SW_MUX_CTL_PAD_GPIO_DISP_B1_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_08)
SW_MUX_CTL Register
12.4.5.127.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 204h
PIO_DISP_B1_08
12.4.5.127.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.127.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_08.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA04 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_DATA01 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: USDHC1
0011 - Select mux mode: ALT3 mux port: TMR3_TIMER2 of instance: TMR3
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT34 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO29 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG02 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA01 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_PCS1 of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO29 of instance: GPIO10
12.4.5.128 SW_MUX_CTL_PAD_GPIO_DISP_B1_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_09)
SW_MUX_CTL Register
12.4.5.128.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 208h
PIO_DISP_B1_09
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12.4.5.128.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.128.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_09.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA05 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_DATA00 of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: USDHC1_WP of instance: USDHC1
0011 - Select mux mode: ALT3 mux port: TMR4_TIMER0 of instance: TMR4
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT35 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO30 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG03 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA00 of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_PCS2 of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO30 of instance: GPIO10
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12.4.5.129 SW_MUX_CTL_PAD_GPIO_DISP_B1_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_10)
SW_MUX_CTL Register
12.4.5.129.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 20Ch
PIO_DISP_B1_10
12.4.5.129.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.129.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_10.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA06 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_EN of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: USDHC1
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Field Description
0011 - Select mux mode: ALT3 mux port: TMR4_TIMER1 of instance: TMR4
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT36 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO4__IO31 of instance: GPIO4_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG04 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_EN of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI3_PCS3 of instance: LPSPI3
1010 - Select mux mode: ALT10 mux port: GPIO10_IO31 of instance: GPIO10
12.4.5.130 SW_MUX_CTL_PAD_GPIO_DISP_B1_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B1_11)
SW_MUX_CTL Register
12.4.5.130.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 210h
PIO_DISP_B1_11
12.4.5.130.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.130.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B1_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B1_11.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA07 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_1G_TX_CLK_IO of instance: ENET_1G
0010 - Select mux mode: ALT2 mux port: ENET_1G_REF_CLK of instance: ENET_1G
0011 - Select mux mode: ALT3 mux port: TMR4_TIMER2 of instance: TMR4
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT37 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO00 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG05 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_CLK of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: ENET_QOS_REF_CLK of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO00 of instance: GPIO11
12.4.5.131 SW_MUX_CTL_PAD_GPIO_DISP_B2_00 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_00)
SW_MUX_CTL Register
12.4.5.131.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 214h
PIO_DISP_B2_00
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12.4.5.131.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.131.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_00
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_DISP_B2_00.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA08 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: WDOG1_B of instance: WDOG1
0010 - Select mux mode: ALT2 mux port: MQS_RIGHT of instance: MQS
0011 - Select mux mode: ALT3 mux port: ENET_1G_TX_ER of instance: ENET_1G
0100 - Select mux mode: ALT4 mux port: SAI1_TX_DATA03 of instance SAI1 and SAI1_RX_DATA01 of
instance SAI1 as output
0101 - Select mux mode: ALT5 mux port: GPIO5__IO01 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG06 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_ER of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO01 of instance: GPIO11
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12.4.5.132 SW_MUX_CTL_PAD_GPIO_DISP_B2_01 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_01)
SW_MUX_CTL Register
12.4.5.132.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 218h
PIO_DISP_B2_01
12.4.5.132.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.132.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_01
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_DISP_B2_01.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA09 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: USDHC1_VSELECT of instance: USDHC1
0010 - Select mux mode: ALT2 mux port: MQS_LEFT of instance: MQS
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Field Description
0011 - Select mux mode: ALT3 mux port: WDOG2_B of instance: WDOG2
0100 - Select mux mode: ALT4 mux port: SAI1_TX_DATA02 of instance SAI1 and SAI1_RX_DATA02 of
instance SAI1 as output
0101 - Select mux mode: ALT5 mux port: GPIO5__IO02 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG07 of instance: SRC
1000 - Select mux mode: ALT8 mux port: EWM_OUT_B of instance: EWM
1001 - Select mux mode: ALT9 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
1010 - Select mux mode: ALT10 mux port: GPIO11_IO02 of instance: GPIO11
12.4.5.133 SW_MUX_CTL_PAD_GPIO_DISP_B2_02 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_02)
SW_MUX_CTL Register
12.4.5.133.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 21Ch
PIO_DISP_B2_02
12.4.5.133.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.133.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_02
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_DISP_B2_02.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA10 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_TX_DATA00 of instance: ENET
0010 - Select mux mode: ALT2 mux port: PIT1_TRIGGER3 of instance: PIT1
0011 - Select mux mode: ALT3 mux port: ARM_TRACE00 of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_TX_DATA01 of instance SAI1 as input and
SAI1_RX_DATA03 of instance SAI1 as output
0101 - Select mux mode: ALT5 mux port: GPIO5__IO03 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG08 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA00 of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO03 of instance: GPIO11
12.4.5.134 SW_MUX_CTL_PAD_GPIO_DISP_B2_03 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_03)
SW_MUX_CTL Register
12.4.5.134.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 220h
PIO_DISP_B2_03
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12.4.5.134.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.134.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_03
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_DISP_B2_03.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA11 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_TX_DATA01 of instance: ENET
0010 - Select mux mode: ALT2 mux port: PIT1_TRIGGER2 of instance: PIT1
0011 - Select mux mode: ALT3 mux port: ARM_TRACE01 of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_MCLK of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO04 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG09 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_DATA01 of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO04 of instance: GPIO11
12.4.5.135 SW_MUX_CTL_PAD_GPIO_DISP_B2_04 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_04)
SW_MUX_CTL Register
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12.4.5.135.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 224h
PIO_DISP_B2_04
12.4.5.135.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.135.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_04
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_DISP_B2_04.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA12 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_TX_EN of instance: ENET
0010 - Select mux mode: ALT2 mux port: PIT1_TRIGGER1 of instance: PIT1
0011 - Select mux mode: ALT3 mux port: ARM_TRACE02 of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_RX_SYNC of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO05 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG10 of instance: SRC
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Field Description
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_EN of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO05 of instance: GPIO11
12.4.5.136 SW_MUX_CTL_PAD_GPIO_DISP_B2_05 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_05)
SW_MUX_CTL Register
12.4.5.136.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 228h
PIO_DISP_B2_05
12.4.5.136.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.136.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
Table continues on the next page...
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Field Description
1 - Force input path of pad GPIO_DISP_B2_05
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 10 iomux modes to be used for pad: GPIO_DISP_B2_05.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA13 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_TX_CLK of instance: ENET
0010 - Select mux mode: ALT2 mux port: ENET_REF_CLK of instance: ENET
0011 - Select mux mode: ALT3 mux port: ARM_TRACE03 of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_RX_BCLK of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO06 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: SRC_BT_CFG11 of instance: SRC
1000 - Select mux mode: ALT8 mux port: ENET_QOS_TX_CLK of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO06 of instance: GPIO11
12.4.5.137 SW_MUX_CTL_PAD_GPIO_DISP_B2_06 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_06)
SW_MUX_CTL Register
12.4.5.137.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 22Ch
PIO_DISP_B2_06
12.4.5.137.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.137.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_06
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_DISP_B2_06.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA14 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_RX_DATA00 of instance: ENET
0010 - Select mux mode: ALT2 mux port: LPUART7_TXD of instance: LPUART7
0011 - Select mux mode: ALT3 mux port: ARM_TRACE_CLK of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_RX_DATA00 of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO07 of instance: GPIO5_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA00 of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO07 of instance: GPIO11
12.4.5.138 SW_MUX_CTL_PAD_GPIO_DISP_B2_07 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_07)
SW_MUX_CTL Register
12.4.5.138.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 230h
PIO_DISP_B2_07
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12.4.5.138.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.138.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_07
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 9 iomux modes to be used for pad: GPIO_DISP_B2_07.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA15 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_RX_DATA01 of instance: ENET
0010 - Select mux mode: ALT2 mux port: LPUART7_RXD of instance: LPUART7
0011 - Select mux mode: ALT3 mux port: ARM_TRACE_SWO of instance: ARM
0100 - Select mux mode: ALT4 mux port: SAI1_TX_DATA00 of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO08 of instance: GPIO5_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_DATA01 of instance: ENET_QOS
1010 - Select mux mode: ALT10 mux port: GPIO11_IO08 of instance: GPIO11
12.4.5.139 SW_MUX_CTL_PAD_GPIO_DISP_B2_08 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_08)
SW_MUX_CTL Register
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12.4.5.139.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 234h
PIO_DISP_B2_08
12.4.5.139.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.139.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_08
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_DISP_B2_08.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA16 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: ENET_RX_EN of instance: ENET
0010 - Select mux mode: ALT2 mux port: LPUART8_TXD of instance: LPUART8
0011 - Select mux mode: ALT3 mux port: ARM_CM7_EVENTO of instance: CM7
0100 - Select mux mode: ALT4 mux port: SAI1_TX_BCLK of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO09 of instance: GPIO5_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_EN of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPUART1_TXD of instance: LPUART1
1010 - Select mux mode: ALT10 mux port: GPIO11_IO09 of instance: GPIO11
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12.4.5.140 SW_MUX_CTL_PAD_GPIO_DISP_B2_09 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_09)
SW_MUX_CTL Register
12.4.5.140.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 238h
PIO_DISP_B2_09
12.4.5.140.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.140.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_09
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_DISP_B2_09.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA17 of instance: VIDEO_MUX
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Field Description
0001 - Select mux mode: ALT1 mux port: ENET_RX_ER of instance: ENET
0010 - Select mux mode: ALT2 mux port: LPUART8_RXD of instance: LPUART8
0011 - Select mux mode: ALT3 mux port: ARM_CM7_EVENTI of instance: CM7
0100 - Select mux mode: ALT4 mux port: SAI1_TX_SYNC of instance: SAI1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO10 of instance: GPIO5_
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_ER of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPUART1_RXD of instance: LPUART1
1010 - Select mux mode: ALT10 mux port: GPIO11_IO10 of instance: GPIO11
12.4.5.141 SW_MUX_CTL_PAD_GPIO_DISP_B2_10 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_10)
SW_MUX_CTL Register
12.4.5.141.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 23Ch
PIO_DISP_B2_10
12.4.5.141.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.141.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_10
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B2_10.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA18 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_IO of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: LPUART2_TXD of instance: LPUART2
0011 - Select mux mode: ALT3 mux port: WDOG2_RESET_B_DEB of instance: WDOG2
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT38 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO11 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: LPI2C3_SCL of instance: LPI2C3
1000 - Select mux mode: ALT8 mux port: ENET_QOS_RX_ER of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: SPDIF_IN of instance: SPDIF
1010 - Select mux mode: ALT10 mux port: GPIO11_IO11 of instance: GPIO11
12.4.5.142 SW_MUX_CTL_PAD_GPIO_DISP_B2_11 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_11)
SW_MUX_CTL Register
12.4.5.142.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 240h
PIO_DISP_B2_11
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12.4.5.142.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.142.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_11
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B2_11.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA19 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_CLK of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: LPUART2_RXD of instance: LPUART2
0011 - Select mux mode: ALT3 mux port: WDOG1_RESET_B_DEB of instance: WDOG1
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT39 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO12 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: LPI2C3_SDA of instance: LPI2C3
1000 - Select mux mode: ALT8 mux port: ENET_QOS_CRS of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: SPDIF_OUT of instance: SPDIF
1010 - Select mux mode: ALT10 mux port: GPIO11_IO12 of instance: GPIO11
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12.4.5.143 SW_MUX_CTL_PAD_GPIO_DISP_B2_12 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_12)
SW_MUX_CTL Register
12.4.5.143.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 244h
PIO_DISP_B2_12
12.4.5.143.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.143.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_12
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B2_12.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA20 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_RST of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: FLEXCAN1
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Field Description
0011 - Select mux mode: ALT3 mux port: LPUART2_CTS_B of instance: LPUART2
0100 - Select mux mode: ALT4 mux port: XBAR1_INOUT40 of instance: XBAR1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO13 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: LPI2C4_SCL of instance: LPI2C4
1000 - Select mux mode: ALT8 mux port: ENET_QOS_COL of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI4_SCK of instance: LPSPI4
1010 - Select mux mode: ALT10 mux port: GPIO11_IO13 of instance: GPIO11
12.4.5.144 SW_MUX_CTL_PAD_GPIO_DISP_B2_13 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_13)
SW_MUX_CTL Register
12.4.5.144.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 248h
PIO_DISP_B2_13
12.4.5.144.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MUX_MODE
Reserved
SION
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
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12.4.5.144.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_13
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 12 iomux modes to be used for pad: GPIO_DISP_B2_13.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA21 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_SVEN of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: FLEXCAN1
0011 - Select mux mode: ALT3 mux port: LPUART2_RTS_B of instance: LPUART2
0100 - Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: ENET
0101 - Select mux mode: ALT5 mux port: GPIO5__IO14 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: LPI2C4_SDA of instance: LPI2C4
1000 - Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_OUT of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI4_SIN of instance: LPSPI4
1010 - Select mux mode: ALT10 mux port: GPIO11_IO14 of instance: GPIO11
12.4.5.145 SW_MUX_CTL_PAD_GPIO_DISP_B2_14 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_14)
SW_MUX_CTL Register
12.4.5.145.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 24Ch
PIO_DISP_B2_14
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12.4.5.145.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.145.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_14
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_DISP_B2_14.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA22 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_PD of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_EXT_DCIC1 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: ENET_1G_REF_CLK of instance: ENET_1G
0101 - Select mux mode: ALT5 mux port: GPIO5__IO15 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: FLEXCAN1_TX of instance: FLEXCAN1
1000 - Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_IN of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI4_SOUT of instance: LPSPI4
1010 - Select mux mode: ALT10 mux port: GPIO11_IO15 of instance: GPIO11
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12.4.5.146 SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control
Register (SW_MUX_CTL_PAD_GPIO_DISP_B2_15)
SW_MUX_CTL Register
12.4.5.146.1 Offset
Register Offset
SW_MUX_CTL_PAD_G 250h
PIO_DISP_B2_15
12.4.5.146.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_MODE
Reserved
SION
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
12.4.5.146.3 Fields
Field Description
31-5 -
— Reserved
4 Software Input On Field.
SION Force the selected mux mode Input path no matter of MUX_MODE functionality.
0 - Input Path is determined by functionality
1 - Force input path of pad GPIO_DISP_B2_15
3-0 MUX Mode Select Field.
MUX_MODE Select 1 of 11 iomux modes to be used for pad: GPIO_DISP_B2_15.
0000 - Select mux mode: ALT0 mux port: VIDEO_MUX_LCDIF_DATA23 of instance: VIDEO_MUX
0001 - Select mux mode: ALT1 mux port: EMVSIM2_POWER_FAIL of instance: EMVSIM2
0010 - Select mux mode: ALT2 mux port: WDOG1_B of instance: WDOG1
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Field Description
0011 - Select mux mode: ALT3 mux port: VIDEO_MUX_EXT_DCIC2 of instance: VIDEO_MUX
0100 - Select mux mode: ALT4 mux port: PIT1_TRIGGER0 of instance: PIT1
0101 - Select mux mode: ALT5 mux port: GPIO5__IO16 of instance: GPIO5_
0110 - Select mux mode: ALT6 mux port: FLEXCAN1_RX of instance: FLEXCAN1
1000 - Select mux mode: ALT8 mux port: ENET_QOS_1588_EVENT0_AUX_IN of instance: ENET_QOS
1001 - Select mux mode: ALT9 mux port: LPSPI4_PCS0 of instance: LPSPI4
1010 - Select mux mode: ALT10 mux port: GPIO11_IO16 of instance: GPIO11
12.4.5.147 SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_00)
SW_PAD_CTL Register
12.4.5.147.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 254h
PIO_EMC_B1_00
12.4.5.147.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
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12.4.5.147.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_00
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_00
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_00
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
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12.4.5.148 SW_PAD_CTL_PAD_GPIO_EMC_B1_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_01)
SW_PAD_CTL Register
12.4.5.148.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 258h
PIO_EMC_B1_01
12.4.5.148.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.148.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
Table continues on the next page...
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Field Description
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_01
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_01
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_01
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.149 SW_PAD_CTL_PAD_GPIO_EMC_B1_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_02)
SW_PAD_CTL Register
12.4.5.149.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 25Ch
PIO_EMC_B1_02
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12.4.5.149.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
W DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.149.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_02
0 - Disabled
1 - Enabled
Table continues on the next page...
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Field Description
3-2 Pull Down Pull Up Field
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_02
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_02
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.150 SW_PAD_CTL_PAD_GPIO_EMC_B1_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_03)
SW_PAD_CTL Register
12.4.5.150.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 260h
PIO_EMC_B1_03
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12.4.5.150.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.150.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_03
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_03
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_03
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.151 SW_PAD_CTL_PAD_GPIO_EMC_B1_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_04)
SW_PAD_CTL Register
12.4.5.151.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 264h
PIO_EMC_B1_04
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12.4.5.151.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.151.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_04
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_04
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_04
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.152 SW_PAD_CTL_PAD_GPIO_EMC_B1_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_05)
SW_PAD_CTL Register
12.4.5.152.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 268h
PIO_EMC_B1_05
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12.4.5.152.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.152.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_05
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_05
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_05
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.153 SW_PAD_CTL_PAD_GPIO_EMC_B1_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_06)
SW_PAD_CTL Register
12.4.5.153.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 26Ch
PIO_EMC_B1_06
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12.4.5.153.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.153.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_06
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_06
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_06
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.154 SW_PAD_CTL_PAD_GPIO_EMC_B1_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_07)
SW_PAD_CTL Register
12.4.5.154.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 270h
PIO_EMC_B1_07
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12.4.5.154.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.154.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_07
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_07
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_07
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.155 SW_PAD_CTL_PAD_GPIO_EMC_B1_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_08)
SW_PAD_CTL Register
12.4.5.155.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 274h
PIO_EMC_B1_08
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12.4.5.155.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.155.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_08
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_08
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_08
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.156 SW_PAD_CTL_PAD_GPIO_EMC_B1_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_09)
SW_PAD_CTL Register
12.4.5.156.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 278h
PIO_EMC_B1_09
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12.4.5.156.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.156.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_09
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_09
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_09
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.157 SW_PAD_CTL_PAD_GPIO_EMC_B1_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_10)
SW_PAD_CTL Register
12.4.5.157.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 27Ch
PIO_EMC_B1_10
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12.4.5.157.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.157.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_10
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_10
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_10
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.158 SW_PAD_CTL_PAD_GPIO_EMC_B1_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_11)
SW_PAD_CTL Register
12.4.5.158.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 280h
PIO_EMC_B1_11
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12.4.5.158.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.158.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_11
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_11
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_11
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.159 SW_PAD_CTL_PAD_GPIO_EMC_B1_12 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_12)
SW_PAD_CTL Register
12.4.5.159.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 284h
PIO_EMC_B1_12
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12.4.5.159.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.159.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_12
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_12
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_12
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.160 SW_PAD_CTL_PAD_GPIO_EMC_B1_13 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_13)
SW_PAD_CTL Register
12.4.5.160.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 288h
PIO_EMC_B1_13
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12.4.5.160.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.160.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_13
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_13
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_13
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.161 SW_PAD_CTL_PAD_GPIO_EMC_B1_14 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_14)
SW_PAD_CTL Register
12.4.5.161.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 28Ch
PIO_EMC_B1_14
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12.4.5.161.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.161.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_14
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_14
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_14
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.162 SW_PAD_CTL_PAD_GPIO_EMC_B1_15 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_15)
SW_PAD_CTL Register
12.4.5.162.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 290h
PIO_EMC_B1_15
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12.4.5.162.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.162.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_15
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_15
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_15
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.163 SW_PAD_CTL_PAD_GPIO_EMC_B1_16 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_16)
SW_PAD_CTL Register
12.4.5.163.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 294h
PIO_EMC_B1_16
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12.4.5.163.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.163.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_16
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_16
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_16
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.164 SW_PAD_CTL_PAD_GPIO_EMC_B1_17 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_17)
SW_PAD_CTL Register
12.4.5.164.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 298h
PIO_EMC_B1_17
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12.4.5.164.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.164.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_17
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_17
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_17
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.165 SW_PAD_CTL_PAD_GPIO_EMC_B1_18 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_18)
SW_PAD_CTL Register
12.4.5.165.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 29Ch
PIO_EMC_B1_18
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12.4.5.165.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.165.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_18
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_18
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_18
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.166 SW_PAD_CTL_PAD_GPIO_EMC_B1_19 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_19)
SW_PAD_CTL Register
12.4.5.166.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2A0h
PIO_EMC_B1_19
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12.4.5.166.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.166.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_19
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_19
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_19
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.167 SW_PAD_CTL_PAD_GPIO_EMC_B1_20 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_20)
SW_PAD_CTL Register
12.4.5.167.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2A4h
PIO_EMC_B1_20
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12.4.5.167.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.167.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_20
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_20
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_20
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.168 SW_PAD_CTL_PAD_GPIO_EMC_B1_21 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_21)
SW_PAD_CTL Register
12.4.5.168.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2A8h
PIO_EMC_B1_21
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12.4.5.168.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.168.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_21
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_21
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_21
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.169 SW_PAD_CTL_PAD_GPIO_EMC_B1_22 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_22)
SW_PAD_CTL Register
12.4.5.169.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2ACh
PIO_EMC_B1_22
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12.4.5.169.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.169.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_22
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_22
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_22
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.170 SW_PAD_CTL_PAD_GPIO_EMC_B1_23 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_23)
SW_PAD_CTL Register
12.4.5.170.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2B0h
PIO_EMC_B1_23
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12.4.5.170.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.170.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_23
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_23
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_23
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.171 SW_PAD_CTL_PAD_GPIO_EMC_B1_24 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_24)
SW_PAD_CTL Register
12.4.5.171.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2B4h
PIO_EMC_B1_24
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12.4.5.171.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.171.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_24
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_24
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_24
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.172 SW_PAD_CTL_PAD_GPIO_EMC_B1_25 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_25)
SW_PAD_CTL Register
12.4.5.172.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2B8h
PIO_EMC_B1_25
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12.4.5.172.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.172.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_25
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_25
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_25
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.173 SW_PAD_CTL_PAD_GPIO_EMC_B1_26 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_26)
SW_PAD_CTL Register
12.4.5.173.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2BCh
PIO_EMC_B1_26
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12.4.5.173.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.173.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_26
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_26
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_26
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.174 SW_PAD_CTL_PAD_GPIO_EMC_B1_27 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_27)
SW_PAD_CTL Register
12.4.5.174.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2C0h
PIO_EMC_B1_27
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.174.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.174.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_27
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1011
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_27
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_27
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.175 SW_PAD_CTL_PAD_GPIO_EMC_B1_28 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_28)
SW_PAD_CTL Register
12.4.5.175.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2C4h
PIO_EMC_B1_28
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.175.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.175.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_28
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1013
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_28
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_28
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.176 SW_PAD_CTL_PAD_GPIO_EMC_B1_29 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_29)
SW_PAD_CTL Register
12.4.5.176.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2C8h
PIO_EMC_B1_29
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.176.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.176.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_29
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1015
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_29
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_29
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.177 SW_PAD_CTL_PAD_GPIO_EMC_B1_30 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_30)
SW_PAD_CTL Register
12.4.5.177.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2CCh
PIO_EMC_B1_30
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.177.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.177.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_30
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1017
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_30
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_30
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.178 SW_PAD_CTL_PAD_GPIO_EMC_B1_31 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_31)
SW_PAD_CTL Register
12.4.5.178.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2D0h
PIO_EMC_B1_31
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.178.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.178.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_31
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1019
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_31
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_31
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.179 SW_PAD_CTL_PAD_GPIO_EMC_B1_32 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_32)
SW_PAD_CTL Register
12.4.5.179.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2D4h
PIO_EMC_B1_32
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.179.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.179.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_32
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_32
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_32
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.180 SW_PAD_CTL_PAD_GPIO_EMC_B1_33 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_33)
SW_PAD_CTL Register
12.4.5.180.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2D8h
PIO_EMC_B1_33
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.180.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.180.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_33
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_33
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_33
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.181 SW_PAD_CTL_PAD_GPIO_EMC_B1_34 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_34)
SW_PAD_CTL Register
12.4.5.181.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2DCh
PIO_EMC_B1_34
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.181.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.181.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_34
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_34
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_34
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.182 SW_PAD_CTL_PAD_GPIO_EMC_B1_35 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_35)
SW_PAD_CTL Register
12.4.5.182.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2E0h
PIO_EMC_B1_35
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.182.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.182.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_35
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_35
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_35
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.183 SW_PAD_CTL_PAD_GPIO_EMC_B1_36 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_36)
SW_PAD_CTL Register
12.4.5.183.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2E4h
PIO_EMC_B1_36
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.183.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.183.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_36
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1029
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_36
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_36
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.184 SW_PAD_CTL_PAD_GPIO_EMC_B1_37 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_37)
SW_PAD_CTL Register
12.4.5.184.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2E8h
PIO_EMC_B1_37
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.184.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.184.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_37
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1031
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_37
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_37
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.185 SW_PAD_CTL_PAD_GPIO_EMC_B1_38 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_38)
SW_PAD_CTL Register
12.4.5.185.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2ECh
PIO_EMC_B1_38
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.185.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.185.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_38
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_38
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_38
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.186 SW_PAD_CTL_PAD_GPIO_EMC_B1_39 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_39)
SW_PAD_CTL Register
12.4.5.186.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2F0h
PIO_EMC_B1_39
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.186.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.186.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_39
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_39
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_39
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.187 SW_PAD_CTL_PAD_GPIO_EMC_B1_40 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_40)
SW_PAD_CTL Register
12.4.5.187.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2F4h
PIO_EMC_B1_40
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.187.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.187.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_40
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_40
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_40
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.188 SW_PAD_CTL_PAD_GPIO_EMC_B1_41 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B1_41)
SW_PAD_CTL Register
12.4.5.188.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2F8h
PIO_EMC_B1_41
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.188.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.188.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B1_41
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B1_41
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B1_41
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.189 SW_PAD_CTL_PAD_GPIO_EMC_B2_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_00)
SW_PAD_CTL Register
12.4.5.189.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 2FCh
PIO_EMC_B2_00
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.189.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.189.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_00
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_00
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_00
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.190 SW_PAD_CTL_PAD_GPIO_EMC_B2_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_01)
SW_PAD_CTL Register
12.4.5.190.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 300h
PIO_EMC_B2_01
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.190.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.190.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_01
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_01
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_01
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.191 SW_PAD_CTL_PAD_GPIO_EMC_B2_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_02)
SW_PAD_CTL Register
12.4.5.191.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 304h
PIO_EMC_B2_02
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.191.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.191.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_02
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_02
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_02
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.192 SW_PAD_CTL_PAD_GPIO_EMC_B2_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_03)
SW_PAD_CTL Register
12.4.5.192.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 308h
PIO_EMC_B2_03
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.192.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.192.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_03
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_03
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_03
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.193 SW_PAD_CTL_PAD_GPIO_EMC_B2_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_04)
SW_PAD_CTL Register
12.4.5.193.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 30Ch
PIO_EMC_B2_04
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.193.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.193.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_04
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_04
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_04
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.194 SW_PAD_CTL_PAD_GPIO_EMC_B2_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_05)
SW_PAD_CTL Register
12.4.5.194.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 310h
PIO_EMC_B2_05
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.194.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.194.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_05
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_05
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_05
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.195 SW_PAD_CTL_PAD_GPIO_EMC_B2_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_06)
SW_PAD_CTL Register
12.4.5.195.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 314h
PIO_EMC_B2_06
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.195.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.195.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_06
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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NXP Semiconductors 1053
Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_06
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_06
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.196 SW_PAD_CTL_PAD_GPIO_EMC_B2_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_07)
SW_PAD_CTL Register
12.4.5.196.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 318h
PIO_EMC_B2_07
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.196.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.196.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_07
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_07
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_07
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.197 SW_PAD_CTL_PAD_GPIO_EMC_B2_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_08)
SW_PAD_CTL Register
12.4.5.197.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 31Ch
PIO_EMC_B2_08
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.197.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.197.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_08
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_08
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_08
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.198 SW_PAD_CTL_PAD_GPIO_EMC_B2_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_09)
SW_PAD_CTL Register
12.4.5.198.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 320h
PIO_EMC_B2_09
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.198.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.198.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_09
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_09
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_09
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.199 SW_PAD_CTL_PAD_GPIO_EMC_B2_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_10)
SW_PAD_CTL Register
12.4.5.199.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 324h
PIO_EMC_B2_10
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.199.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.199.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_10
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_10
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_10
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.200 SW_PAD_CTL_PAD_GPIO_EMC_B2_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_11)
SW_PAD_CTL Register
12.4.5.200.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 328h
PIO_EMC_B2_11
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.200.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.200.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_11
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_11
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_11
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.201 SW_PAD_CTL_PAD_GPIO_EMC_B2_12 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_12)
SW_PAD_CTL Register
12.4.5.201.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 32Ch
PIO_EMC_B2_12
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.201.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.201.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_12
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_12
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_12
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.202 SW_PAD_CTL_PAD_GPIO_EMC_B2_13 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_13)
SW_PAD_CTL Register
12.4.5.202.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 330h
PIO_EMC_B2_13
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.202.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.202.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_13
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_13
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_13
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.203 SW_PAD_CTL_PAD_GPIO_EMC_B2_14 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_14)
SW_PAD_CTL Register
12.4.5.203.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 334h
PIO_EMC_B2_14
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.203.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.203.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_14
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_14
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_14
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.204 SW_PAD_CTL_PAD_GPIO_EMC_B2_15 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_15)
SW_PAD_CTL Register
12.4.5.204.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 338h
PIO_EMC_B2_15
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.204.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.204.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_15
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_15
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_15
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.205 SW_PAD_CTL_PAD_GPIO_EMC_B2_16 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_16)
SW_PAD_CTL Register
12.4.5.205.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 33Ch
PIO_EMC_B2_16
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.205.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.205.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_16
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_16
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_16
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.206 SW_PAD_CTL_PAD_GPIO_EMC_B2_17 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_17)
SW_PAD_CTL Register
12.4.5.206.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 340h
PIO_EMC_B2_17
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12.4.5.206.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.206.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_17
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_17
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_17
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.207 SW_PAD_CTL_PAD_GPIO_EMC_B2_18 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_18)
SW_PAD_CTL Register
12.4.5.207.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 344h
PIO_EMC_B2_18
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12.4.5.207.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.207.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_18
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_18
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_18
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.208 SW_PAD_CTL_PAD_GPIO_EMC_B2_19 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_19)
SW_PAD_CTL Register
12.4.5.208.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 348h
PIO_EMC_B2_19
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12.4.5.208.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.208.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_19
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_19
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_19
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.209 SW_PAD_CTL_PAD_GPIO_EMC_B2_20 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_EMC_B2_20)
SW_PAD_CTL Register
12.4.5.209.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 34Ch
PIO_EMC_B2_20
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12.4.5.209.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.209.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_EMC_B2_20
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Memory Map and register definition
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_EMC_B2_20
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_EMC_B2_20
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.210 SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_00)
SW_PAD_CTL Register
12.4.5.210.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 350h
PIO_AD_00
12.4.5.210.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.210.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_00
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_00
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_00
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_00
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_00
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Memory Map and register definition
Field Description
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.211 SW_PAD_CTL_PAD_GPIO_AD_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_01)
SW_PAD_CTL Register
12.4.5.211.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 354h
PIO_AD_01
12.4.5.211.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.211.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_01
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_01
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_01
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_01
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_01
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.212 SW_PAD_CTL_PAD_GPIO_AD_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_02)
SW_PAD_CTL Register
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12.4.5.212.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 358h
PIO_AD_02
12.4.5.212.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.212.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_02
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_02
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_02
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_02
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_02
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.213 SW_PAD_CTL_PAD_GPIO_AD_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_03)
SW_PAD_CTL Register
12.4.5.213.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 35Ch
PIO_AD_03
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12.4.5.213.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.213.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_03
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_03
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_03
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_03
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_03
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.214 SW_PAD_CTL_PAD_GPIO_AD_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_04)
SW_PAD_CTL Register
12.4.5.214.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 360h
PIO_AD_04
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12.4.5.214.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.214.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_04
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_04
Table continues on the next page...
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Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_04
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_04
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_04
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.215 SW_PAD_CTL_PAD_GPIO_AD_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_05)
SW_PAD_CTL Register
12.4.5.215.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 364h
PIO_AD_05
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12.4.5.215.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.215.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_05
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_05
Table continues on the next page...
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Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_05
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_05
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_05
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.216 SW_PAD_CTL_PAD_GPIO_AD_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_06)
SW_PAD_CTL Register
12.4.5.216.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 368h
PIO_AD_06
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12.4.5.216.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.216.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_06
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_06
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_06
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_06
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_06
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.217 SW_PAD_CTL_PAD_GPIO_AD_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_07)
SW_PAD_CTL Register
12.4.5.217.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 36Ch
PIO_AD_07
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Memory Map and register definition
12.4.5.217.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.217.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_07
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_07
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_07
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_07
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_07
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.218 SW_PAD_CTL_PAD_GPIO_AD_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_08)
SW_PAD_CTL Register
12.4.5.218.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 370h
PIO_AD_08
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Memory Map and register definition
12.4.5.218.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.218.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_08
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_08
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_08
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_08
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_08
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.219 SW_PAD_CTL_PAD_GPIO_AD_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_09)
SW_PAD_CTL Register
12.4.5.219.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 374h
PIO_AD_09
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Memory Map and register definition
12.4.5.219.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.219.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_09
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_09
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_09
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_09
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_09
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.220 SW_PAD_CTL_PAD_GPIO_AD_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_10)
SW_PAD_CTL Register
12.4.5.220.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 378h
PIO_AD_10
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Memory Map and register definition
12.4.5.220.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.220.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_10
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_10
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_10
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_10
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_10
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.221 SW_PAD_CTL_PAD_GPIO_AD_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_11)
SW_PAD_CTL Register
12.4.5.221.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 37Ch
PIO_AD_11
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Memory Map and register definition
12.4.5.221.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.221.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_11
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_11
Table continues on the next page...
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1104 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_11
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_11
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_11
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.222 SW_PAD_CTL_PAD_GPIO_AD_12 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_12)
SW_PAD_CTL Register
12.4.5.222.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 380h
PIO_AD_12
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Memory Map and register definition
12.4.5.222.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.222.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_12
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_12
Table continues on the next page...
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1106 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_12
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_12
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_12
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.223 SW_PAD_CTL_PAD_GPIO_AD_13 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_13)
SW_PAD_CTL Register
12.4.5.223.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 384h
PIO_AD_13
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Memory Map and register definition
12.4.5.223.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.223.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_13
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_13
Table continues on the next page...
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1108 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_13
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_13
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_13
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.224 SW_PAD_CTL_PAD_GPIO_AD_14 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_14)
SW_PAD_CTL Register
12.4.5.224.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 388h
PIO_AD_14
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Memory Map and register definition
12.4.5.224.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.224.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_14
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_14
Table continues on the next page...
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1110 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_14
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_14
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_14
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.225 SW_PAD_CTL_PAD_GPIO_AD_15 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_15)
SW_PAD_CTL Register
12.4.5.225.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 38Ch
PIO_AD_15
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Memory Map and register definition
12.4.5.225.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.225.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_15
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_15
Table continues on the next page...
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1112 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_15
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_15
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_15
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.226 SW_PAD_CTL_PAD_GPIO_AD_16 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_16)
SW_PAD_CTL Register
12.4.5.226.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 390h
PIO_AD_16
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Memory Map and register definition
12.4.5.226.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.226.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_16
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_16
Table continues on the next page...
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1114 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_16
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_16
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_16
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.227 SW_PAD_CTL_PAD_GPIO_AD_17 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_17)
SW_PAD_CTL Register
12.4.5.227.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 394h
PIO_AD_17
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Memory Map and register definition
12.4.5.227.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.227.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_17
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_17
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_17
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_17
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_17
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.228 SW_PAD_CTL_PAD_GPIO_AD_18 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_18)
SW_PAD_CTL Register
12.4.5.228.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 398h
PIO_AD_18
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Memory Map and register definition
12.4.5.228.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.228.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_18
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_18
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_18
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_18
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_18
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.229 SW_PAD_CTL_PAD_GPIO_AD_19 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_19)
SW_PAD_CTL Register
12.4.5.229.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 39Ch
PIO_AD_19
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Memory Map and register definition
12.4.5.229.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.229.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_19
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_19
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_19
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_19
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_19
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.230 SW_PAD_CTL_PAD_GPIO_AD_20 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_20)
SW_PAD_CTL Register
12.4.5.230.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3A0h
PIO_AD_20
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Memory Map and register definition
12.4.5.230.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.230.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_20
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_20
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_20
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_20
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_20
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.231 SW_PAD_CTL_PAD_GPIO_AD_21 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_21)
SW_PAD_CTL Register
12.4.5.231.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3A4h
PIO_AD_21
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Memory Map and register definition
12.4.5.231.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.231.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_21
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_21
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_21
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_21
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_21
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.232 SW_PAD_CTL_PAD_GPIO_AD_22 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_22)
SW_PAD_CTL Register
12.4.5.232.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3A8h
PIO_AD_22
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Memory Map and register definition
12.4.5.232.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.232.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_22
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_22
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_22
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_22
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_22
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.233 SW_PAD_CTL_PAD_GPIO_AD_23 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_23)
SW_PAD_CTL Register
12.4.5.233.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3ACh
PIO_AD_23
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Memory Map and register definition
12.4.5.233.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.233.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_23
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_23
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_23
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_23
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_23
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.234 SW_PAD_CTL_PAD_GPIO_AD_24 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_24)
SW_PAD_CTL Register
12.4.5.234.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3B0h
PIO_AD_24
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Memory Map and register definition
12.4.5.234.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.234.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_24
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_24
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_24
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_24
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_24
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.235 SW_PAD_CTL_PAD_GPIO_AD_25 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_25)
SW_PAD_CTL Register
12.4.5.235.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3B4h
PIO_AD_25
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Memory Map and register definition
12.4.5.235.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.235.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_25
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_25
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_25
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_25
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_25
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.236 SW_PAD_CTL_PAD_GPIO_AD_26 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_26)
SW_PAD_CTL Register
12.4.5.236.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3B8h
PIO_AD_26
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Memory Map and register definition
12.4.5.236.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.236.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_26
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_26
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_26
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_26
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_26
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.237 SW_PAD_CTL_PAD_GPIO_AD_27 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_27)
SW_PAD_CTL Register
12.4.5.237.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3BCh
PIO_AD_27
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Memory Map and register definition
12.4.5.237.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.237.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_27
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_27
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_27
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_27
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_27
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.238 SW_PAD_CTL_PAD_GPIO_AD_28 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_28)
SW_PAD_CTL Register
12.4.5.238.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3C0h
PIO_AD_28
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Memory Map and register definition
12.4.5.238.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.238.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_28
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_28
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_28
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_28
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_28
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.239 SW_PAD_CTL_PAD_GPIO_AD_29 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_29)
SW_PAD_CTL Register
12.4.5.239.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3C4h
PIO_AD_29
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Memory Map and register definition
12.4.5.239.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.239.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_29
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_29
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_29
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_29
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_29
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.240 SW_PAD_CTL_PAD_GPIO_AD_30 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_30)
SW_PAD_CTL Register
12.4.5.240.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3C8h
PIO_AD_30
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Memory Map and register definition
12.4.5.240.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.240.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_30
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_30
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_30
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_30
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_30
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.241 SW_PAD_CTL_PAD_GPIO_AD_31 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_31)
SW_PAD_CTL Register
12.4.5.241.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3CCh
PIO_AD_31
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Memory Map and register definition
12.4.5.241.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.241.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_31
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_31
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_31
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_31
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_31
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.242 SW_PAD_CTL_PAD_GPIO_AD_32 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_32)
SW_PAD_CTL Register
12.4.5.242.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3D0h
PIO_AD_32
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Memory Map and register definition
12.4.5.242.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.242.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_32
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_32
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_32
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_32
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_32
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.243 SW_PAD_CTL_PAD_GPIO_AD_33 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_33)
SW_PAD_CTL Register
12.4.5.243.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3D4h
PIO_AD_33
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Memory Map and register definition
12.4.5.243.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.243.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_33
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_33
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_33
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_33
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_33
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.244 SW_PAD_CTL_PAD_GPIO_AD_34 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_34)
SW_PAD_CTL Register
12.4.5.244.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3D8h
PIO_AD_34
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Memory Map and register definition
12.4.5.244.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.244.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_34
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_34
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_34
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_34
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_34
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.245 SW_PAD_CTL_PAD_GPIO_AD_35 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_AD_35)
SW_PAD_CTL Register
12.4.5.245.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3DCh
PIO_AD_35
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Memory Map and register definition
12.4.5.245.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.245.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_AD_35
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_AD_35
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_AD_35
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_AD_35
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_AD_35
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.246 SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_00)
SW_PAD_CTL Register
12.4.5.246.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3E0h
PIO_SD_B1_00
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Memory Map and register definition
12.4.5.246.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.246.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_00
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_00
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_00
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.247 SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_01)
SW_PAD_CTL Register
12.4.5.247.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3E4h
PIO_SD_B1_01
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Memory Map and register definition
12.4.5.247.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.247.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_01
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_01
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_01
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.248 SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_02)
SW_PAD_CTL Register
12.4.5.248.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3E8h
PIO_SD_B1_02
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Memory Map and register definition
12.4.5.248.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.248.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_02
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_02
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_02
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.249 SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_03)
SW_PAD_CTL Register
12.4.5.249.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3ECh
PIO_SD_B1_03
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Memory Map and register definition
12.4.5.249.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.249.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_03
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_03
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_03
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.250 SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_04)
SW_PAD_CTL Register
12.4.5.250.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3F0h
PIO_SD_B1_04
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Memory Map and register definition
12.4.5.250.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.250.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_04
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_04
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_04
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.251 SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B1_05)
SW_PAD_CTL Register
12.4.5.251.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3F4h
PIO_SD_B1_05
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Memory Map and register definition
12.4.5.251.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.251.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B1_05
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B1_05
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B1_05
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.252 SW_PAD_CTL_PAD_GPIO_SD_B2_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_00)
SW_PAD_CTL Register
12.4.5.252.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3F8h
PIO_SD_B2_00
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Memory Map and register definition
12.4.5.252.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.252.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_00
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_00
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_00
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.253 SW_PAD_CTL_PAD_GPIO_SD_B2_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_01)
SW_PAD_CTL Register
12.4.5.253.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 3FCh
PIO_SD_B2_01
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Memory Map and register definition
12.4.5.253.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.253.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_01
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_01
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_01
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.254 SW_PAD_CTL_PAD_GPIO_SD_B2_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_02)
SW_PAD_CTL Register
12.4.5.254.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 400h
PIO_SD_B2_02
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Memory Map and register definition
12.4.5.254.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.254.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_02
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_02
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_02
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.255 SW_PAD_CTL_PAD_GPIO_SD_B2_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_03)
SW_PAD_CTL Register
12.4.5.255.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 404h
PIO_SD_B2_03
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Memory Map and register definition
12.4.5.255.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.255.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_03
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_03
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_03
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.256 SW_PAD_CTL_PAD_GPIO_SD_B2_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_04)
SW_PAD_CTL Register
12.4.5.256.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 408h
PIO_SD_B2_04
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Memory Map and register definition
12.4.5.256.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.256.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_04
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_04
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_04
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.257 SW_PAD_CTL_PAD_GPIO_SD_B2_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_05)
SW_PAD_CTL Register
12.4.5.257.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 40Ch
PIO_SD_B2_05
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Memory Map and register definition
12.4.5.257.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.257.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_05
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_05
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_05
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.258 SW_PAD_CTL_PAD_GPIO_SD_B2_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_06)
SW_PAD_CTL Register
12.4.5.258.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 410h
PIO_SD_B2_06
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Memory Map and register definition
12.4.5.258.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
12.4.5.258.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_06
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_06
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_06
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.259 SW_PAD_CTL_PAD_GPIO_SD_B2_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_07)
SW_PAD_CTL Register
12.4.5.259.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 414h
PIO_SD_B2_07
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Memory Map and register definition
12.4.5.259.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.259.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_07
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_07
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_07
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.260 SW_PAD_CTL_PAD_GPIO_SD_B2_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_08)
SW_PAD_CTL Register
12.4.5.260.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 418h
PIO_SD_B2_08
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Memory Map and register definition
12.4.5.260.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.260.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_08
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_08
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_08
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.261 SW_PAD_CTL_PAD_GPIO_SD_B2_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_09)
SW_PAD_CTL Register
12.4.5.261.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 41Ch
PIO_SD_B2_09
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Memory Map and register definition
12.4.5.261.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.261.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_09
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_09
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_09
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.262 SW_PAD_CTL_PAD_GPIO_SD_B2_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_10)
SW_PAD_CTL Register
12.4.5.262.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 420h
PIO_SD_B2_10
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Memory Map and register definition
12.4.5.262.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.262.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_10
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_10
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_10
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.263 SW_PAD_CTL_PAD_GPIO_SD_B2_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_SD_B2_11)
SW_PAD_CTL Register
12.4.5.263.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 424h
PIO_SD_B2_11
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Memory Map and register definition
12.4.5.263.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.263.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_SD_B2_11
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_SD_B2_11
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_SD_B2_11
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.264 SW_PAD_CTL_PAD_GPIO_DISP_B1_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_00)
SW_PAD_CTL Register
12.4.5.264.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 428h
PIO_DISP_B1_00
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Memory Map and register definition
12.4.5.264.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.264.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_00
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_00
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_00
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.265 SW_PAD_CTL_PAD_GPIO_DISP_B1_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_01)
SW_PAD_CTL Register
12.4.5.265.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 42Ch
PIO_DISP_B1_01
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12.4.5.265.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.265.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_01
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_01
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_01
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.266 SW_PAD_CTL_PAD_GPIO_DISP_B1_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_02)
SW_PAD_CTL Register
12.4.5.266.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 430h
PIO_DISP_B1_02
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Memory Map and register definition
12.4.5.266.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.266.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_02
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_02
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_02
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.267 SW_PAD_CTL_PAD_GPIO_DISP_B1_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_03)
SW_PAD_CTL Register
12.4.5.267.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 434h
PIO_DISP_B1_03
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12.4.5.267.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.267.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_03
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_03
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_03
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.268 SW_PAD_CTL_PAD_GPIO_DISP_B1_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_04)
SW_PAD_CTL Register
12.4.5.268.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 438h
PIO_DISP_B1_04
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Memory Map and register definition
12.4.5.268.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.268.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_04
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_04
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_04
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.269 SW_PAD_CTL_PAD_GPIO_DISP_B1_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_05)
SW_PAD_CTL Register
12.4.5.269.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 43Ch
PIO_DISP_B1_05
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NXP Semiconductors 1199
Memory Map and register definition
12.4.5.269.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
12.4.5.269.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_05
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_05
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_05
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.270 SW_PAD_CTL_PAD_GPIO_DISP_B1_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_06)
SW_PAD_CTL Register
12.4.5.270.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 440h
PIO_DISP_B1_06
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Memory Map and register definition
12.4.5.270.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.270.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_06
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_06
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_06
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.271 SW_PAD_CTL_PAD_GPIO_DISP_B1_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_07)
SW_PAD_CTL Register
12.4.5.271.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 444h
PIO_DISP_B1_07
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Memory Map and register definition
12.4.5.271.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.271.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_07
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_07
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_07
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.272 SW_PAD_CTL_PAD_GPIO_DISP_B1_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_08)
SW_PAD_CTL Register
12.4.5.272.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 448h
PIO_DISP_B1_08
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Memory Map and register definition
12.4.5.272.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.272.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_08
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_08
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_08
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.273 SW_PAD_CTL_PAD_GPIO_DISP_B1_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_09)
SW_PAD_CTL Register
12.4.5.273.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 44Ch
PIO_DISP_B1_09
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Memory Map and register definition
12.4.5.273.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.273.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_09
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_09
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_09
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.274 SW_PAD_CTL_PAD_GPIO_DISP_B1_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_10)
SW_PAD_CTL Register
12.4.5.274.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 450h
PIO_DISP_B1_10
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Memory Map and register definition
12.4.5.274.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.274.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_10
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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1210 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_10
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_10
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.275 SW_PAD_CTL_PAD_GPIO_DISP_B1_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B1_11)
SW_PAD_CTL Register
12.4.5.275.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 454h
PIO_DISP_B1_11
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Memory Map and register definition
12.4.5.275.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
PDRV
PULL
ODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
12.4.5.275.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B1_11
0 - Disabled
1 - Enabled
3-2 Pull Down Pull Up Field
Table continues on the next page...
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1212 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
Field Description
PULL Control signal to enable internal pull-up/down resistors
Select one out of next values for pad: GPIO_DISP_B1_11
00 - Forbidden
01 - Internal pullup resistor enabled
10 - Internal pulldown resistor enabled
11 - No Pull
1 PDRV Field
PDRV Control signal to configure the pad drive strength.
Select one out of next values for pad: GPIO_DISP_B1_11
0 - high drive strength
1 - normal drive strength
0 -
— Reserved
12.4.5.276 SW_PAD_CTL_PAD_GPIO_DISP_B2_00 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_00)
SW_PAD_CTL Register
12.4.5.276.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 458h
PIO_DISP_B2_00
12.4.5.276.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
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Memory Map and register definition
12.4.5.276.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_00
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_00
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_00
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_00
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_00
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.277 SW_PAD_CTL_PAD_GPIO_DISP_B2_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_01)
SW_PAD_CTL Register
12.4.5.277.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 45Ch
PIO_DISP_B2_01
12.4.5.277.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.5.277.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
Table continues on the next page...
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Memory Map and register definition
Field Description
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_01
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_01
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_01
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_01
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_01
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.278 SW_PAD_CTL_PAD_GPIO_DISP_B2_02 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_02)
SW_PAD_CTL Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.278.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 460h
PIO_DISP_B2_02
12.4.5.278.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.5.278.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE
Table continues on the next page...
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Memory Map and register definition
Field Description
If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_02
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_02
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_02
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_02
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_02
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.279 SW_PAD_CTL_PAD_GPIO_DISP_B2_03 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_03)
SW_PAD_CTL Register
12.4.5.279.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 464h
PIO_DISP_B2_03
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.279.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.5.279.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_03
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_03
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1219
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_03
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_03
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_03
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.280 SW_PAD_CTL_PAD_GPIO_DISP_B2_04 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_04)
SW_PAD_CTL Register
12.4.5.280.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 468h
PIO_DISP_B2_04
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1220 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.280.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.5.280.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_04
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_04
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1221
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_04
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_04
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_04
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.281 SW_PAD_CTL_PAD_GPIO_DISP_B2_05 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_05)
SW_PAD_CTL Register
12.4.5.281.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 46Ch
PIO_DISP_B2_05
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1222 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.281.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
12.4.5.281.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_05
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_05
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1223
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_05
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_05
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_05
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.282 SW_PAD_CTL_PAD_GPIO_DISP_B2_06 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_06)
SW_PAD_CTL Register
12.4.5.282.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 470h
PIO_DISP_B2_06
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1224 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.282.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.282.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_06
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_06
Table continues on the next page...
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NXP Semiconductors 1225
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_06
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_06
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_06
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.283 SW_PAD_CTL_PAD_GPIO_DISP_B2_07 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_07)
SW_PAD_CTL Register
12.4.5.283.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 474h
PIO_DISP_B2_07
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1226 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.283.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.283.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_07
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_07
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1227
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_07
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_07
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_07
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.284 SW_PAD_CTL_PAD_GPIO_DISP_B2_08 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_08)
SW_PAD_CTL Register
12.4.5.284.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 478h
PIO_DISP_B2_08
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1228 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.284.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.284.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_08
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_08
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1229
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_08
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_08
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_08
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.285 SW_PAD_CTL_PAD_GPIO_DISP_B2_09 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_09)
SW_PAD_CTL Register
12.4.5.285.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 47Ch
PIO_DISP_B2_09
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1230 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.285.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.285.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_09
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_09
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1231
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_09
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_09
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_09
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.286 SW_PAD_CTL_PAD_GPIO_DISP_B2_10 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_10)
SW_PAD_CTL Register
12.4.5.286.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 480h
PIO_DISP_B2_10
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1232 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.286.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.286.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_10
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_10
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1233
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_10
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_10
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_10
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.287 SW_PAD_CTL_PAD_GPIO_DISP_B2_11 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_11)
SW_PAD_CTL Register
12.4.5.287.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 484h
PIO_DISP_B2_11
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1234 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.287.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.287.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_11
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_11
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1235
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_11
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_11
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_11
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.288 SW_PAD_CTL_PAD_GPIO_DISP_B2_12 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_12)
SW_PAD_CTL Register
12.4.5.288.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 488h
PIO_DISP_B2_12
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1236 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.288.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.288.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_12
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_12
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1237
Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_12
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_12
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_12
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.289 SW_PAD_CTL_PAD_GPIO_DISP_B2_13 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_13)
SW_PAD_CTL Register
12.4.5.289.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 48Ch
PIO_DISP_B2_13
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1238 NXP Semiconductors
Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.289.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.289.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_13
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_13
Table continues on the next page...
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Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_13
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_13
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_13
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.290 SW_PAD_CTL_PAD_GPIO_DISP_B2_14 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_14)
SW_PAD_CTL Register
12.4.5.290.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 490h
PIO_DISP_B2_14
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.290.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
12.4.5.290.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_14
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_14
Table continues on the next page...
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Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_14
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_14
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_14
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.291 SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_15)
SW_PAD_CTL Register
12.4.5.291.1 Offset
Register Offset
SW_PAD_CTL_PAD_G 494h
PIO_DISP_B2_15
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.291.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DWP_LOCK
Reserved
DWP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ODE PUS PUE DSE SRE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
12.4.5.291.3 Fields
Field Description
31-30 Domain write protection lock
DWP_LOCK Once DWP_LOCK bit i is set the write to DWP bit i will be blocked.
00 - Neither of DWP bits is locked
01 - The lower DWP bit is locked
10 - The higher DWP bit is locked
11 - Both DWP bits are locked
29-28 Domain write protection
DWP These 2 bits determine which core is forbidden to change bits 6:0. When bit 0 is set, CM7 is forbidden.
When bit 1 is set, CM4 is forbidden.
00 - Both cores are allowed
01 - CM7 is forbidden
10 - CM4 is forbidden
11 - Both cores are forbidden
27-5 -
— Reserved
4 Open Drain Field
ODE If set to 1, the output driver drives only logic 0. The drain of the internal transistor is open. It means that
logic 1 has to be driven by an external component. This option is essential if connection between the pad
and an external component is bi-directional. If ODE = 0, then the output driver drives logic 1 and logic 0.
Select one out of next values for pad: GPIO_DISP_B2_15
0 - Disabled
1 - Enabled
3 Pull Up / Down Config. Field
PUS Select one out of next values for pad: GPIO_DISP_B2_15
Table continues on the next page...
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Memory Map and register definition
Field Description
0 - Weak pull down
1 - Weak pull up
2 Pull / Keep Select Field
PUE Select one out of next values for pad: GPIO_DISP_B2_15
0 - Pull Disable, Highz
1 - Pull Enable
1 Drive Strength Field
DSE Select one out of next values for pad: GPIO_DISP_B2_15
0 - normal drive strength
1 - high drive strength
0 Slew Rate Field
SRE Select one out of next values for pad: GPIO_DISP_B2_15
0 - Fast Slew Rate
1 - Slow Slew Rate
12.4.5.292 FLEXCAN1_RX_SELECT_INPUT DAISY Register (FLEX
CAN1_RX_SELECT_INPUT)
DAISY Register
12.4.5.292.1 Offset
Register Offset
FLEXCAN1_RX_SELE 498h
CT_INPUT
12.4.5.292.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.292.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: FLEXCAN1, In Pin: canrx
00 - Selecting Pad: GPIO_AD_07 for Mode: ALT1
01 - Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT6
12.4.5.293 FLEXCAN2_RX_SELECT_INPUT DAISY Register (FLEX
CAN2_RX_SELECT_INPUT)
DAISY Register
12.4.5.293.1 Offset
Register Offset
FLEXCAN2_RX_SELE 49Ch
CT_INPUT
12.4.5.293.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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12.4.5.293.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: FLEXCAN2, In Pin: canrx
0 - Selecting Pad: GPIO_AD_01 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_31 for Mode: ALT2
12.4.5.294 CCM_ENET_QOS_REF_CLK_SELECT_INPUT DAISY
Register (CCM_ENET_QOS_REF_CLK_SELECT_INPUT)
DAISY Register
12.4.5.294.1 Offset
Register Offset
CCM_ENET_QOS_REF_ 4A0h
CLK_SELECT_INPUT
12.4.5.294.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.294.3 Fields
Field Description
31-2 -
Table continues on the next page...
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Chapter 12 IOMUX Controller (IOMUXC)
Field Description
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: ref_clk
00 - Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT3
01 - Selecting Pad: GPIO_SD_B2_07 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT9
12.4.5.295 CCM_ENET_QOS_TX_CLK_SELECT_INPUT DAISY
Register (CCM_ENET_QOS_TX_CLK_SELECT_INPUT)
DAISY Register
12.4.5.295.1 Offset
Register Offset
CCM_ENET_QOS_TX_ 4A4h
CLK_SELECT_INPUT
12.4.5.295.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.295.3 Fields
Field Description
31-1 -
— Reserved
Table continues on the next page...
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Memory Map and register definition
Field Description
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: tx_clk
0 - Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT8
12.4.5.296 ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register
(ENET_IPG_CLK_RMII_SELECT_INPUT)
DAISY Register
12.4.5.296.1 Offset
Register Offset
ENET_IPG_CLK_RMII_ 4A8h
SELECT_INPUT
12.4.5.296.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.296.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: ipg_clk_rmii
00 - Selecting Pad: GPIO_AD_29 for Mode: ALT2
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Field Description
01 - Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT4
12.4.5.297 ENET_MAC0_MDIO_SELECT_INPUT DAISY Register
(ENET_MAC0_MDIO_SELECT_INPUT)
DAISY Register
12.4.5.297.1 Offset
Register Offset
ENET_MAC0_MDIO_S 4ACh
ELECT_INPUT
12.4.5.297.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.297.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_mdio
0 - Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_33 for Mode: ALT3
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Memory Map and register definition
12.4.5.298 ENET_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register
(ENET_MAC0_RXDATA_SELECT_INPUT_0)
DAISY Register
12.4.5.298.1 Offset
Register Offset
ENET_MAC0_RXDATA_ 4B0h
SELECT_INPUT_0
12.4.5.298.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.298.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_rxdata0
0 - Selecting Pad: GPIO_AD_26 for Mode: ALT3
1 - Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT1
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12.4.5.299 ENET_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register
(ENET_MAC0_RXDATA_SELECT_INPUT_1)
DAISY Register
12.4.5.299.1 Offset
Register Offset
ENET_MAC0_RXDATA_ 4B4h
SELECT_INPUT_1
12.4.5.299.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.299.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_rxdata1
0 - Selecting Pad: GPIO_AD_27 for Mode: ALT3
1 - Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT1
12.4.5.300 ENET_MAC0_RXEN_SELECT_INPUT DAISY Register
(ENET_MAC0_RXEN_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.300.1 Offset
Register Offset
ENET_MAC0_RXEN_S 4B8h
ELECT_INPUT
12.4.5.300.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.300.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_rxen
0 - Selecting Pad: GPIO_AD_24 for Mode: ALT3
1 - Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT1
12.4.5.301 ENET_MAC0_RXERR_SELECT_INPUT DAISY Register
(ENET_MAC0_RXERR_SELECT_INPUT)
DAISY Register
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12.4.5.301.1 Offset
Register Offset
ENET_MAC0_RXERR_ 4BCh
SELECT_INPUT
12.4.5.301.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.301.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_rxerr
0 - Selecting Pad: GPIO_AD_25 for Mode: ALT3
1 - Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT1
12.4.5.302 ENET_MAC0_TXCLK_SELECT_INPUT DAISY Register
(ENET_MAC0_TXCLK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.302.1 Offset
Register Offset
ENET_MAC0_TXCLK_ 4C0h
SELECT_INPUT
12.4.5.302.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.302.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: enet, In Pin: mac0_txclk
0 - Selecting Pad: GPIO_AD_29 for Mode: ALT3
1 - Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT1
12.4.5.303 ENET_1G_IPG_CLK_RMII_SELECT_INPUT DAISY Register
(ENET_1G_IPG_CLK_RMII_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.303.1 Offset
Register Offset
ENET_1G_IPG_CLK_ 4C4h
RMII_SELECT_INPUT
12.4.5.303.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.303.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: ipg_clk_rmii
00 - Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3
01 - Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3
10 - Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2
11 - Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4
12.4.5.304 ENET_1G_MAC0_MDIO_SELECT_INPUT DAISY Register
(ENET_1G_MAC0_MDIO_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.304.1 Offset
Register Offset
ENET_1G_MAC0_MDI 4C8h
O_SELECT_INPUT
12.4.5.304.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.304.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_mdio
00 - Selecting Pad: GPIO_EMC_B1_41 for Mode: ALT7
01 - Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT2
10 - Selecting Pad: GPIO_AD_17 for Mode: ALT9
11 - Selecting Pad: GPIO_AD_33 for Mode: ALT9
12.4.5.305 ENET_1G_MAC0_RXCLK_SELECT_INPUT DAISY Register
(ENET_1G_MAC0_RXCLK_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.305.1 Offset
Register Offset
ENET_1G_MAC0_RXC 4CCh
LK_SELECT_INPUT
12.4.5.305.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.305.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxclk
00 - Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT7
01 - Selecting Pad: GPIO_SD_B2_01 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT1
12.4.5.306 ENET_1G_MAC0_RXDATA_0_SELECT_INPUT DAISY
Register (ENET_1G_MAC0_RXDATA_0_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.306.1 Offset
Register Offset
ENET_1G_MAC0_RXD 4D0h
ATA_0_SELECT_INPUT
12.4.5.306.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.306.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxdata_0
00 - Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT2
01 - Selecting Pad: GPIO_SD_B2_02 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT1
12.4.5.307 ENET_1G_MAC0_RXDATA_1_SELECT_INPUT DAISY
Register (ENET_1G_MAC0_RXDATA_1_SELECT_INPUT)
DAISY Register
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12.4.5.307.1 Offset
Register Offset
ENET_1G_MAC0_RXD 4D4h
ATA_1_SELECT_INPUT
12.4.5.307.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.307.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxdata_1
00 - Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT2
01 - Selecting Pad: GPIO_SD_B2_03 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT1
12.4.5.308 ENET_1G_MAC0_RXDATA_2_SELECT_INPUT DAISY
Register (ENET_1G_MAC0_RXDATA_2_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.308.1 Offset
Register Offset
ENET_1G_MAC0_RXD 4D8h
ATA_2_SELECT_INPUT
12.4.5.308.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.308.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxdata_2
00 - Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT7
01 - Selecting Pad: GPIO_SD_B2_04 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT1
12.4.5.309 ENET_1G_MAC0_RXDATA_3_SELECT_INPUT DAISY
Register (ENET_1G_MAC0_RXDATA_3_SELECT_INPUT)
DAISY Register
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12.4.5.309.1 Offset
Register Offset
ENET_1G_MAC0_RXD 4DCh
ATA_3_SELECT_INPUT
12.4.5.309.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.309.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxdata_3
00 - Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT7
01 - Selecting Pad: GPIO_SD_B2_05 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT1
12.4.5.310 ENET_1G_MAC0_RXEN_SELECT_INPUT DAISY Register
(ENET_1G_MAC0_RXEN_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.310.1 Offset
Register Offset
ENET_1G_MAC0_RXE 4E0h
N_SELECT_INPUT
12.4.5.310.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.310.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxen
00 - Selecting Pad: GPIO_EMC_B2_17 for Mode: ALT2
01 - Selecting Pad: GPIO_SD_B2_00 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT1
12.4.5.311 ENET_1G_MAC0_RXERR_SELECT_INPUT DAISY Register
(ENET_1G_MAC0_RXERR_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.311.1 Offset
Register Offset
ENET_1G_MAC0_RXE 4E4h
RR_SELECT_INPUT
12.4.5.311.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.311.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_rxerr
0 - Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT2
12.4.5.312 ENET_1G_MAC0_TXCLK_SELECT_INPUT DAISY Register
(ENET_1G_MAC0_TXCLK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.312.1 Offset
Register Offset
ENET_1G_MAC0_TXC 4E8h
LK_SELECT_INPUT
12.4.5.312.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.312.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_1G, In Pin: mac0_txclk
00 - Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT2
01 - Selecting Pad: GPIO_SD_B2_11 for Mode: ALT2
10 - Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT1
12.4.5.313 ENET_QOS_GMII_MDI_I_SELECT_INPUT DAISY Register
(ENET_QOS_GMII_MDI_I_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.313.1 Offset
Register Offset
ENET_QOS_GMII_MDI_ 4ECh
I_SELECT_INPUT
12.4.5.313.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.313.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: gmii_mdi_i
0 - Selecting Pad: GPIO_EMC_B2_20 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_27 for Mode: ALT9
12.4.5.314 ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 DAISY
Register (ENET_QOS_PHY_RXD_I_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.314.1 Offset
Register Offset
ENET_QOS_PHY_RXD_ 4F0h
I_SELECT_INPUT_0
12.4.5.314.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.314.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: phy_rxd_i0
0 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT8
12.4.5.315 ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 DAISY
Register (ENET_QOS_PHY_RXD_I_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.315.1 Offset
Register Offset
ENET_QOS_PHY_RXD_ 4F4h
I_SELECT_INPUT_1
12.4.5.315.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.315.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: phy_rxd_i1
0 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT8
12.4.5.316 ENET_QOS_PHY_RXDV_I_SELECT_INPUT DAISY Register
(ENET_QOS_PHY_RXDV_I_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.316.1 Offset
Register Offset
ENET_QOS_PHY_RXD 4F8h
V_I_SELECT_INPUT
12.4.5.316.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.316.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: phy_rxdv_i
0 - Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT8
12.4.5.317 ENET_QOS_PHY_RXER_I_SELECT_INPUT DAISY Register
(ENET_QOS_PHY_RXER_I_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.317.1 Offset
Register Offset
ENET_QOS_PHY_RXE 4FCh
R_I_SELECT_INPUT
12.4.5.317.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.317.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY instance: ENET_QOS, In Pin: phy_rxer_i
00 - Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT9
01 - Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT8
10 - Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT8
12.4.5.318 FLEXPWM1_PWMA_SELECT_INPUT_0 DAISY Register
(FLEXPWM1_PWMA_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.318.1 Offset
Register Offset
FLEXPWM1_PWMA_SE 500h
LECT_INPUT_0
12.4.5.318.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.318.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwma0
0 - Selecting Pad: GPIO_EMC_B1_23 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_00 for Mode: ALT4
12.4.5.319 FLEXPWM1_PWMA_SELECT_INPUT_1 DAISY Register
(FLEXPWM1_PWMA_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.319.1 Offset
Register Offset
FLEXPWM1_PWMA_SE 504h
LECT_INPUT_1
12.4.5.319.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.319.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwma1
0 - Selecting Pad: GPIO_EMC_B1_25 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_02 for Mode: ALT4
12.4.5.320 FLEXPWM1_PWMA_SELECT_INPUT_2 DAISY Register
(FLEXPWM1_PWMA_SELECT_INPUT_2)
DAISY Register
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Memory Map and register definition
12.4.5.320.1 Offset
Register Offset
FLEXPWM1_PWMA_SE 508h
LECT_INPUT_2
12.4.5.320.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.320.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwma2
0 - Selecting Pad: GPIO_EMC_B1_27 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_04 for Mode: ALT4
12.4.5.321 FLEXPWM1_PWMB_SELECT_INPUT_0 DAISY Register
(FLEXPWM1_PWMB_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.321.1 Offset
Register Offset
FLEXPWM1_PWMB_SE 50Ch
LECT_INPUT_0
12.4.5.321.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.321.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwmb0
0 - Selecting Pad: GPIO_EMC_B1_24 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_01 for Mode: ALT4
12.4.5.322 FLEXPWM1_PWMB_SELECT_INPUT_1 DAISY Register
(FLEXPWM1_PWMB_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.322.1 Offset
Register Offset
FLEXPWM1_PWMB_SE 510h
LECT_INPUT_1
12.4.5.322.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.322.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwmb1
0 - Selecting Pad: GPIO_EMC_B1_26 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_03 for Mode: ALT4
12.4.5.323 FLEXPWM1_PWMB_SELECT_INPUT_2 DAISY Register
(FLEXPWM1_PWMB_SELECT_INPUT_2)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.323.1 Offset
Register Offset
FLEXPWM1_PWMB_SE 514h
LECT_INPUT_2
12.4.5.323.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.323.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm1, In Pin: pwmb2
0 - Selecting Pad: GPIO_EMC_B1_28 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_05 for Mode: ALT4
12.4.5.324 FLEXPWM2_PWMA_SELECT_INPUT_0 DAISY Register
(FLEXPWM2_PWMA_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.324.1 Offset
Register Offset
FLEXPWM2_PWMA_SE 518h
LECT_INPUT_0
12.4.5.324.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.324.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwma0
0 - Selecting Pad: GPIO_EMC_B1_06 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_24 for Mode: ALT4
12.4.5.325 FLEXPWM2_PWMA_SELECT_INPUT_1 DAISY Register
(FLEXPWM2_PWMA_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.325.1 Offset
Register Offset
FLEXPWM2_PWMA_SE 51Ch
LECT_INPUT_1
12.4.5.325.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.325.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwma1
0 - Selecting Pad: GPIO_EMC_B1_08 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_26 for Mode: ALT4
12.4.5.326 FLEXPWM2_PWMA_SELECT_INPUT_2 DAISY Register
(FLEXPWM2_PWMA_SELECT_INPUT_2)
DAISY Register
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Memory Map and register definition
12.4.5.326.1 Offset
Register Offset
FLEXPWM2_PWMA_SE 520h
LECT_INPUT_2
12.4.5.326.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.326.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwma2
0 - Selecting Pad: GPIO_EMC_B1_10 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_28 for Mode: ALT4
12.4.5.327 FLEXPWM2_PWMB_SELECT_INPUT_0 DAISY Register
(FLEXPWM2_PWMB_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.327.1 Offset
Register Offset
FLEXPWM2_PWMB_SE 524h
LECT_INPUT_0
12.4.5.327.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.327.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwmb0
0 - Selecting Pad: GPIO_EMC_B1_07 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_25 for Mode: ALT4
12.4.5.328 FLEXPWM2_PWMB_SELECT_INPUT_1 DAISY Register
(FLEXPWM2_PWMB_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.328.1 Offset
Register Offset
FLEXPWM2_PWMB_SE 528h
LECT_INPUT_1
12.4.5.328.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.328.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwmb1
0 - Selecting Pad: GPIO_EMC_B1_09 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_27 for Mode: ALT4
12.4.5.329 FLEXPWM2_PWMB_SELECT_INPUT_2 DAISY Register
(FLEXPWM2_PWMB_SELECT_INPUT_2)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.329.1 Offset
Register Offset
FLEXPWM2_PWMB_SE 52Ch
LECT_INPUT_2
12.4.5.329.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.329.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm2, In Pin: pwmb2
0 - Selecting Pad: GPIO_EMC_B1_11 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_29 for Mode: ALT4
12.4.5.330 FLEXPWM3_PWMA_SELECT_INPUT_0 DAISY Register
(FLEXPWM3_PWMA_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.330.1 Offset
Register Offset
FLEXPWM3_PWMA_SE 530h
LECT_INPUT_0
12.4.5.330.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.330.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwma0
0 - Selecting Pad: GPIO_EMC_B1_29 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT11
12.4.5.331 FLEXPWM3_PWMA_SELECT_INPUT_1 DAISY Register
(FLEXPWM3_PWMA_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.331.1 Offset
Register Offset
FLEXPWM3_PWMA_SE 534h
LECT_INPUT_1
12.4.5.331.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.331.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwma1
0 - Selecting Pad: GPIO_EMC_B1_31 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT11
12.4.5.332 FLEXPWM3_PWMA_SELECT_INPUT_2 DAISY Register
(FLEXPWM3_PWMA_SELECT_INPUT_2)
DAISY Register
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Memory Map and register definition
12.4.5.332.1 Offset
Register Offset
FLEXPWM3_PWMA_SE 538h
LECT_INPUT_2
12.4.5.332.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.332.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwma2
0 - Selecting Pad: GPIO_EMC_B1_33 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT11
12.4.5.333 FLEXPWM3_PWMA_SELECT_INPUT_3 DAISY Register
(FLEXPWM3_PWMA_SELECT_INPUT_3)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.333.1 Offset
Register Offset
FLEXPWM3_PWMA_SE 53Ch
LECT_INPUT_3
12.4.5.333.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.333.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwma3
0 - Selecting Pad: GPIO_EMC_B1_21 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT11
12.4.5.334 FLEXPWM3_PWMB_SELECT_INPUT_0 DAISY Register
(FLEXPWM3_PWMB_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.334.1 Offset
Register Offset
FLEXPWM3_PWMB_SE 540h
LECT_INPUT_0
12.4.5.334.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.334.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwmb0
0 - Selecting Pad: GPIO_EMC_B1_30 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT11
12.4.5.335 FLEXPWM3_PWMB_SELECT_INPUT_1 DAISY Register
(FLEXPWM3_PWMB_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.335.1 Offset
Register Offset
FLEXPWM3_PWMB_SE 544h
LECT_INPUT_1
12.4.5.335.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.335.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwmb1
0 - Selecting Pad: GPIO_EMC_B1_32 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT11
12.4.5.336 FLEXPWM3_PWMB_SELECT_INPUT_2 DAISY Register
(FLEXPWM3_PWMB_SELECT_INPUT_2)
DAISY Register
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Memory Map and register definition
12.4.5.336.1 Offset
Register Offset
FLEXPWM3_PWMB_SE 548h
LECT_INPUT_2
12.4.5.336.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.336.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwmb2
0 - Selecting Pad: GPIO_EMC_B1_34 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT11
12.4.5.337 FLEXPWM3_PWMB_SELECT_INPUT_3 DAISY Register
(FLEXPWM3_PWMB_SELECT_INPUT_3)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.337.1 Offset
Register Offset
FLEXPWM3_PWMB_SE 54Ch
LECT_INPUT_3
12.4.5.337.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.337.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexpwm3, In Pin: pwmb3
0 - Selecting Pad: GPIO_EMC_B1_22 for Mode: ALT1
1 - Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT11
12.4.5.338 FLEXSPI1_I_DQS_FA_SELECT_INPUT DAISY Register
(FLEXSPI1_I_DQS_FA_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.338.1 Offset
Register Offset
FLEXSPI1_I_DQS_FA_ 550h
SELECT_INPUT
12.4.5.338.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.338.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_dqs_fa
00 - Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT6
01 - Selecting Pad: GPIO_AD_17 for Mode: ALT3
10 - Selecting Pad: GPIO_SD_B2_05 for Mode: ALT1
12.4.5.339 FLEXSPI1_I_IO_FA_SELECT_INPUT_0 DAISY Register
(FLEXSPI1_I_IO_FA_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.339.1 Offset
Register Offset
FLEXSPI1_I_IO_FA_SEL 554h
ECT_INPUT_0
12.4.5.339.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.339.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fa0
0 - Selecting Pad: GPIO_AD_20 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_08 for Mode: ALT1
12.4.5.340 FLEXSPI1_I_IO_FA_SELECT_INPUT_1 DAISY Register
(FLEXSPI1_I_IO_FA_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.340.1 Offset
Register Offset
FLEXSPI1_I_IO_FA_SEL 558h
ECT_INPUT_1
12.4.5.340.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.340.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fa1
0 - Selecting Pad: GPIO_AD_21 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_09 for Mode: ALT1
12.4.5.341 FLEXSPI1_I_IO_FA_SELECT_INPUT_2 DAISY Register
(FLEXSPI1_I_IO_FA_SELECT_INPUT_2)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.341.1 Offset
Register Offset
FLEXSPI1_I_IO_FA_SEL 55Ch
ECT_INPUT_2
12.4.5.341.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.341.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fa2
0 - Selecting Pad: GPIO_AD_22 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_10 for Mode: ALT1
12.4.5.342 FLEXSPI1_I_IO_FA_SELECT_INPUT_3 DAISY Register
(FLEXSPI1_I_IO_FA_SELECT_INPUT_3)
DAISY Register
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Memory Map and register definition
12.4.5.342.1 Offset
Register Offset
FLEXSPI1_I_IO_FA_SEL 560h
ECT_INPUT_3
12.4.5.342.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.342.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fa3
0 - Selecting Pad: GPIO_AD_23 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_11 for Mode: ALT1
12.4.5.343 FLEXSPI1_I_IO_FB_SELECT_INPUT_0 DAISY Register
(FLEXSPI1_I_IO_FB_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.343.1 Offset
Register Offset
FLEXSPI1_I_IO_FB_SEL 564h
ECT_INPUT_0
12.4.5.343.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.343.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fb0
0 - Selecting Pad: GPIO_AD_15 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_03 for Mode: ALT1
12.4.5.344 FLEXSPI1_I_IO_FB_SELECT_INPUT_1 DAISY Register
(FLEXSPI1_I_IO_FB_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.344.1 Offset
Register Offset
FLEXSPI1_I_IO_FB_SEL 568h
ECT_INPUT_1
12.4.5.344.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.344.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fb1
0 - Selecting Pad: GPIO_AD_14 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_02 for Mode: ALT1
12.4.5.345 FLEXSPI1_I_IO_FB_SELECT_INPUT_2 DAISY Register
(FLEXSPI1_I_IO_FB_SELECT_INPUT_2)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.345.1 Offset
Register Offset
FLEXSPI1_I_IO_FB_SEL 56Ch
ECT_INPUT_2
12.4.5.345.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.345.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fb2
0 - Selecting Pad: GPIO_AD_13 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_01 for Mode: ALT1
12.4.5.346 FLEXSPI1_I_IO_FB_SELECT_INPUT_3 DAISY Register
(FLEXSPI1_I_IO_FB_SELECT_INPUT_3)
DAISY Register
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Memory Map and register definition
12.4.5.346.1 Offset
Register Offset
FLEXSPI1_I_IO_FB_SEL 570h
ECT_INPUT_3
12.4.5.346.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.346.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_io_fb3
0 - Selecting Pad: GPIO_AD_12 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_00 for Mode: ALT1
12.4.5.347 FLEXSPI1_I_SCK_FA_SELECT_INPUT DAISY Register
(FLEXSPI1_I_SCK_FA_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.347.1 Offset
Register Offset
FLEXSPI1_I_SCK_FA_ 574h
SELECT_INPUT
12.4.5.347.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.347.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_sck_fa
0 - Selecting Pad: GPIO_AD_19 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_07 for Mode: ALT1
12.4.5.348 FLEXSPI1_I_SCK_FB_SELECT_INPUT DAISY Register
(FLEXSPI1_I_SCK_FB_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.348.1 Offset
Register Offset
FLEXSPI1_I_SCK_FB_ 578h
SELECT_INPUT
12.4.5.348.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.348.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi1, In Pin: i_sck_fb
0 - Selecting Pad: GPIO_AD_16 for Mode: ALT3
1 - Selecting Pad: GPIO_SD_B2_04 for Mode: ALT1
12.4.5.349 FLEXSPI2_I_IO_FA_SELECT_INPUT_0 DAISY Register
(FLEXSPI2_I_IO_FA_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.349.1 Offset
Register Offset
FLEXSPI2_I_IO_FA_SEL 57Ch
ECT_INPUT_0
12.4.5.349.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.349.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi2, In Pin: i_io_fa0
0 - Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT4
1 - Selecting Pad: GPIO_SD_B1_02 for Mode: ALT6
12.4.5.350 FLEXSPI2_I_IO_FA_SELECT_INPUT_1 DAISY Register
(FLEXSPI2_I_IO_FA_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.350.1 Offset
Register Offset
FLEXSPI2_I_IO_FA_SEL 580h
ECT_INPUT_1
12.4.5.350.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.350.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi2, In Pin: i_io_fa1
0 - Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT4
1 - Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6
12.4.5.351 FLEXSPI2_I_IO_FA_SELECT_INPUT_2 DAISY Register
(FLEXSPI2_I_IO_FA_SELECT_INPUT_2)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.351.1 Offset
Register Offset
FLEXSPI2_I_IO_FA_SEL 584h
ECT_INPUT_2
12.4.5.351.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.351.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi2, In Pin: i_io_fa2
0 - Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT4
1 - Selecting Pad: GPIO_SD_B1_04 for Mode: ALT6
12.4.5.352 FLEXSPI2_I_IO_FA_SELECT_INPUT_3 DAISY Register
(FLEXSPI2_I_IO_FA_SELECT_INPUT_3)
DAISY Register
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Memory Map and register definition
12.4.5.352.1 Offset
Register Offset
FLEXSPI2_I_IO_FA_SEL 588h
ECT_INPUT_3
12.4.5.352.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.352.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi2, In Pin: i_io_fa3
0 - Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT4
1 - Selecting Pad: GPIO_SD_B1_05 for Mode: ALT6
12.4.5.353 FLEXSPI2_I_SCK_FA_SELECT_INPUT DAISY Register
(FLEXSPI2_I_SCK_FA_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.353.1 Offset
Register Offset
FLEXSPI2_I_SCK_FA_ 58Ch
SELECT_INPUT
12.4.5.353.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.353.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: flexspi2, In Pin: i_sck_fa
0 - Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT4
1 - Selecting Pad: GPIO_SD_B1_01 for Mode: ALT6
12.4.5.354 GPT3_CAPIN1_SELECT_INPUT DAISY Register (GPT3_
CAPIN1_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.354.1 Offset
Register Offset
GPT3_CAPIN1_SELE 590h
CT_INPUT
12.4.5.354.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.354.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: gpt3, In Pin: capin1
0 - Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_06 for Mode: ALT3
12.4.5.355 GPT3_CAPIN2_SELECT_INPUT DAISY Register (GPT3_
CAPIN2_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.355.1 Offset
Register Offset
GPT3_CAPIN2_SELE 594h
CT_INPUT
12.4.5.355.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.355.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: gpt3, In Pin: capin2
0 - Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_07 for Mode: ALT3
12.4.5.356 GPT3_CLKIN_SELECT_INPUT DAISY Register (GPT3_CLK
IN_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.356.1 Offset
Register Offset
GPT3_CLKIN_SELECT_ 598h
INPUT
12.4.5.356.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.356.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: gpt3, In Pin: clkin
0 - Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_11 for Mode: ALT3
12.4.5.357 KPP_COL_SELECT_INPUT_6 DAISY Register (KPP_COL_
SELECT_INPUT_6)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.357.1 Offset
Register Offset
KPP_COL_SELECT_I 59Ch
NPUT_6
12.4.5.357.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.357.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: kpp, In Pin: col6
0 - Selecting Pad: GPIO_AD_23 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_03 for Mode: ALT8
12.4.5.358 KPP_COL_SELECT_INPUT_7 DAISY Register (KPP_COL_
SELECT_INPUT_7)
DAISY Register
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Memory Map and register definition
12.4.5.358.1 Offset
Register Offset
KPP_COL_SELECT_I 5A0h
NPUT_7
12.4.5.358.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.358.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: kpp, In Pin: col7
0 - Selecting Pad: GPIO_AD_21 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_01 for Mode: ALT8
12.4.5.359 KPP_ROW_SELECT_INPUT_6 DAISY Register (KPP_
ROW_SELECT_INPUT_6)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.359.1 Offset
Register Offset
KPP_ROW_SELECT_I 5A4h
NPUT_6
12.4.5.359.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.359.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: kpp, In Pin: row6
0 - Selecting Pad: GPIO_AD_22 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_02 for Mode: ALT8
12.4.5.360 KPP_ROW_SELECT_INPUT_7 DAISY Register (KPP_
ROW_SELECT_INPUT_7)
DAISY Register
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Memory Map and register definition
12.4.5.360.1 Offset
Register Offset
KPP_ROW_SELECT_I 5A8h
NPUT_7
12.4.5.360.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.360.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: kpp, In Pin: row7
0 - Selecting Pad: GPIO_AD_20 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_00 for Mode: ALT8
12.4.5.361 LPI2C1_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2
C1_LPI2C_SCL_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.361.1 Offset
Register Offset
LPI2C1_LPI2C_SCL_ 5ACh
SELECT_INPUT
12.4.5.361.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.361.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c1, In Pin: lpi2c_scl
0 - Selecting Pad: GPIO_AD_08 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_32 for Mode: ALT0
12.4.5.362 LPI2C1_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2
C1_LPI2C_SDA_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.362.1 Offset
Register Offset
LPI2C1_LPI2C_SDA_ 5B0h
SELECT_INPUT
12.4.5.362.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.362.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c1, In Pin: lpi2c_sda
0 - Selecting Pad: GPIO_AD_09 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_33 for Mode: ALT0
12.4.5.363 LPI2C2_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2
C2_LPI2C_SCL_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.363.1 Offset
Register Offset
LPI2C2_LPI2C_SCL_ 5B4h
SELECT_INPUT
12.4.5.363.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.363.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c2, In Pin: lpi2c_scl
0 - Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT9
1 - Selecting Pad: GPIO_AD_18 for Mode: ALT9
12.4.5.364 LPI2C2_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2
C2_LPI2C_SDA_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.364.1 Offset
Register Offset
LPI2C2_LPI2C_SDA_ 5B8h
SELECT_INPUT
12.4.5.364.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.364.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c2, In Pin: lpi2c_sda
0 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT9
1 - Selecting Pad: GPIO_AD_19 for Mode: ALT9
12.4.5.365 LPI2C3_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2
C3_LPI2C_SCL_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.365.1 Offset
Register Offset
LPI2C3_LPI2C_SCL_ 5BCh
SELECT_INPUT
12.4.5.365.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.365.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c3, In Pin: lpi2c_scl
0 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT6
12.4.5.366 LPI2C3_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2
C3_LPI2C_SDA_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.366.1 Offset
Register Offset
LPI2C3_LPI2C_SDA_ 5C0h
SELECT_INPUT
12.4.5.366.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.366.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c3, In Pin: lpi2c_sda
0 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B2_11 for Mode: ALT6
12.4.5.367 LPI2C4_LPI2C_SCL_SELECT_INPUT DAISY Register (LPI2
C4_LPI2C_SCL_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.367.1 Offset
Register Offset
LPI2C4_LPI2C_SCL_ 5C4h
SELECT_INPUT
12.4.5.367.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.367.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c4, In Pin: lpi2c_scl
0 - Selecting Pad: GPIO_AD_24 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B2_12 for Mode: ALT6
12.4.5.368 LPI2C4_LPI2C_SDA_SELECT_INPUT DAISY Register (LPI2
C4_LPI2C_SDA_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.368.1 Offset
Register Offset
LPI2C4_LPI2C_SDA_ 5C8h
SELECT_INPUT
12.4.5.368.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.368.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpi2c4, In Pin: lpi2c_sda
0 - Selecting Pad: GPIO_AD_25 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT6
12.4.5.369 LPSPI1_LPSPI_PCS_SELECT_INPUT_0 DAISY Register
(LPSPI1_LPSPI_PCS_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.369.1 Offset
Register Offset
LPSPI1_LPSPI_PCS_ 5CCh
SELECT_INPUT_0
12.4.5.369.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.369.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi1, In Pin: lpspi_pcs0
0 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_29 for Mode: ALT0
12.4.5.370 LPSPI1_LPSPI_SCK_SELECT_INPUT DAISY Register
(LPSPI1_LPSPI_SCK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.370.1 Offset
Register Offset
LPSPI1_LPSPI_SCK_ 5D0h
SELECT_INPUT
12.4.5.370.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.370.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi1, In Pin: lpspi_sck
0 - Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_28 for Mode: ALT0
12.4.5.371 LPSPI1_LPSPI_SDI_SELECT_INPUT DAISY Register
(LPSPI1_LPSPI_SDI_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.371.1 Offset
Register Offset
LPSPI1_LPSPI_SDI_SEL 5D4h
ECT_INPUT
12.4.5.371.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.371.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi1, In Pin: lpspi_sdi
0 - Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_31 for Mode: ALT0
12.4.5.372 LPSPI1_LPSPI_SDO_SELECT_INPUT DAISY Register
(LPSPI1_LPSPI_SDO_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.372.1 Offset
Register Offset
LPSPI1_LPSPI_SDO_ 5D8h
SELECT_INPUT
12.4.5.372.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.372.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi1, In Pin: lpspi_sdo
0 - Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_30 for Mode: ALT0
12.4.5.373 LPSPI2_LPSPI_PCS_SELECT_INPUT_0 DAISY Register
(LPSPI2_LPSPI_PCS_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.373.1 Offset
Register Offset
LPSPI2_LPSPI_PCS_ 5DCh
SELECT_INPUT_0
12.4.5.373.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.373.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi2, In Pin: lpspi_pcs0
0 - Selecting Pad: GPIO_AD_25 for Mode: ALT1
1 - Selecting Pad: GPIO_SD_B2_08 for Mode: ALT6
12.4.5.374 LPSPI2_LPSPI_PCS_SELECT_INPUT_1 DAISY Register
(LPSPI2_LPSPI_PCS_SELECT_INPUT_1)
DAISY Register
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Memory Map and register definition
12.4.5.374.1 Offset
Register Offset
LPSPI2_LPSPI_PCS_ 5E0h
SELECT_INPUT_1
12.4.5.374.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.374.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi2, In Pin: lpspi_pcs1
0 - Selecting Pad: GPIO_AD_21 for Mode: ALT2
1 - Selecting Pad: GPIO_SD_B2_11 for Mode: ALT6
12.4.5.375 LPSPI2_LPSPI_SCK_SELECT_INPUT DAISY Register
(LPSPI2_LPSPI_SCK_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.375.1 Offset
Register Offset
LPSPI2_LPSPI_SCK_ 5E4h
SELECT_INPUT
12.4.5.375.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.375.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi2, In Pin: lpspi_sck
0 - Selecting Pad: GPIO_AD_24 for Mode: ALT1
1 - Selecting Pad: GPIO_SD_B2_07 for Mode: ALT6
12.4.5.376 LPSPI2_LPSPI_SDI_SELECT_INPUT DAISY Register
(LPSPI2_LPSPI_SDI_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.376.1 Offset
Register Offset
LPSPI2_LPSPI_SDI_SEL 5E8h
ECT_INPUT
12.4.5.376.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.376.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi2, In Pin: lpspi_sdi
0 - Selecting Pad: GPIO_AD_27 for Mode: ALT1
1 - Selecting Pad: GPIO_SD_B2_10 for Mode: ALT6
12.4.5.377 LPSPI2_LPSPI_SDO_SELECT_INPUT DAISY Register
(LPSPI2_LPSPI_SDO_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.377.1 Offset
Register Offset
LPSPI2_LPSPI_SDO_ 5ECh
SELECT_INPUT
12.4.5.377.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.377.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi2, In Pin: lpspi_sdo
0 - Selecting Pad: GPIO_AD_26 for Mode: ALT1
1 - Selecting Pad: GPIO_SD_B2_09 for Mode: ALT6
12.4.5.378 LPSPI3_LPSPI_PCS_SELECT_INPUT_0 DAISY Register
(LPSPI3_LPSPI_PCS_SELECT_INPUT_0)
DAISY Register
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Memory Map and register definition
12.4.5.378.1 Offset
Register Offset
LPSPI3_LPSPI_PCS_ 5F0h
SELECT_INPUT_0
12.4.5.378.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.378.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_pcs0
0 - Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT9
12.4.5.379 LPSPI3_LPSPI_PCS_SELECT_INPUT_1 DAISY Register
(LPSPI3_LPSPI_PCS_SELECT_INPUT_1)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.379.1 Offset
Register Offset
LPSPI3_LPSPI_PCS_ 5F4h
SELECT_INPUT_1
12.4.5.379.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.379.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_pcs1
0 - Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT9
12.4.5.380 LPSPI3_LPSPI_PCS_SELECT_INPUT_2 DAISY Register
(LPSPI3_LPSPI_PCS_SELECT_INPUT_2)
DAISY Register
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Memory Map and register definition
12.4.5.380.1 Offset
Register Offset
LPSPI3_LPSPI_PCS_ 5F8h
SELECT_INPUT_2
12.4.5.380.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.380.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_pcs2
0 - Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT9
12.4.5.381 LPSPI3_LPSPI_PCS_SELECT_INPUT_3 DAISY Register
(LPSPI3_LPSPI_PCS_SELECT_INPUT_3)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.381.1 Offset
Register Offset
LPSPI3_LPSPI_PCS_ 5FCh
SELECT_INPUT_3
12.4.5.381.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.381.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_pcs3
0 - Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_10 for Mode: ALT9
12.4.5.382 LPSPI3_LPSPI_SCK_SELECT_INPUT DAISY Register
(LPSPI3_LPSPI_SCK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.382.1 Offset
Register Offset
LPSPI3_LPSPI_SCK_ 600h
SELECT_INPUT
12.4.5.382.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.382.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_sck
0 - Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT9
12.4.5.383 LPSPI3_LPSPI_SDI_SELECT_INPUT DAISY Register
(LPSPI3_LPSPI_SDI_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.383.1 Offset
Register Offset
LPSPI3_LPSPI_SDI_SEL 604h
ECT_INPUT
12.4.5.383.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.383.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_sdi
0 - Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT9
12.4.5.384 LPSPI3_LPSPI_SDO_SELECT_INPUT DAISY Register
(LPSPI3_LPSPI_SDO_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.384.1 Offset
Register Offset
LPSPI3_LPSPI_SDO_ 608h
SELECT_INPUT
12.4.5.384.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.384.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi3, In Pin: lpspi_sdo
0 - Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT8
1 - Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT9
12.4.5.385 LPSPI4_LPSPI_PCS_SELECT_INPUT_0 DAISY Register
(LPSPI4_LPSPI_PCS_SELECT_INPUT_0)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.385.1 Offset
Register Offset
LPSPI4_LPSPI_PCS_ 60Ch
SELECT_INPUT_0
12.4.5.385.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.385.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi4, In Pin: lpspi_pcs0
0 - Selecting Pad: GPIO_SD_B2_01 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT9
12.4.5.386 LPSPI4_LPSPI_SCK_SELECT_INPUT DAISY Register
(LPSPI4_LPSPI_SCK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.386.1 Offset
Register Offset
LPSPI4_LPSPI_SCK_ 610h
SELECT_INPUT
12.4.5.386.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.386.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi4, In Pin: lpspi_sck
0 - Selecting Pad: GPIO_SD_B2_00 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B2_12 for Mode: ALT9
12.4.5.387 LPSPI4_LPSPI_SDI_SELECT_INPUT DAISY Register
(LPSPI4_LPSPI_SDI_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.387.1 Offset
Register Offset
LPSPI4_LPSPI_SDI_SEL 614h
ECT_INPUT
12.4.5.387.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.387.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi4, In Pin: lpspi_sdi
0 - Selecting Pad: GPIO_SD_B2_03 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B2_13 for Mode: ALT9
12.4.5.388 LPSPI4_LPSPI_SDO_SELECT_INPUT DAISY Register
(LPSPI4_LPSPI_SDO_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.388.1 Offset
Register Offset
LPSPI4_LPSPI_SDO_ 618h
SELECT_INPUT
12.4.5.388.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.388.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpspi4, In Pin: lpspi_sdo
0 - Selecting Pad: GPIO_SD_B2_02 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT9
12.4.5.389 LPUART1_LPUART_RXD_SELECT_INPUT DAISY Register
(LPUART1_LPUART_RXD_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.389.1 Offset
Register Offset
LPUART1_LPUART_R 61Ch
XD_SELECT_INPUT
12.4.5.389.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.389.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart1, In Pin: lpuart_rxd
00 - Selecting Pad: GPIO_AD_25 for Mode: ALT0
01 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT9
12.4.5.390 LPUART1_LPUART_TXD_SELECT_INPUT DAISY Register
(LPUART1_LPUART_TXD_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.390.1 Offset
Register Offset
LPUART1_LPUART_T 620h
XD_SELECT_INPUT
12.4.5.390.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.390.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart1, In Pin: lpuart_txd
00 - Selecting Pad: GPIO_AD_24 for Mode: ALT0
01 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT9
12.4.5.391 LPUART10_LPUART_RXD_SELECT_INPUT DAISY
Register (LPUART10_LPUART_RXD_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.391.1 Offset
Register Offset
LPUART10_LPUART_ 624h
RXD_SELECT_INPUT
12.4.5.391.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.391.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart10, In Pin: lpuart_rxd
0 - Selecting Pad: GPIO_AD_16 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_33 for Mode: ALT8
12.4.5.392 LPUART10_LPUART_TXD_SELECT_INPUT DAISY
Register (LPUART10_LPUART_TXD_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.392.1 Offset
Register Offset
LPUART10_LPUART_ 628h
TXD_SELECT_INPUT
12.4.5.392.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.392.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart10, In Pin: lpuart_txd
0 - Selecting Pad: GPIO_AD_15 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_32 for Mode: ALT8
12.4.5.393 LPUART7_LPUART_RXD_SELECT_INPUT DAISY Register
(LPUART7_LPUART_RXD_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.393.1 Offset
Register Offset
LPUART7_LPUART_R 62Ch
XD_SELECT_INPUT
12.4.5.393.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.393.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart7, In Pin: lpuart_rxd
0 - Selecting Pad: GPIO_AD_01 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B2_07 for Mode: ALT2
12.4.5.394 LPUART7_LPUART_TXD_SELECT_INPUT DAISY Register
(LPUART7_LPUART_TXD_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.394.1 Offset
Register Offset
LPUART7_LPUART_T 630h
XD_SELECT_INPUT
12.4.5.394.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.394.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart7, In Pin: lpuart_txd
0 - Selecting Pad: GPIO_AD_00 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT2
12.4.5.395 LPUART8_LPUART_RXD_SELECT_INPUT DAISY Register
(LPUART8_LPUART_RXD_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.395.1 Offset
Register Offset
LPUART8_LPUART_R 634h
XD_SELECT_INPUT
12.4.5.395.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.395.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart8, In Pin: lpuart_rxd
0 - Selecting Pad: GPIO_AD_03 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT2
12.4.5.396 LPUART8_LPUART_TXD_SELECT_INPUT DAISY Register
(LPUART8_LPUART_TXD_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.396.1 Offset
Register Offset
LPUART8_LPUART_T 638h
XD_SELECT_INPUT
12.4.5.396.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.396.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: lpuart8, In Pin: lpuart_txd
0 - Selecting Pad: GPIO_AD_02 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT2
12.4.5.397 QTIMER1_TMR0_INPUT_SELECT_INPUT DAISY Register
(QTIMER1_TMR0_INPUT_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.397.1 Offset
Register Offset
QTIMER1_TMR0_INP 63Ch
UT_SELECT_INPUT
12.4.5.397.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.397.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer1, In Pin: tmr0_input
00 - Selecting Pad: GPIO_EMC_B1_17 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT3
12.4.5.398 QTIMER1_TMR1_INPUT_SELECT_INPUT DAISY Register
(QTIMER1_TMR1_INPUT_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.398.1 Offset
Register Offset
QTIMER1_TMR1_INP 640h
UT_SELECT_INPUT
12.4.5.398.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.398.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer1, In Pin: tmr1_input
00 - Selecting Pad: GPIO_EMC_B1_38 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT3
12.4.5.399 QTIMER1_TMR2_INPUT_SELECT_INPUT DAISY Register
(QTIMER1_TMR2_INPUT_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.399.1 Offset
Register Offset
QTIMER1_TMR2_INP 644h
UT_SELECT_INPUT
12.4.5.399.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.399.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer1, In Pin: tmr2_input
0 - Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT3
12.4.5.400 QTIMER2_TMR0_INPUT_SELECT_INPUT DAISY Register
(QTIMER2_TMR0_INPUT_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.400.1 Offset
Register Offset
QTIMER2_TMR0_INP 648h
UT_SELECT_INPUT
12.4.5.400.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.400.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer2, In Pin: tmr0_input
00 - Selecting Pad: GPIO_EMC_B1_18 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT3
12.4.5.401 QTIMER2_TMR1_INPUT_SELECT_INPUT DAISY Register
(QTIMER2_TMR1_INPUT_SELECT_INPUT)
DAISY Register
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Chapter 12 IOMUX Controller (IOMUXC)
12.4.5.401.1 Offset
Register Offset
QTIMER2_TMR1_INP 64Ch
UT_SELECT_INPUT
12.4.5.401.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.401.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer2, In Pin: tmr1_input
00 - Selecting Pad: GPIO_EMC_B1_39 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT3
12.4.5.402 QTIMER2_TMR2_INPUT_SELECT_INPUT DAISY Register
(QTIMER2_TMR2_INPUT_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.402.1 Offset
Register Offset
QTIMER2_TMR2_INP 650h
UT_SELECT_INPUT
12.4.5.402.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.402.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer2, In Pin: tmr2_input
0 - Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT3
12.4.5.403 QTIMER3_TMR0_INPUT_SELECT_INPUT DAISY Register
(QTIMER3_TMR0_INPUT_SELECT_INPUT)
DAISY Register
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12.4.5.403.1 Offset
Register Offset
QTIMER3_TMR0_INP 654h
UT_SELECT_INPUT
12.4.5.403.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.403.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer3, In Pin: tmr0_input
00 - Selecting Pad: GPIO_EMC_B1_19 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_17 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT3
12.4.5.404 QTIMER3_TMR1_INPUT_SELECT_INPUT DAISY Register
(QTIMER3_TMR1_INPUT_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.404.1 Offset
Register Offset
QTIMER3_TMR1_INP 658h
UT_SELECT_INPUT
12.4.5.404.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.404.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer3, In Pin: tmr1_input
00 - Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT2
01 - Selecting Pad: GPIO_EMC_B2_18 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT3
12.4.5.405 QTIMER3_TMR2_INPUT_SELECT_INPUT DAISY Register
(QTIMER3_TMR2_INPUT_SELECT_INPUT)
DAISY Register
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12.4.5.405.1 Offset
Register Offset
QTIMER3_TMR2_INP 65Ch
UT_SELECT_INPUT
12.4.5.405.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.405.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer3, In Pin: tmr2_input
0 - Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT3
12.4.5.406 QTIMER4_TMR0_INPUT_SELECT_INPUT DAISY Register
(QTIMER4_TMR0_INPUT_SELECT_INPUT)
DAISY Register
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12.4.5.406.1 Offset
Register Offset
QTIMER4_TMR0_INP 660h
UT_SELECT_INPUT
12.4.5.406.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.406.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer4, In Pin: tmr0_input
00 - Selecting Pad: GPIO_EMC_B1_20 for Mode: ALT2
01 - Selecting Pad: GPIO_AD_04 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT3
12.4.5.407 QTIMER4_TMR1_INPUT_SELECT_INPUT DAISY Register
(QTIMER4_TMR1_INPUT_SELECT_INPUT)
DAISY Register
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12.4.5.407.1 Offset
Register Offset
QTIMER4_TMR1_INP 664h
UT_SELECT_INPUT
12.4.5.407.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.407.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer4, In Pin: tmr1_input
00 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT2
01 - Selecting Pad: GPIO_AD_05 for Mode: ALT9
10 - Selecting Pad: GPIO_DISP_B1_10 for Mode: ALT3
12.4.5.408 QTIMER4_TMR2_INPUT_SELECT_INPUT DAISY Register
(QTIMER4_TMR2_INPUT_SELECT_INPUT)
DAISY Register
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12.4.5.408.1 Offset
Register Offset
QTIMER4_TMR2_INP 668h
UT_SELECT_INPUT
12.4.5.408.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.408.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: qtimer4, In Pin: tmr2_input
0 - Selecting Pad: GPIO_AD_06 for Mode: ALT9
1 - Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT3
12.4.5.409 SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT DAISY
Register (SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT)
DAISY Register
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12.4.5.409.1 Offset
Register Offset
SAI1_IPG_CLK_SAI_ 66Ch
MCLK_SELECT_INPUT
12.4.5.409.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.409.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: ipg_clk_sai_mclk
0 - Selecting Pad: GPIO_AD_17 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_03 for Mode: ALT4
12.4.5.410 SAI1_SAI_RXBCLK_SELECT_INPUT DAISY Register (SAI1
_SAI_RXBCLK_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.410.1 Offset
Register Offset
SAI1_SAI_RXBCLK_ 670h
SELECT_INPUT
12.4.5.410.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.410.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: sai_rxbclk
0 - Selecting Pad: GPIO_AD_19 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_05 for Mode: ALT4
12.4.5.411 SAI1_SAI_RXDATA_SELECT_INPUT_0 DAISY Register
(SAI1_SAI_RXDATA_SELECT_INPUT_0)
DAISY Register
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12.4.5.411.1 Offset
Register Offset
SAI1_SAI_RXDATA_ 674h
SELECT_INPUT_0
12.4.5.411.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.411.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: sai_rxdata0
0 - Selecting Pad: GPIO_AD_20 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_06 for Mode: ALT4
12.4.5.412 SAI1_SAI_RXSYNC_SELECT_INPUT DAISY Register (SAI1
_SAI_RXSYNC_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.412.1 Offset
Register Offset
SAI1_SAI_RXSYNC_ 678h
SELECT_INPUT
12.4.5.412.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.412.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: sai_rxsync
0 - Selecting Pad: GPIO_AD_18 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_04 for Mode: ALT4
12.4.5.413 SAI1_SAI_TXBCLK_SELECT_INPUT DAISY Register (SAI1
_SAI_TXBCLK_SELECT_INPUT)
DAISY Register
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12.4.5.413.1 Offset
Register Offset
SAI1_SAI_TXBCLK_ 67Ch
SELECT_INPUT
12.4.5.413.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.413.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: sai_txbclk
0 - Selecting Pad: GPIO_AD_22 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_08 for Mode: ALT4
12.4.5.414 SAI1_SAI_TXSYNC_SELECT_INPUT DAISY Register (SAI1
_SAI_TXSYNC_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.414.1 Offset
Register Offset
SAI1_SAI_TXSYNC_ 680h
SELECT_INPUT
12.4.5.414.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.414.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: sai1, In Pin: sai_txsync
0 - Selecting Pad: GPIO_AD_23 for Mode: ALT0
1 - Selecting Pad: GPIO_DISP_B2_09 for Mode: ALT4
12.4.5.415 EMVSIM1_SIO_SELECT_INPUT DAISY Register (EMVS
IM1_SIO_SELECT_INPUT)
DAISY Register
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12.4.5.415.1 Offset
Register Offset
EMVSIM1_SIO_SELE 69Ch
CT_INPUT
12.4.5.415.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.415.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM1, In Pin: sio
0 - Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_00 for Mode: ALT0
12.4.5.416 EMVSIM1_IPP_SIMPD_SELECT_INPUT DAISY Register
(EMVSIM1_IPP_SIMPD_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.416.1 Offset
Register Offset
EMVSIM1_IPP_SIMPD_ 6A0h
SELECT_INPUT
12.4.5.416.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.416.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM1, In Pin: ipp_simpd
0 - Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_04 for Mode: ALT0
12.4.5.417 EMVSIM1_POWER_FAIL_SELECT_INPUT DAISY Register
(EMVSIM1_POWER_FAIL_SELECT_INPUT)
DAISY Register
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12.4.5.417.1 Offset
Register Offset
EMVSIM1_POWER_FA 6A4h
IL_SELECT_INPUT
12.4.5.417.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.417.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM1, In Pin: power_fail
0 - Selecting Pad: GPIO_EMC_B2_16 for Mode: ALT8
1 - Selecting Pad: GPIO_AD_05 for Mode: ALT0
12.4.5.418 EMVSIM2_SIO_SELECT_INPUT DAISY Register (EMVS
IM2_SIO_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.418.1 Offset
Register Offset
EMVSIM2_SIO_SELE 6A8h
CT_INPUT
12.4.5.418.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.418.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM2, In Pin: sio
0 - Selecting Pad: GPIO_AD_06 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT1
12.4.5.419 EMVSIM2_IPP_SIMPD_SELECT_INPUT DAISY Register
(EMVSIM2_IPP_SIMPD_SELECT_INPUT)
DAISY Register
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12.4.5.419.1 Offset
Register Offset
EMVSIM2_IPP_SIMPD_ 6ACh
SELECT_INPUT
12.4.5.419.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.419.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM2, In Pin: ipp_simpd
0 - Selecting Pad: GPIO_AD_10 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT1
12.4.5.420 EMVSIM2_POWER_FAIL_SELECT_INPUT DAISY Register
(EMVSIM2_POWER_FAIL_SELECT_INPUT)
DAISY Register
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12.4.5.420.1 Offset
Register Offset
EMVSIM2_POWER_FA 6B0h
IL_SELECT_INPUT
12.4.5.420.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.420.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: EMVSIM2, In Pin: power_fail
0 - Selecting Pad: GPIO_AD_11 for Mode: ALT2
1 - Selecting Pad: GPIO_DISP_B2_15 for Mode: ALT1
12.4.5.421 SPDIF_SPDIF_IN1_SELECT_INPUT DAISY Register (SPDI
F_SPDIF_IN1_SELECT_INPUT)
DAISY Register
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12.4.5.421.1 Offset
Register Offset
SPDIF_SPDIF_IN1_ 6B4h
SELECT_INPUT
12.4.5.421.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.421.3 Fields
Field Description
31-2 -
— Reserved
1-0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: spdif, In Pin: spdif_in1
00 - Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT1
01 - Selecting Pad: GPIO_AD_15 for Mode: ALT0
10 - Selecting Pad: GPIO_DISP_B2_10 for Mode: ALT9
12.4.5.422 USB_OTG2_OC_SELECT_INPUT DAISY Register (USB_
OTG2_OC_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.422.1 Offset
Register Offset
USB_OTG2_OC_SELE 6B8h
CT_INPUT
12.4.5.422.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.422.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usb, In Pin: otg2_oc
0 - Selecting Pad: GPIO_AD_06 for Mode: ALT0
1 - Selecting Pad: GPIO_AD_30 for Mode: ALT1
12.4.5.423 USB_OTG_OC_SELECT_INPUT DAISY Register (USB_
OTG_OC_SELECT_INPUT)
DAISY Register
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12.4.5.423.1 Offset
Register Offset
USB_OTG_OC_SELEC 6BCh
T_INPUT
12.4.5.423.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.423.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usb, In Pin: otg_oc
0 - Selecting Pad: GPIO_AD_11 for Mode: ALT0
1 - Selecting Pad: GPIO_AD_35 for Mode: ALT1
12.4.5.424 USBPHY1_USB_ID_SELECT_INPUT DAISY Register
(USBPHY1_USB_ID_SELECT_INPUT)
DAISY Register
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Memory Map and register definition
12.4.5.424.1 Offset
Register Offset
USBPHY1_USB_ID_S 6C0h
ELECT_INPUT
12.4.5.424.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.424.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usbphy1, In Pin: usb_id
0 - Selecting Pad: GPIO_AD_09 for Mode: ALT0
1 - Selecting Pad: GPIO_AD_33 for Mode: ALT1
12.4.5.425 USBPHY2_USB_ID_SELECT_INPUT DAISY Register
(USBPHY2_USB_ID_SELECT_INPUT)
DAISY Register
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12.4.5.425.1 Offset
Register Offset
USBPHY2_USB_ID_S 6C4h
ELECT_INPUT
12.4.5.425.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.425.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usbphy2, In Pin: usb_id
0 - Selecting Pad: GPIO_AD_08 for Mode: ALT0
1 - Selecting Pad: GPIO_AD_32 for Mode: ALT1
12.4.5.426 USDHC1_IPP_CARD_DET_SELECT_INPUT DAISY
Register (USDHC1_IPP_CARD_DET_SELECT_INPUT)
DAISY Register
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12.4.5.426.1 Offset
Register Offset
USDHC1_IPP_CARD_ 6C8h
DET_SELECT_INPUT
12.4.5.426.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.426.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usdhc1, In Pin: ipp_card_det
0 - Selecting Pad: GPIO_AD_32 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT2
12.4.5.427 USDHC1_IPP_WP_ON_SELECT_INPUT DAISY Register
(USDHC1_IPP_WP_ON_SELECT_INPUT)
DAISY Register
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12.4.5.427.1 Offset
Register Offset
USDHC1_IPP_WP_ON_ 6CCh
SELECT_INPUT
12.4.5.427.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.427.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usdhc1, In Pin: ipp_wp_on
0 - Selecting Pad: GPIO_AD_33 for Mode: ALT4
1 - Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT2
12.4.5.428 USDHC2_IPP_CARD_DET_SELECT_INPUT DAISY
Register (USDHC2_IPP_CARD_DET_SELECT_INPUT)
DAISY Register
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12.4.5.428.1 Offset
Register Offset
USDHC2_IPP_CARD_ 6D0h
DET_SELECT_INPUT
12.4.5.428.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.428.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usdhc2, In Pin: ipp_card_det
0 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_26 for Mode: ALT11
12.4.5.429 USDHC2_IPP_WP_ON_SELECT_INPUT DAISY Register
(USDHC2_IPP_WP_ON_SELECT_INPUT)
DAISY Register
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12.4.5.429.1 Offset
Register Offset
USDHC2_IPP_WP_ON_ 6D4h
SELECT_INPUT
12.4.5.429.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.429.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: usdhc2, In Pin: ipp_wp_on
0 - Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT1
1 - Selecting Pad: GPIO_AD_27 for Mode: ALT11
12.4.5.430 XBAR1_IN_SELECT_INPUT_20 DAISY Register (XBAR1_IN
_SELECT_INPUT_20)
DAISY Register
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12.4.5.430.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6D8h
INPUT_20
12.4.5.430.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.430.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in20
0 - Selecting Pad: GPIO_EMC_B2_00 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2
12.4.5.431 XBAR1_IN_SELECT_INPUT_21 DAISY Register (XBAR1_IN
_SELECT_INPUT_21)
DAISY Register
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12.4.5.431.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6DCh
INPUT_21
12.4.5.431.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.431.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in21
0 - Selecting Pad: GPIO_EMC_B2_01 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2
12.4.5.432 XBAR1_IN_SELECT_INPUT_22 DAISY Register (XBAR1_IN
_SELECT_INPUT_22)
DAISY Register
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12.4.5.432.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6E0h
INPUT_22
12.4.5.432.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.432.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in22
0 - Selecting Pad: GPIO_EMC_B2_02 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2
12.4.5.433 XBAR1_IN_SELECT_INPUT_23 DAISY Register (XBAR1_IN
_SELECT_INPUT_23)
DAISY Register
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12.4.5.433.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6E4h
INPUT_23
12.4.5.433.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.433.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in23
0 - Selecting Pad: GPIO_EMC_B2_03 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2
12.4.5.434 XBAR1_IN_SELECT_INPUT_24 DAISY Register (XBAR1_IN
_SELECT_INPUT_24)
DAISY Register
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12.4.5.434.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6E8h
INPUT_24
12.4.5.434.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.434.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in24
0 - Selecting Pad: GPIO_EMC_B2_04 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2
12.4.5.435 XBAR1_IN_SELECT_INPUT_25 DAISY Register (XBAR1_IN
_SELECT_INPUT_25)
DAISY Register
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12.4.5.435.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6ECh
INPUT_25
12.4.5.435.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.435.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in25
0 - Selecting Pad: GPIO_EMC_B2_05 for Mode: ALT6
1 - Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2
12.4.5.436 XBAR1_IN_SELECT_INPUT_26 DAISY Register (XBAR1_IN
_SELECT_INPUT_26)
DAISY Register
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12.4.5.436.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6F0h
INPUT_26
12.4.5.436.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.436.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in26
0 - Selecting Pad: GPIO_EMC_B2_06 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_00 for Mode: ALT4
12.4.5.437 XBAR1_IN_SELECT_INPUT_27 DAISY Register (XBAR1_IN
_SELECT_INPUT_27)
DAISY Register
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12.4.5.437.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6F4h
INPUT_27
12.4.5.437.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.437.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in27
0 - Selecting Pad: GPIO_EMC_B2_07 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_01 for Mode: ALT4
12.4.5.438 XBAR1_IN_SELECT_INPUT_28 DAISY Register (XBAR1_IN
_SELECT_INPUT_28)
DAISY Register
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12.4.5.438.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6F8h
INPUT_28
12.4.5.438.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.438.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in28
0 - Selecting Pad: GPIO_EMC_B2_08 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_02 for Mode: ALT4
12.4.5.439 XBAR1_IN_SELECT_INPUT_29 DAISY Register (XBAR1_IN
_SELECT_INPUT_29)
DAISY Register
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12.4.5.439.1 Offset
Register Offset
XBAR1_IN_SELECT_ 6FCh
INPUT_29
12.4.5.439.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.439.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in29
0 - Selecting Pad: GPIO_EMC_B2_09 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_03 for Mode: ALT4
12.4.5.440 XBAR1_IN_SELECT_INPUT_30 DAISY Register (XBAR1_IN
_SELECT_INPUT_30)
DAISY Register
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12.4.5.440.1 Offset
Register Offset
XBAR1_IN_SELECT_ 700h
INPUT_30
12.4.5.440.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.440.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in30
0 - Selecting Pad: GPIO_EMC_B2_10 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_04 for Mode: ALT4
12.4.5.441 XBAR1_IN_SELECT_INPUT_31 DAISY Register (XBAR1_IN
_SELECT_INPUT_31)
DAISY Register
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12.4.5.441.1 Offset
Register Offset
XBAR1_IN_SELECT_ 704h
INPUT_31
12.4.5.441.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.441.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in31
0 - Selecting Pad: GPIO_EMC_B2_11 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_05 for Mode: ALT4
12.4.5.442 XBAR1_IN_SELECT_INPUT_32 DAISY Register (XBAR1_IN
_SELECT_INPUT_32)
DAISY Register
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12.4.5.442.1 Offset
Register Offset
XBAR1_IN_SELECT_ 708h
INPUT_32
12.4.5.442.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.442.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in32
0 - Selecting Pad: GPIO_EMC_B2_12 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_06 for Mode: ALT4
12.4.5.443 XBAR1_IN_SELECT_INPUT_33 DAISY Register (XBAR1_IN
_SELECT_INPUT_33)
DAISY Register
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12.4.5.443.1 Offset
Register Offset
XBAR1_IN_SELECT_ 70Ch
INPUT_33
12.4.5.443.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.443.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in33
0 - Selecting Pad: GPIO_EMC_B2_13 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_07 for Mode: ALT4
12.4.5.444 XBAR1_IN_SELECT_INPUT_34 DAISY Register (XBAR1_IN
_SELECT_INPUT_34)
DAISY Register
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12.4.5.444.1 Offset
Register Offset
XBAR1_IN_SELECT_ 710h
INPUT_34
12.4.5.444.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.444.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in34
0 - Selecting Pad: GPIO_EMC_B2_14 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_08 for Mode: ALT4
12.4.5.445 XBAR1_IN_SELECT_INPUT_35 DAISY Register (XBAR1_IN
_SELECT_INPUT_35)
DAISY Register
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12.4.5.445.1 Offset
Register Offset
XBAR1_IN_SELECT_ 714h
INPUT_35
12.4.5.445.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
DAISY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12.4.5.445.3 Fields
Field Description
31-1 -
— Reserved
0 Selecting Pads Involved in Daisy Chain.
DAISY Instance: xbar1, In Pin: xbar_in35
0 - Selecting Pad: GPIO_EMC_B2_15 for Mode: ALT6
1 - Selecting Pad: GPIO_DISP_B1_09 for Mode: ALT4
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Chapter 13
General Purpose Input/Output (GPIO)
13.1 Chip-specific GPIO information
Table 13-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
GPIO_MUX2_IOn and GPIO_MUX3_IOn signals can be routed to the standard GPIO
modules (GPIO2 and GPIO3), or they can be routed to high speed GPIO modules
(CM7_GPIO2 and CM7_GPIO3). By default, all of the GPIO_MUX2 and GPIO_MUX3
signals route to the standard GPIO2 and GPIO3 modules. To use high speed GPIOs, the
IOMUXC_GPR40 - IOMUC_GPR43 registers must be reconfigured to route the desired
signals to the CM7_GPIO2 and/or CM7_GPIO3 modules.
13.2 Overview
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose
pins that can be configured as either inputs or outputs.
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When configured as an output, it is possible to write to an internal register to control the
state driven on the output pin. When configured as an input, it is possible to detect the
state of the input by reading the state of an internal register. In addition, the GPIO
peripheral can produce CORE interrupts.
13.2.1 Block Diagram
The GPIO subsystem contains multiple GPIO blocks, which can generate and control up
to 32 signals for general purpose.
The block diagram for the GPIO block is provided below.
GDIR
gdir
DR dr
PSR in
IP Bus Interface
Interrupt Control Unit
ICR0
ICR1
EDGE_SEL int_31_16
ISR int_15_0
int_31_0
IMR
Figure 13-1. GPIO Block Diagram
13.2.2 Features
The GPIO includes the following features:
• General purpose input/output logic capabilities:
• Drives specific data to output using the data register (DR)
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• Controls the direction of the signal using the GPIO direction register (GDIR)
• Enables the core to sample the status of the corresponding inputs by reading the
pad sample register (PSR).
• GPIO interrupt capabilities:
• Supports 32 interrupts
• Identifies interrupt edges
• Generates three active-high interrupts to the SoC interrupt controller
13.3 Functional Description
The GPIO is one of the blocks controlling the IOMUX of the chip.
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Functional Description
Block
This block is not
configured as a GPIO
GPIO IOMUX
DR input_on
GDIR
PSR Direction
Data_out
ICR1 Data_in
ICR2 PAD1
EDGE_SEL
IMR
ISR
IOMUXC alternate input
SW_MUX_CTL_PAD_*
MUX_MODE
SW_PAD_CTL_PAD_*
pad settings
IOMUX input_on
Direction
Data_out
Data_in
PAD2
Figure 13-2. Chip IOMUX Scheme
A GPIO signal can operate as a general-purpose input/output when the IOMUX is set to
GPIO mode. Each GPIO signal may be independently configured as either an input or an
output using the GPIO direction register (GDIR).
When configured as an output (GDIR[GDIR] = 1), the value in the data bit in the GPIO
data register (DR) is driven on the corresponding GPIO line. When a signal is configured
as an input (GDIR[GDIR] = 0), the state of the input can be read from the corresponding
PSR[PSR] bit.
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Chapter 13 General Purpose Input/Output (GPIO)
The GPIO functionality is provided through eight registers, an edge-detect circuit, and
interrupt generation logic.
The eight registers are:
• Data register (DR)
• GPIO direction register (GDIR)
• Pad sample register (PSR)
• Interrupt control registers (ICR1, ICR2)
• Edge select register (EDGE_SEL)
• Interrupt mask register (IMR)
• Interrupt status register (ISR)
The above registers are described in detail in the Register section.
Each GPIO input has a dedicated edge-detect circuit which can be configured through
software to detect rising edges, falling edges, logic low-levels or logic high-levels on the
input signals. The outputs of the edge detect circuits are optionally masked by setting the
corresponding bit in the interrupt mask register (IMR). These qualified outputs are OR'ed
together to generate two one-bit interrupt lines:
• Combined interrupt indication for GPIOx signals 0 - 15
• Combined interrupt indication for GPIOx signals 16 - 31
In addition, GPIO1 provides visibility to each of its 8 low order interrupt sources (i.e.
GPIO1 interrupt n, for n = 0 – 7). However, individual interrupt indications from other
GPIOx are not available.
The GPIO edge detection is described further in Interrupt Control Unit.
13.3.1 GPIO pad structure
The functional diagram for the GPIO pad is provided below.
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Functional Description
output buffer enable (OBE)
PAD
DSE
Output
Driver
SRE
Driver PUS
SPEED Config
Logic
ODE
Resd
PU / PD / Keeper
PKE Logic
pull_en_b
input buffer enable (IBE)
PU / PD Keeper
IND
Input
Receiver esd clamp or
HYS trigger circuit
Figure 13-3. GPIO pad functional diagram
The abbreviations for the acronyms in the block diagram are provided below:
DSE - Drive Strength Enable
ODE - Open Drain Enable
SRE - Slew Rate Enable
PKE - Pull / Keep Enable
IND - Input data
HYS - Hysteresis Enable
PUS - Pull Select
PU - Pull-up
PD - Pull-down
13.3.1.1 Input Driver
Input driver characteristics
• Selectable Schmitt trigger or CMOS input mode
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Chapter 13 General Purpose Input/Output (GPIO)
• Keeper structure with buffer at the input receiver output to Core
• Receiver is tri-stated when I/O supply (OVDD) is powered down. The keeper at the
receiver output keeps it's previous state.
13.3.1.1.1 Schmitt trigger
The anti-jamming functionality of the Schmitt trigger is illustrated below.
Vo
Vi
Vt- Vt+
Figure 13-4. Schmitt trigger transfer characteristic
Vt+
noisy input voltage
Vth
Vt-
cmos receiver output with multiple
transitions caused by input noise
noise is filtered out in receiver with
hysteresis mode
time
Figure 13-5. Receiver output in CMOS and hysteresis
13.3.1.1.2 Input keeper
A simple latch to hold the input value when OVDD is powered down, or the first inverter
is tri-stated. Input buffer’s keeper is always enabled for all the pads.
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Functional Description
13.3.1.2 Output Driver
Output driver characteristics
• Selectable CMOS or open-drain output type
• Selectable pull-keeper enable signal to enable/disable the pull-up/down and output
keeper
• Selectable pull-up resistors of 22K, 47K, 100K and a pull-down resistor of
100KOhm. Unsilicided P+ poly resistor is used to limit resistance variation to within
+/- 20%.
• Pull-up, pull-down, and pad keeper are disabled in output mode.
• Seven drive strengths in each operating mode
• Additional 2-bit slew rate control to select between 50, 100, and 200 MHz IO cell
operation range with reduced switching noise
OVDD
OVDD
Predriver
do
Vpad
Output buffer
OVSS
OVSS
Figure 13-6. Output Driver Functional Diagram
13.3.1.2.1 Drive strength
Drive strength selection can be use to make the impedance matched and get better signal
integrity.
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Chapter 13 General Purpose Input/Output (GPIO)
13.3.1.2.2 Output keeper
A simple latch to hold the input value. The input value here refers to DO (data out), not
data from PAD.
measure
PKE = VDD
keeper_n
OVDD
DO
pad
OBE
keeper_p OVDD
OVDD
Figure 13-7. Keeper functional diagram
13.3.1.2.3 PU / PD / Keeper Logic
When Keeper is enabled, the pull-up and pull-down are disabled, and the output value of
the pad depends on the Keeper. The output keeper is powered by OVDD. When the core
VDD is powered down or the first inverter is tri-stated, the pad’s state can be kept.
Keeper and Pull can’t be enabled together.
13.3.1.2.4 Open drain
Open drain is a circuit technique which allows multiple devices to communication over a
single wire bi-directionally. Open drain drivers usually operate with an external or
internal pull-up resistor that holds the signal line high until a device sinks enough current
to pull the line low, usually used for a bus with multiple devices.
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Functional Description
OVDD1 OVDD2
external
If internal pull-up resistor (Rpu) is
Rpu Rpu
used, output level will depend on
OVDD1
If external Rpu is used, output level
will depend on OVDD2
OVSS1
Figure 13-8. Output buffer in open drain mode
13.3.2 Interrupt Control Unit
In addition to the general-purpose input/output function, the edge-detect logic in the
GPIO peripheral reflects whether a transition has occurred on a given GPIO signal that is
configured as an input (GDIR[GDIR] = 0). The interrupt control registers (ICR1 and
ICR2) may be used to independently configure the interrupt condition of each input
signal (low-to-high transition, high-to-low transition, low, or high). For information about
ICR1 and ICR2 settings, see the Register section.
The interrupt control unit is built of 32 interrupt control subunits, where each subunit
handles a single interrupt line.
13.3.3 Clocks
The following table describes the clock sources for GPIO. Please see the CCM for clock
setting, configuration and gating information.
Table 13-2. GPIO Clocks
Clock name Description
ipg_clk_s Peripheral access clock
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13.4 External Signals
The following table describes the external signals of GPIO.
Table 13-3. GPIO External Signals
Signal Description
IOn GPIO Signal
13.5 Application Information
13.5.1 GPIO Read Mode
The programming sequence for reading input signals should be as follows:
1. Configure IOMUX to select GPIO mode (via IOMUX Controller (IOMUXC)).
2. Configure GPIO direction register to input (GDIR[GDIR] = 0b).
3. Read value from data register/pad status register.
A pseudocode description to read [input3:input0] values is as follows:
// SET INPUTS TO GPIO MODE.
write sw_mux_ctl_<input0>_<input1>_<input2>_<input3>, 32'h00000000
// SET GDIR TO INPUT.
write GDIR[31:4,input3_bit, input2_bit, input1_bit, input0_bit,] 32'hxxxxxxx0
// READ INPUT VALUE FROM DR.
read DR
// READ INPUT VALUE FROM PSR.
read PSR
NOTE
While the GPIO direction is set to input (GDIR[GDIR] = 0), a
read access to DR does not return DR data. Instead, it returns
the PSR data, which is the corresponding input signal value.
13.5.2 GPIO Write Mode
The programming sequence for driving output signals should be as follows:
1. Configure IOMUX to select GPIO mode (via IOMUXC). If needed, enable SION to
read the loopback pad value through PSR.
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GPIO register descriptions
2. Configure GPIO direction register to output (GDIR[GDIR] = 1b).
3. Write value to data register (DR).
A pseudocode description to drive 4'b0101 on [output3:output0] is as follows:
// SET PADS TO GPIO MODE VIA IOMUX.
write sw_mux_ctl_pad_<output[0-3]>.mux_mode, <GPIO_MUX_MODE>
// Enable loopback to capture pad value into PSR in output mode
write sw_mux_ctl_pad_<output[0-3]>.sion, 1
// SET GDIR=1 TO OUTPUT BITS.
write GDIR[31:4,output3_bit,output2_bit, output1_bit, output0_bit,] 32'hxxxxxxxF
// WRITE OUTPUT VALUE=4’b0101 TO DR.
write DR, 32'hxxxxxxx5
// READ OUTPUT VALUE FROM PSR ONLY.
read_cmp PSR, 32'hxxxxxxx5
13.6 GPIO register descriptions
There are eight 32-bit GPIO registers. All registers are accessible from the IP interface.
Only 32-bit access is supported.
The GPIO memory map is shown in the following table.
13.6.1 GPIO memory map
CM7_GPIO2 base address: 4200_8000h
CM7_GPIO3 base address: 4200_C000h
GPIO1 base address: 4012_C000h
GPIO2 base address: 4013_0000h
GPIO3 base address: 4013_4000h
GPIO4 base address: 4013_8000h
GPIO5 base address: 4013_C000h
GPIO6 base address: 4014_0000h
GPIO7 base address: 40C5_C000h
GPIO8 base address: 40C6_0000h
GPIO9 base address: 40C6_4000h
GPIO10 base address: 40C6_8000h
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GPIO11 base address: 40C6_C000h
GPIO12 base address: 40C7_0000h
GPIO13 base address: 40CA_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 GPIO data register (DR) 32 RW 0000_0000
4 GPIO direction register (GDIR) 32 RW 0000_0000
8 GPIO pad status register (PSR) 32 RO 0000_0000
C GPIO interrupt configuration register1 (ICR1) 32 RW 0000_0000
10 GPIO interrupt configuration register2 (ICR2) 32 RW 0000_0000
14 GPIO interrupt mask register (IMR) 32 RW 0000_0000
18 GPIO interrupt status register (ISR) 32 W1C 0000_0000
1C GPIO edge select register (EDGE_SEL) 32 RW 0000_0000
84 GPIO data register SET (DR_SET) 32 WO 0000_0000
88 GPIO data register CLEAR (DR_CLEAR) 32 WO 0000_0000
8C GPIO data register TOGGLE (DR_TOGGLE) 32 WO 0000_0000
13.6.2 GPIO data register (DR)
The 32-bit DR register stores data that is ready to be driven to the output lines. If the
IOMUXC is in GPIO mode and a given GPIO direction bit is set, then the corresponding
DR bit is driven to the output. If a given GPIO direction bit is cleared, then a read of DR
register reflects the value of the corresponding signal. Two wait states are required in
read access for synchronization.
The results of a read of a DR bit depends on the IOMUXC input mode settings and the
corresponding GDIR bit as follows:
• If GDIR[n] is set and IOMUXC input mode is GPIO, then reading DR[n] returns the
contents of DR[n].
• If GDIR[n] is cleared and IOMUXC input mode is GPIO, then reading DR[n] returns
the corresponding input signal's value.
• If GDIR[n] is set and IOMUXC input mode is not GPIO, then reading DR[n] returns
the contents of DR[n].
• If GDIR[n] is cleared and IOMUXC input mode is not GPIO, then reading DR[n]
always returns zero.
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GPIO register descriptions
13.6.2.1 Offset
Register Offset
DR 0h
13.6.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.2.3 Fields
Field Description
31-0 DR data bits
DR This register defines the value of the GPIO output when the signal is configured as an output
(GDIR[n]=1). Writes to this register are stored in a register. Reading DR register returns the value stored
in the register if the signal is configured as an output (GDIR[n]=1), or the input signal's value if configured
as an input (GDIR[n]=0).
NOTE: The IOMUXC must be configured to GPIO mode for the DR register value to connect with the
signal. Reading the data register with the input path disabled always returns a zero value.
13.6.3 GPIO direction register (GDIR)
The GDIR register functions as direction control when the IOMUXC is in GPIO mode.
Each bit specifies the direction of a one-bit signal. The mapping of each DIR bit to a
corresponding SoC signal is determined by the SoC's pin assignment and the IOMUX
table. For more details consult the IOMUXC chapter.
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13.6.3.1 Offset
Register Offset
GDIR 4h
13.6.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GDIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GDIR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.3.3 Fields
Field Description
31-0 GPIO direction bits
GDIR Bit n of this register defines the direction of the GPIO[n] signal.
NOTE: The GDIR register affects only the direction of the I/O signal when the corresponding bit in the
IOMUXC is configured for GPIO.
0b - GPIO is configured as input.
1b - GPIO is configured as output.
13.6.4 GPIO pad status register (PSR)
The PSR register is a read-only register. Each bit stores the value of the corresponding
input signal (as configured in the IOMUX). This register is clocked with the ipg_clk_s
clock, meaning that the input signal is sampled only when accessing this location. Two
wait states are required any time this register is accessed for synchronization.
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GPIO register descriptions
13.6.4.1 Offset
Register Offset
PSR 8h
13.6.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.4.3 Fields
Field Description
31-0 GPIO pad status bits
PSR Reading the PSR register returns the state of the corresponding input signal.
NOTE: The IOMUXC must be configured to GPIO mode for the PSR register to reflect the state of the
corresponding signal.
13.6.5 GPIO interrupt configuration register1 (ICR1)
The ICR1 register contains 16 two-bit fields, where each field specifies the interrupt
configuration for a different input signal.
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13.6.5.1 Offset
Register Offset
ICR1 Ch
13.6.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 ICR9 ICR8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.5.3 Fields
Field Description
31-30 Interrupt configuration field for GPIO interrupt 15
ICR15 This bit field controls the active condition of the interrupt function for GPIO interrupt 15.
00 - Interrupt 15 is low-level sensitive.
01 - Interrupt 15 is high-level sensitive.
10 - Interrupt 15 is rising-edge sensitive.
11 - Interrupt 15 is falling-edge sensitive.
29-28 Interrupt configuration field for GPIO interrupt 14
ICR14 This bit field controls the active condition of the interrupt function for GPIO interrupt 14.
00 - Interrupt 14 is low-level sensitive.
01 - Interrupt 14 is high-level sensitive.
10 - Interrupt 14 is rising-edge sensitive.
11 - Interrupt 14 is falling-edge sensitive.
27-26 Interrupt configuration field for GPIO interrupt 13
ICR13 This bit field controls the active condition of the interrupt function for GPIO interrupt 13.
00 - Interrupt 13 is low-level sensitive.
01 - Interrupt 13 is high-level sensitive.
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Field Description
10 - Interrupt 13 is rising-edge sensitive.
11 - Interrupt 13 is falling-edge sensitive.
25-24 Interrupt configuration field for GPIO interrupt 12
ICR12 This bit field controls the active condition of the interrupt function for GPIO interrupt 12.
00 - Interrupt 12 is low-level sensitive.
01 - Interrupt 12 is high-level sensitive.
10 - Interrupt 12 is rising-edge sensitive.
11 - Interrupt 12 is falling-edge sensitive.
23-22 Interrupt configuration field for GPIO interrupt 11
ICR11 This bit field controls the active condition of the interrupt function for GPIO interrupt 11.
00 - Interrupt 11 is low-level sensitive.
01 - Interrupt 11 is high-level sensitive.
10 - Interrupt 11 is rising-edge sensitive.
11 - Interrupt 11 is falling-edge sensitive.
21-20 Interrupt configuration field for GPIO interrupt 10
ICR10 This bit field controls the active condition of the interrupt function for GPIO interrupt 10.
00 - Interrupt 10 is low-level sensitive.
01 - Interrupt 10 is high-level sensitive.
10 - Interrupt 10 is rising-edge sensitive.
11 - Interrupt 10 is falling-edge sensitive.
19-18 Interrupt configuration field for GPIO interrupt 9
ICR9 This bit field controls the active condition of the interrupt function for GPIO interrupt 9.
00 - Interrupt 9 is low-level sensitive.
01 - Interrupt 9 is high-level sensitive.
10 - Interrupt 9 is rising-edge sensitive.
11 - Interrupt 9 is falling-edge sensitive.
17-16 Interrupt configuration field for GPIO interrupt 8
ICR8 This bit field controls the active condition of the interrupt function for GPIO interrupt 8.
00 - Interrupt 8 is low-level sensitive.
01 - Interrupt 8 is high-level sensitive.
10 - Interrupt 8 is rising-edge sensitive.
11 - Interrupt 8 is falling-edge sensitive.
15-14 Interrupt configuration field for GPIO interrupt 7
ICR7 This bit field controls the active condition of the interrupt function for GPIO interrupt 7.
00 - Interrupt 7 is low-level sensitive.
01 - Interrupt 7 is high-level sensitive.
10 - Interrupt 7 is rising-edge sensitive.
11 - Interrupt 7 is falling-edge sensitive.
13-12 Interrupt configuration field for GPIO interrupt 6
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Field Description
ICR6 This bit field controls the active condition of the interrupt function for GPIO interrupt 6.
00 - Interrupt 6 is low-level sensitive.
01 - Interrupt 6 is high-level sensitive.
10 - Interrupt 6 is rising-edge sensitive.
11 - Interrupt 6 is falling-edge sensitive.
11-10 Interrupt configuration field for GPIO interrupt 5
ICR5 This bit field controls the active condition of the interrupt function for GPIO interrupt 5.
00 - Interrupt 5 is low-level sensitive.
01 - Interrupt 5 is high-level sensitive.
10 - Interrupt 5 is rising-edge sensitive.
11 - Interrupt 5 is falling-edge sensitive.
9-8 Interrupt configuration field for GPIO interrupt 4
ICR4 This bit field controls the active condition of the interrupt function for GPIO interrupt 4.
00 - Interrupt 4 is low-level sensitive.
01 - Interrupt 4 is high-level sensitive.
10 - Interrupt 4 is rising-edge sensitive.
11 - Interrupt 4 is falling-edge sensitive.
7-6 Interrupt configuration field for GPIO interrupt 3
ICR3 This bit field controls the active condition of the interrupt function for GPIO interrupt 3.
00 - Interrupt 3 is low-level sensitive.
01 - Interrupt 3 is high-level sensitive.
10 - Interrupt 3 is rising-edge sensitive.
11 - Interrupt 3 is falling-edge sensitive.
5-4 Interrupt configuration field for GPIO interrupt 2
ICR2 This bit field controls the active condition of the interrupt function for GPIO interrupt 2.
00 - Interrupt 2 is low-level sensitive.
01 - Interrupt 2 is high-level sensitive.
10 - Interrupt 2 is rising-edge sensitive.
11 - Interrupt 2 is falling-edge sensitive.
3-2 Interrupt configuration field for GPIO interrupt 1
ICR1 This bit field controls the active condition of the interrupt function for GPIO interrupt 1.
00 - Interrupt 1 is low-level sensitive.
01 - Interrupt 1 is high-level sensitive.
10 - Interrupt 1 is rising-edge sensitive.
11 - Interrupt 1 is falling-edge sensitive.
1-0 Interrupt configuration field for GPIO interrupt 0
ICR0 This bit field controls the active condition of the interrupt function for GPIO interrupt 0.
00 - Interrupt 0 is low-level sensitive.
01 - Interrupt 0 is high-level sensitive.
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Field Description
10 - Interrupt 0 is rising-edge sensitive.
11 - Interrupt 0 is falling-edge sensitive.
13.6.6 GPIO interrupt configuration register2 (ICR2)
The ICR2 register contains 16 two-bit fields, where each field specifies the interrupt
configuration for a different input signal.
13.6.6.1 Offset
Register Offset
ICR2 10h
13.6.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ICR31 ICR30 ICR29 ICR28 ICR27 ICR26 ICR25 ICR24
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ICR23 ICR22 ICR21 ICR20 ICR19 ICR18 ICR17 ICR16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.6.3 Fields
Field Description
31-30 Interrupt configuration field for GPIO interrupt 31
ICR31 This bit field controls the active condition of the interrupt function for GPIO interrupt 31.
00 - Interrupt 31 is low-level sensitive.
01 - Interrupt 31 is high-level sensitive.
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Field Description
10 - Interrupt 31 is rising-edge sensitive.
11 - Interrupt 31 is falling-edge sensitive.
29-28 Interrupt configuration field for GPIO interrupt 30
ICR30 This bit field controls the active condition of the interrupt function for GPIO interrupt 30.
00 - Interrupt 30 is low-level sensitive.
01 - Interrupt 30 is high-level sensitive.
10 - Interrupt 30 is rising-edge sensitive.
11 - Interrupt 30 is falling-edge sensitive.
27-26 Interrupt configuration field for GPIO interrupt 29
ICR29 This bit field controls the active condition of the interrupt function for GPIO interrupt 29.
00 - Interrupt 29 is low-level sensitive.
01 - Interrupt 29 is high-level sensitive.
10 - Interrupt 29 is rising-edge sensitive.
11 - Interrupt 29 is falling-edge sensitive.
25-24 Interrupt configuration field for GPIO interrupt 28
ICR28 This bit field controls the active condition of the interrupt function for GPIO interrupt 28.
00 - Interrupt 28 is low-level sensitive.
01 - Interrupt 28 is high-level sensitive.
10 - Interrupt 28 is rising-edge sensitive.
11 - Interrupt 28 is falling-edge sensitive.
23-22 Interrupt configuration field for GPIO interrupt 27
ICR27 This bit field controls the active condition of the interrupt function for GPIO interrupt 27.
00 - Interrupt 27 is low-level sensitive.
01 - Interrupt 27 is high-level sensitive.
10 - Interrupt 27 is rising-edge sensitive.
11 - Interrupt 27 is falling-edge sensitive.
21-20 Interrupt configuration field for GPIO interrupt 26
ICR26 This bit field controls the active condition of the interrupt function for GPIO interrupt 26.
00 - Interrupt 26 is low-level sensitive.
01 - Interrupt 26 is high-level sensitive.
10 - Interrupt 26 is rising-edge sensitive.
11 - Interrupt 26 is falling-edge sensitive.
19-18 Interrupt configuration field for GPIO interrupt 25
ICR25 This bit field controls the active condition of the interrupt function for GPIO interrupt 25.
00 - Interrupt 25 is low-level sensitive.
01 - Interrupt 25 is high-level sensitive.
10 - Interrupt 25 is rising-edge sensitive.
11 - Interrupt 25 is falling-edge sensitive.
17-16 Interrupt configuration field for GPIO interrupt 24
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GPIO register descriptions
Field Description
ICR24 This bit field controls the active condition of the interrupt function for GPIO interrupt 24.
00 - Interrupt 24 is low-level sensitive.
01 - Interrupt 24 is high-level sensitive.
10 - Interrupt 24 is rising-edge sensitive.
11 - Interrupt 24 is falling-edge sensitive.
15-14 Interrupt configuration field for GPIO interrupt 23
ICR23 This bit field controls the active condition of the interrupt function for GPIO interrupt 23.
00 - Interrupt 23 is low-level sensitive.
01 - Interrupt 23 is high-level sensitive.
10 - Interrupt 23 is rising-edge sensitive.
11 - Interrupt 23 is falling-edge sensitive.
13-12 Interrupt configuration field for GPIO interrupt 22
ICR22 This bit field controls the active condition of the interrupt function for GPIO interrupt 22.
00 - Interrupt 22 is low-level sensitive.
01 - Interrupt 22 is high-level sensitive.
10 - Interrupt 22 is rising-edge sensitive.
11 - Interrupt 22 is falling-edge sensitive.
11-10 Interrupt configuration field for GPIO interrupt 21
ICR21 This bit field controls the active condition of the interrupt function for GPIO interrupt 21.
00 - Interrupt 21 is low-level sensitive.
01 - Interrupt 21 is high-level sensitive.
10 - Interrupt 21 is rising-edge sensitive.
11 - Interrupt 21 is falling-edge sensitive.
9-8 Interrupt configuration field for GPIO interrupt 20
ICR20 This bit field controls the active condition of the interrupt function for GPIO interrupt 20.
00 - Interrupt 20 is low-level sensitive.
01 - Interrupt 20 is high-level sensitive.
10 - Interrupt 20 is rising-edge sensitive.
11 - Interrupt 20 is falling-edge sensitive.
7-6 Interrupt configuration field for GPIO interrupt 19
ICR19 This bit field controls the active condition of the interrupt function for GPIO interrupt 19.
00 - Interrupt 19 is low-level sensitive.
01 - Interrupt 19 is high-level sensitive.
10 - Interrupt 19 is rising-edge sensitive.
11 - Interrupt 19 is falling-edge sensitive.
5-4 Interrupt configuration field for GPIO interrupt 18
ICR18 This bit field controls the active condition of the interrupt function for GPIO interrupt 18.
00 - Interrupt 18 is low-level sensitive.
01 - Interrupt 18 is high-level sensitive.
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Field Description
10 - Interrupt 18 is rising-edge sensitive.
11 - Interrupt 18 is falling-edge sensitive.
3-2 Interrupt configuration field for GPIO interrupt 17
ICR17 This bit field controls the active condition of the interrupt function for GPIO interrupt 17.
00 - Interrupt 17 is low-level sensitive.
01 - Interrupt 17 is high-level sensitive.
10 - Interrupt 17 is rising-edge sensitive.
11 - Interrupt 17 is falling-edge sensitive.
1-0 Interrupt configuration field for GPIO interrupt 16
ICR16 This bit field controls the active condition of the interrupt function for GPIO interrupt 16.
00 - Interrupt 16 is low-level sensitive.
01 - Interrupt 16 is high-level sensitive.
10 - Interrupt 16 is rising-edge sensitive.
11 - Interrupt 16 is falling-edge sensitive.
13.6.7 GPIO interrupt mask register (IMR)
The IMR register contains masking bits for each interrupt line.
13.6.7.1 Offset
Register Offset
IMR 14h
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13.6.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IMR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IMR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.7.3 Fields
Field Description
31-0 Interrupt Mask bits
IMR This register is used to enable or disable the interrupt function on each of the 32 GPIO signals.
Bit IMR[n] (n=0...31) controls interrupt n as follows:
0b - Interrupt n is disabled.
1b - Interrupt n is enabled.
13.6.8 GPIO interrupt status register (ISR)
The ISR register functions as an interrupt status indicator. Each bit indicates whether an
interrupt condition has been met for the corresponding input signal. When an interrupt
condition is met (as determined by the corresponding interrupt condition register field),
the corresponding bit in this register is set. Two wait states are required in read access for
synchronization. One wait state is required for reset.
13.6.8.1 Offset
Register Offset
ISR 18h
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13.6.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ISR
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.8.3 Fields
Field Description
31-0 Interrupt status bits
ISR Bit n of this register is asserted (active high) when the active condition (as determined by the
corresponding ICR bit) is detected on the GPIO input and is waiting for service. The value of this register
is independent of the value in IMR register.
When the active condition has been detected, the corresponding bit remains set until cleared by software.
Status flags are cleared by writing a 1 to the corresponding bit position.
13.6.9 GPIO edge select register (EDGE_SEL)
The EDGE_SEL register may be used to override the ICR registers' configuration. If the
GPIO_EDGE_SEL bit is set, then a rising edge or falling edge in the corresponding
signal generates an interrupt. This register provides backward compatibility. On reset all
bits are cleared (ICR is not overridden).
13.6.9.1 Offset
Register Offset
EDGE_SEL 1Ch
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GPIO register descriptions
13.6.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GPIO_EDGE_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPIO_EDGE_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.9.3 Fields
Field Description
31-0 Edge select
GPIO_EDGE_S When EDGE_SEL[n] is set, the GPIO disregards the ICR[n] setting, and detects any edge on the
EL corresponding input signal.
13.6.10 GPIO data register SET (DR_SET)
The SET register of DR.
13.6.10.1 Offset
Register Offset
DR_SET 84h
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13.6.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W DR_SET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W DR_SET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.10.3 Fields
Field Description
31-0 Set
DR_SET Writing a 1 to a bit in this register sets the corresponding bit in DR
13.6.11 GPIO data register CLEAR (DR_CLEAR)
The CLEAR register of DR.
13.6.11.1 Offset
Register Offset
DR_CLEAR 88h
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GPIO register descriptions
13.6.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W DR_CLEAR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W DR_CLEAR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.11.3 Fields
Field Description
31-0 Clear
DR_CLEAR Writing a 1 to a bit in this register clears the corresponding bit in DR
13.6.12 GPIO data register TOGGLE (DR_TOGGLE)
The TOGGLE register of DR.
13.6.12.1 Offset
Register Offset
DR_TOGGLE 8Ch
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13.6.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W DR_TOGGLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W DR_TOGGLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13.6.12.3 Fields
Field Description
31-0 Toggle
DR_TOGGLE Writing a 1 to a bit in this register toggles the corresponding bit in DR
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Chapter 14
Clock and Power Management
14.1 Introduction
This chip targets many applications with power requirements that include low power
consumption, long battery life, always-on capability, instant-on capability, and doesn't
require active cooling. To meet these requirements, the chip design focuses on reducing
current consumption, while simultaneously enabling the maximum level of peak
performance, and also a balanced level of sustained performance. The chip architecture
uses a wide range of power-management techniques, used in combination, for system
design flexibility.
This chapter describes these architecture details as a high-level clock and power
management overview of the chip. This overview chapter covers:
• Structural components of the power and clock management systems
• Clock generation and distribution system
• Power generation and distribution system
• Power mode definition
• Power and clock and management techniques supported.
NOTE
All numerical values in this chapter are either typical values or
used as an example. Please see the datasheet for accurate
values.
14.2 Components of Clock and Power Management
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Power Management
The centralized clock generation, power generation and distribution are implemented by
the following blocks:
Table 14-1. Clock and Power Components
IP Module Description
Crystal OSC (XTALOSC) The XTALOSC includes a 24 MHz and 32 kHz oscillators. The 24MHz crystal
oscillator is the primary clock source for all the PLLs, and clock generation for
the CPU and high-speed interfaces. The 32KHz crystal oscillator is the primary
clock source for the RTC as well as the low-speed clock source for CCM/SRC/
GPC. See the Crystal Oscillator (XTALOSC) chapter for details of the XTALOSC
block.
PLLs and PFDs The PLLs and their associated PFDs generate the clocks with various
frequencies required to feed the CCM clock generator that supplies the different
functional blocks. See the PLL and PFD section in Clock Controller Module
(CCM) for information on the PLL and PFD architecture, functional description
and programming model.
Clock Control Module (CCM) The CCM module provides control for clock generation, division, distribution,
synchronization, and coarse-level gating. See Clock Controller Module (CCM) for
information on the CCM architecture, functional description and programming
model.
Low Power Clock Gating (LPCG) The LPCG distributes the clocks to all blocks in the SoC and handles automated
clock gating and block level software-controllable clock gating. See Clock
Controller Module (CCM) for information on the LPCG architecture and functional
description.
General Power Controller (GPC) This module controls the power state of the SoC. The GPC handles the power
gating under low power modes and also manages the power up / power down
sequences. See the General Power Controller (GPC) chapter for information on
the GPC architecture, functional description and programming model.
Power Management Unit (PMU) This module generates the internal power supplies distributed to the entire SoC.
See the Power Management Unit (PMU) chapter for information on the PMU
architecture, functional description, and programming model.
System Reset Controller (SRC) This module generates the reset signals to all the modules in the SoC. The SRC
will appropriately assert reset signals for power transitions, entry, and exit. See
the System Reset Controller (SRC) chapter for information on the SRC
architecture, functional description and programming model.
Power Gating and Memory Controller This module is a power management component, which controls the power
(PGMC) gating of power domains and memory low power mode. See Power Gating and
Memory Controller (PGMC) chapter for information on PGMC architecture,
functional description, and programming model.
DCDC Converter (DCDC) This module generates the power supply for chip's core logic. See DCDC
converter (DCDC) chapter for information on functional description, and
programming model.
Together, the modules listed above provide enhanced power-management features with
the centralized control for the clock, reset, and power-management signals on the SoC.
14.3 Power Management
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Chapter 14 Clock and Power Management
The power management design on the chip satisfies many use cases that depend on a key
balance of performance and low-power consumption. In order to meet these criteria, the
system power management needs to be dynamic and flexible. This is accomplished on a
multi-core system by utilizing a power scheme that considers each CPU domain, and
arbitrates the appropriate power mode configuration to satisfy the needs of both CPUs,
and the system as a whole. The following are additional features supported by the power
management architecture:
• Programmable power mode transition rules
• Independent operation mode for individual CPU cores
• Intelligent clock and power management for multi-core architecture
• Unified power management interface (UPI) for all on-chip resources, including
clock, power, reset, and peripherals
A high-level view of the power management controllers and connections is shown below:
CM7 CM4
IRQ / wakeup
IRQ / wakeup
WFI / sleep
WFI / sleep
CMC0 CMC1
save / restore
SSARC
GPC
RDC domain
UPI
save request
assignment
OSC enable
OSC / PLL lock
save / restore
STOP Mode LP Mode reset req / done
PLL
lock
OSC/PLL PLL
CCM clock gate
SRC PMU DCDC PGMC
enable
clocks system power
resets gating iso
lpcg
LPSR power
(ANA, DIG)
LPSR WAKEUP DISPLAY MEGA SNVS
DMA Memory Audio Coin
Display Peripherals SNVS_LP
SNVS_HP
Analog Peripherals
Cell
ENET, USB,
DEBUG DMA SD
Timers Bus Bus Bus
Low-Speed
Comms
Functional Blocks
Figure 14-1. Power Management Block Diagram
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Power Management
14.3.1 Resources and Chip Domains
The chip is divided into resources and domains. Resources are controlled by resource
controllers. Domains are grouped by central bus controllers and crossbars. Some domains
reside within larger domains, which may have power dependencies. For illustrative
representation of the power domains and bus configurations, please see the Power
Management Block Diagram and the System Bus Diagram. The Resource types and Chip
Domains are listed in the tables below:
Table 14-2. Resources
Resource Description
CPU Platforms The processor and associated on-platform peripherals that support the complex. The
CPU Platforms supported on this chip are the CM7 and the CM4 platforms.
System Controllers The System Controllers are the associated peripherals that control or define the power
management resources for the chip. These modules include GPC, PMU, CCM, SRC,
SSARC, PGMC, and RDC.
Functional blocks The functional blocks are comprised of all the other peripherals, other than System
Controllers. These modules include external memory controllers, timers, high-speed
and low-speed peripherals, audio and video peripherals, connectivity, and others.
Table 14-3. Chip Domains
Domain Description
CM7 The Cortex-M7 core and platform, which includes FlexRAM (TCM) and GPIO2-3.
CM4 The Cortex-M4 core and platform, which includes LMEM (TCM).
WAKEUP The WAKEUP Domain contains the memory controllers and analog on the chip. The
CM7 platform (incl JTAGC and debug components) also reside within WAKEUP, but
the CM7 functions as it's own domain. The specific modules in WAKEUP include:
EWM, WDOG1-3, eDMA, DMAMUX0 (WAKEUP), ACMP1-4, LPADC1-2, ADC_ETC,
DAC, XBAR1-3, KPP, IOMUXC, IOMUXC_GPR, GPIO1-6, LPUART1-10, MTR,
FLEXCAN1-2 (CANFD), QDC1-4, PIT1, AOI1-2, GPT1-6, TMR1-4, FlexPWM1-4,
LPI2C1-4, LPSPI1-4, FlexIO1-2, EMVSIM1-2, FlexSP1-2, SEMC, MECC1-2, XECC
(XECC_FLEXSPI1-2, XECC_SEMC), IEE.
MEGA Contains the connectivity peripherals and audio peripherals. The specific modules
include: ENET1G, ENET, ENET QoS, uSDHC, USB, CAAM, ASRC, MQS, SAI1-3,
SPDIF.
DISPLAY The DISPLAY Domain contains the display and graphics peripherals on the chip. The
specific modules include: GPU2D, PXP, eLCDIF, LCDIFv2, CSI, MIPI_CSI2, MIPI_DSI,
VIDEO_MUX (incl DCIC1,2)
LPSR The LPSR Domain contains the System Control blocks and associated peripherals.
The CM4 platform and portions of SNVS (SNVS_LP) also reside within LPSR, but
function as their own domains. The specific modules of LPSR include: GPC, PGMC,
DCDC, SRC, SSARC, PMU (ANADIG), TEMPSENSE, XTALOSC, CCM, OCOTP,
SNVS_HP, KEYMGR, WDOG (CM4), IOMUXC_SNVS, IOMUXC_LPSR, MU, xRDC2
(CM4, CM7), RDC1-2, SEMA4, SEMA42, eDMA, DMAMUX1 (LPSR), GPIO7-12, PDM,
SAI4, PIT2, LPUART11-12, LPSPI5-6, LPI2C5-6, FLEXCAN3 (CANFD)
Table continues on the next page...
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Chapter 14 Clock and Power Management
Table 14-3. Chip Domains (continued)
Domain Description
SNVS The SNVS Domain contains SNVS_LP, which connects to a coin cell or non-
interruptible power source. This domain also contains IOMUXC_SNVS, SRAM, and
GPIO13.
14.3.2 Power Management Unit (PMU)
The PMU has the following components integrated for power management:
• DCDC
• Generates the core power supply
• Supports dynamic voltage scaling
• LDOs
• Internal logic power supply
• Power Switches for sophisticated power mode management
The typical power architecture of the chip is shown below. The use case illustrated shows
the whole system working with a single 3.3V power supply and a coin cell. This is the
power system configuration of traditional MCU. Depending on the application, other
power supply schemes may be used, including bypassing the DCDC converter and using
an external voltage regulator or PMIC.
NOTE
The on-chip DCDC converter is suitable for consumer and
industrial applications up to the rated temperature specified in
their respective market datasheets. For automotive applications,
please check the automotive datasheet or consult with your
NXP representative for appropriate power supply requirements.
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Power Management
3.3V
DCDC_IN
DCDC_ANA
DCDC
DCDC_DIG
VDDA_1P8_IN
VDDA_SOC_IN
SOC Domain LPSR Domain
VDD_LPSR_IN
Cortex-M7 LDO_LPSR_ANA
32KB I$ 32KB D$ VDD_LPSR_ANA
512KB TCM
USB, Ethernet, LDO_LPSR_DIG
SD/eMMC, Audio VDD_LPSR_DIG
LCD, CSI, Temperature
PXP, GC355 Sensor
SOC (AlwaysON) RC OSCs
Cortex-M4
LDO_PLL PLLs 16KB D$ 16KB I$
VDDA_1P0 256KB TCM
eFuse
VDDA_MIPI_1P8
VDDA_MIPI_1P0 MIPI PHY LPSR
Peripherals
VDDA_USB_1P8
VDDA_USB_3P3 USB PHY x2
GPIO PADs NVCC_LPSR
VDDA_ADC_3P3 ADC x2
VDDA_ADC_1P8
DAC SNVS Domain VDD_SNVS_IN Coin
LDO_SNVS_ANA
VDD_SNVS_ANA
Cell
ACMP x4
NVCC_EMC1 GPIO PADs 4KB RAM LDO_SNVS_DIG
NVCC_EMC2 VDD_SNVS_DIG
GPIO PADs
NVCC_GPIO GPIO PADs DryICE
NVCC_DISP1 GPIO PADs 32KHz XTAL
NVCC_DISP2 GPIO PADs 32KHz RC OSC
NVCC_SD1 GPIO PADs SNVS LP
NVCC_SD2 GPIO PADs GPIO PADs NVCC_SNVS
Figure 14-2. Power Architecture
14.3.3 Body Biasing (BB)
Forward Body Biasing (FBB) and Reverse Body Biasing (RBB) are implemented for
performance boost and power reduction. The list and figure below define the power
domains that support BB.
• FBB is implemented in the CM7 platform in order to achieve higher performance.
• RBB is implemented in the LPSR domain to reduce power consumption in LPSR
mode.
• RBB is implemented in the SoC to reduce power consumption in low-power modes.
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Chapter 14 Clock and Power Management
wbias pwr
Charge Pump
switch CM7 FBB
wbias pwr
switch
OR LPSR RBB
wbias pwr
switch SOC RBB
Figure 14-3. Supported Body Biasing
NOTE
Software must ensure that FBB and RBB are not enabled
simultaneously. Only one of them can be used at a time.
14.3.4 Power Modes
The chip resources abide by CPU or system-level power modes, depending on their
resource assignment. Resources are assigned to one of four categories, which are defined
below.
Table 14-4. Resources Categories
Category Description
Private A resource that are fully owned and controlled by one CPU platform. These resources
can be controlled by hardware and software.
Shared A resource that is shared by more than one CPU platform. These resources are limited
by the other CPU power state. Software must take into regard, shared resources, since
they are limited by other CPU power states. If a shared resource supports Setpoint
control, then it is recommended that the resource is under Setpoint control, rather than
CPU platform control.
Public A resource that is managed at the system-level, which is not owned and controlled by
any of the CPU platforms. These resources can only be controlled by hardware.
Unassigned A resource that is not assigned as private, shared, or public. This is the default state of
a resource after reset.
Resources can be assigned to different CPU domains by the RDC. If one CPU wants to
put the chip into a power mode, it must arbitrate with the other CPU to ensure the
appropriate power state is chosen for shared resources. Depending on the resource type,
varying power control mechanisms are followed. Private and Shared resources follow the
power modes defined by the CPU (CPU mode). Public resources are configured by
system-level settings (Setpoint mode).
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Power Management
RDC
REQ Domain_0 power mode
CM7 CMC0 CPU0
power mode
REQ CPU1
Domain_1 power mode
CM4 CMC1 power mode
Domain_3 power mode
Domain_4 power mode
Figure 14-4. Domain Assignment
14.3.4.1 CPU Mode
The CPU platforms both support the same power states that are defined as CPU modes.
The CPU Modes are detailed below.
Table 14-5. CPU Mode
CPU Mode Description
RUN The CPU is active and running.
WAIT The CPU is in the WFI state. The CPU core and L1 cache are clock gated, TCM and
peripheral can still be alive. The chip can wakeup from this mode from IRQ with a very
short latency.
STOP The CPU is in the WFI state. The CPU core, L1 cache, TCM, and it's private
peripherals are all clock gated. The chip requires a longer time to wakeup from this
mode.
SUSPEND The CPU core and L1 cache are power gated (except the M4 cache). The TCM is in
retention mode. SUSPEND mode consumes the least amount of power, while keeping
parts of the the system alive. But the chip requires a much longer time to wakeup from
this mode.
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Chapter 14 Clock and Power Management
SL
P
EU
EE
AK
P
W
RUN
SL
P
E
EE
WA
LE
P
S
KE
EU
SLEEP
WAKEUP
UP
AK
W
WAIT SUSPEND
STOP
Figure 14-5. CPU Modes
For the modules / resources outside (public) of the CPU platform domain, the power is
managed by Setpoint mode. There are up to 16 Setpoints supported. In each Setpoint, the
state of the modules is configurable. The power mode of the chip is a combination of the
Setpoint and CPU mode. Please refer to the specific System Controller blocks / modules
for more information on their specific configuration options for Setpoint mode.
14.3.4.1.1 Memory Power Connection
A few of the power connections that exist in this chip are shown below:
• M7 Cache and TCM memory:
• M7 core and memory peripheral logics are on the same power domain, which are
on/off together
• When operating, memory array is supplied from VDD_SOC_IN
• Supported modes
• M7 on, cache and TCM on
• M7 off, cache off, TCM off
• No access to TCM memory when M7 core is power gated
• M4 Cache & TCM memory:
• Supported modes
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Power Management
• M4 on, cache and TCM on
• M4 off, cache and TCM on
• M4 off, cache on, TCM off
• OCRAM memories:
• Controller and memory peripheral logics are on the same power domain, which
are always on when VDD_SOC_IN is there
• It will only be off when then entire SOC domain is off
14.3.4.2 Setpoint Mode
Setpoints are preconfigured power states (up to 16) that are defined within the System
Controller resources. Resources that aren't owned by either CPU, follow Setpoint mode
to define the system-level settings for clocking, power, BB, and reset. Please see the
respective System Controller chapters for more details on the specifc controls supported
by Setpoint mode.
Resources
Private 0 Shared Private 1 Public
SP change SP change
CPU0 CPU ACK REQ (WFI, IRQ)
CPU CPU1
mode
Setpoint mode
(CM7) SP change SP change (CM4)
REQ (WFI, IRQ) ACK
Figure 14-6. Setpoint Mode
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Chapter 14 Clock and Power Management
14.3.4.2.1 Setpoint Arbitration
The power mode of the CPU platforms is independent of the other. But the shared
resources must have a target Setpoint and a lookup table of allowed Setpoints for each
CPU mode transition. The GPC will arbitrate between the target Setpoint, and allowed
Setpoints, in order to determine the appropriate and accepted Setpoint setting. The lookup
tables in GPC are a 16x16 bit table, that work for one domain. If more than one Setpoint
is allowed, control logic first checks if any Setpoints match the request from CM7 or
CM4. If both match, the selection is done, and based on priority of CPUs. If none match,
logic will compare priority of Setpoints, and select the high-priority Setpoint. If the
priority is the same, Setpoint in the biggest value will be selected.
14.3.4.3 Standby Mode
Standby mode is the third low-power mode, besides CPU mode and Setpoint mode.
Standby mode is related to the state of both CPU platforms, and has a much shorter
transition time than Setpoint. The GPC SBC state machine starts when CMC sends a
standby request. It looks at all CMC standby statuses, and if any CPU platform is not in
sleep mode, this standby request will be refused. CPU mode and Setpoint transition can't
be broken by a wakeup event once it starts. A key benefit of Standby mode, is the
Standby transition can be broken after any step completes, due to a wakeup requirement.
14.3.5 Power Sequence
The software flow for low-power entry and exit are listed below.
NOTE
The power flow assumes all resource assignments are complete
after reset
1. CPU decides to enter any low power mode according its current loading
2. Software handshaking: set ipg_stop/doze in IOMUXC_GPR register; polling
corresponding ips_stop_ack
• Note: DMA/ENET (bus masters) should complete the handshake first, then
flash/memories (bus slaves)
3. Set CPU target mode and system target/allowed setpoint in GPC registers
4. WFI/WFE
• CPU mode transition stage: SSARC restore database; clock/power of CPU
private resources are shut off
• Setpoint transition stage: clock/power of public resource are shut off
• System enter target low power state and waiting for wakeup event
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5. Wakeup event comes
• Setpoint transition stage: power recover, then clock recover for public resources
• CPU transition stage: power recover, then clock recover for CPU private
resources; SSARC recover database
• CPU wakeup when core clock is recovered
6. CPU enter wakeup event ISR and recover the field before entering low power state
Please see GPC for a detailed sequence.
14.4 Clock Generation
The clock system is designed to provide a scalable, powerful, and easy-to-use clock
solution.
14.4.1 Overview
The overall clock system for the chip is shown in the diagram below.
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Chapter 14 Clock and Power Management
CCM LPCG
Clock Root Generation LPCG
Blocks
Module Clocks
clock slices Clock Roots
cg
mux
cg div cg
:
cg
24 MHz RC OSC cg
400M, 48M, 16M, 32k
Clock Source from
cg
PLL/PFD/Divider cg
PLLs cg
mux
cg div cg
32 kHz :
to on-chip
PFDs peripherals
PLL/PFD Enable
PLL / PFD
Pre-Dividers
Control
PLL Lock
OSC / PLL Lock
Clock Gating Control
OSC Enable
STOP Mode
Low Power Mode Clock Enable
Clock Gate
GPC SRC
reset req
LP Mode Control reset done Reset Control
Figure 14-7. Clock System
The OSCs, PLLs, PFDs and Pre-Dividers generate the clock sources with fixed or
variable frequency. The clock sources feed the clock root generation logic inside CCM,
which generates numerous clock roots required for core, bus, and peripheral blocks.
These clock roots are branched to each module through the LPCG logic, which contains
the clock gating cells for each clock. Control signals for the LPCGs are in CCM (clock
enable signal). Some of the clocks need to be gated off during reset, because of this, the
SRC module will also send clock gate signals to the LPCG.
In low power mode, GPC will drive the low power mode state signal to CCM, then CCM
will enable clock gating based on the configuration. At the same time, CCM may also
deassert enable signals for PLLs and PFDs, so these modules can power off during low
power modes. When the chip enters STOP mode, CCM may deassert the OSC enable
signal to shut off the OSC, it may also assert the STOP mode signal to set OSC to low
power mode.
The detailed functional description for each block will be described in the following
sections.
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Clock Generation
14.4.2 Oscillator
This chip has two crystal oscillators and four RC oscillators:
Table 14-6. Oscillators
Oscillator Description
24 MHz Crystal Oscillator (24M The primary clock source for all PLLs to generate the clocks for CPU, bus, and
XTALOSC) high-speed interfaces
32 kHz Crystal Oscillator (32K XTALOSC) The primary clock source for RTC as well as low-power clock source for CCM,
SRC, and GPC. The typical frequency is 32.768KHz.
48 MHz RC Oscillator (48M RCOSC) Generates the 24 MHz clock source for the chip during startup, before the
24MHz crystal oscillator is ready. The 48M RCOSC can also be used as an
alternative 24 MHz clock source in low power mode, when the crystal oscillator is
turned off, or in a system that doesn't have a crystal oscillator.
32 kHz RC Oscillator (32K RCOSC) The 32 kHz clock source for the chip during startup when 32 kHz crystal is not
ready. It can also be used as alternative 32 kHz clock source when the external
32 kHz crystal oscillator is not stable, or in system which does not have any
crystal oscillator. The switch from external 32 kHz to internal 32 kHz RC is
controlled by hardware, and it happens automatically when the system detects a
loss of the 32 kHz crystal clock.
16 MHz RC Oscillator (16M RCOSC) The clock source in low power mode.
400 MHz RC Oscillator (400M RCOSC) The clock source during chip boot up, before PLLs are enabled, or in low-power
mode when the PLLs are turned off.
See Crystal Oscillator (XTALOSC) chapter for functional description details and the
programming model on these blocks.
14.4.3 PLL and PFD
The PLLs are used in the chip to generate the high speed clocks required by the modules
in SoC. A few PLLs are equipped with Phase Fractional Dividers (PFDs) in order to
generate additional frequencies. The following PLLs are used in this chip:
Table 14-7. PLLs
PLL Description Spread Spectrum Configurable
ARM_PLL The ARM_PLL is used to generate the clock for - Yes
the Arm Cortex-M7 platform. It is a
programmable integer-frequency multiplier PLL,
capable of an output frequency over 1 GHz.
SYS_PLL1 An AVPLL that is used primarily by the ENET Yes 1 GHz
module. It has a dedicated frequency of 1GHz.
Table continues on the next page...
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Chapter 14 Clock and Power Management
Table 14-7. PLLs (continued)
PLL Description Spread Spectrum Configurable
SYS_PLL2 The SYS_PLL2 main output clock has a Yes 528 MHz
dedicated frequency of 528MHz, but has several
configurable PFDs.
SYS_PLL3 The SYS_PLL3 main output clock has a - 480 MHz
dedicated frequency of 480MHz, but has several
configurable PFDs.
AUDIO_PLL An AVPLL used to generate reference clocks, Yes Yes
mainly for serial audio interfaces, and external
audio codecs. This fractional multiplier PLL
provides a low-jitter and high precision audio
clock with standardized audio frequencies. The
PLL's oscillator frequency range is from 650MHz
to 1300MHz, and the frequency resolution is
better than 1Hz.
VIDEO_PLL An AVPLL used to generate reference clocks, Yes Yes
mainly for display and video interfaces. This
fractional multiplier PLL provides a low-jitter and
high-precision video clock at standardized video
frequencies. The PLL's oscillator frequency
range is from 650MHz to 1300MHz, and the
frequency resolution is better than 1Hz.
NOTE
Please see the datasheet for all supported maximum PLL
frequencies
The following PLLs also feature the following dedicated dividers, which provides fixed
frequencies for system usage:
• SYS_PLL1_DIV2: dedicated 500MHz clock
• SYS_PLL1_DIV5: dedicated 200MHz clock
• SYS_PLL3_DIV2: dedicated 240MHz clock
Each PLL can use one of the following clock sources as it's reference clock:
• Primary Option: 24 MHz clock from 24 MHz oscillator (XTAL)
• Secondary Option: 24 MHz clock from 48 MHz RCOSC (divided by 2)
Only the AUDIO_PLL and VIDEO_PLL have the capability to spread spectrum the
generated signal. They do not require exact/constant frequency, and can be changed as a
part of dynamic frequency scaling procedure and/or can be spread-spectrum modulated.
The main output clocks for the System PLLs (SYS_PLLx_CLK) are not configurable,
but their PFDs are. Each PFD works independently by interpolating the VCO of the PLL
to which it is connected. It effectively takes the PLL VCO frequency and produces 18/N
x Fvco at it's output where N ranges from 12 to 35. PFD is a completely digital design
with no analog components or feedback loops. The frequency switch time is much faster
than a PLL because keeping the base PLL locked and changing the integer N only
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Clock Generation
changes the logical combination of the interpolated outputs of the VCO. Note that the
PFD not only enables faster frequency changes than a PLL, but also allows the
configuration to be safely changed "on-the-fly" without going through the output clock
disabling/enabling process.
The basic logical connections for the PLLs, PFDs and Dividers is shown in the diagram
below:
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Chapter 14 Clock and Power Management
PLL_CTRL[ENABLE_CLK]
PLL_CTRL[BYPASS]
PLL_CTRL[POWERUP]
PLL core DIV
configurable
ARM_PLL
ARM_PLL_CTRL[POST_DIV_SEL]
ARM_PLL
24M
PLL_CTRL[ENABLE_CLK]
XTALOSC PLL_CTRL[BYPASS]
PLL_CTRL[POWERUP]
PLL core 1 GHz
SYS_PLL1_CLK
SYS_PLL1 DIV2 500 MHz
SYS_PLL1_DIV2
DIV5 200 MHz
SYS_PLL1_DIV5
PLL_CTRL[ENABLE_CLK]
PLL_CTRL[BYPASS]
PLL_CTRL[POWERUP]
PLL core 528 MHz
SYS_PLL2_CLK
SYS_PLL2[PFD0_FRAC]
configurable
SYS_PLL2 PFD0 SYS_PLL2_PFD0
SYS_PLL2[PFD1_FRAC]
configurable
PFD1 SYS_PLL2_PFD1
SYS_PLL2[PFD2_FRAC]
configurable
PFD2 SYS_PLL2_PFD2
SYS_PLL2[PFD3_FRAC]
PLL_CTRL[ENABLE_CLK] configurable
PLL_CTRL[BYPASS] PFD3 SYS_PLL2_PFD3
PLL_CTRL[POWERUP]
PLL core 480 MHz
SYS_PLL3_CLK
SYS_PLL3[PFD0_FRAC]
configurable
SYS_PLL3 PFD0 SYS_PLL3_PFD0
SYS_PLL3[PFD1_FRAC]
configurable
PFD1 SYS_PLL3_PFD1
SYS_PLL3[PFD2_FRAC]
configurable
PFD2 SYS_PLL3_PFD2
SYS_PLL3[PFD3_FRAC]
configurable
PFD3 SYS_PLL3_PFD3
PLL_CTRL[ENABLE_CLK]
PLL_CTRL[BYPASS] 240 MHz
PLL_CTRL[POWERUP] DIV2 SYS_PLL3_DIV2
PLL core configurable
AUDIO_PLL
AUDIO_PLL
PLL_CTRL[ENABLE_CLK]
PLL_CTRL[BYPASS]
PLL_CTRL[POWERUP]
PLL core configurable
VIDEO_PLL
VIDEO_PLL
LEGEND
XTALOSC PFD Phase Fractional Divider DIV Post Divider
RCOSC PLL AVPLL DIV Fixed Divider
Figure 14-8. PLL and PFD
PLL configuration and control functions are accessible via individual PLL and PFD
configuration and status registers. Each PLL has a dedicated configuration register.
Software can directly enable / disable the PLL, or change it's clock frequency. In addition
to the register interface, each PLL also has a dedicated ENABLE input, and a LOCK
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Clock Generation
output, to support the PLL disable / enable control from CCM. The CCM block contains
the detailed descriptions of the memory mapped registers, and control functions of the
clock generation sub-module. Please see CCM for more information.
14.4.4 Clock Root Generation
Clock generation in the CCM creates clock roots for on-chip peripherals. Each clock root
will have a dedicated clock slice. It takes the clock source from Oscillators, PLL/PFD or
Pre-Dividers, and generate the clock root with required frequency.
The CCM can manage on-chip peripheral clocks by controlling the low power clock
gating cells (LPCGs) before the clock roots enter the peripherals.
Clock Source from Clock Root 0
Clock Slice0
PLL/PFD/Divider
Clock Root 1
Clock Slice1
...
Clock Root N
Clock SliceN
Figure 14-9. Clock Root Generation from Clock Slice
The LPCGs are implemented to control peripheral functions, and there could be several
LPCGs for each functions in a peripheral.
For details on the programming model, please refer to CCM Memory Map/Register
Definition.
14.4.5 Low Power Clock Gating (LPCG)
The clock roots generated inside CCM are distributed to the entire SoC through LPCG.
The LPCG block receives the root clocks from CCM and splits them to clock branches
for each functional block. The clock branches are individually gated clocks.
The LPCG can be programmed directly or controlled by CPU Low-Power Mode
(CPULPM) according to the low-power signal from GPC. The settings for LPCG in
CPULPM are defined by a 3-bit clock dependent level setting in the LPCGx_DOMAIN
register. The configuration of the LPCGx_DOMAIN[LEVELn] settings are as follows:
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Chapter 14 Clock and Power Management
• 3b’000: The clock source is not needed in any mode, and can be turned off
• 3’b001: The clock source is needed in RUN mode, but not needed in WAIT or STOP
mode
• 3’b010: The clock source is needed in RUN and WAIT mode, but not needed in
STOP mode
• 3’b011: The clock source is needed in RUN, WAIT, and STOP mode
• 3’b100: The clock source is always on in any mode (including SUSPEND)
• Others: Reserved
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Clock Generation
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1448 NXP Semiconductors
Chapter 15
Clock Controller Module (CCM)
15.1 Chip-specific CCM information
Table 15-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
NOTE
• SYS_PLL1 has a fixed frequency of 1GHz and is primarily
used by the ENET modules
• SYS_PLL2 has a fixed frequency of 528MHz
• SYS_PLL3 has a fixed frequency of 480MHz
15.2 Overview
The Clock Control Module (CCM) manages the on-chip module clocks. The oscillators,
PLLs, and Phase Fractional Dividers (PFD) will generate clock sources with fixed or
variable frequencies.
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Overview
15.2.1 Block diagram
CCM LPCG
Clock Root Generation
LPCG
Blocks
clock slices Module Clocks
Clock Roots
cg
mux
: cg div
cg
cg
24 MHz RC OSC cg
400M, 48M, 16M, 32k Clock Source from
PLL/PFD/Divider cg
cg
PLLs cg
mux
: cg div
cg
32 kHz
PFDs to on-chip
peripherals
PLL/PFD Enable
PLL / PFD
Pre-Dividers Control
PLL Lock
Stop Mode
Low Power Mode Clock Gating Control Clock Enable
CCM_CLKO2
CCM_CLKO1
Clock Gate
GPC SRC
Figure 15-1. CCM block diagram
The clock root generation logic inside CCM will generate various clock roots required for
core, bus, and peripheral blocks. These clock roots will be delivered to each module
through LPCG, which contains the clock gating logic for each clock.
The control signal for LPCGs in CCM will be the source for clock enable signals. Since
some of the clocks need to be gated off during the reset, the System Reset Controller
(SRC) will also send clock gate signals to the LPCG.
In low power mode, the General Power Controller (GPC) will drive the low power mode
state signal to CCM, and CCM will enable clock gating based on the configuration. At
the same time, CCM may also de-assert enable signals for PLLs, so these modules can be
powered off during the low power mode.
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Chapter 15 Clock Controller Module (CCM)
15.2.2 Features
The CCM includes the following features:
• Clock Root
• Supports 8 clock sources for each clock root
• 8-bit divider supports up to divide by 256 in each clock root
• Each clock root can be shutdown by software
• 4-bit fractional divide (numerator and denominator)
• 16 preset clock root Setpoints transitions on power mode change
• Clock Group
• Synchronous clock group where each clock can change on-the-fly
• Clock group can be shutdown by software
• 16 preset clock group Setpoint transitions on power mode change
• Peripheral clocks can be auto gated according to CPU platform, software, or system
power mode
• PLLs and oscillators can be auto shutdown according to CPU platform, software, or
system power mode
• Two access control schemes: Trustzone, and Domain
• Each component can be protected independently
• Independent setting for user, privileged, secure, non-secure
• Whitelist that can control Domain Mode access
• Access control setting can be locked independently
15.3 System Clocks
The table found here shows the CCM output clocks' system-level connectivity.
Table 15-2. System Clocks Table
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
ACMPn acmp1_fast_clk ACMP_CLK_ROOT clk_enable_acmp1 (LPCG58)
acmp1_ipg_clk BUS_CLK_ROOT clk_enable_acmp1 (LPCG58)
acmp1_ipg_clk_s BUS_CLK_ROOT clk_enable_acmp1 (LPCG58)
acmp1_slow_clk BUS_CLK_ROOT clk_enable_acmp1 (LPCG58)
acmp2_fast_clk ACMP_CLK_ROOT clk_enable_acmp2 (LPCG59)
acmp2_ipg_clk BUS_CLK_ROOT clk_enable_acmp2 (LPCG59)
acmp2_ipg_clk_s BUS_CLK_ROOT clk_enable_acmp2 (LPCG59)
acmp2_slow_clk BUS_CLK_ROOT clk_enable_acmp2 (LPCG59)
Table continues on the next page...
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System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
acmp3_fast_clk ACMP_CLK_ROOT clk_enable_acmp3 (LPCG60)
acmp3_ipg_clk BUS_CLK_ROOT clk_enable_acmp3 (LPCG60)
acmp3_ipg_clk_s BUS_CLK_ROOT clk_enable_acmp3 (LPCG60)
acmp3_slow_clk BUS_CLK_ROOT clk_enable_acmp3 (LPCG60)
acmp4_fast_clk ACMP_CLK_ROOT clk_enable_acmp4 (LPCG61)
acmp4_ipg_clk BUS_CLK_ROOT clk_enable_acmp4 (LPCG61)
acmp4_ipg_clk_s BUS_CLK_ROOT clk_enable_acmp4 (LPCG61)
acmp4_clk BUS_CLK_ROOT clk_enable_acmp4 (LPCG61)
ADC_ET adc_etc_ipg_clk BUS_CLK_ROOT clk_enable_adc_etc (LPCG48)
C
AIPS aips_tz1_hclk BUS_CLK_ROOT clk_enable_sim_per (LPCG5)
aips_tz1_ipg_clk BUS_CLK_ROOT clk_enable_sim_per (LPCG5)
aips_tz2_hclk BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
aips_tz2_ipg_clk BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
aips_tz3_hclk BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
aips_tz3_ipg_clk BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
aips_tz4_hclk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
aips_tz4_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
AOIn aoi1_ipg_clk BUS_CLK_ROOT clk_enable_aoi1 (LPCG46)
aoi2_ipg_clk BUS_CLK_ROOT clk_enable_aoi2 (LPCG47)
ARM CM4 cm4_imxrt_FCLK M4_CLK_ROOT clk_enable_cm4 (LPCG1)
cm4_imxrt_HCLK M4_CLK_ROOT clk_enable_cm4 (LPCG1)
cm4_imxrt_mmcau_hclk M4_CLK_ROOT clk_enable_cm4 (LPCG1)
cm4_imxrt_tcmc_hclk M4_CLK_ROOT clk_enable_lpsrmem (LPCG27)
cm4_lp_gasket_clk_free_running M4_CLK_ROOT -
nmi_glue_cm4_fclk M4_CLK_ROOT clk_enable_cm4 (LPCG1)
ARM CM7 cm7_imxrt_ccm_cm7_clk_root M7_CLK_ROOT clk_enable_cm7 (LPCG0)
cm7_imxrt_cm7_core_stclk M7_SYSTICK_CLK_ROOT clk_enable_cm7 (LPCG0)
ASRC asrc_asrck_clock_a SAI2_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_asrck_clock_b SAI3_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_asrck_clock_c SAI4_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_asrck_clock_d MIC_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_asrck_clock_e MQS_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_ipg_clk ASRC_CLK_ROOT clk_enable_asrc (LPCG119)
asrc_mem_ipg_clk ASRC_CLK_ROOT clk_enable_asrc (LPCG119)
CAAM caam_aclk BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_exsc_aclk_exsc BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
caam_exsc_ipg_clk BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_ipg_clk BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_ipg_clk_s BUS_CLK_ROOT clk_enable_caam (LPCG40)
Table continues on the next page...
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1452 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
caam_kma_caam_ips_clk BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_mem_caam_clk BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_rng_async_bridge_clock BUS_CLK_ROOT clk_enable_caam (LPCG40)
caam_snvs_ipg_clk BUS_CLK_ROOT clk_enable_caam (LPCG40)
CCM ccm_ipg_clk RCOSC_16M clk_enable_ccm (LPCG10)
ccm_ipg_clk_s RCOSC_16M clk_enable_ccm (LPCG10)
CANn can1_ipg_clk BUS_CLK_ROOT clk_enable_can1 (LPCG83)
can1_ipg_clk_chi BUS_CLK_ROOT clk_enable_can1 (LPCG83)
can1_ipg_clk_pe CAN1_CLK_ROOT or clk_enable_can1 (LPCG83)
BUS_CLK_ROOT
can1_ipg_clk_pe_nogate CAN1_CLK_ROOT or clk_enable_can1 (LPCG83)
BUS_CLK_ROOT
can1_ipg_clk_s BUS_CLK_ROOT clk_enable_can1 (LPCG83)
can1_osc_clk OSC_24M clk_enable_can1 (LPCG83)
can1_ipt_clk OSC_24M clk_enable_can1 (LPCG83)
can2_ipg_clk BUS_CLK_ROOT clk_enable_can2 (LPCG84)
can2_ipg_clk_chi BUS_CLK_ROOT clk_enable_can2 (LPCG84)
can2_ipg_clk_pe CAN2_CLK_ROOT or clk_enable_can2 (LPCG84)
BUS_CLK_ROOT
can2_ipg_clk_pe_nogate CAN2_CLK_ROOT or clk_enable_can2 (LPCG84)
BUS_CLK_ROOT
can2_ipg_clk_s BUS_CLK_ROOT clk_enable_can2 (LPCG84)
can2_osc_clk OSC_24M clk_enable_can2 (LPCG84)
can2_ipt_clk OSC_24M clk_enable_can2 (LPCG84)
can3_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_can3 (LPCG85)
can3_ipg_clk_chi BUS_LPSR_CLK_ROOT clk_enable_can3 (LPCG85)
can3_ipg_clk_pe CAN3_CLK_ROOT or clk_enable_can3 (LPCG85)
BUS_LPSR_CLK_ROOT
can3_ipg_clk_pe_nogate CAN3_CLK_ROOT or clk_enable_can3 (LPCG85)
BUS_LPSR_CLK_ROOT
can3_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_can3 (LPCG85)
can3_osc_clk OSC_24M clk_enable_can3 (LPCG85)
can3_ipt_clk OSC_24M clk_enable_can3 (LPCG85)
CDOG cdog_ahb_clk BUS_LPSR_CLK_ROOT clk_enable_cdog (LPCG116)
CSI csi_csi_hclk BUS_CLK_ROOT clk_enable_csi (LPCG133)
csi_ipg_clk BUS_CLK_ROOT clk_enable_csi (LPCG133)
csi_ipg_clk_s BUS_CLK_ROOT clk_enable_csi (LPCG133)
csi_ipg_clk_s_raw BUS_CLK_ROOT clk_enable_csi (LPCG133)
DAC dac_ipg_clk BUS_CLK_ROOT clk_enable_dac (LPCG57)
dac_ipg_clk_s BUS_CLK_ROOT clk_enable_dac (LPCG57)
Table continues on the next page...
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System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
DMA_CH dma_ch_mux_ipg_clk BUS_CLK_ROOT clk_enable_edma (LPCG22)
_MUXn
dma_ch_mux_ipg_clk_s BUS_CLK_ROOT clk_enable_edma (LPCG22)
dma_ch_mux_lpsr_ipg_clk M4_CLK_ROOT clk_enable_edma_lpsr (LPCG23)
dma_ch_mux_lpsr_ipg_clk_s M4_CLK_ROOT clk_enable_edma_lpsr (LPCG23)
DCDC dcdc_clk_24M RCOSC_16M clk_enable_dcdc (LPCG8)
dcdc_ipg_clk RCOSC_16M clk_enable_dcdc (LPCG8)
eDMAn edma_hclk BUS_CLK_ROOT clk_enable_edma (LPCG22)
edma_ipg_clk BUS_CLK_ROOT clk_enable_edma (LPCG22)
edma_lpsr_hclk M4_CLK_ROOT clk_enable_edma_lpsr (LPCG23)
edma_lpsr_ipg_clk M4_CLK_ROOT clk_enable_edma_lpsr (LPCG23)
ENET1G enet_1g_ipg_clk BUS_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_ipg_clk_mac0 BUS_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_ipg_clk_mac0_s BUS_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_ipg_clk_rmii ENET2_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_ipg_clk_s BUS_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_ipg_clk_time ENET_TIMER2_CLK_ROOT clk_enable_enet_1g (LPCG113)
enet_1g_txc_sampling_clk ENET2_CLK_ROOT clk_enable_enet_1g (LPCG113)
ENET enet_ipg_clk BUS_CLK_ROOT clk_enable_enet (LPCG112)
enet_ipg_clk_mac0 BUS_CLK_ROOT clk_enable_enet (LPCG112)
enet_ipg_clk_mac0_s BUS_CLK_ROOT clk_enable_enet (LPCG112)
enet_ipg_clk_rmii ENET1_CLK_ROOT clk_enable_enet (LPCG112)
enet_ipg_clk_s BUS_CLK_ROOT clk_enable_enet (LPCG112)
enet_ipg_clk_time ENET_TIMER1_CLK_ROOT clk_enable_enet (LPCG112)
ENET enet_qos_aclk_i BUS_CLK_ROOT clk_enable_enet_qos (LPCG114)
QOS enet_qos_clk_csr_i BUS_CLK_ROOT clk_enable_enet_qos (LPCG114)
enet_qos_clk_ptp_ref_i ENET_TIMER3_CLK_ROOT clk_enable_enet_qos (LPCG114)
EWM ewm_ipg_clk BUS_CLK_ROOT clk_enable_ewm (LPCG18)
ewm_ipg_clk_s BUS_CLK_ROOT clk_enable_ewm (LPCG18)
ewm_lpo_clk_0 RCOSC_16M clk_enable_ewm (LPCG18)
ewm_lpo_clk_1 ref_1m_clk (1MHz clock clk_enable_ewm (LPCG18)
generated from the 400MHz RC
oscillator)
ewm_lpo_clk_2 BUS_CLK_ROOT clk_enable_ewm (LPCG18)
ewm_lpo_clk_3 BUS_CLK_ROOT clk_enable_ewm (LPCG18)
FlexIOn flexio1_flexio_clk FLEXIO1_CLK_ROOT clk_enable_flexio1 (LPCG53)
flexio1_ipt_clk FLEXIO1_CLK_ROOT clk_enable_flexio1 (LPCG53)
flexio1_pclk BUS_CLK_ROOT clk_enable_flexio1 (LPCG53)
flexio2_flexio_clk FLEXIO2_CLK_ROOT clk_enable_flexio2 (LPCG54)
flexio2_ipt_clk FLEXIO2_CLK_ROOT clk_enable_flexio2 (LPCG54)
flexio2_pclk BUS_CLK_ROOT clk_enable_flexio2 (LPCG54)
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
FlexPWM flexpwm1_ipg_clk_0 BUS_CLK_ROOT clk_enable_flexpwm1 (LPCG79)
n flexpwm1_ipg_clk_1 BUS_CLK_ROOT clk_enable_flexpwm1 (LPCG79)
flexpwm1_ipg_clk_2 BUS_CLK_ROOT clk_enable_flexpwm1 (LPCG79)
flexpwm1_ipg_clk_3 BUS_CLK_ROOT clk_enable_flexpwm1 (LPCG79)
flexpwm2_ipg_clk_0 BUS_CLK_ROOT clk_enable_flexpwm2 (LPCG80)
flexpwm2_ipg_clk_1 BUS_CLK_ROOT clk_enable_flexpwm2 (LPCG80)
flexpwm2_ipg_clk_2 BUS_CLK_ROOT clk_enable_flexpwm2 (LPCG80)
flexpwm2_ipg_clk_3 BUS_CLK_ROOT clk_enable_flexpwm2 (LPCG80)
flexpwm3_ipg_clk_0 BUS_CLK_ROOT clk_enable_flexpwm3 (LPCG81)
flexpwm3_ipg_clk_1 BUS_CLK_ROOT clk_enable_flexpwm3 (LPCG81)
flexpwm3_ipg_clk_2 BUS_CLK_ROOT clk_enable_flexpwm3 (LPCG81)
flexpwm3_ipg_clk_3 BUS_CLK_ROOT clk_enable_flexpwm3 (LPCG81)
flexpwm4_ipg_clk_0 BUS_CLK_ROOT clk_enable_flexpwm4 (LPCG82)
flexpwm4_ipg_clk_1 BUS_CLK_ROOT clk_enable_flexpwm4 (LPCG82)
flexpwm4_ipg_clk_2 BUS_CLK_ROOT clk_enable_flexpwm4 (LPCG82)
flexpwm4_ipg_clk_3 BUS_CLK_ROOT clk_enable_flexpwm4 (LPCG82)
FlexSPIn flexspi1_hclk BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
flexspi1_ipg_clk BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
flexspi1_ipg_clk_s BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
flexspi1_ipg_clk_sfck FLEXSPI1_CLK_ROOT clk_enable_flexspi1 (LPCG28)
flexspi2_hclk BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
flexspi2_ipg_clk BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
flexspi2_ipg_clk_s BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
flexspi2_ipg_clk_sfck FLEXSPI2_CLK_ROOT clk_enable_flexspi2 (LPCG29)
GPC gpc_ipg_clk RCOSC_16M clk_enable_gpc (LPCG11)
gpc_clk_32k RCOSC_16M clk_enable_gpc (LPCG11)
GPIOn gpio1_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio2_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio3_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio4_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio5_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio6_ipg_clk_s BUS_CLK_ROOT clk_enable_gpio (LPCG51)
gpio7_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio8_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio9_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio10_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio11_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio12_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_gpio (LPCG51)
gpio13_ipg_clk_s RCOSC_32K clk_enable_gpio (LPCG51)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1455
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
GPTn gpt1_ipg_clk GPT1_CLK_ROOT clk_enable_gpt1 (LPCG64)
gpt1_ipg_clk_s GPT1_CLK_ROOT clk_enable_gpt1 (LPCG64)
gpt1_ipg_clk_32k GPT1_CLK_ROOT clk_enable_gpt1 (LPCG64)
gpt1_ipg_clk_highfreq GPT1_CLK_ROOT clk_enable_gpt1 (LPCG64)
gpt1_ipg_clk_24m RCOSC_16M clk_enable_gpt1 (LPCG64)
gpt2_ipg_clk GPT2_CLK_ROOT clk_enable_gpt2 (LPCG65)
gpt2_ipg_clk_s GPT2_CLK_ROOT clk_enable_gpt2 (LPCG65)
gpt2_ipg_clk_32k GPT2_CLK_ROOT clk_enable_gpt2 (LPCG65)
gpt2_ipg_clk_highfreq GPT2_CLK_ROOT clk_enable_gpt2 (LPCG65)
gpt2_ipg_clk_24m RCOSC_16M clk_enable_gpt2 (LPCG65)
gpt3_ipg_clk GPT3_CLK_ROOT clk_enable_gpt3 (LPCG66)
gpt3_ipg_clk_s GPT3_CLK_ROOT clk_enable_gpt3 (LPCG66)
gpt3_ipg_clk_32k GPT3_CLK_ROOT clk_enable_gpt3 (LPCG66)
gpt3_ipg_clk_highfreq GPT3_CLK_ROOT clk_enable_gpt3 (LPCG66)
gpt3_ipg_clk_24m RCOSC_16M clk_enable_gpt3 (LPCG66)
gpt4_ipg_clk GPT4_CLK_ROOT clk_enable_gpt4 (LPCG67)
gpt4_ipg_clk_s GPT4_CLK_ROOT clk_enable_gpt4 (LPCG67)
gpt4_ipg_clk_32k GPT4_CLK_ROOT clk_enable_gpt4 (LPCG67)
gpt4_ipg_clk_highfreq GPT4_CLK_ROOT clk_enable_gpt4 (LPCG67)
gpt4_ipg_clk_24m RCOSC_16M clk_enable_gpt4 (LPCG67)
gpt5_ipg_clk GPT5_CLK_ROOT clk_enable_gpt5 (LPCG68)
gpt5_ipg_clk_s GPT5_CLK_ROOT clk_enable_gpt5 (LPCG68)
gpt5_ipg_clk_32k GPT5_CLK_ROOT clk_enable_gpt5 (LPCG68)
gpt5_ipg_clk_highfreq GPT5_CLK_ROOT clk_enable_gpt5 (LPCG68)
gpt5_ipg_clk_24m RCOSC_16M clk_enable_gpt5 (LPCG68)
gpt6_ipg_clk GPT6_CLK_ROOT clk_enable_gpt6 (LPCG69)
gpt6_ipg_clk_s GPT6_CLK_ROOT clk_enable_gpt6 (LPCG69)
gpt6_ipg_clk_32k GPT6_CLK_ROOT clk_enable_gpt6 (LPCG69)
gpt6_ipg_clk_highfreq GPT6_CLK_ROOT clk_enable_gpt6 (LPCG69)
gpt6_ipg_clk_24m RCOSC_16M clk_enable_gpt6 (LPCG69)
GPU2D gpu2d_aclk BUS_CLK_ROOT clk_enable_gpu2d (LPCG128)
gpu2d_clk2x GPU2D_CLK_ROOT clk_enable_gpu2d (LPCG128)
gpu2d_hclk BUS_CLK_ROOT clk_enable_gpu2d (LPCG128)
IEE iee_iee_clk BUS_CLK_ROOT clk_enable_iee (LPCG35)
iee_pclk BUS_CLK_ROOT clk_enable_iee (LPCG35)
IOMUXC iomux_ipt_clk_io BUS_CLK_ROOT clk_enable_iomuxc (LPCG49)
iomuxc_ipg_clk_s BUS_CLK_ROOT clk_enable_iomuxc (LPCG49)
iomux_lpsr_ipt_clk_io BUS_LPSR_CLK_ROOT clk_enable_iomuxc_lpsr (LPCG50)
iomuxc_gpr_ipg_clk_s BUS_CLK_ROOT clk_enable_iomuxc (LPCG49)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1456 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
iomuxc_ipg_clk_s BUS_CLK_ROOT clk_enable_iomuxc (LPCG49)
iomuxc_lpsr_gpr_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_iomuxc_lpsr (LPCG50)
iomuxc_lpsr_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_iomuxc_lpsr (LPCG50)
JTAG jtag_mux_ipg_clk M4_CLK_ROOT clk_enable_jtag_mux (LPCG41)
jtag_mux_tck - -
KPP kpp_ipg_clk_s BUS_CLK_ROOT clk_enable_kpp (LPCG52)
kpp_ipg_clk_32k BUS_CLK_ROOT clk_enable_kpp (LPCG52)
eLCDIF elcdif_apb_clk BUS_CLK_ROOT clk_enable_elcdif (LPCG129)
elcdif_pix_clk ELCDIF_CLK_ROOT clk_enable_elcdif (LPCG129)
LCDIFv2 lcdifv2_apb_clk BUS_CLK_ROOT clk_enable_lcdifv2 (LPCG130)
lcdifv2_bus_clk BUS_CLK_ROOT clk_enable_lcdifv2 (LPCG130)
lcdifv2_pix_clk LCDIFV2_CLK_ROOT clk_enable_lcdifv2 (LPCG130)
LPADCn adc1_adc_clk ADC1_CLK_ROOT clk_enable_adc1 (LPCG55)
adc1_ipg_clk BUS_CLK_ROOT clk_enable_adc1 (LPCG55)
adc1_ipg_clk_s BUS_CLK_ROOT clk_enable_adc1 (LPCG55)
adc2_adc_clk ADC2_CLK_ROOT clk_enable_adc2 (LPCG56)
adc2_ipg_clk BUS_CLK_ROOT clk_enable_adc2 (LPCG56)
adc2_ipg_clk_s BUS_CLK_ROOT clk_enable_adc2 (LPCG56)
LPI2Cn lpi2c1_ipg_clk BUS_CLK_ROOT clk_enable_lpi2c1 (LPCG98)
lpi2c1_ipg_clk_s BUS_CLK_ROOT clk_enable_lpi2c1 (LPCG98)
lpi2c1_ipt_clk LPI2C1_CLK_ROOT clk_enable_lpi2c1 (LPCG98)
lpi2c1_lpi2c_clk LPI2C1_CLK_ROOT clk_enable_lpi2c1 (LPCG98)
lpi2c1_lpi2c_div_clk LPI2C1_CLK_ROOT clk_enable_lpi2c1 (LPCG98)
lpi2c2_ipg_clk BUS_CLK_ROOT clk_enable_lpi2c2 (LPCG99)
lpi2c2_ipg_clk_s BUS_CLK_ROOT clk_enable_lpi2c2 (LPCG99)
lpi2c2_ipt_clk LPI2C2_CLK_ROOT clk_enable_lpi2c2 (LPCG99)
lpi2c2_lpi2c_clk LPI2C2_CLK_ROOT clk_enable_lpi2c2 (LPCG99)
lpi2c2_lpi2c_div_clk LPI2C2_CLK_ROOT clk_enable_lpi2c2 (LPCG99)
lpi2c3_ipg_clk BUS_CLK_ROOT clk_enable_lpi2c3 (LPCG100)
lpi2c3_ipg_clk_s BUS_CLK_ROOT clk_enable_lpi2c3 (LPCG100)
lpi2c3_ipt_clk LPI2C3_CLK_ROOT clk_enable_lpi2c3 (LPCG100)
lpi2c3_lpi2c_clk LPI2C3_CLK_ROOT clk_enable_lpi2c3 (LPCG100)
lpi2c3_lpi2c_div_clk LPI2C3_CLK_ROOT clk_enable_lpi2c3 (LPCG100)
lpi2c4_ipg_clk BUS_CLK_ROOT clk_enable_lpi2c4 (LPCG101)
lpi2c4_ipg_clk_s BUS_CLK_ROOT clk_enable_lpi2c4 (LPCG101)
lpi2c4_ipt_clk LPI2C4_CLK_ROOT clk_enable_lpi2c4 (LPCG101)
lpi2c4_lpi2c_clk LPI2C4_CLK_ROOT clk_enable_lpi2c4 (LPCG101)
lpi2c4_lpi2c_div_clk LPI2C4_CLK_ROOT clk_enable_lpi2c4 (LPCG101)
lpi2c5_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpi2c5 (LPCG102)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1457
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
lpi2c5_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpi2c5 (LPCG102)
lpi2c5_ipt_clk LPI2C5_CLK_ROOT clk_enable_lpi2c5 (LPCG102)
lpi2c5_lpi2c_clk LPI2C5_CLK_ROOT clk_enable_lpi2c5 (LPCG102)
lpi2c5_lpi2c_div_clk LPI2C5_CLK_ROOT clk_enable_lpi2c5 (LPCG102)
lpi2c6_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpi2c6 (LPCG103)
lpi2c6_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpi2c6 (LPCG103)
lpi2c6_ipt_clk LPI2C6_CLK_ROOT clk_enable_lpi2c6 (LPCG103)
lpi2c6_lpi2c_clk LPI2C6_CLK_ROOT clk_enable_lpi2c6 (LPCG103)
lpi2c6_lpi2c_div_clk LPI2C6_CLK_ROOT clk_enable_lpi2c6 (LPCG103)
LPSPIn lpspi1_ipg_clk BUS_CLK_ROOT clk_enable_lpspi1 (LPCG104)
lpspi1_ipg_clk_s BUS_CLK_ROOT clk_enable_lpspi1 (LPCG104)
lpspi1_ipt_clk_lpspi LPSPI1_CLK_ROOT clk_enable_lpspi1 (LPCG104)
lpspi1_lpspi_clk LPSPI1_CLK_ROOT clk_enable_lpspi1 (LPCG104)
lpspi1_lpspi_div_clk LPSPI1_CLK_ROOT clk_enable_lpspi1 (LPCG104)
lpspi2_ipg_clk BUS_CLK_ROOT clk_enable_lpspi2 (LPCG105)
lpspi2_ipg_clk_s BUS_CLK_ROOT clk_enable_lpspi2 (LPCG105)
lpspi2_ipt_clk_lpspi LPSPI2_CLK_ROOT clk_enable_lpspi2 (LPCG105)
lpspi2_lpspi_clk LPSPI2_CLK_ROOT clk_enable_lpspi2 (LPCG105)
lpspi2_lpspi_div_clk LPSPI2_CLK_ROOT clk_enable_lpspi2 (LPCG105)
lpspi3_ipg_clk BUS_CLK_ROOT clk_enable_lpspi3 (LPCG106)
lpspi3_ipg_clk_s BUS_CLK_ROOT clk_enable_lpspi3 (LPCG106)
lpspi3_ipt_clk_lpspi LPSPI3_CLK_ROOT clk_enable_lpspi3 (LPCG106)
lpspi3_lpspi_clk LPSPI3_CLK_ROOT clk_enable_lpspi3 (LPCG106)
lpspi3_lpspi_div_clk LPSPI3_CLK_ROOT clk_enable_lpspi3 (LPCG106)
lpspi4_ipg_clk BUS_CLK_ROOT clk_enable_lpspi4 (LPCG107)
lpspi4_ipg_clk_s BUS_CLK_ROOT clk_enable_lpspi4 (LPCG107)
lpspi4_ipt_clk_lpspi LPSPI4_CLK_ROOT clk_enable_lpspi4 (LPCG107)
lpspi4_lpspi_clk LPSPI4_CLK_ROOT clk_enable_lpspi4 (LPCG107)
lpspi4_lpspi_div_clk LPSPI4_CLK_ROOT clk_enable_lpspi4 (LPCG107)
lpspi5_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpspi5 (LPCG108)
lpspi5_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpspi5 (LPCG108)
lpspi5_ipt_clk_lpspi LPSPI5_CLK_ROOT clk_enable_lpspi5 (LPCG108)
lpspi5_lpspi_clk LPSPI5_CLK_ROOT clk_enable_lpspi5 (LPCG108)
lpspi5_lpspi_div_clk LPSPI5_CLK_ROOT clk_enable_lpspi5 (LPCG108)
lpspi6_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpspi6 (LPCG109)
lpspi6_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpspi6 (LPCG109)
lpspi6_ipt_clk_lpspi LPSPI6_CLK_ROOT clk_enable_lpspi6 (LPCG109)
lpspi6_lpspi_clk LPSPI6_CLK_ROOT clk_enable_lpspi6 (LPCG109)
lpspi6_lpspi_div_clk LPSPI6_CLK_ROOT clk_enable_lpspi6 (LPCG109)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1458 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
LPUARTn lpuart1_ipg_clk BUS_CLK_ROOT clk_enable_lpuart1 (LPCG86)
lpuart1_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart1 (LPCG86)
lpuart1_lpuart_baud_clk LPUART1_CLK_ROOT clk_enable_lpuart1 (LPCG86)
lpuart1_lpuart_baud_gated_clk LPUART1_CLK_ROOT clk_enable_lpuart1 (LPCG86)
lpuart1_lpuart_baud_gated_clk_b LPUART1_CLK_ROOT clk_enable_lpuart1 (LPCG86)
lpuart2_ipg_clk BUS_CLK_ROOT clk_enable_lpuart2 (LPCG87)
lpuart2_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart2 (LPCG87)
lpuart2_lpuart_baud_clk LPUART2_CLK_ROOT clk_enable_lpuart2 (LPCG87)
lpuart2_lpuart_baud_gated_clk LPUART2_CLK_ROOT clk_enable_lpuart2 (LPCG87)
lpuart2_lpuart_baud_gated_clk_b LPUART2_CLK_ROOT clk_enable_lpuart2 (LPCG87)
lpuart3_ipg_clk BUS_CLK_ROOT clk_enable_lpuart3 (LPCG88)
lpuart3_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart3 (LPCG88)
lpuart3_lpuart_baud_clk LPUART3_CLK_ROOT clk_enable_lpuart3 (LPCG88)
lpuart3_lpuart_baud_gated_clk LPUART3_CLK_ROOT clk_enable_lpuart3 (LPCG88)
lpuart3_lpuart_baud_gated_clk_b LPUART3_CLK_ROOT clk_enable_lpuart3 (LPCG88)
lpuart4_ipg_clk BUS_CLK_ROOT clk_enable_lpuart4 (LPCG89)
lpuart4_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart4 (LPCG89)
lpuart4_lpuart_baud_clk LPUART4_CLK_ROOT clk_enable_lpuart4 (LPCG89)
lpuart4_lpuart_baud_gated_clk LPUART4_CLK_ROOT clk_enable_lpuart4 (LPCG89)
lpuart4_lpuart_baud_gated_clk_b LPUART4_CLK_ROOT clk_enable_lpuart4 (LPCG89)
lpuart5_ipg_clk BUS_CLK_ROOT clk_enable_lpuart5 (LPCG90)
lpuart5_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart5 (LPCG90)
lpuart5_lpuart_baud_clk LPUART5_CLK_ROOT clk_enable_lpuart5 (LPCG90)
lpuart5_lpuart_baud_gated_clk LPUART5_CLK_ROOT clk_enable_lpuart5 (LPCG90)
lpuart5_lpuart_baud_gated_clk_b LPUART5_CLK_ROOT clk_enable_lpuart5 (LPCG90)
lpuart6_ipg_clk BUS_CLK_ROOT clk_enable_lpuart6 (LPCG91)
lpuart6_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart6 (LPCG91)
lpuart6_lpuart_baud_clk LPUART6_CLK_ROOT clk_enable_lpuart6 (LPCG91)
lpuart6_lpuart_baud_gated_clk LPUART6_CLK_ROOT clk_enable_lpuart6 (LPCG91)
lpuart6_lpuart_baud_gated_clk_b LPUART6_CLK_ROOT clk_enable_lpuart6 (LPCG91)
lpuart7_ipg_clk BUS_CLK_ROOT clk_enable_lpuart7 (LPCG92)
lpuart7_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart7 (LPCG92)
lpuart7_lpuart_baud_clk LPUART7_CLK_ROOT clk_enable_lpuart7 (LPCG92)
lpuart7_lpuart_baud_gated_clk LPUART7_CLK_ROOT clk_enable_lpuart7 (LPCG92)
lpuart7_lpuart_baud_gated_clk_b LPUART7_CLK_ROOT clk_enable_lpuart7 (LPCG92)
lpuart8_ipg_clk BUS_CLK_ROOT clk_enable_lpuart8 (LPCG93)
lpuart8_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart8 (LPCG93)
lpuart8_lpuart_baud_clk LPUART8_CLK_ROOT clk_enable_lpuart8 (LPCG93)
lpuart8_lpuart_baud_gated_clk LPUART8_CLK_ROOT clk_enable_lpuart8 (LPCG93)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1459
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
lpuart8_lpuart_baud_gated_clk_b LPUART8_CLK_ROOT clk_enable_lpuart8 (LPCG93)
lpuart9_ipg_clk BUS_CLK_ROOT clk_enable_lpuart9 (LPCG94)
lpuart9_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart9 (LPCG94)
lpuart9_lpuart_baud_clk LPUART9_CLK_ROOT clk_enable_lpuart9 (LPCG94)
lpuart9_lpuart_baud_gated_clk LPUART9_CLK_ROOT clk_enable_lpuart9 (LPCG94)
lpuart9_lpuart_baud_gated_clk_b LPUART9_CLK_ROOT clk_enable_lpuart9 (LPCG94)
lpuart10_ipg_clk BUS_CLK_ROOT clk_enable_lpuart10 (LPCG95)
lpuart10_ipg_clk_s BUS_CLK_ROOT clk_enable_lpuart10 (LPCG95)
lpuart10_lpuart_baud_clk LPUART10_CLK_ROOT clk_enable_lpuart10 (LPCG95)
lpuart10_lpuart_baud_gated_clk LPUART10_CLK_ROOT clk_enable_lpuart10 (LPCG95)
lpuart10_lpuart_baud_gated_clk_b LPUART10_CLK_ROOT clk_enable_lpuart10 (LPCG95)
lpuart11_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpuart11 (LPCG96)
lpuart11_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpuart11 (LPCG96)
lpuart11_lpuart_baud_clk LPUART11_CLK_ROOT clk_enable_lpuart11 (LPCG96)
lpuart11_lpuart_baud_gated_clk LPUART11_CLK_ROOT clk_enable_lpuart11 (LPCG96)
lpuart11_lpuart_baud_gated_clk_b LPUART11_CLK_ROOT clk_enable_lpuart11 (LPCG96)
lpuart12_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_lpuart12 (LPCG97)
lpuart12_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_lpuart12 (LPCG97)
lpuart12_lpuart_baud_clk LPUART12_CLK_ROOT clk_enable_lpuart12 (LPCG97)
lpuart12_lpuart_baud_gated_clk LPUART12_CLK_ROOT clk_enable_lpuart12 (LPCG97)
lpuart12_lpuart_baud_gated_clk_b LPUART12_CLK_ROOT clk_enable_lpuart12 (LPCG97)
MECCn mecc1_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
mecc1_ipg_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
mecc1_ipg_clk_s BUS_CLK_ROOT clk_enable_ocram (LPCG25)
mecc2_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
mecc2_ipg_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
mecc2_ipg_clk_s BUS_CLK_ROOT clk_enable_ocram (LPCG25)
MIPI CSI mipi_csi_clk CSI2_CLK_ROOT clk_enable_mipi_csi (LPCG132)
mipi_csi_clk_esc CSI2_ESC_CLK_ROOT clk_enable_mipi_csi (LPCG132)
mipi_csi_clk_ui CSI2_UI_CLK_ROOT clk_enable_mipi_csi (LPCG132)
mipi_csi_pclk BUS_CLK_ROOT clk_enable_mipi_csi (LPCG132)
MIPI DSI mipi_dsi_CLKREF MIPI_REF_CLK_ROOT clk_enable_mipi_dsi (LPCG131)
mipi_dsi_dpi_pclk BUS_CLK_ROOT clk_enable_mipi_dsi (LPCG131)
mipi_dsi_pclk BUS_CLK_ROOT clk_enable_mipi_dsi (LPCG131)
mipi_dsi_RxClkEsc MIPI_ESC_CLK_ROOT clk_enable_mipi_dsi (LPCG131)
mipi_dsi_TxClkEsc MIPI_ESC_CLK_ROOT clk_enable_mipi_dsi (LPCG131)
MQS mqs_bclk MQS_CLK_ROOT clk_enable_mqs (LPCG120)
mqs_hmclk SAI3_CLK_ROOT clk_enable_mqs (LPCG120)
MU mu_ipg_clk_dsp BUS_LPSR_CLK_ROOT clk_enable_mu_b (LPCG21)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1460 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
mu_ipg_clk_mcu BUS_LPSR_CLK_ROOT clk_enable_mu_a (LPCG20)
mu_ipg_clk_s_dsp BUS_LPSR_CLK_ROOT clk_enable_mu_b (LPCG21)
mu_ipg_clk_s_mcu BUS_LPSR_CLK_ROOT clk_enable_mu_a (LPCG20)
OCRAMn ocram1_mem_mecc_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
ocram2_mem_mecc_clk BUS_CLK_ROOT clk_enable_ocram (LPCG25)
PDM mic_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_app MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_app_fifo MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_app_nonstop MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dc MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec1 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec2 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec3 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec4 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec5 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec6 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec7 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec160 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec161 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec162 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec163 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec164 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec165 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec166 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_dec167 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_fir MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_hb MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_inp MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad_dec0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad_dec160 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad_ndec0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad_noise0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
mic_ipg_clk_vad_zcd0 MIC_CLK_ROOT clk_enable_mic (LPCG121)
PITn pit1_ipg_clk BUS_CLK_ROOT clk_enable_pit1 (LPCG62)
pit1_ipg_clk_s BUS_CLK_ROOT clk_enable_pit1 (LPCG62)
pit1_ipg_clk_sync BUS_CLK_ROOT clk_enable_pit1 (LPCG62)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1461
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
pit2_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_pit2 (LPCG63)
pit2_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_pit2 (LPCG63)
pit2_ipg_clk_sync BUS_LPSR_CLK_ROOT clk_enable_pit2 (LPCG63)
PXP pxp_clk BUS_CLK_ROOT clk_enable_pxp (LPCG127)
QDCn enc1_ipg_clk BUS_CLK_ROOT clk_enable_enc1 (LPCG74)
enc2_ipg_clk BUS_CLK_ROOT clk_enable_enc2 (LPCG75)
enc3_ipg_clk BUS_CLK_ROOT clk_enable_enc3 (LPCG76)
enc4_ipg_clk BUS_CLK_ROOT clk_enable_enc4 (LPCG77)
QTIMERn qtimer1_clk0 BUS_CLK_ROOT clk_enable_qtimer1 (LPCG70)
qtimer1_clk1 BUS_CLK_ROOT clk_enable_qtimer1 (LPCG70)
qtimer1_clk2 BUS_CLK_ROOT clk_enable_qtimer1 (LPCG70)
qtimer1_clk3 BUS_CLK_ROOT clk_enable_qtimer1 (LPCG70)
qtimer2_clk0 BUS_CLK_ROOT clk_enable_qtimer2 (LPCG71)
qtimer2_clk1 BUS_CLK_ROOT clk_enable_qtimer2 (LPCG71)
qtimer2_clk2 BUS_CLK_ROOT clk_enable_qtimer2 (LPCG71)
qtimer2_clk3 BUS_CLK_ROOT clk_enable_qtimer2 (LPCG71)
qtimer3_clk0 BUS_CLK_ROOT clk_enable_qtimer3 (LPCG72)
qtimer3_clk1 BUS_CLK_ROOT clk_enable_qtimer3 (LPCG72)
qtimer3_clk2 BUS_CLK_ROOT clk_enable_qtimer3 (LPCG72)
qtimer3_clk3 BUS_CLK_ROOT clk_enable_qtimer3 (LPCG72)
qtimer4_clk0 BUS_CLK_ROOT clk_enable_qtimer4 (LPCG73)
qtimer4_clk1 BUS_CLK_ROOT clk_enable_qtimer4 (LPCG73)
qtimer4_clk2 BUS_CLK_ROOT clk_enable_qtimer4 (LPCG73)
qtimer4_clk3 BUS_CLK_ROOT clk_enable_qtimer4 (LPCG73)
RDC rdc_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_rdc (LPCG30)
rdc_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_rdc (LPCG30)
SAIn sai1_ipg_clk BUS_CLK_ROOT clk_enable_sai1 (LPCG123)
sai1_ipg_clk_s BUS_CLK_ROOT clk_enable_sai1 (LPCG123)
sai1_ipg_clk_sai_mclk IOMUXC_GPR_GPR0[SAI_MCLK clk_enable_sai1 (LPCG123)
1_SEL]
sai1_ipt_clk_sai_bclk SAI1_CLK_ROOT clk_enable_sai1 (LPCG123)
sai1_ipt_clk_sai_bclk_b SAI1_CLK_ROOT clk_enable_sai1 (LPCG123)
sai1_mclk_in2 IOMUXC_GPR_GPR0[SAI_MCLK clk_enable_sai1 (LPCG123)
2_SEL]
sai1_mclk_in3 IOMUXC_GPR_GPR0[SAI_MCLK clk_enable_sai1 (LPCG123)
3_SEL]
sai2_ipg_clk BUS_CLK_ROOT clk_enable_sai2 (LPCG124)
sai2_ipg_clk_s BUS_CLK_ROOT clk_enable_sai2 (LPCG124)
sai2_ipg_clk_sai_mclk SAI2_CLK_ROOT clk_enable_sai2 (LPCG124)
sai2_ipt_clk_sai_bclk SAI2_CLK_ROOT clk_enable_sai2 (LPCG124)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1462 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
sai2_ipt_clk_sai_bclk_b SAI2_CLK_ROOT clk_enable_sai2 (LPCG124)
sai2_mclk_in2 SAI2_CLK_ROOT clk_enable_sai2 (LPCG124)
sai2_mclk_in3 IOMUXC_GPR_GPR1[SA2_MCL clk_enable_sai2 (LPCG124)
K3_SEL]
sai3_ipg_clk BUS_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_ipg_clk_s BUS_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_ipg_clk_sai_mclk SAI3_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_ipt_clk_sai_bclk SAI3_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_ipt_clk_sai_bclk_b SAI3_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_mclk_in2 SAI3_CLK_ROOT clk_enable_sai3 (LPCG125)
sai3_mclk_in3 IOMUXC_GPR_GPR2[SA3_MCL clk_enable_sai3 (LPCG125)
K3_SEL]
sai4_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_ipg_clk_sai_mclk SAI4_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_ipt_clk_sai_bclk SAI4_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_ipt_clk_sai_bclk_b SAI4_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_mclk_in2 SAI4_CLK_ROOT clk_enable_sai4 (LPCG126)
sai4_mclk_in3 SAI4_CLK_ROOT clk_enable_sai4 (LPCG126)
SEMAn sema_hs_clk BUS_LPSR_CLK_ROOT clk_enable_sema (LPCG19)
sema1_clk BUS_LPSR_CLK_ROOT clk_enable_sema (LPCG19)
sema2_clk BUS_LPSR_CLK_ROOT clk_enable_sema (LPCG19)
SEMC semc_ipg_clk SEMC_CLK_ROOT clk_enable_semc (LPCG33)
EMVSIMn sim1_ipg_clk BUS_CLK_ROOT clk_enable_sim1 (LPCG110)
sim1_ipg_clk_s BUS_CLK_ROOT clk_enable_sim1 (LPCG110)
sim1_ipg_sim_clk EMV1_CLK_ROOT clk_enable_sim1 (LPCG110)
sim1_ipg_ungated_sim_clk EMV1_CLK_ROOT clk_enable_sim1 (LPCG110)
sim2_ipg_clk BUS_CLK_ROOT clk_enable_sim2 (LPCG111)
sim2_ipg_clk_s BUS_CLK_ROOT clk_enable_sim2 (LPCG111)
sim2_ipg_sim_clk EMV2_CLK_ROOT clk_enable_sim2 (LPCG111)
sim2_ipg_ungated_sim_clk EMV2_CLK_ROOT clk_enable_sim2 (LPCG111)
SNVS snvs_hp_wrapper_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_snvs_hp (LPCG38)
snvs_hp_wrapper_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_snvs_hp (LPCG38)
SPDIF spdif_gclkw_t0 BUS_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_extal_clk OSC_24M clk_enable_spdif (LPCG122)
spdif_ipg_clk_s BUS_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_tx_clk SPDIF_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_tx_clk1 SAI1_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_tx_clk2 SAI2_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_tx_clk3 SAI3_CLK_ROOT clk_enable_spdif (LPCG122)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1463
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
spdif_tx_clk4 SAI4_CLK_ROOT clk_enable_spdif (LPCG122)
spdif_tx_clk5 MIC_CLK_ROOT clk_enable_spdif (LPCG122)
SSARC ssarc_hp_ahb_clk M4_CLK_ROOT clk_enable_ssarc (LPCG12)
ssarc_lp_ipg_clk RCOSC_16M clk_enable_ssarc (LPCG12)
ssarc_lp_ahb_clk M4_CLK_ROOT clk_enable_ssarc (LPCG12)
USB usb_ipg_ahb_clk BUS_CLK_ROOT clk_enable_usb (LPCG115)
usb_ipg_clk_s BUS_CLK_ROOT clk_enable_usb (LPCG115)
usb_ipg_clk_s_pl301 BUS_CLK_ROOT clk_enable_usb (LPCG115)
USBPHY usbphy1_ipg_clk BUS_CLK_ROOT clk_enable_usb (LPCG115)
n usbphy1_ipg_clk_s BUS_CLK_ROOT clk_enable_usb (LPCG115)
usbphy1_clk_xtal OSC_24M clk_enable_usb (LPCG115)
usbphy2_ipg_clk BUS_CLK_ROOT clk_enable_usb (LPCG115)
usbphy2_clk_xtal OSC_24M clk_enable_usb (LPCG115)
usbphy2_ipg_clk_s BUS_CLK_ROOT clk_enable_usb (LPCG115)
USDHCn usdhc1_hclk BUS_CLK_ROOT clk_enable_usdhc1 (LPCG117)
usdhc1_ipg_clk BUS_CLK_ROOT clk_enable_usdhc1 (LPCG117)
usdhc1_ipg_clk_perclk USDHC1_CLK_ROOT clk_enable_usdhc1 (LPCG117)
usdhc1_ipg_clk_s BUS_CLK_ROOT clk_enable_usdhc1 (LPCG117)
usdhc2_hclk BUS_CLK_ROOT clk_enable_usdhc2 (LPCG118)
usdhc2_ipg_clk BUS_CLK_ROOT clk_enable_usdhc2 (LPCG118)
usdhc2_ipg_clk_perclk USDHC2_CLK_ROOT clk_enable_usdhc2 (LPCG118)
usdhc2_ipg_clk_s BUS_CLK_ROOT clk_enable_usdhc2 (LPCG118)
VIDMUX video_mux_dcic1_hsp_clk BUS_CLK_ROOT clk_enable_dcic_mipi (LPCG134)
video_mux_dcic2_hsp_clk BUS_CLK_ROOT clk_enable_dcic_lcd (LPCG135)
video_mux_ipg_clk_s BUS_CLK_ROOT clk_enable_video_mux (LPCG136)
WDOGn wdog1_ipg_clk BUS_CLK_ROOT clk_enable_wdog1 (LPCG14)
wdog1_ipg_clk_s BUS_CLK_ROOT clk_enable_wdog1 (LPCG14)
wdog1_ipg_clk_32k BUS_CLK_ROOT clk_enable_wdog1 (LPCG14)
wdog2_ipg_clk BUS_CLK_ROOT clk_enable_wdog2 (LPCG15)
wdog2_ipg_clk_s BUS_CLK_ROOT clk_enable_wdog2 (LPCG15)
wdog2_ipg_clk_32k BUS_CLK_ROOT clk_enable_wdog2 (LPCG15)
wdog3_ipg_clk_gated BUS_CLK_ROOT clk_enable_wdog3 (LPCG16)
wdog3_ipg_clk_s BUS_CLK_ROOT clk_enable_wdog3 (LPCG16)
wdog3_ipg_clk_ungated BUS_CLK_ROOT clk_enable_wdog3 (LPCG16)
wdog3_ipt_clk BUS_CLK_ROOT clk_enable_wdog3 (LPCG16)
wdog3_ext_clk ref_1m_clk (1MHz clock clk_enable_wdog3 (LPCG16)
generated from the 400MHz RC
oscillator)
wdog4_ipg_clk_gated BUS_LPSR_CLK_ROOT clk_enable_wdog4 (LPCG17)
wdog4_ipg_clk_s BUS_LPSR_CLK_ROOT clk_enable_wdog4 (LPCG17)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1464 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
wdog4_ipg_clk_ungated BUS_LPSR_CLK_ROOT clk_enable_wdog4 (LPCG17)
wdog4_ipt_clk BUS_LPSR_CLK_ROOT clk_enable_wdog4 (LPCG17)
wdog4_ext_clk ref_1m_clk (1MHz clock clk_enable_wdog4 (LPCG17)
generated from the 400MHz RC
oscillator)
XBARn xbar1_ipb_clk BUS_CLK_ROOT clk_enable_xbar1 (LPCG43)
xbar2_ipb_clk BUS_CLK_ROOT clk_enable_xbar2 (LPCG44)
xbar3_ipb_clk BUS_CLK_ROOT clk_enable_xbar3 (LPCG45)
XECC xecc_flexspi1_clk BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
xecc_flexspi1_ipg_clk BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
xecc_flexspi1_ipg_clk_s BUS_CLK_ROOT clk_enable_flexspi1 (LPCG28)
xecc_flexspi2_clk BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
xecc_flexspi2_ipg_clk BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
xecc_flexspi2_ipg_clk_s BUS_CLK_ROOT clk_enable_flexspi2 (LPCG29)
xecc_semc_clk SEMC_CLK_ROOT clk_enable_semc (LPCG33)
xecc_semc_ipg_clk SEMC_CLK_ROOT clk_enable_semc (LPCG33)
xecc_semc_ipg_clk_s SEMC_CLK_ROOT clk_enable_semc (LPCG33)
XRDC2 xrdc2_mdac_ahb_m7_ipg_clk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mdac_ahbc_m4_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mdac_ahbs_m4_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mdac_axi_m7_ipg_clk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mdac_caam_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_caam_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_csi_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_csi_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_edma_m4_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mdac_edma_m7_ipg_clk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mdac_enet_1g_rx_ipg_clk_d BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
0
xrdc2_mdac_enet_1g_rx_ipg_clk_d BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
1
xrdc2_mdac_enet_1g_tx_ipg_clk_d BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
0
xrdc2_mdac_enet_1g_tx_ipg_clk_d BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
1
xrdc2_mdac_enet_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_enet_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_enet_qos_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_enet_qos_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_gpu_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_gpu_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1465
System Clocks
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
xrdc2_mdac_elcdif_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_elcdif_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_lcdifv2_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_lcdifv2_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_pxp_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_pxp_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_mdac_ssarc_ipg_clk_d0 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mdac_ssarc_ipg_clk_d1 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mdac_usb_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_usb_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_usdhc1_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_usdhc1_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_usdhc2_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mdac_usdhc2_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m (LPCG3)
xrdc2_mgr_d0_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_m7_xrdc (LPCG31)
xrdc2_mgr_d1_ipg_clk BUS_LPSR_CLK_ROOT clk_enable_m4_xrdc (LPCG32)
xrdc2_mrc_caam_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_caam_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_caam_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi1_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi1_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi1_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi2_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi2_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_flexspi2_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_m4lmem_hclk M4_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mrc_m4lmem_ipg_clk_d0 M4_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mrc_m4lmem_ipg_clk_d1 M4_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_mrc_m7_ocram_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_m7_ocram_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_m7_ocram_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc1_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc1_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc1_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc2_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc2_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_mecc2_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_semc_hclk SEMC_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_mrc_semc_ipg_clk_d0 SEMC_CLK_ROOT clk_enable_sim_m7 (LPCG2)
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1466 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Table 15-2. System Clocks Table (continued)
Module Module Clock Clock Root LPCG Enable (LPCGx_DIRECT[ON])
xrdc2_mrc_semc_ipg_clk_d1 SEMC_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv0_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv0_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv0_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv0_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv0_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv1_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv1_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv1_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv4_hclk BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv4_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_gpv4_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_msc_romcp_hclk M4_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_msc_romcp_ipg_clk_d0 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_msc_romcp_ipg_clk_d1 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_pac_aips1_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips1_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips2_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips2_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips3_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips3_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_m7 (LPCG2)
xrdc2_pac_aips4_ipg_clk_d0 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_pac_aips4_ipg_clk_d1 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_pac_gpu_hclk BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_pac_gpu_ipg_clk_d0 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_pac_gpu_ipg_clk_d1 BUS_CLK_ROOT clk_enable_sim_disp (LPCG4)
xrdc2_pac_scdog_hclk BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_pac_scdog_ipg_clk_d0 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
xrdc2_pac_scdog_ipg_clk_d1 BUS_LPSR_CLK_ROOT clk_enable_sim_lpsr (LPCG6)
15.4 Clock Tree
The figure below illustrates the clock sources from the PLLs.
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Clock Tree
ARM_PLL DIV
SYS_PLL1
1GHz
(1 GHz)
/2
/5
SYS_PLL2
(528 MHz) SYS_PLL2[PFD0_FRAC]
PFD0
SYS_PLL2[PFD1_FRAC]
PFD1
SYS_PLL2[PFD2_FRAC]
PFD2
SYS_PLL2[PFD3_FRAC]
PFD3
SYS_PLL3
(480 MHz) SYS_PLL3[PFD0_FRAC]
PFD0
SYS_PLL3[PFD1_FRAC]
PFD1
SYS_PLL3[PFD2_FRAC]
PFD2
SYS_PLL3[PFD3_FRAC]
PFD3
/2
AUDIO_PLL
VIDEO_PLL
RCOSC_400M
RCOSC_48M
/2
RCOSC_16M
OSC_RC_48M_DIV2
OSC_32K
SYS_PLL3_PFD1
SYS_PLL2_PFD1
SYS_PLL3_PFD2
SYS_PLL2_PFD2
SYS_PLL3_PFD3
SYS_PLL2_PFD3
SYS_PLL3_PFD0
SYS_PLL2_PFD0
SYS_PLL3_DIV2
SYS_PLL1_DIV2
SYS_PLL1_DIV5
SYS_PLL3_OUT
SYS_PLL1_CLK
SYS_PLL2_CLK
OSC_RC_400M
OSC_24M
OSC_RC_48M
OSC_RC_16M
PLL_AUDIO
PLL_VIDEO
OSC_24M
PLL_ARM
OSC_32K
The figure below illustrates the clock roots of CCM and clock root generation.
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Chapter 15 Clock Controller Module (CCM)
CLOCK_ROOT0_CONTROL[MUX]
CLOCK_ROOT0_CONTROL[DIV] LPCG
cg M7_CLK_ROOT
cg \
CLOCK_ROOT1_CONTROL[MUX]
CLOCK_ROOT1_CONTROL[DIV]
M4_CLK_ROOT
cg cg \
CLOCK_ROOT2_CONTROL[MUX]
CLOCK_ROOT2_CONTROL[DIV]
BUS_CLK_ROOT
cg cg \
CLOCK_ROOT3_CONTROL[MUX]
CLOCK_ROOT3_CONTROL[DIV]
cg BUS_LPSR_CLK_ROOT cg
LPCG6
CLOCK_ROOT4_CONTROL[MUX]
CLOCK_ROOT4_CONTROL[DIV]
cg SEMC_CLK_ROOT cg
LPCG33
LPCG2
CLOCK_ROOT5_CONTROL[MUX]
CLOCK_ROOT5_CONTROL[DIV]
CSSYS_CLK_ROOT cg
cg
LPCG42
CLOCK_ROOT6_CONTROL[MUX]
CLOCK_ROOT6_CONTROL[DIV]
CSTRACE_CLK_ROOT cg
cg
LPCG42
CLOCK_ROOT7_CONTROL[MUX] CLOCK_ROOT7_CONTROL[DIV]
M4_SYSTICK_CLK_ROOT cg
cg
LPCG1
CLOCK_ROOT8_CONTROL[MUX]
CLOCK_ROOT8_CONTROL[DIV]
cg
M7_SYSTICK_CLK_ROOT cg
LPCG0
CLOCK_ROOT9_CONTROL[MUX]
CLOCK_ROOT9_CONTROL[DIV]
cg ADC1_CLK_ROOT cg
LPCG55
CLOCK_ROOT10_CONTROL[MUX]
CLOCK_ROOT10_CONTROL[DIV]
cg ADC2_CLK_ROOT cg
LPCG56
CLOCK_ROOT11_CONTROL[MUX]
CLOCK_ROOT11_CONTROL[DIV]
cg ACMP_CLK_ROOT cg
LPCG58 -
CLOCK_ROOT12_CONTROL[MUX]
LPCG61
CLOCK_ROOT12_CONTROL[DIV]
cg FLEXIO1_CLK_ROOT cg
LPCG53
CLOCK_ROOT13_CONTROL[MUX]
CLOCK_ROOT13_CONTROL[DIV]
cg FLEXIO2_CLK_ROOT cg
LPCG54
CLOCK_ROOT14_CONTROL[MUX]
CLOCK_ROOT14_CONTROL[DIV]
cg GPT1_CLK_ROOT cg
LPCG64
CLOCK_ROOT15_CONTROL[MUX]
CLOCK_ROOT15_CONTROL[DIV]
GPT2_CLK_ROOT
cg cg
CLOCK_ROOT16_CONTROL[MUX] LPCG65
CLOCK_ROOT16_CONTROL[DIV]
GPT3_CLK_ROOT
cg cg
LPCG66
CLOCK_ROOT17_CONTROL[MUX]
CLOCK_ROOT17_CONTROL[DIV]
GPT4_CLK_ROOT
cg cg
LPCG67
CLOCK_ROOT18_CONTROL[MUX]
CLOCK_ROOT18_CONTROL[DIV]
cg GPT5_CLK_ROOT cg
LPCG68
CLOCK_ROOT19_CONTROL[MUX]
CLOCK_ROOT19_CONTROL[DIV]
cg GPT6_CLK_ROOT cg
LPCG69
OSC_RC_48M_DIV2
SYS_PLL3_PFD1
SYS_PLL2_PFD1
SYS_PLL3_PFD2
SYS_PLL2_PFD2
SYS_PLL3_PFD3
SYS_PLL2_PFD3
SYS_PLL3_PFD0
SYS_PLL2_PFD0
SYS_PLL3_DIV2
SYS_PLL1_DIV2
SYS_PLL1_DIV5
SYS_PLL3_OUT
SYS_PLL1_CLK
SYS_PLL2_CLK
OSC_RC_400M
OSC_RC_48M
OSC_RC_16M
PLL_AUDIO
PLL_VIDEO
OSC_24M
PLL_ARM
OSC_32K
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Clock Tree
CLOCK_ROOT20_CONTROL[MUX] CLOCK_ROOT20_CONTROL[DIV] LPCG
cg FLEXSPI1_CLK_ROOT cg
LPCG28
CLOCK_ROOT21_CONTROL[MUX] CLOCK_ROOT21_CONTROL[DIV]
cg FLEXSPI2_CLK_ROOT cg
LPCG29
CLOCK_ROOT22_CONTROL[MUX] CLOCK_ROOT22_CONTROL[DIV]
CAN1_CLK_ROOT cg
cg
CLOCK_ROOT23_CONTROL[MUX] LPCG83
CLOCK_ROOT23_CONTROL[DIV]
cg CAN2_CLK_ROOT cg
LPCG84
CLOCK_ROOT24_CONTROL[MUX]
CLOCK_ROOT24_CONTROL[DIV]
cg CAN3_CLK_ROOT cg
LPCG85
CLOCK_ROOT25_CONTROL[MUX]
CLOCK_ROOT25_CONTROL[DIV]
LPUART1_CLK_ROOT
cg cg
LPCG86
CLOCK_ROOT26_CONTROL[MUX]
CLOCK_ROOT26_CONTROL[DIV]
LPUART2_CLK_ROOT cg
cg
LPCG87
CLOCK_ROOT27_CONTROL[MUX] CLOCK_ROOT27_CONTROL[DIV]
cg
LPUART3_CLK_ROOT cg
LPCG88
CLOCK_ROOT28_CONTROL[MUX]
CLOCK_ROOT28_CONTROL[DIV]
LPUART4_CLK_ROOT
cg cg
LPCG89
CLOCK_ROOT29_CONTROL[MUX]
CLOCK_ROOT29_CONTROL[DIV]
cg
LPUART5_CLK_ROOT cg
LPCG90
CLOCK_ROOT30_CONTROL[MUX]
CLOCK_ROOT30_CONTROL[DIV]
cg LPUART6_CLK_ROOT cg
LPCG91
CLOCK_ROOT31_CONTROL[MUX]
CLOCK_ROOT31_CONTROL[DIV]
LPUART7_CLK_ROOT
cg cg
LPCG92
CLOCK_ROOT32_CONTROL[MUX]
CLOCK_ROOT32_CONTROL[DIV]
cg
LPUART8_CLK_ROOT cg
CLOCK_ROOT33_CONTROL[MUX] LPCG93
CLOCK_ROOT33_CONTROL[DIV]
cg LPUART9_CLK_ROOT cg
LPCG94
CLOCK_ROOT34_CONTROL[MUX] CLOCK_ROOT34_CONTROL[DIV]
cg LPUART10_CLK_ROOT cg
LPCG95
CLOCK_ROOT35_CONTROL[MUX]
CLOCK_ROOT35_CONTROL[DIV]
LPUART11_CLK_ROOT cg
cg
LPCG96
CLOCK_ROOT36_CONTROL[MUX] CLOCK_ROOT36_CONTROL[DIV]
cg
LPUART12_CLK_ROOT cg
LPCG97
CLOCK_ROOT37_CONTROL[MUX]
CLOCK_ROOT37_CONTROL[DIV]
cg LPI2C1_CLK_ROOT cg
LPCG98
CLOCK_ROOT38_CONTROL[MUX] CLOCK_ROOT38_CONTROL[DIV]
cg LPI2C2_CLK_ROOT cg
LPCG99
CLOCK_ROOT39_CONTROL[MUX]
CLOCK_ROOT39_CONTROL[DIV]
cg LPI2C3_CLK_ROOT cg
LPCG100
OSC_RC_48M_DIV2
SYS_PLL3_PFD1
SYS_PLL2_PFD1
SYS_PLL3_PFD2
SYS_PLL2_PFD2
SYS_PLL3_PFD3
SYS_PLL2_PFD3
SYS_PLL3_PFD0
SYS_PLL2_PFD0
SYS_PLL3_DIV2
SYS_PLL1_DIV2
SYS_PLL1_DIV5
SYS_PLL3_OUT
SYS_PLL1_CLK
SYS_PLL2_CLK
OSC_RC_400M
OSC_RC_48M
OSC_RC_16M
PLL_AUDIO
PLL_VIDEO
OSC_24M
PLL_ARM
OSC_32K
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Chapter 15 Clock Controller Module (CCM)
CLOCK_ROOT40_CONTROL[MUX]
CLOCK_ROOT40_CONTROL[DIV] LPCG
cg LPI2C4_CLK_ROOT cg
LPCG101
CLOCK_ROOT41_CONTROL[MUX]
CLOCK_ROOT41_CONTROL[DIV]
LPI2C5_CLK_ROOT cg
cg
LPCG102
CLOCK_ROOT42_CONTROL[MUX]
CLOCK_ROOT42_CONTROL[DIV]
cg LPI2C6_CLK_ROOT cg
CLOCK_ROOT43_CONTROL[MUX]
LPCG103
CLOCK_ROOT43_CONTROL[DIV] LPSPI1_CLK_ROOT
cg
cg
LPCG104
CLOCK_ROOT44_CONTROL[MUX]
CLOCK_ROOT44_CONTROL[DIV]
LPSPI2_CLK_ROOT
cg cg
LPCG105
CLOCK_ROOT45_CONTROL[MUX]
CLOCK_ROOT45_CONTROL[DIV]
LPSPI3_CLK_ROOT
cg
cg
LPCG106
CLOCK_ROOT46_CONTROL[MUX]
CLOCK_ROOT46_CONTROL[DIV]
LPSPI4_CLK_ROOT
cg
cg
LPCG107
CLOCK_ROOT47_CONTROL[MUX]
CLOCK_ROOT47_CONTROL[DIV]
LPSPI5_CLK_ROOT
cg cg
LPCG108
CLOCK_ROOT48_CONTROL[MUX]
CLOCK_ROOT48_CONTROL[DIV]
LPSPI6_CLK_ROOT
cg cg
LPCG109
CLOCK_ROOT49_CONTROL[MUX]
CLOCK_ROOT49_CONTROL[DIV]
EMV1_CLK_ROOT cg
cg
LPCG110
CLOCK_ROOT50_CONTROL[MUX]
CLOCK_ROOT50_CONTROL[DIV]
cg EMV2_CLK_ROOT cg
LPCG111
CLOCK_ROOT51_CONTROL[MUX]
CLOCK_ROOT51_CONTROL[DIV]
ENET1_CLK_ROOT cg
cg
LPCG112
CLOCK_ROOT52_CONTROL[MUX]
CLOCK_ROOT52_CONTROL[DIV]
cg ENET2_CLK_ROOT cg
CLOCK_ROOT53_CONTROL[MUX] LPCG113
CLOCK_ROOT53_CONTROL[DIV]
ENET_QOS_CLK_ROOT cg
cg
LPCG114
CLOCK_ROOT54_CONTROL[MUX]
CLOCK_ROOT54_CONTROL[DIV]
cg
ENET_25M_CLK_ROOT
CLOCK_ROOT55_CONTROL[MUX]
CLOCK_ROOT55_CONTROL[DIV]
ENET_TIMER1_CLK_ROOT cg
cg
LPCG112
CLOCK_ROOT56_CONTROL[MUX]
CLOCK_ROOT56_CONTROL[DIV]
ENET_TIMER2_CLK_ROOT cg
cg
LPCG113
CLOCK_ROOT57_CONTROL[MUX] CLOCK_ROOT57_CONTROL[DIV]
cg
ENET_TIMER3_CLK_ROOT cg
LPCG114
CLOCK_ROOT58_CONTROL[MUX]
CLOCK_ROOT58_CONTROL[DIV]
USDHC1_CLK_ROOT
cg
cg
CLOCK_ROOT59_CONTROL[MUX]
LPCG117
CLOCK_ROOT59_CONTROL[DIV]
USDHC2_CLK_ROOT
cg
cg
LPCG118
OSC_RC_48M_DIV2
SYS_PLL3_PFD1
SYS_PLL2_PFD1
SYS_PLL3_PFD2
SYS_PLL2_PFD2
SYS_PLL3_PFD3
SYS_PLL2_PFD3
SYS_PLL3_PFD0
SYS_PLL2_PFD0
SYS_PLL3_DIV2
SYS_PLL1_DIV2
SYS_PLL1_DIV5
SYS_PLL3_OUT
SYS_PLL1_CLK
SYS_PLL2_CLK
OSC_RC_400M
OSC_RC_48M
OSC_RC_16M
PLL_AUDIO
PLL_VIDEO
OSC_24M
PLL_ARM
OSC_32K
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Clock Tree
CLOCK_ROOT60_CONTROL[MUX]
CLOCK_ROOT60_CONTROL[DIV] LPCG
cg ASRC_CLK_ROOT cg
LPCG119
CLOCK_ROOT61_CONTROL[MUX]
CLOCK_ROOT61_CONTROL[DIV]
MQS_CLK_ROOT cg
cg
LPCG119
CLOCK_ROOT62_CONTROL[MUX]
CLOCK_ROOT62_CONTROL[DIV] LPCG120
cg MIC_CLK_ROOT cg
LPCG119
LPCG121
CLOCK_ROOT63_CONTROL[MUX] LPCG122
CLOCK_ROOT63_CONTROL[DIV] SPDIF_CLK_ROOT
cg cg
LPCG122
CLOCK_ROOT64_CONTROL[MUX]
CLOCK_ROOT64_CONTROL[DIV] SAI1_CLK_ROOT
cg cg
LPCG122
CLOCK_ROOT65_CONTROL[MUX] LPCG123
CLOCK_ROOT65_CONTROL[DIV]
SAI2_CLK_ROOT
cg
cg
LPCG122
CLOCK_ROOT66_CONTROL[MUX] LPCG124
CLOCK_ROOT66_CONTROL[DIV] LPCG119
SAI3_CLK_ROOT
cg
cg
LPCG120
LPCG122
CLOCK_ROOT67_CONTROL[MUX] LPCG125
CLOCK_ROOT67_CONTROL[DIV] LPCG119
SAI4_CLK_ROOT
cg cg
LPCG122
CLOCK_ROOT68_CONTROL[MUX] LPCG126
CLOCK_ROOT68_CONTROL[DIV] LPCG119
GPU2D_CLK_ROOT
cg
CLOCK_ROOT69_CONTROL[MUX]
CLOCK_ROOT69_CONTROL[DIV]
ELCDIF_CLK_ROOT cg
cg
LPCG129
CLOCK_ROOT70_CONTROL[MUX]
CLOCK_ROOT70_CONTROL[DIV]
cg LCDIFV2_CLK_ROOT cg
LPCG130
CLOCK_ROOT71_CONTROL[MUX]
CLOCK_ROOT71_CONTROL[DIV]
MIPI_REF_CLK_ROOT cg
cg
LPCG131
CLOCK_ROOT72_CONTROL[MUX]
CLOCK_ROOT72_CONTROL[DIV]
cg MIPI_ESC_CLK_ROOT cg
CLOCK_ROOT73_CONTROL[MUX]
LPCG131
CLOCK_ROOT73_CONTROL[DIV]
cg CSI2_CLK_ROOT cg
LPCG132
CLOCK_ROOT74_CONTROL[MUX]
CLOCK_ROOT74_CONTROL[DIV]
cg
CSI2_ESC_CLK_ROOT cg
LPCG132
CLOCK_ROOT75_CONTROL[MUX]
CLOCK_ROOT75_CONTROL[DIV]
CSI2_UI_CLK_ROOT cg
cg
LPCG132
CLOCK_ROO76_CONTROL[MUX]
CLOCK_ROOT76_CONTROL[DIV]
CSI_CLK_ROOT
cg
CLOCK_ROOT77_CONTROL[MUX]
CLOCK_ROO77_CONTROL[DIV]
cg CCM_CLKO1_CLK_ROOT
CLOCK_ROOT78_CONTROL[MUX]
CLOCK_ROOT78_CONTROL[DIV]
cg CCM_CLKO2_CLK_ROOT
OSC_RC_48M_DIV2
SYS_PLL3_PFD1
SYS_PLL2_PFD1
SYS_PLL3_PFD2
SYS_PLL2_PFD2
SYS_PLL3_PFD3
SYS_PLL2_PFD3
SYS_PLL3_PFD0
SYS_PLL2_PFD0
SYS_PLL3_DIV2
SYS_PLL1_DIV2
SYS_PLL1_DIV5
SYS_PLL3_OUT
SYS_PLL1_CLK
SYS_PLL2_CLK
OSC_RC_400M
OSC_RC_48M
OSC_RC_16M
PLL_AUDIO
PLL_VIDEO
OSC_24M
PLL_ARM
OSC_32K
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Chapter 15 Clock Controller Module (CCM)
15.5 Functional description
The following sections describe the functionality of CCM:
• Clock Source
• Clock Root
• Clock Gate
• Clock Group
• General Purpose Registers (GPR)
15.5.1 CCM Modes
CCM functional blocks support the following modes:
• Unassigned Mode
• Domain Mode
• CPU Low Power Mode (CPULPM)
• Setpoint Mode
NOTE
In any of the modes, every register in any Domain is readable.
But write access will be restricted for protection.
15.5.1.1 Unassigned Mode
If a clock is not assigned to Domain or Setpoint Mode or CPU Low Power Mode, it
automatically assumes Unassigned Mode. After reset, all clock sources, clock roots,
clock gates, and clock groups remain in Unassigned Mode.
In Unassigned Mode, Domain access control scheme is disabled, but Trustzone access
control is still active.
Clock Source
In Unassigned Mode, clock source setting comes from OSCPLLn_DIRECT registers
(PLL/OSC is required to function in GPC mode). These register can only be accessed in
Unassigned Mode if Trustzone authentication is passed. They have no effect in CPULPM
or Setpoint Mode and are not writable in these modes.
Clock Root
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Functional description
In this mode, the clock root setting comes from the CLOCK_ROOTn_CONTROL
registers. These registers can only be accessed in Unassigned Mode if Trustzone
authentication is passed.
Clock Group
In Unassigned Mode, the clock group setting comes from
CLOCK_GROUPn_CONTROLregisters. These registers can be modified from any
domain in Unassigned Mode after passing Trustzone authentication.
Clock Gate (LPCG)
For this mode, the clock gate setting comes from the LPCGn_DIRECT registers. These
register can only be accessed in Unassigned Mode if Trustzone authentication is passed.
They cannot be modified or will not have any effect in CPULPM or Setpoint Mode.
15.5.1.2 Domain Mode
In Domain Mode, domain access control is enabled.
Clock Source
In this mode, clock source setting comes from OSCPLLn_DIRECT register. This register
can only be accessed if Trustzone authentication is passed and access comes from domain
in Whitelist. This register have no effect in CPU Low Power Mode and Setpoint Mode
and is not writable.
Clock Root
In this mode, the Domain based authentication is activated and only domains on the
Whitelist can change the value of the CLOCK_ROOTn_CONTROL register.
Clock Group
In this mode, the clock group setting comes from CLOCK_GROUPn_CONTROL. Since
Domain based authentication is active in this mode, only the domains available on the
Whitelist can modify these registers.
Clock Gate (LPCG)
For this mode, the clock gate setting come from the LPCGn_DIRECT register. This
register can only be accessed in if Trustzone authentication is passed and access comes
from domain in Whitelist. This register cannot be modified or will not have any effect in
CPU Low Power Mode or Setpoint Mode.
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Chapter 15 Clock Controller Module (CCM)
NOTE
The Domain setting register can be written from any domain in
Unassigned Mode, but need to pass Trustzone authentication.
15.5.1.3 CPU Low Power Mode (CPULPM)
The CPU Low power Mode will control the OSC/PLL/LPCG according to the low power
signal from the GPC.
Clock Source
In this mode, there are 3-bit fields in OSCPLLn_DOMAIN register, which helps select
the clock source dependency level for each CPU platform. The valid values are as
follows:
• 0: This clock source is not needed in any mode
• 1: This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
• 2: This clock source is needed in RUN and WAIT mode, but not needed in STOP
mode
• 3: This clock source is needed in RUN, WAIT and STOP mode
• 4: this clock source is needed in RUN, WAIT, STOP and SUSPEND mode
Clock Root
Clock Root does not support this mode.
Clock Group
Clock Group does not support this mode.
Clock Gate (LPCG)
There are 3-bit clock dependent levels setting for each CPU platform in the register
LPCGn_DOMAIN. The valid values are the same as the values shown for clock source.
The clock gate calculates whether the clock is dependent for each CPU platform and if
not required, it will be shut down.
15.5.1.4 Setpoint Mode
Clock Source
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Functional description
The Setpoint registers define 16 work points of clock source using 16 bits for system
work modes through OSCPLLn_SETPOINT registers.
As the system work mode transitions from one Setpoint to another, the clock source will
look up the corresponding value and source the clock according to the response on the
request from General Power Controller (GPC).
Clock Root
For clock roots running in this mode, the CLOCK_ROOTn_CONTROL register does not
affect the clock root, and all the write access will be blocked.
The Setpoint registers define 16 work points of clock roots using 16 bits for system work
modes. As the system work mode transition from one Setpoint to another, the clock root
will look up corresponding value and changes the clock root setting to the value
requested by GPC.
Please refer to CLOCK_ROOTn_SETPOINTm register to see which clock roots support
Setpoints.
Speed Grade:
In Setpoints, speed grade information needs to be provided for clock root channel through
CLOCK_ROOTn_SETPOINTm. The clock channel uses this information to determine
whether to change the clock setting before or after a change in system supply voltage. A
smaller grade value refers to faster clock speed.
Speed grade is being used by Setpoint logic to determine whether the clock is
transitioning up or down between a Setpoint transition. Setpoint logic handles
relationship between other components, such as power control. Each Setpoint setting is
associated with a speed grade setting. A smaller speed grade value indicates higher speed.
For example, the value of 0 refers to the fastest clock and the value of 15 refers to the
slowest clock. For Setpoint setting with same speed, speed grade relation can be any or
higher, lower or equal.
Clock Group
In this mode, the CLOCK_GROUPn_CONTROL registers do not affect the clock group
and all write access is blocked.
The Setpoint registers define 16 work points of clock channel for system work modes. As
the system work mode transition from one Setpoint to another, clock group will look up
the corresponding value and change the clock group setting to the corresponding value
requested from GPC.
In Setpoints, speed grade information needs to be provided for clock root channel through
CLOCK_ROOTn_SETPOINTm.
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Chapter 15 Clock Controller Module (CCM)
Clock Gate (LPCG)
The Setpoint registers define 16 work points of clock gate for system work modes. As the
system work mode transition from one Setpoint to another, clock gate will look up
corresponding value and change the clock gate setting to the corresponding value
requested from GPC.
In Setpoint Mode, the Domain setting register will not affect clock source, and all write
access is blocked.
NOTE
These registers can only be changed in Unassigned Mode after
passing Trustzone authentication.
After the clock channel, source, root, or gate is assigned to
Setpoint Mode, the registers cannot be changed by application.
If application needs to change the Setpoint value, the clock
channel should be switched to Unassigned Mode.
15.5.2 Clock Sources
Clock roots are generated from various clock sources, which can be either oscillators or
PLLs. Clock sources are implemented to control PLLs and oscillators by automatically
turning them OFF or ON on system low power actions.
The following table shows the clock sources and the associated control registers.
Table 15-3. Clock Sources
Control Register Clock Source Typical PFD value Description
OSCPLL0 OSC_RC_16M - 16MHz RC OSC Output
OSCPLL1 OSC_RC_48M - 48MHz RC OSC Output
OSCPLL2 OSC_RC_48M_DIV2 - 48MHz divided by 2 clock output
OSCPLL3 OSC_RC_400M - 400MHz RC OSC output
OSCPLL4 OSC_24M - VCO (Not connected to the clock tree)
OSCPLL5 OSC_24M_CLK - 24MHz main output clock
OSCPLL6 ARM_PLL - VCO (Not connected to the clock tree)
OSCPLL7 ARM_PLL_CLK 4 ARM PLL main output clock
OSCPLL8 SYS_PLL2 - VCO (Not connected to the clock tree)
OSCPLL9 SYS_PLL2_CLK 1 System PLL2 main output clock
OSCPLL10 SYS_PLL2_PFD0 27 System PLL2 PFD0 clock
OSCPLL11 SYS_PLL2_PFD1 16 System PLL2 PFD1 clock
Table continues on the next page...
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Functional description
Table 15-3. Clock Sources (continued)
Control Register Clock Source Typical PFD value Description
OSCPLL12 SYS_PLL2_PFD2 24 System PLL2 PFD2 clock
OSCPLL13 SYS_PLL2_PFD3 32 System PLL2 PFD3 clock
OSCPLL14 SYS_PLL3 - VCO (Not connected to the clock tree)
OSCPLL15 SYS_PLL3_CLK 1 System PLL3 main output
OSCPLL16 SYS_PLL3_DIV2 2 System PLL3 divided by 2 clock
OSCPLL17 SYS_PLL3_PFD0 13 System PLL3 PFD0 clock
OSCPLL18 SYS_PLL3_PFD1 17 System PLL3 PFD1 clock
OSCPLL19 SYS_PLL3_PFD2 32 System PLL3 PFD2 clock
OSCPLL20 SYS_PLL3_PFD3 24 System PLL3 PFD3 clock
OSCPLL21 SYS_PLL1 - VCO (Not connected to the clock tree)
OSCPLL22 SYS_PLL1_CLK 1 System PLL1 main clock output
OSCPLL23 SYS_PLL1_DIV2 2 System PLL1 divided by 2 clock
OSCPLL24 SYS_PLL1_DIV5 5 System PLL1 divided by 5 clock
OSCPLL25 AUDIO_PLL - VCO (Not connected to the clock tree)
OSCPLL26 AUDIO_PLL_CLK - Audio PLL main clock
OSCPLL27 VIDEO_PLL - VCO (Not connected to the clock tree)
OSCPLL28 VIDEO_PLL_CLK - Video PLL main clock output
NOTE
The clock source calculates whether the clock is required for
each CPU domain. If clock source is not needed for any
domain, clock will be shutdown.
The typical PDF value for AUDIO_PLL_CLK and
VIDEO_PLL_CLK depends on the user application.
15.5.3 Clock Root
CCM clock root generation contains multiple clock root channels. All clock roots are
asynchronous, even when all the clock root setting are the same.
All clock channel contains an 8-to-1 MUX, and an 8-bit divider. The clock MUX selects
1 clock out of 8 clock inputs. The 8-bit divider can divide selected clock by up to 256.
The clock output of the clock channel can be gated off.
The clock root channel setting can be changed from any value to any value, and at any
time. It is also possible to change the clock setting when the clock root channel is gating
off. If more than one setting is changed at the same time, internal logic will use a
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Chapter 15 Clock Controller Module (CCM)
procedure to change the setting. The procedure will make sure the clock output is not
faster than the current clock root setting or target clock root setting. If the application
does care about the clock during transition, software will need to change the setting one
field at a time. This typically happens when a clock must be faster than the given
frequency. In this case, the application needs to change each field one at a time and wait
for the field to take effect before changing the next field.
Although a clock root channel is designed to be able to switch clocks regardless of clock
input status. When the current selected clock input is off, the application needs to avoid
changing the clock MUX after the clock input is turned on. This will lead to unstable
behavior for the clock root and loading peripherals (peripherals driven by a clock). To
avoid this scenario, the application can either switch the clock MUX before turning on
the clock input, or wait until the clock input is stable before changing the MUX option.
The clock root channels have 3 working modes, Unassigned Mode, Domain Mode, and
Setpoint Mode. Unassigned Mode is an implicit mode, if a clock channel is not assigned
to Domain or Setpoint Mode, it defaults to Unassigned Mode. After reset, all clock root
channels are in Unassigned Mode.
All registers are readable for any Domain in any mode, but write access are restricted. In
Unassigned Mode, Domain access control scheme is disabled, but Trustzone access
control is still active. In Unassigned Mode and Domain Mode, the clock root setting
comes from the CLOCK_ROOTn_CONTROL register. This register can be written from
any Domain in Unassigned Mode, but needs to pass Trustzone authentication.
In Domain control Mode, Domain based authentication is activate and only the Domain
on the Whitelist can change the value of CLOCK_ROOTn_CONTROL register. In
Setpoint Mode, this register does not affect the clock root, and all write access will be
blocked. CLOCK_ROOTn_SETPOINT registers define 16 work points of the clock
channel for system work modes. As system work mode transitions from one Setpoint to
another, the clock root will look up the corresponding value and will change the clock
root setting to the value requested from GPC. These registers can only be changed in
Unassigned Mode, after passing Trustzone authentication.
After the clock channel is assigned to Setpoint Mode, CLOCK_ROOTn_SETPOINT
registers cannot be changed by the application. If the application needs to change the
Setpoint value, Unassigned Mode needs to be switched to, before doing any modification.
In Setpoints, speed grade information needs to be provided for the clock root channel.
The table below shows the Clock roots and the associated control registers.
UD, NM and OD represent Under-drive, Nominal, and Over-drive frequencies.
If 'SP' is blank, Setpoint is present, and if 'SP' is N, Setpoint is not present.
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Functional description
Table 15-4. Clock Roots
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
CLOCK_ROOT0 M7_CLK_ROOT 240 700 1000 000 - OSC_RC_48M_DIV2
600 +ECC 800 +ECC 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - PLL_ARM_CLK
101 - SYS_PLL1_CLK
110 - SYS_PLL3_CLK
111 - VIDEO_PLL_CLK
CLOCK_ROOT1 M4_CLK_ROOT 120 240 400 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_CLK
111 - SYS_PLL1_DIV5
CLOCK_ROOT2 BUS_CLK_ROOT 100 200 240 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_CLK
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT3 BUS_LPSR_CLK_ROOT 60 120 160 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_CLK
111 - SYS_PLL1_DIV5
CLOCK_ROOT4 SEMC_CLK_ROOT 132 200 200 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV5
101 - SYS_PLL2_CLK
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
110 - SYS_PLL2_PFD1
111 - SYS_PLL3_PFD0
CLOCK_ROOT5 CSSYS_CLK_ROOT 66 132 132 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT6 CSTRACE_CLK_ROOT 88 132 132 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_PFD1
111 - SYS_PLL2_CLK
CLOCK_ROOT7 M4_SYSTICK_CLK_ROO 50 50 50 N 000 - OSC_RC_48M_DIV2
T 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD0
111 - SYS_PLL1_DIV5
CLOCK_ROOT8 M7_SYSTICK_CLK_ROO 50 50 50 N 000 - OSC_RC_48M_DIV2
T 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL3_DIV2
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD0
CLOCK_ROOT9 ADC1_CLK_ROOT 66 88 88 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT10 ADC2_CLK_ROOT 66 88 88 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT11 ACMP_CLK_ROOT 240 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_CLK
101 - SYS_PLL1_DIV5
110 - AUDIO_PLL_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT12 FLEXIO1_CLK_ROOT 80 120 120 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT13 FLEXIO2_CLK_ROOT 80 120 120 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT14 GPT1_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL3_PFD2
111 - SYS_PLL3_PFD3
CLOCK_ROOT15 GPT2_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - AUDIO_PLL_CLK
111 - VIDEO_PLL_CLK
CLOCK_ROOT16 GPT3_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - AUDIO_PLL_CLK
111 - VIDEO_PLL_CLK
CLOCK_ROOT17 GPT4_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL3_PFD2
111 - SYS_PLL3_PFD3
CLOCK_ROOT18 GPT5_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL3_PFD2
111 - SYS_PLL3_PFD3
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
CLOCK_ROOT19 GPT6_CLK_ROOT 80 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL3_PFD2
111 - SYS_PLL3_PFD3
CLOCK_ROOT20 FLEXSPI1_CLK_ROOT 111 332 332 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD0
101 - SYS_PLL2_CLK
110 - SYS_PLL2_PFD2
111 - SYS_PLL3_CLK
CLOCK_ROOT21 FLEXSPI2_CLK_ROOT 111 332 332 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD0
101 - SYS_PLL2_CLK
110 - SYS_PLL2_PFD2
111 - SYS_PLL3_CLK
CLOCK_ROOT22 CAN1_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT23 CAN2_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT24 CAN3_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD3
111 - SYS_PLL1_DIV5
CLOCK_ROOT25 LPUART1_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT26 LPUART2_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT27 LPUART3_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT28 LPUART4_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT29 LPUART5_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT30 LPUART6_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT31 LPUART7_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT32 LPUART8_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT33 LPUART9_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT34 LPUART10_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT35 LPUART11_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD3
111 - SYS_PLL1_DIV5
CLOCK_ROOT36 LPUART12_CLK_ROOT 80 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD3
111 - SYS_PLL1_DIV5
CLOCK_ROOT37 LPI2C1_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
CLOCK_ROOT38 LPI2C2_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT39 LPI2C3_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT40 LPI2C4_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT41 LPI2C5_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD3
111 - SYS_PLL1_DIV5
CLOCK_ROOT42 LPI2C6_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
110 - SYS_PLL2_PFD3
111 - SYS_PLL1_DIV5
CLOCK_ROOT43 LPSPI1_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT44 LPSPI2_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT45 LPSPI3_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT46 LPSPI4_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT47 LPSPI5_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL3_PFD2
111 - SYS_PLL1_DIV5
CLOCK_ROOT48 LPSPI6_CLK_ROOT 90 135 135 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - SYS_PLL3_PFD2
111 - SYS_PLL1_DIV5
CLOCK_ROOT49 EMV1_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT50 EMV2_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_DIV2
101 - SYS_PLL1_DIV5
110 - SYS_PLL2_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT51 ENET1_CLK_ROOT 50 50 50 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT52 ENET2_CLK_ROOT 50 125 125 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT53 ENET_QOS_CLK_ROOT 50 125 125 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT54 ENET_25M_CLK_ROOT 50 50 50 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT55 ENET_TIMER1_CLK_RO 100 200 200 N 000 - OSC_RC_48M_DIV2
OT 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT56 ENET_TIMER2_CLK_RO 100 200 200 N 000 - OSC_RC_48M_DIV2
OT 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
CLOCK_ROOT57 ENET_TIMER3_CLK_RO 100 200 200 N 000 - OSC_RC_48M_DIV2
OT 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV2
101 - AUDIO_PLL_CLK
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD1
CLOCK_ROOT58 USDHC1_CLK_ROOT 100 200 200 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL2_PFD0
110 - SYS_PLL1_DIV5
111 - PLL_ARM_CLK
CLOCK_ROOT59 USDHC2_CLK_ROOT 100 400 400 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL2_PFD0
110 - SYS_PLL1_DIV5
111 - PLL_ARM_CLK
CLOCK_ROOT60 ASRC_CLK_ROOT 60 240 240 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV5
101 - SYS_PLL3_DIV2
110 - AUDIO_PLL_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT61 MQS_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL1_DIV5
101 - SYS_PLL3_DIV2
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
110 - AUDIO_PLL_CLK
111 - SYS_PLL2_PFD3
CLOCK_ROOT62 MIC_CLK_ROOT 60 80 80 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - AUDIO_PLL_CLK
111 - SYS_PLL1_DIV5
CLOCK_ROOT63 SPDIF_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - AUDIO_PLL_CLK
101 - SYS_PLL3_CLK
110 - SYS_PLL3_PFD2
111 - SYS_PLL2_PFD3
CLOCK_ROOT64 SAI1_CLK_ROOT 33 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - AUDIO_PLL_CLK
101 - SYS_PLL3_PFD2
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD3
CLOCK_ROOT65 SAI2_CLK_ROOT 33 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - AUDIO_PLL_CLK
101 - SYS_PLL3_PFD2
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD3
CLOCK_ROOT66 SAI3_CLK_ROOT 33 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
100 - AUDIO_PLL_CLK
101 - SYS_PLL3_PFD2
110 - SYS_PLL1_DIV5
111 - SYS_PLL2_PFD3
CLOCK_ROOT67 SAI4_CLK_ROOT 33 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL3_PFD3
101 - SYS_PLL3_CLK
110 - AUDIO_PLL_CLK
111 - SYS_PLL1_DIV5
CLOCK_ROOT68 GPU2D_CLK_ROOT 176 500 500 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL2_PFD1
110 - SYS_PLL3_CLK
111 - VIDEO_PLL_CLK
CLOCK_ROOT69 ELCDIF_CLK_ROOT 82 150 150 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL2_PFD2
110 - SYS_PLL3_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT70 LCDIFV2_CLK_ROOT 82 150 150 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL2_PFD2
110 - SYS_PLL3_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT71 MIPI_REF_CLK_ROOT 133 133 133 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL2_PFD0
110 - SYS_PLL3_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT72 MIPI_ESC_CLK_ROOT 66 133 133 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_CLK
101 - SYS_PLL2_PFD0
110 - SYS_PLL3_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT73 CSI2_CLK_ROOT 133 200 200 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT74 CSI2_ESC_CLK_ROOT 133 133 133 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD0
111 - VIDEO_PLL_CLK
CLOCK_ROOT75 CSI2_UI_CLK_ROOT 200 200 200 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL3_CLK
110 - SYS_PLL2_PFD0
111 - VIDEO_PLL_CLK
Table continues on the next page...
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Functional description
Table 15-4. Clock Roots (continued)
Control Register Clock Roots Max Frequency (MHz) SP Source Select
UD NM OD (FBB) (CLOCK_ROOTn_CONTRO
L[MUX])
CLOCK_ROOT76 CSI_CLK_ROOT 66 66 66 N 000 - OSC_RC_48M_DIV2
001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL3_CLK
110 - SYS_PLL3_PFD1
111 - VIDEO_PLL_CLK
CLOCK_ROOT77 CCM_CLKO1_CLK_ROO 120 120 120 000 - OSC_RC_48M_DIV2
T 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD2
101 - SYS_PLL2_CLK
110 - SYS_PLL3_PFD1
111 - SYS_PLL1_DIV5
CLOCK_ROOT78 CCM_CLKO2_CLK_ROO 200 200 200 000 - OSC_RC_48M_DIV2
T 001 - OSC_24M
010 - OSC_RC_400M
011 - OSC_RC_16M
100 - SYS_PLL2_PFD3
101 - OSC_RC_48M
110 - SYS_PLL3_PFD1
111 - AUDIO_PLL_CLK
NOTE
The frequency values of the cores are dependent on the part
configuration. Please see the datasheet for supported core
frequencies.
15.5.4 Clock Gate
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Chapter 15 Clock Controller Module (CCM)
Before a clock root goes to on-chip peripherals, the clock roots go through the Low
Power Clock Gates (LPCG). These LPCGs are implemented to perform automatic clock
gating when a domain enters or leaves low-power states. LPCGs are implemented to
control peripheral functions. Different LPCGs could interface different clocks of the
same peripheral.
Clock gates implements four modes: Unassigned Mode, Domain Mode, CPU Low Power
Mode, and Setpoint Mode. Unassigned Mode is an implicit mode. If a clock gate is not
assigned to Domain, Setpoint Mode or CPU Low Power Mode, the default mode is
Unassigned Mode. After reset, all clock gates work in Unassigned Mode. All registers are
readable for any domain in any mode, but write access is restricted for protection. In
Unassigned Mode, Domain access control scheme is disabled, but Trustzone access
control is still active.
In Unassigned Mode, clock gate settings come from LPCGn_DIRECT registers.
Application can only change clock gate status by accessing LPCGn_DIRECT registers.
These can only be accessed in Unassigned Mode if Trustzone authentication was passed.
LPCGn_DIRECT registers have no effect and are not writable in CPULPM or Setpoint
Mode.
In Domain Mode, the clock gate setting come from the LPCGn_DIRECT register. This
register can only be accessed in if Trustzone authentication is passed and access comes
from domain in Whitelist.
In CPULPM, there are 3-bit clock dependent level settings for each CPU platform in the
LPCGx_DOMAIN registers. The bigger the 3-bit value is, the stronger the clock
dependency. Valid values are as follows:
• 0: This clock is not needed in any mode
• 1: This clock is needed in RUN mode, but not needed in WAIT, STOP mode
• 2: This clock is needed in RUN and WAIT mode, but not needed in STOP mode
• 3: This clock is needed in RUN, WAIT and STOP mode
• 4: This clock is always on in any mode (including SUSPEND)
NOTE
The clock gates calculate whether the clock is dependent for
each CPU Domain. If clock is not needed for any domain, the
clock will be shutdown. The Domain setting register can be
written from any domain in Unassigned Mode, but needs to
pass Trustzone authentication. In Domain control Mode, the
Domain setting register is locked and not changeable. If the
application needs to change the Domain setting, it should
switch the clock gate back into Unassigned Mode. In Setpoint
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Functional description
Mode, the Domain register does not affect the clock gate, and
all write accesses are blocked.
The Setpoint registers define 16 work points of the clock gates by 16 register bits for
system work modes. As the work modes transition from one Setpoint to another, the
clock gate will look up corresponding value and will gate the clock according to the value
requested by GPC. These registers can only be changed in Unassigned Mode, after
passing Trustzone authentication. After the clock gate is assigned to Setpoint Mode,
Setpoint registers cannot be changed by the application. If the application needs to
change Setpoint value, the clock gate must be switched to Unassigned Mode as a first
step.
Table 15-5. Clock Gate Table
Gating Registers LPCG Enable
LPCG0 clk_enable_cm7
LPCG1 clk_enable_cm4
LPCG2 clk_enable_sim_m7
LPCG3 clk_enable_sim_m
LPCG4 clk_enable_sim_disp
LPCG5 clk_enable_sim_per
LPCG6 clk_enable_sim_lpsr
LPCG7 clk_enable_anadig
LPCG8 clk_enable_dcdc
LPCG9 clk_enable_src
LPCG10 clk_enable_ccm
LPCG11 clk_enable_gpc
LPCG12 clk_enable_ssarc
LPCG13 clk_enable_sim_r
LPCG14 clk_enable_wdog1
LPCG15 clk_enable_wdog2
LPCG16 clk_enable_wdog3
LPCG17 clk_enable_wdog4
LPCG18 clk_enable_ewm
LPCG19 clk_enable_sema
LPCG20 clk_enable_mu_a
LPCG21 clk_enable_mu_b
LPCG22 clk_enable_edma
LPCG23 clk_enable_edma_lpsr
LPCG24 clk_enable_romcp
LPCG25 clk_enable_ocram
LPCG26 clk_enable_flexram
LPCG27 clk_enable_lpsrmem
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-5. Clock Gate Table (continued)
Gating Registers LPCG Enable
LPCG28 clk_enable_flexspi1
LPCG29 clk_enable_flexspi2
LPCG30 clk_enable_rdc
LPCG31 clk_enable_m7_xrdc
LPCG32 clk_enable_m4_xrdc
LPCG33 clk_enable_semc
LPCG34 clk_enable_xecc
LPCG35 clk_enable_iee
LPCG36 clk_enable_key_manager
LPCG37 clk_enable_ocotp
LPCG38 clk_enable_snvs_hp
LPCG39 clk_enable_snvs
LPCG40 clk_enable_caam
LPCG41 clk_enable_jtag_mux
LPCG42 clk_enable_cstrace
LPCG43 clk_enable_xbar1
LPCG44 clk_enable_xbar2
LPCG45 clk_enable_xbar3
LPCG46 clk_enable_aoi1
LPCG47 clk_enable_aoi2
LPCG48 clk_enable_adc_etc
LPCG49 clk_enable_iomuxc
LPCG50 clk_enable_iomuxc_lpsr
LPCG51 clk_enable_gpio
LPCG52 clk_enable_kpp
LPCG53 clk_enable_flexio1
LPCG54 clk_enable_flexio2
LPCG55 clk_enable_adc1
LPCG56 clk_enable_adc2
LPCG57 clk_enable_dac
LPCG58 clk_enable_acmp1
LPCG59 clk_enable_acmp2
LPCG60 clk_enable_acmp3
LPCG61 clk_enable_acmp4
LPCG62 clk_enable_pit1
LPCG63 clk_enable_pit2
LPCG64 clk_enable_gpt1
LPCG65 clk_enable_gpt2
LPCG66 clk_enable_gpt3
Table continues on the next page...
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Functional description
Table 15-5. Clock Gate Table (continued)
Gating Registers LPCG Enable
LPCG67 clk_enable_gpt4
LPCG68 clk_enable_gpt5
LPCG69 clk_enable_gpt6
LPCG70 clk_enable_qtimer1
LPCG71 clk_enable_qtimer2
LPCG72 clk_enable_qtimer3
LPCG73 clk_enable_qtimer4
LPCG74 clk_enable_enc1
LPCG75 clk_enable_enc2
LPCG76 clk_enable_enc3
LPCG77 clk_enable_enc4
LPCG78 Reserved
LPCG79 clk_enable_flexpwm1
LPCG80 clk_enable_flexpwm2
LPCG81 clk_enable_flexpwm3
LPCG82 clk_enable_flexpwm4
LPCG83 clk_enable_can1
LPCG84 clk_enable_can2
LPCG85 clk_enable_can3
LPCG86 clk_enable_lpuart1
LPCG87 clk_enable_lpuart2
LPCG88 clk_enable_lpuart3
LPCG89 clk_enable_lpuart4
LPCG90 clk_enable_lpuart5
LPCG91 clk_enable_lpuart6
LPCG92 clk_enable_lpuart7
LPCG93 clk_enable_lpuart8
LPCG94 clk_enable_lpuart9
LPCG95 clk_enable_lpuart10
LPCG96 clk_enable_lpuart11
LPCG97 clk_enable_lpuart12
LPCG98 clk_enable_lpi2c1
LPCG99 clk_enable_lpi2c2
LPCG100 clk_enable_lpi2c3
LPCG101 clk_enable_lpi2c4
LPCG102 clk_enable_lpi2c5
LPCG103 clk_enable_lpi2c6
LPCG104 clk_enable_lpspi1
LPCG105 clk_enable_lpspi2
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Table 15-5. Clock Gate Table (continued)
Gating Registers LPCG Enable
LPCG106 clk_enable_lpspi3
LPCG107 clk_enable_lpspi4
LPCG108 clk_enable_lpspi5
LPCG109 clk_enable_lpspi6
LPCG110 clk_enable_sim1
LPCG111 clk_enable_sim2
LPCG112 clk_enable_enet
LPCG113 clk_enable_enet_1g
LPCG114 clk_enable_enet_qos
LPCG115 clk_enable_usb
LPCG116 clk_enable_cdog
LPCG117 clk_enable_usdhc1
LPCG118 clk_enable_usdhc2
LPCG119 clk_enable_asrc
LPCG120 clk_enable_mqs
LPCG121 clk_enable_mic
LPCG122 clk_enable_spdif
LPCG123 clk_enable_sai1
LPCG124 clk_enable_sai2
LPCG125 clk_enable_sai3
LPCG126 clk_enable_sai4
LPCG127 clk_enable_pxp
LPCG128 clk_enable_gpu2d
LPCG129 clk_enable_elcdif
LPCG130 clk_enable_lcdifv2
LPCG131 clk_enable_mipi_dsi
LPCG132 clk_enable_mipi_csi
LPCG133 clk_enable_csi
LPCG134 clk_enable_dcic_mipi
LPCG135 clk_enable_dcic_lcd
LPCG136 clk_enable_video_mux
15.5.5 Clock Group
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Functional description
Clock group creates a divided clock for a secondary clock input or a peripheral. The
generated clock is synchronized to its parent clock. Each group contains a 4-bit clock
divider which can divide up to 16. There is an 8-bit reset divider on clock divider. Clock
divider will be synchronized on reset divider overflow. Reset divider and clock divider
should be set in same write operation.
There are 2 clock groups in this chip as shown in the table below. Flexram clock group
generates flexram AXI port clock, and the mipi_esc clock group generates mipi esc
clock.
Each clock supports a 4-bit divider, which can divide down by 16. In a clock group, a
restart cycle needs to be set. This restart cycle value should be a common multiple of all
dividers in the clock group.
NOTE
If the wrong restart cycle value is set, the group behaviour will
become unpredictable and the clocks cannot be recovered even
after writing the correct value.
Each clock group contains a Manage counter. The figure below shows the manage
counter and the group controls.
CM7 PLATFORM
M7_CLK_ROOT
CLOCK_GROUPn_CONTROL[DIV0] FLEXRAM CLOCK
CLOCK_GROUPn_CONTROL[RSTDIV]
mipi_dsi_RxClkEsc
MIPI_ESC_CLK_ROOT
CLOCK_GROUPn_CONTROL[DIV0] mipi_dsi_TxClkEsc
CLOCK_GROUPn_CONTROL[RSTDIV]
The clock group setting can be changed from any value to another value at any time. It
can also be changed while the clock group is gated OFF. The clock group will update the
setting on restart counter overflow. However, the clock group will take a few cycles to
complete the action due to synchronous signal generation.
The clock groups can work in all modes.
The following table lists the clock groups.
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Chapter 15 Clock Controller Module (CCM)
Control Register Clock Group
CLOCK_GROUP0 flexram_clk_group
CLOCK_GROUP1 mipi_esc_clk_group
15.5.6 Clock Observe
The clock observe slices are used to observe on-chip clocks or signals. Each observe
channel contains a 512-to-1 MUX, an inverter, and an 8-bit divider. The clock MUX
selects one observe signal out of 512 inputs. The 8-bit divider can divide the selected
clock by up to 256. The inverter is selectable by software. If any of the settings change,
the logic will be automatically reset. However, if the settings remain unchanged, a reset
can be forced by writing "1" to OBSERVEn_CONTROL[RESET]. The table below
shows the target signal, selection index, and the slice number. The target signal can be
observed at associated slice number when the corresponding index is selected via
OBSERVEn_CONTROL[SELECT].
NOTE
The observe functionality is for debug purposes only, and the
accuracy is not guaranteed. Use of this field should be limited
to room temperature, and frequency limited to less than 400
MHz.
Target SELECT index Slice Number
M7_CLK_ROOT 128 4
M4_CLK_ROOT 129 0
BUS_CLK_ROOT 130 2
BUS_LPSR_CLK_ROOT 131 0
SEMC_CLK_ROOT 132 2
CSSYS_CLK_ROOT 133 2
CSTRACE_CLK_ROOT 134 2
M4_SYSTICK_CLK_ROOT 135 0
M7_SYSTICK_CLK_ROOT 136 2
ADC1_CLK_ROOT 137 2
ADC2_CLK_ROOT 138 2
ACMP_CLK_ROOT 139 2
FLEXIO1_CLK_ROOT 140 2
FLEXIO2_CLK_ROOT 141 2
GPT1_CLK_ROOT 142 2
GPT2_CLK_ROOT 143 2
Table continues on the next page...
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Functional description
Target SELECT index Slice Number
GPT3_CLK_ROOT 144 2
GPT4_CLK_ROOT 145 2
GPT5_CLK_ROOT 146 2
GPT6_CLK_ROOT 147 2
FLEXSPI1_CLK_ROOT 148 2
FLEXSPI2_CLK_ROOT 149 2
CAN1_CLK_ROOT 150 2
CAN2_CLK_ROOT 151 2
CAN3_CLK_ROOT 152 0
LPUART1_CLK_ROOT 153 2
LPUART2_CLK_ROOT 154 2
LPUART3_CLK_ROOT 155 2
LPUART4_CLK_ROOT 156 2
LPUART5_CLK_ROOT 157 2
LPUART6_CLK_ROOT 158 2
LPUART7_CLK_ROOT 159 2
LPUART8_CLK_ROOT 160 2
LPUART9_CLK_ROOT 161 2
LPUART10_CLK_ROOT 162 2
LPUART11_CLK_ROOT 163 0
LPUART12_CLK_ROOT 164 0
LPI2C1_CLK_ROOT 165 2
LPI2C2_CLK_ROOT 166 2
LPI2C3_CLK_ROOT 167 2
LPI2C4_CLK_ROOT 168 2
LPI2C5_CLK_ROOT 169 0
LPI2C6_CLK_ROOT 170 0
LPSPI1_CLK_ROOT 171 2
LPSPI2_CLK_ROOT 172 2
LPSPI3_CLK_ROOT 173 2
LPSPI4_CLK_ROOT 174 2
LPSPI5_CLK_ROOT 175 0
LPSPI6_CLK_ROOT 176 0
EMV1_CLK_ROOT 177 2
EMV2_CLK_ROOT 178 2
ENET1_CLK_ROOT 179 2
ENET2_CLK_ROOT 180 2
ENET_QOS_CLK_ROOT 181 2
ENET_25M_CLK_ROOT 182 2
ENET_TIMER1_CLK_ROOT 183 2
ENET_TIMER2_CLK_ROOT 184 2
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Target SELECT index Slice Number
ENET_TIMER3_CLK_ROOT 185 2
USDHC1_CLK_ROOT 186 2
USDHC2_CLK_ROOT 187 2
ASRC_CLK_ROOT 188 2
MQS_CLK_ROOT 189 2
MIC_CLK_ROOT 190 0
SPDIF_CLK_ROOT 191 2
SAI1_CLK_ROOT 192 2
SAI2_CLK_ROOT 193 2
SAI3_CLK_ROOT 194 2
SAI4_CLK_ROOT 195 0
GPU2D_CLK_ROOT 196 2
ELCDIF_CLK_ROOT 197 2
LCDIFV2_CLK_ROOT 198 2
MIPI_REF_CLK_ROOT 199 2
MIPI_ESC_CLK_ROOT 200 2
CSI2_CLK_ROOT 201 2
CSI2_ESC_CLK_ROOT 202 2
CSI2_UI_CLK_ROOT 203 2
CSI_CLK_ROOT 204 2
CCM_CKO1_CLK_ROOT 205 0
CCM_CKO2_CLK_ROOT 206 2
CM7_CORE_STCLKEN 207 4
CCM_FLEXRAM_CLK_ROOT 208 4
MIPI_DSI_TXESC 209 2
MIPI_DSI_RXESC 210 2
OSC_RC_16M 224 0
OSC_RC_48M 225 0
OSC_RC_48M_DIV2 226 0
OSC_RC_400M 227 0
OSC_24M_OUT 229 0
PLL_ARM_OUT 231 2
SYS_PLL2_OUT 233 2
SYS_PLL2_PFD0 234 2
SYS_PLL2_PFD1 235 2
SYS_PLL2_PFD2 236 2
SYS_PLL2_PFD3 237 2
SYS_PLL3_OUT 239 2
SYS_PLL3_DIV2 240 2
SYS_PLL3_PFD0 241 2
SYS_PLL3_PFD1 242 2
Table continues on the next page...
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Functional description
Target SELECT index Slice Number
SYS_PLL3_PFD2 243 2
SYS_PLL3_PFD3 244 2
SYS_PLL1_OUT 246 2
SYS_PLL1_DIV2 247 2
SYS_PLL1_DIV5 248 2
PLL_AUDIO_OUT 250 2
PLL_VIDEO_OUT 252 2
Observe slice can measure frequency on selected signals or clocks. Each time an observe
signal selection changes, all measurement data will be reset, and the measurement will
restart. During measurement, the register value may change, and read from registers may
not be valid. To get the measurement result, software must turn OFF the observe slice
before the measurement results are read. For frequency measurements, a 32KHz clock is
used as a time reference. The 32KHz clock is divided down to 64Hz resolution. The
measurement unit records the maximum and minimum value that has occurred. The
observe signal can be directly read from the OBSERVEn_STATUS0 register. The clock
root channels have 2 work modes: unassigned mode and domain mode. In both modes,
the clock root setting comes from the OBSERVEn_CONTROL register. In unassigned
mode, this register can be written from any domain, but it needs to pass trustzone
authentication. In domain mode, the domain based authentication is activated, and only
the domains listed in the Whitelist can change the value of the OBSERVEn_CONTROL
register.
NOTE
The observe functionality is for debug purposes only, and the
accuracy is not guaranteed. Use of this field should be limited
to room temperature, and frequency limited to less than 400
MHz.
15.5.7 General Purpose Registers (GPR)
The general purpose registers provide miscellaneous controls and data saving functions.
The GPRs are divided in two regions - shared and private region.
In shared region, all CPU domains access the same registers. If any CPU updates the
value in the shared region, all the other CPU domains can read out the new value. The
registers have an access control bit field to protect it from being changed unexpectedly.
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Chapter 15 Clock Controller Module (CCM)
In private region, each CPU domain has its own register. A CPU domain can only access
registers belonging to itself. Since all the registers share the same address, a CPU domain
will not have access to registers belonging to another CPU domain.
Shared registers have 2 work modes, Unassigned Mode and Domain Mode. Private
registers work in Unassigned Mode only. Whitelist is ignored by private registers.
Unassigned Mode is an implicit mode, if a shared register is not assigned to Domain
Mode, the default mode is Unassigned Mode. After reset, all registers work in
Unassigned Mode.
All registers are readable for any domain in any mode, but write access is restricted for
protection. In Unassigned Mode, Domain access control scheme is disabled, but
Trustzone access control is still active.
Type GPR Position Width Description
Shared 0 0 4 Setpoint LPCG
response time. This
value need be set when
Setpoint controlled
LPCG is controlling a
clock slower than
16MHz. The value need
be no less than the
multiple number of the
slowest clock to 16M
cycle.
Private 0 0 4 Domain LPCG
response time. This
value need be set when
CPU domain low power
controlled LPCG is
controlling a clock
slower than 16MHz.
The value need be no
less than the multiple
number of the slowest
clock to 16M cycle.
NOTE
A larger response time will lead to Low power Mode and
Setpoint transition penalty time.
15.5.8 Reset
The reset of CCM will be released along with system early reset and clocks are provided
during system reset. For each power domain, early reset of the power domain in which
that clock group and clock gate reside, will be fed for correct power up and reset flow.
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External Signals
15.6 External Signals
The table below shows the external signals associated with CCM block.
Table 15-6. External Signals
External Signal Description
CCM_CLKO1 Clock output 1 for off-chip devices or to monitor on-chip
clocks.
CCM_CLKO2 Clock output 2 for off-chip devices or to monitor on-chip
clocks.
CCM_ENET_REF_CLK_25M ENET 25 MHz Reference Clock. In RMII mode, this reference
clock may be used as a clock source for a ENET PHY IC.
15.7 Analog IP (AI) Interface
The chip has various analog IP and components that are controlled via an AI interface.
The AI control registers are used to indirectly program the analog components on the AI
bus. The following table shows the AI interface registers relative to their respective
analog components and power domains.
Power Domain Analog Component AI Registers
SOC2PLL SYS_PLL1 (1G) VDDSOC2PLL_AI_CTRL_1G
AUDIO_PLL VDDSOC2PLL_AI_WDATA_1G
VIDEO_PLL VDDSOC2PLL_AI_RDATA_1G
VDDSOC2PLL_AI_CTRL_AUDIO
VDDSOC2PLL_AI_WDATA_AUDIO
VDDSOC2PLL_AI_RDATA_AUDIO
VDDSOC2PLL_AI_CTRL_VIDEO
VDDSOC2PLL_AI_WDATA_VIDEO
VDDSOC2PLL_AI_RDATA_VIDEO
SOC PHY LDO VDDSOC_AI_CTRL
VDDSOC_AI_WDATA
VDDSOC_AI_RDATA
PMU_LDO_PLL
LPSR Bandgap VDDLPSR_AI_CTRL
Tempsensor VDDLPSR_AI_WDATA
RCOSC_400M VDDLPSR_AI_RDATA_REFTOP
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Power Domain Analog Component AI Registers
PMU_REF_CTRL
VDDLPSR_AI400M_CTRL
VDDLPSR_AI400M_WDATA
VDDLPSR_AI400M_RDATA
VDDLPSR_AI_RDATA_TMPSNS
Follow the steps below to perform register accesses through the AI interface.
Steps to perform a write operation of an analog component's AI interface:
1. Write *AI_CTRL register
• Set RWB value to 0
• Set ADDR value to the analog component's relative AI control register to be
accessed
2. Write *AI_WDATA
• Set Data[31:0] value to the analog component's relative AI control register value
to be written
3. Write *CTRL IP Toggle
• Set TOGGLE value to 1 in the bit position for the respective analog component.
The toggle will initiate the write sequence.
Steps to perform a read operation of an analog component's AI interface:
1. Write *AI_CTRL register
• Set RWB value to 1
• Set ADDR value to the analog component's relative AI control register to be
accessed
2. Write *CTRL IP Toggle
• Set TOGGLE value to 1 in the bit position for the respective analog component.
The toggle will initiate the read sequence
3. Read *CTRL
• Poll this register until the respective analog component's busy bit is low,
indicating the read transaction has completed.
4. Read *AI_RDATA
• Read Data[31:0]. The contents of the Read Data register is the value of the
analog component's respective AI register's contents.
NOTE
Varying IP will have a corresponding identical toggle bit
NOTE
For PLL operations, follow the PLL enable sequence first.
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Programming Guidelines
15.8 Programming Guidelines
The Clock Controller Module contains the following Fractional and Integer PLLs:
• Fractional PLLs:
• SYS_PLL1
• AUDIO PLL
• VIDEO PLL
• Integer PLLs:
• SYS_PLL2
• SYS_PLL3
• ARM PLL
The PLLs can work in either GPC mode or Software mode (default). In GPC mode, GPC
is the master and drives all the slaves and the users can configure the Setpoint registers.
In Software mode, the users can configure all the registers.
The equations given below help to calculate the output frequency for PLLs based on the
mode (Software or GPC) and type of PLL (Fractional or Integer).
• During Software mode (default):
• For Fractional PLLs (SYS_PLL1, AUDIO_PLL, VIDEO_PLL):
• Output frequency = Fref * (CTRL0[DIV_SELECT] +
(NUMERATOR[NUM]/DENOMINATOR[DENOM]))
• For Integer PLLs (SYS_PLL2, SYS_PLL3, ARM_PLL):
• Output frequency = Fref * MFI
• During GPC mode:
• For Fractional PLLs (SYS_PLL1, AUDIO_PLL, VIDEO_PLL):
• Output frequency = Fref * (SYS_PLLx_DIV_SELECT[DIV_SELECT] +
(SYS_PLLx_NUMERATOR[NUM]/
SYS_PLLx_DENOMINATOR[DENOM]))
• For Integer PLLs (SYS_PLL2, SYS_PLL3, ARM_PLL):
• Output frequency = Fref * MFI
Fref is the PLL Reference Frequency sourced from 24MHz.
NOTE
For SYS_PLL2 and SYS_PLL3, MFI is a fixed value of 22 and
20 respectively.
For ARM_PLL, MFI is equivalent to
ARM_PLL_CTRL[DIV_SELECT]/
ARM_PLL_CTRL[POST_DIV_SELECT].
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Chapter 15 Clock Controller Module (CCM)
15.8.1 Spread Spectrum Parameters
The SYS_PLL1, SYS_PLL2, AUDIO_PLL, VIDEO_PLL and the related PFDs support
spread spectrum (down spread). The equations given below help to calculate spread
spectrum range, and modulation frequency based on the mode (Software or GPC) and
type of PLL (Fractional or Integer).
• During Software mode (default):
• For Fractional PLLs (SYS_PLL1, AUDIO_PLL, VIDEO_PLL):
• Spread spectrum range = Fref * SPREAD_SPECTRUM[STOP]/
DENOMINATOR[DENOM]
• Modulation frequency = Fref * SPREAD_SPECTRUM[STEP]/
(2*SPREAD_SPECTRUM[STOP])
• For Integer PLL (SYS_PLL2):
• Spread spectrum range = Fref * SYS_PLL2_SS[STOP]/
SYS_PLL2_MFD[MFD]
• Modulation frequency= Fref * SYS_PLL2_SS[STEP]/
(SYS_PLL2_SS[STOP] *2)
• During GPC mode:
• For Fractional PLLs (SYS_PLL1, AUDIO_PLL, VIDEO_PLL):
• Spread spectrum range = Fref * SYS_PLLx_SS[STOP]/
SYS_PLLx_DENOMINATOR[DENOM]
• Modulation frequency = Fref * SYS_PLLx_SS[STEP]/
(2*SYS_PLLx_SS[STOP])
• For Integer PLL (SYS_PLL2):
• Spread spectrum range = Fref * SYS_PLL2_SS[STOP]/
SYS_PLL2_MFD[MFD]
• Modulation frequency= Fref * SYS_PLL2_SS[STEP]/
(SYS_PLL2_SS[STOP] *2)
Fref is the PLL Reference Frequency sourced from 24MHz.
The spread range indicates how much frequency the PLL will sweep down. For example,
a spread range of 6MHz would mean that the PLL will sweep from 'Target_frequency' to
'Target_Frequency - 6MHz' and sweep back.
15.8.2 PLL Enable Sequence
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Programming Guidelines
The following sequence has to be followed to enable ARM_PLL, SYS_PLL2 and
SYS_PLL3. The PLLs should be powered down and output should be disabled before
beginning the sequence.
1. Enable the reference voltage by setting
PMU_REF_CTRL[REF_CONTROL_MODE].
2. Configure the PLL registers such as xx_DIV_SELECT/xx_MFN/xx_MFD/xx_SS
described in the PLL Register Descriptions section.
3. Enable the internal LDO (ARM_PLL does not have internal LDO).
4. Wait till the LDO is stable. This can be monitored through the
xx_PLL_CTRL[xx_PLL_STABLE] bit.
5. Enable xx_PLL_CTRL[POWERUP] to power up the PLL.
6. Wait till the PLL lock time is complete. The following are the PLL lock times for
various PLLs:
PLL Lock Time (us)
ARM_PLL 50
SYS_PLL3 50
SYS_PLL2 450
SYS_PLL1/AUDIO_PLL/VIDEO_PLL 450
7. Enable clock output through xx_PLL_CTRL[ENABLE_CLK]
The following sequence has to be followed for SYS_PLL1, AUDIO_PLL and
VIDEO_PLL:
1. Enable the reference voltage by setting
PMU_REF_CTRL[REF_CONTROL_MODE].
2. Configure the PLL registers such as xx_DIV_SELECT/xx_MFN/xx_MFD/xx_SS
described in the PLL Register Descriptions section.
3. Enable the internal LDO.
4. Wait till the LDO is stable. This can be monitored through the
xx_PLL_CTRL[xx_PLL_STABLE] bit.
5. Power up the PLL by enabling xx_PLL_CTRL[POWERUP] and assert
xx_PLL_CTRL[HOLD_RING_OFF]
6. When the PLL lock time is halfway through, de-assert the
xx_PLL_CTRL[HOLD_RING_OFF]
7. Wait till the PLL lock time is complete. The PLL lock times can be found in the table
above.
8. Enable clock output through xx_PLL_CTRL[ENABLE_CLK]
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Chapter 15 Clock Controller Module (CCM)
NOTE
• In order to avoid unstable clocks that might alter the PFD's
state machine, all PFDs are required to be clock-gated
when the PLL is not locked.
• PFD's input can be changed on-the fly, while PLL's input
cannot be changed on-the-fly (except for MFN).
• The initialization for software and GPC modes is handled
by Setpoints automatically.
15.9 Memory Map and register definition
This section includes the CCM module memory map and detailed descriptions of all
registers.
NOTE
For related IPS Domain Slot control, please see IPS Domain
Registers in Power Management Unit (PMU) chapter.
15.9.1 CCM register descriptions
15.9.1.1 CCM memory map
CCM base address: 40CC_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Clock root control (CLOCK_ROOT0_CONTROL) 32 RW 0000_0000
4 Clock root control (CLOCK_ROOT0_CONTROL_SET) 32 RW 0000_0000
8 Clock root control (CLOCK_ROOT0_CONTROL_CLR) 32 RW 0000_0000
C Clock root control (CLOCK_ROOT0_CONTROL_TOG) 32 RW 0000_0000
20 - 2720 Clock root working status (CLOCK_ROOT0_STATUS0 - 32 RO 0000_0000
CLOCK_ROOT78_STATUS0)
24 - 2724 Clock root low power status (CLOCK_ROOT0_STATUS1 - 32 RO 0000_0000
CLOCK_ROOT78_STATUS1)
2C - 272C Clock root configuration (CLOCK_ROOT0_CONFIG - 32 RO Table 15-6
CLOCK_ROOT78_CONFIG)
30 Clock root access control (CLOCK_ROOT0_AUTHEN) 32 RW 0000_0000
34 Clock root access control (CLOCK_ROOT0_AUTHEN_SET) 32 RW 0000_0000
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
38 Clock root access control (CLOCK_ROOT0_AUTHEN_CLR) 32 RW 0000_0000
3C Clock root access control (CLOCK_ROOT0_AUTHEN_TOG) 32 RW 0000_0000
40 - 277C Setpoint setting (CLOCK_ROOT0_SETPOINT0 - 32 RW 0000_0000
CLOCK_ROOT78_SETPOINT15)
80 Clock root control (CLOCK_ROOT1_CONTROL) 32 RW 0000_0000
84 Clock root control (CLOCK_ROOT1_CONTROL_SET) 32 RW 0000_0000
88 Clock root control (CLOCK_ROOT1_CONTROL_CLR) 32 RW 0000_0000
8C Clock root control (CLOCK_ROOT1_CONTROL_TOG) 32 RW 0000_0000
B0 Clock root access control (CLOCK_ROOT1_AUTHEN) 32 RW 0000_0000
B4 Clock root access control (CLOCK_ROOT1_AUTHEN_SET) 32 RW 0000_0000
B8 Clock root access control (CLOCK_ROOT1_AUTHEN_CLR) 32 RW 0000_0000
BC Clock root access control (CLOCK_ROOT1_AUTHEN_TOG) 32 RW 0000_0000
100 Clock root control (CLOCK_ROOT2_CONTROL) 32 RW 0000_0000
104 Clock root control (CLOCK_ROOT2_CONTROL_SET) 32 RW 0000_0000
108 Clock root control (CLOCK_ROOT2_CONTROL_CLR) 32 RW 0000_0000
10C Clock root control (CLOCK_ROOT2_CONTROL_TOG) 32 RW 0000_0000
130 Clock root access control (CLOCK_ROOT2_AUTHEN) 32 RW 0000_0000
134 Clock root access control (CLOCK_ROOT2_AUTHEN_SET) 32 RW 0000_0000
138 Clock root access control (CLOCK_ROOT2_AUTHEN_CLR) 32 RW 0000_0000
13C Clock root access control (CLOCK_ROOT2_AUTHEN_TOG) 32 RW 0000_0000
180 Clock root control (CLOCK_ROOT3_CONTROL) 32 RW 0000_0000
184 Clock root control (CLOCK_ROOT3_CONTROL_SET) 32 RW 0000_0000
188 Clock root control (CLOCK_ROOT3_CONTROL_CLR) 32 RW 0000_0000
18C Clock root control (CLOCK_ROOT3_CONTROL_TOG) 32 RW 0000_0000
1B0 Clock root access control (CLOCK_ROOT3_AUTHEN) 32 RW 0000_0000
1B4 Clock root access control (CLOCK_ROOT3_AUTHEN_SET) 32 RW 0000_0000
1B8 Clock root access control (CLOCK_ROOT3_AUTHEN_CLR) 32 RW 0000_0000
1BC Clock root access control (CLOCK_ROOT3_AUTHEN_TOG) 32 RW 0000_0000
200 Clock root control (CLOCK_ROOT4_CONTROL) 32 RW 0000_0000
204 Clock root control (CLOCK_ROOT4_CONTROL_SET) 32 RW 0000_0000
208 Clock root control (CLOCK_ROOT4_CONTROL_CLR) 32 RW 0000_0000
20C Clock root control (CLOCK_ROOT4_CONTROL_TOG) 32 RW 0000_0000
230 Clock root access control (CLOCK_ROOT4_AUTHEN) 32 RW 0000_0000
234 Clock root access control (CLOCK_ROOT4_AUTHEN_SET) 32 RW 0000_0000
238 Clock root access control (CLOCK_ROOT4_AUTHEN_CLR) 32 RW 0000_0000
23C Clock root access control (CLOCK_ROOT4_AUTHEN_TOG) 32 RW 0000_0000
280 Clock root control (CLOCK_ROOT5_CONTROL) 32 RW 0000_0000
284 Clock root control (CLOCK_ROOT5_CONTROL_SET) 32 RW 0000_0000
288 Clock root control (CLOCK_ROOT5_CONTROL_CLR) 32 RW 0000_0000
28C Clock root control (CLOCK_ROOT5_CONTROL_TOG) 32 RW 0000_0000
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Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
2B0 Clock root access control (CLOCK_ROOT5_AUTHEN) 32 RW 0000_0000
2B4 Clock root access control (CLOCK_ROOT5_AUTHEN_SET) 32 RW 0000_0000
2B8 Clock root access control (CLOCK_ROOT5_AUTHEN_CLR) 32 RW 0000_0000
2BC Clock root access control (CLOCK_ROOT5_AUTHEN_TOG) 32 RW 0000_0000
300 Clock root control (CLOCK_ROOT6_CONTROL) 32 RW 0000_0000
304 Clock root control (CLOCK_ROOT6_CONTROL_SET) 32 RW 0000_0000
308 Clock root control (CLOCK_ROOT6_CONTROL_CLR) 32 RW 0000_0000
30C Clock root control (CLOCK_ROOT6_CONTROL_TOG) 32 RW 0000_0000
330 Clock root access control (CLOCK_ROOT6_AUTHEN) 32 RW 0000_0000
334 Clock root access control (CLOCK_ROOT6_AUTHEN_SET) 32 RW 0000_0000
338 Clock root access control (CLOCK_ROOT6_AUTHEN_CLR) 32 RW 0000_0000
33C Clock root access control (CLOCK_ROOT6_AUTHEN_TOG) 32 RW 0000_0000
380 Clock root control (CLOCK_ROOT7_CONTROL) 32 RW 0000_0000
384 Clock root control (CLOCK_ROOT7_CONTROL_SET) 32 RW 0000_0000
388 Clock root control (CLOCK_ROOT7_CONTROL_CLR) 32 RW 0000_0000
38C Clock root control (CLOCK_ROOT7_CONTROL_TOG) 32 RW 0000_0000
3B0 Clock root access control (CLOCK_ROOT7_AUTHEN) 32 RW 0000_0000
3B4 Clock root access control (CLOCK_ROOT7_AUTHEN_SET) 32 RW 0000_0000
3B8 Clock root access control (CLOCK_ROOT7_AUTHEN_CLR) 32 RW 0000_0000
3BC Clock root access control (CLOCK_ROOT7_AUTHEN_TOG) 32 RW 0000_0000
400 Clock root control (CLOCK_ROOT8_CONTROL) 32 RW 0000_0000
404 Clock root control (CLOCK_ROOT8_CONTROL_SET) 32 RW 0000_0000
408 Clock root control (CLOCK_ROOT8_CONTROL_CLR) 32 RW 0000_0000
40C Clock root control (CLOCK_ROOT8_CONTROL_TOG) 32 RW 0000_0000
430 Clock root access control (CLOCK_ROOT8_AUTHEN) 32 RW 0000_0000
434 Clock root access control (CLOCK_ROOT8_AUTHEN_SET) 32 RW 0000_0000
438 Clock root access control (CLOCK_ROOT8_AUTHEN_CLR) 32 RW 0000_0000
43C Clock root access control (CLOCK_ROOT8_AUTHEN_TOG) 32 RW 0000_0000
480 Clock root control (CLOCK_ROOT9_CONTROL) 32 RW 0000_0000
484 Clock root control (CLOCK_ROOT9_CONTROL_SET) 32 RW 0000_0000
488 Clock root control (CLOCK_ROOT9_CONTROL_CLR) 32 RW 0000_0000
48C Clock root control (CLOCK_ROOT9_CONTROL_TOG) 32 RW 0000_0000
4B0 Clock root access control (CLOCK_ROOT9_AUTHEN) 32 RW 0000_0000
4B4 Clock root access control (CLOCK_ROOT9_AUTHEN_SET) 32 RW 0000_0000
4B8 Clock root access control (CLOCK_ROOT9_AUTHEN_CLR) 32 RW 0000_0000
4BC Clock root access control (CLOCK_ROOT9_AUTHEN_TOG) 32 RW 0000_0000
500 Clock root control (CLOCK_ROOT10_CONTROL) 32 RW 0000_0000
504 Clock root control (CLOCK_ROOT10_CONTROL_SET) 32 RW 0000_0000
508 Clock root control (CLOCK_ROOT10_CONTROL_CLR) 32 RW 0000_0000
50C Clock root control (CLOCK_ROOT10_CONTROL_TOG) 32 RW 0000_0000
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
530 Clock root access control (CLOCK_ROOT10_AUTHEN) 32 RW 0000_0000
534 Clock root access control (CLOCK_ROOT10_AUTHEN_SET) 32 RW 0000_0000
538 Clock root access control (CLOCK_ROOT10_AUTHEN_CLR) 32 RW 0000_0000
53C Clock root access control (CLOCK_ROOT10_AUTHEN_TOG) 32 RW 0000_0000
580 Clock root control (CLOCK_ROOT11_CONTROL) 32 RW 0000_0000
584 Clock root control (CLOCK_ROOT11_CONTROL_SET) 32 RW 0000_0000
588 Clock root control (CLOCK_ROOT11_CONTROL_CLR) 32 RW 0000_0000
58C Clock root control (CLOCK_ROOT11_CONTROL_TOG) 32 RW 0000_0000
5B0 Clock root access control (CLOCK_ROOT11_AUTHEN) 32 RW 0000_0000
5B4 Clock root access control (CLOCK_ROOT11_AUTHEN_SET) 32 RW 0000_0000
5B8 Clock root access control (CLOCK_ROOT11_AUTHEN_CLR) 32 RW 0000_0000
5BC Clock root access control (CLOCK_ROOT11_AUTHEN_TOG) 32 RW 0000_0000
600 Clock root control (CLOCK_ROOT12_CONTROL) 32 RW 0000_0000
604 Clock root control (CLOCK_ROOT12_CONTROL_SET) 32 RW 0000_0000
608 Clock root control (CLOCK_ROOT12_CONTROL_CLR) 32 RW 0000_0000
60C Clock root control (CLOCK_ROOT12_CONTROL_TOG) 32 RW 0000_0000
630 Clock root access control (CLOCK_ROOT12_AUTHEN) 32 RW 0000_0000
634 Clock root access control (CLOCK_ROOT12_AUTHEN_SET) 32 RW 0000_0000
638 Clock root access control (CLOCK_ROOT12_AUTHEN_CLR) 32 RW 0000_0000
63C Clock root access control (CLOCK_ROOT12_AUTHEN_TOG) 32 RW 0000_0000
680 Clock root control (CLOCK_ROOT13_CONTROL) 32 RW 0000_0000
684 Clock root control (CLOCK_ROOT13_CONTROL_SET) 32 RW 0000_0000
688 Clock root control (CLOCK_ROOT13_CONTROL_CLR) 32 RW 0000_0000
68C Clock root control (CLOCK_ROOT13_CONTROL_TOG) 32 RW 0000_0000
6B0 Clock root access control (CLOCK_ROOT13_AUTHEN) 32 RW 0000_0000
6B4 Clock root access control (CLOCK_ROOT13_AUTHEN_SET) 32 RW 0000_0000
6B8 Clock root access control (CLOCK_ROOT13_AUTHEN_CLR) 32 RW 0000_0000
6BC Clock root access control (CLOCK_ROOT13_AUTHEN_TOG) 32 RW 0000_0000
700 Clock root control (CLOCK_ROOT14_CONTROL) 32 RW 0000_0000
704 Clock root control (CLOCK_ROOT14_CONTROL_SET) 32 RW 0000_0000
708 Clock root control (CLOCK_ROOT14_CONTROL_CLR) 32 RW 0000_0000
70C Clock root control (CLOCK_ROOT14_CONTROL_TOG) 32 RW 0000_0000
730 Clock root access control (CLOCK_ROOT14_AUTHEN) 32 RW 0000_0000
734 Clock root access control (CLOCK_ROOT14_AUTHEN_SET) 32 RW 0000_0000
738 Clock root access control (CLOCK_ROOT14_AUTHEN_CLR) 32 RW 0000_0000
73C Clock root access control (CLOCK_ROOT14_AUTHEN_TOG) 32 RW 0000_0000
780 Clock root control (CLOCK_ROOT15_CONTROL) 32 RW 0000_0000
784 Clock root control (CLOCK_ROOT15_CONTROL_SET) 32 RW 0000_0000
788 Clock root control (CLOCK_ROOT15_CONTROL_CLR) 32 RW 0000_0000
78C Clock root control (CLOCK_ROOT15_CONTROL_TOG) 32 RW 0000_0000
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Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
7B0 Clock root access control (CLOCK_ROOT15_AUTHEN) 32 RW 0000_0000
7B4 Clock root access control (CLOCK_ROOT15_AUTHEN_SET) 32 RW 0000_0000
7B8 Clock root access control (CLOCK_ROOT15_AUTHEN_CLR) 32 RW 0000_0000
7BC Clock root access control (CLOCK_ROOT15_AUTHEN_TOG) 32 RW 0000_0000
800 Clock root control (CLOCK_ROOT16_CONTROL) 32 RW 0000_0000
804 Clock root control (CLOCK_ROOT16_CONTROL_SET) 32 RW 0000_0000
808 Clock root control (CLOCK_ROOT16_CONTROL_CLR) 32 RW 0000_0000
80C Clock root control (CLOCK_ROOT16_CONTROL_TOG) 32 RW 0000_0000
830 Clock root access control (CLOCK_ROOT16_AUTHEN) 32 RW 0000_0000
834 Clock root access control (CLOCK_ROOT16_AUTHEN_SET) 32 RW 0000_0000
838 Clock root access control (CLOCK_ROOT16_AUTHEN_CLR) 32 RW 0000_0000
83C Clock root access control (CLOCK_ROOT16_AUTHEN_TOG) 32 RW 0000_0000
880 Clock root control (CLOCK_ROOT17_CONTROL) 32 RW 0000_0000
884 Clock root control (CLOCK_ROOT17_CONTROL_SET) 32 RW 0000_0000
888 Clock root control (CLOCK_ROOT17_CONTROL_CLR) 32 RW 0000_0000
88C Clock root control (CLOCK_ROOT17_CONTROL_TOG) 32 RW 0000_0000
8B0 Clock root access control (CLOCK_ROOT17_AUTHEN) 32 RW 0000_0000
8B4 Clock root access control (CLOCK_ROOT17_AUTHEN_SET) 32 RW 0000_0000
8B8 Clock root access control (CLOCK_ROOT17_AUTHEN_CLR) 32 RW 0000_0000
8BC Clock root access control (CLOCK_ROOT17_AUTHEN_TOG) 32 RW 0000_0000
900 Clock root control (CLOCK_ROOT18_CONTROL) 32 RW 0000_0000
904 Clock root control (CLOCK_ROOT18_CONTROL_SET) 32 RW 0000_0000
908 Clock root control (CLOCK_ROOT18_CONTROL_CLR) 32 RW 0000_0000
90C Clock root control (CLOCK_ROOT18_CONTROL_TOG) 32 RW 0000_0000
930 Clock root access control (CLOCK_ROOT18_AUTHEN) 32 RW 0000_0000
934 Clock root access control (CLOCK_ROOT18_AUTHEN_SET) 32 RW 0000_0000
938 Clock root access control (CLOCK_ROOT18_AUTHEN_CLR) 32 RW 0000_0000
93C Clock root access control (CLOCK_ROOT18_AUTHEN_TOG) 32 RW 0000_0000
980 Clock root control (CLOCK_ROOT19_CONTROL) 32 RW 0000_0000
984 Clock root control (CLOCK_ROOT19_CONTROL_SET) 32 RW 0000_0000
988 Clock root control (CLOCK_ROOT19_CONTROL_CLR) 32 RW 0000_0000
98C Clock root control (CLOCK_ROOT19_CONTROL_TOG) 32 RW 0000_0000
9B0 Clock root access control (CLOCK_ROOT19_AUTHEN) 32 RW 0000_0000
9B4 Clock root access control (CLOCK_ROOT19_AUTHEN_SET) 32 RW 0000_0000
9B8 Clock root access control (CLOCK_ROOT19_AUTHEN_CLR) 32 RW 0000_0000
9BC Clock root access control (CLOCK_ROOT19_AUTHEN_TOG) 32 RW 0000_0000
A00 Clock root control (CLOCK_ROOT20_CONTROL) 32 RW 0000_0000
A04 Clock root control (CLOCK_ROOT20_CONTROL_SET) 32 RW 0000_0000
A08 Clock root control (CLOCK_ROOT20_CONTROL_CLR) 32 RW 0000_0000
A0C Clock root control (CLOCK_ROOT20_CONTROL_TOG) 32 RW 0000_0000
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
A30 Clock root access control (CLOCK_ROOT20_AUTHEN) 32 RW 0000_0000
A34 Clock root access control (CLOCK_ROOT20_AUTHEN_SET) 32 RW 0000_0000
A38 Clock root access control (CLOCK_ROOT20_AUTHEN_CLR) 32 RW 0000_0000
A3C Clock root access control (CLOCK_ROOT20_AUTHEN_TOG) 32 RW 0000_0000
A80 Clock root control (CLOCK_ROOT21_CONTROL) 32 RW 0000_0000
A84 Clock root control (CLOCK_ROOT21_CONTROL_SET) 32 RW 0000_0000
A88 Clock root control (CLOCK_ROOT21_CONTROL_CLR) 32 RW 0000_0000
A8C Clock root control (CLOCK_ROOT21_CONTROL_TOG) 32 RW 0000_0000
AB0 Clock root access control (CLOCK_ROOT21_AUTHEN) 32 RW 0000_0000
AB4 Clock root access control (CLOCK_ROOT21_AUTHEN_SET) 32 RW 0000_0000
AB8 Clock root access control (CLOCK_ROOT21_AUTHEN_CLR) 32 RW 0000_0000
ABC Clock root access control (CLOCK_ROOT21_AUTHEN_TOG) 32 RW 0000_0000
B00 Clock root control (CLOCK_ROOT22_CONTROL) 32 RW 0000_0000
B04 Clock root control (CLOCK_ROOT22_CONTROL_SET) 32 RW 0000_0000
B08 Clock root control (CLOCK_ROOT22_CONTROL_CLR) 32 RW 0000_0000
B0C Clock root control (CLOCK_ROOT22_CONTROL_TOG) 32 RW 0000_0000
B30 Clock root access control (CLOCK_ROOT22_AUTHEN) 32 RW 0000_0000
B34 Clock root access control (CLOCK_ROOT22_AUTHEN_SET) 32 RW 0000_0000
B38 Clock root access control (CLOCK_ROOT22_AUTHEN_CLR) 32 RW 0000_0000
B3C Clock root access control (CLOCK_ROOT22_AUTHEN_TOG) 32 RW 0000_0000
B80 Clock root control (CLOCK_ROOT23_CONTROL) 32 RW 0000_0000
B84 Clock root control (CLOCK_ROOT23_CONTROL_SET) 32 RW 0000_0000
B88 Clock root control (CLOCK_ROOT23_CONTROL_CLR) 32 RW 0000_0000
B8C Clock root control (CLOCK_ROOT23_CONTROL_TOG) 32 RW 0000_0000
BB0 Clock root access control (CLOCK_ROOT23_AUTHEN) 32 RW 0000_0000
BB4 Clock root access control (CLOCK_ROOT23_AUTHEN_SET) 32 RW 0000_0000
BB8 Clock root access control (CLOCK_ROOT23_AUTHEN_CLR) 32 RW 0000_0000
BBC Clock root access control (CLOCK_ROOT23_AUTHEN_TOG) 32 RW 0000_0000
C00 Clock root control (CLOCK_ROOT24_CONTROL) 32 RW 0000_0000
C04 Clock root control (CLOCK_ROOT24_CONTROL_SET) 32 RW 0000_0000
C08 Clock root control (CLOCK_ROOT24_CONTROL_CLR) 32 RW 0000_0000
C0C Clock root control (CLOCK_ROOT24_CONTROL_TOG) 32 RW 0000_0000
C30 Clock root access control (CLOCK_ROOT24_AUTHEN) 32 RW 0000_0000
C34 Clock root access control (CLOCK_ROOT24_AUTHEN_SET) 32 RW 0000_0000
C38 Clock root access control (CLOCK_ROOT24_AUTHEN_CLR) 32 RW 0000_0000
C3C Clock root access control (CLOCK_ROOT24_AUTHEN_TOG) 32 RW 0000_0000
C80 Clock root control (CLOCK_ROOT25_CONTROL) 32 RW 0000_0000
C84 Clock root control (CLOCK_ROOT25_CONTROL_SET) 32 RW 0000_0000
C88 Clock root control (CLOCK_ROOT25_CONTROL_CLR) 32 RW 0000_0000
C8C Clock root control (CLOCK_ROOT25_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1518 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
CB0 Clock root access control (CLOCK_ROOT25_AUTHEN) 32 RW 0000_0000
CB4 Clock root access control (CLOCK_ROOT25_AUTHEN_SET) 32 RW 0000_0000
CB8 Clock root access control (CLOCK_ROOT25_AUTHEN_CLR) 32 RW 0000_0000
CBC Clock root access control (CLOCK_ROOT25_AUTHEN_TOG) 32 RW 0000_0000
D00 Clock root control (CLOCK_ROOT26_CONTROL) 32 RW 0000_0000
D04 Clock root control (CLOCK_ROOT26_CONTROL_SET) 32 RW 0000_0000
D08 Clock root control (CLOCK_ROOT26_CONTROL_CLR) 32 RW 0000_0000
D0C Clock root control (CLOCK_ROOT26_CONTROL_TOG) 32 RW 0000_0000
D30 Clock root access control (CLOCK_ROOT26_AUTHEN) 32 RW 0000_0000
D34 Clock root access control (CLOCK_ROOT26_AUTHEN_SET) 32 RW 0000_0000
D38 Clock root access control (CLOCK_ROOT26_AUTHEN_CLR) 32 RW 0000_0000
D3C Clock root access control (CLOCK_ROOT26_AUTHEN_TOG) 32 RW 0000_0000
D80 Clock root control (CLOCK_ROOT27_CONTROL) 32 RW 0000_0000
D84 Clock root control (CLOCK_ROOT27_CONTROL_SET) 32 RW 0000_0000
D88 Clock root control (CLOCK_ROOT27_CONTROL_CLR) 32 RW 0000_0000
D8C Clock root control (CLOCK_ROOT27_CONTROL_TOG) 32 RW 0000_0000
DB0 Clock root access control (CLOCK_ROOT27_AUTHEN) 32 RW 0000_0000
DB4 Clock root access control (CLOCK_ROOT27_AUTHEN_SET) 32 RW 0000_0000
DB8 Clock root access control (CLOCK_ROOT27_AUTHEN_CLR) 32 RW 0000_0000
DBC Clock root access control (CLOCK_ROOT27_AUTHEN_TOG) 32 RW 0000_0000
E00 Clock root control (CLOCK_ROOT28_CONTROL) 32 RW 0000_0000
E04 Clock root control (CLOCK_ROOT28_CONTROL_SET) 32 RW 0000_0000
E08 Clock root control (CLOCK_ROOT28_CONTROL_CLR) 32 RW 0000_0000
E0C Clock root control (CLOCK_ROOT28_CONTROL_TOG) 32 RW 0000_0000
E30 Clock root access control (CLOCK_ROOT28_AUTHEN) 32 RW 0000_0000
E34 Clock root access control (CLOCK_ROOT28_AUTHEN_SET) 32 RW 0000_0000
E38 Clock root access control (CLOCK_ROOT28_AUTHEN_CLR) 32 RW 0000_0000
E3C Clock root access control (CLOCK_ROOT28_AUTHEN_TOG) 32 RW 0000_0000
E80 Clock root control (CLOCK_ROOT29_CONTROL) 32 RW 0000_0000
E84 Clock root control (CLOCK_ROOT29_CONTROL_SET) 32 RW 0000_0000
E88 Clock root control (CLOCK_ROOT29_CONTROL_CLR) 32 RW 0000_0000
E8C Clock root control (CLOCK_ROOT29_CONTROL_TOG) 32 RW 0000_0000
EB0 Clock root access control (CLOCK_ROOT29_AUTHEN) 32 RW 0000_0000
EB4 Clock root access control (CLOCK_ROOT29_AUTHEN_SET) 32 RW 0000_0000
EB8 Clock root access control (CLOCK_ROOT29_AUTHEN_CLR) 32 RW 0000_0000
EBC Clock root access control (CLOCK_ROOT29_AUTHEN_TOG) 32 RW 0000_0000
F00 Clock root control (CLOCK_ROOT30_CONTROL) 32 RW 0000_0000
F04 Clock root control (CLOCK_ROOT30_CONTROL_SET) 32 RW 0000_0000
F08 Clock root control (CLOCK_ROOT30_CONTROL_CLR) 32 RW 0000_0000
F0C Clock root control (CLOCK_ROOT30_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1519
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
F30 Clock root access control (CLOCK_ROOT30_AUTHEN) 32 RW 0000_0000
F34 Clock root access control (CLOCK_ROOT30_AUTHEN_SET) 32 RW 0000_0000
F38 Clock root access control (CLOCK_ROOT30_AUTHEN_CLR) 32 RW 0000_0000
F3C Clock root access control (CLOCK_ROOT30_AUTHEN_TOG) 32 RW 0000_0000
F80 Clock root control (CLOCK_ROOT31_CONTROL) 32 RW 0000_0000
F84 Clock root control (CLOCK_ROOT31_CONTROL_SET) 32 RW 0000_0000
F88 Clock root control (CLOCK_ROOT31_CONTROL_CLR) 32 RW 0000_0000
F8C Clock root control (CLOCK_ROOT31_CONTROL_TOG) 32 RW 0000_0000
FB0 Clock root access control (CLOCK_ROOT31_AUTHEN) 32 RW 0000_0000
FB4 Clock root access control (CLOCK_ROOT31_AUTHEN_SET) 32 RW 0000_0000
FB8 Clock root access control (CLOCK_ROOT31_AUTHEN_CLR) 32 RW 0000_0000
FBC Clock root access control (CLOCK_ROOT31_AUTHEN_TOG) 32 RW 0000_0000
1000 Clock root control (CLOCK_ROOT32_CONTROL) 32 RW 0000_0000
1004 Clock root control (CLOCK_ROOT32_CONTROL_SET) 32 RW 0000_0000
1008 Clock root control (CLOCK_ROOT32_CONTROL_CLR) 32 RW 0000_0000
100C Clock root control (CLOCK_ROOT32_CONTROL_TOG) 32 RW 0000_0000
1030 Clock root access control (CLOCK_ROOT32_AUTHEN) 32 RW 0000_0000
1034 Clock root access control (CLOCK_ROOT32_AUTHEN_SET) 32 RW 0000_0000
1038 Clock root access control (CLOCK_ROOT32_AUTHEN_CLR) 32 RW 0000_0000
103C Clock root access control (CLOCK_ROOT32_AUTHEN_TOG) 32 RW 0000_0000
1080 Clock root control (CLOCK_ROOT33_CONTROL) 32 RW 0000_0000
1084 Clock root control (CLOCK_ROOT33_CONTROL_SET) 32 RW 0000_0000
1088 Clock root control (CLOCK_ROOT33_CONTROL_CLR) 32 RW 0000_0000
108C Clock root control (CLOCK_ROOT33_CONTROL_TOG) 32 RW 0000_0000
10B0 Clock root access control (CLOCK_ROOT33_AUTHEN) 32 RW 0000_0000
10B4 Clock root access control (CLOCK_ROOT33_AUTHEN_SET) 32 RW 0000_0000
10B8 Clock root access control (CLOCK_ROOT33_AUTHEN_CLR) 32 RW 0000_0000
10BC Clock root access control (CLOCK_ROOT33_AUTHEN_TOG) 32 RW 0000_0000
1100 Clock root control (CLOCK_ROOT34_CONTROL) 32 RW 0000_0000
1104 Clock root control (CLOCK_ROOT34_CONTROL_SET) 32 RW 0000_0000
1108 Clock root control (CLOCK_ROOT34_CONTROL_CLR) 32 RW 0000_0000
110C Clock root control (CLOCK_ROOT34_CONTROL_TOG) 32 RW 0000_0000
1130 Clock root access control (CLOCK_ROOT34_AUTHEN) 32 RW 0000_0000
1134 Clock root access control (CLOCK_ROOT34_AUTHEN_SET) 32 RW 0000_0000
1138 Clock root access control (CLOCK_ROOT34_AUTHEN_CLR) 32 RW 0000_0000
113C Clock root access control (CLOCK_ROOT34_AUTHEN_TOG) 32 RW 0000_0000
1180 Clock root control (CLOCK_ROOT35_CONTROL) 32 RW 0000_0000
1184 Clock root control (CLOCK_ROOT35_CONTROL_SET) 32 RW 0000_0000
1188 Clock root control (CLOCK_ROOT35_CONTROL_CLR) 32 RW 0000_0000
118C Clock root control (CLOCK_ROOT35_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1520 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
11B0 Clock root access control (CLOCK_ROOT35_AUTHEN) 32 RW 0000_0000
11B4 Clock root access control (CLOCK_ROOT35_AUTHEN_SET) 32 RW 0000_0000
11B8 Clock root access control (CLOCK_ROOT35_AUTHEN_CLR) 32 RW 0000_0000
11BC Clock root access control (CLOCK_ROOT35_AUTHEN_TOG) 32 RW 0000_0000
1200 Clock root control (CLOCK_ROOT36_CONTROL) 32 RW 0000_0000
1204 Clock root control (CLOCK_ROOT36_CONTROL_SET) 32 RW 0000_0000
1208 Clock root control (CLOCK_ROOT36_CONTROL_CLR) 32 RW 0000_0000
120C Clock root control (CLOCK_ROOT36_CONTROL_TOG) 32 RW 0000_0000
1230 Clock root access control (CLOCK_ROOT36_AUTHEN) 32 RW 0000_0000
1234 Clock root access control (CLOCK_ROOT36_AUTHEN_SET) 32 RW 0000_0000
1238 Clock root access control (CLOCK_ROOT36_AUTHEN_CLR) 32 RW 0000_0000
123C Clock root access control (CLOCK_ROOT36_AUTHEN_TOG) 32 RW 0000_0000
1280 Clock root control (CLOCK_ROOT37_CONTROL) 32 RW 0000_0000
1284 Clock root control (CLOCK_ROOT37_CONTROL_SET) 32 RW 0000_0000
1288 Clock root control (CLOCK_ROOT37_CONTROL_CLR) 32 RW 0000_0000
128C Clock root control (CLOCK_ROOT37_CONTROL_TOG) 32 RW 0000_0000
12B0 Clock root access control (CLOCK_ROOT37_AUTHEN) 32 RW 0000_0000
12B4 Clock root access control (CLOCK_ROOT37_AUTHEN_SET) 32 RW 0000_0000
12B8 Clock root access control (CLOCK_ROOT37_AUTHEN_CLR) 32 RW 0000_0000
12BC Clock root access control (CLOCK_ROOT37_AUTHEN_TOG) 32 RW 0000_0000
1300 Clock root control (CLOCK_ROOT38_CONTROL) 32 RW 0000_0000
1304 Clock root control (CLOCK_ROOT38_CONTROL_SET) 32 RW 0000_0000
1308 Clock root control (CLOCK_ROOT38_CONTROL_CLR) 32 RW 0000_0000
130C Clock root control (CLOCK_ROOT38_CONTROL_TOG) 32 RW 0000_0000
1330 Clock root access control (CLOCK_ROOT38_AUTHEN) 32 RW 0000_0000
1334 Clock root access control (CLOCK_ROOT38_AUTHEN_SET) 32 RW 0000_0000
1338 Clock root access control (CLOCK_ROOT38_AUTHEN_CLR) 32 RW 0000_0000
133C Clock root access control (CLOCK_ROOT38_AUTHEN_TOG) 32 RW 0000_0000
1380 Clock root control (CLOCK_ROOT39_CONTROL) 32 RW 0000_0000
1384 Clock root control (CLOCK_ROOT39_CONTROL_SET) 32 RW 0000_0000
1388 Clock root control (CLOCK_ROOT39_CONTROL_CLR) 32 RW 0000_0000
138C Clock root control (CLOCK_ROOT39_CONTROL_TOG) 32 RW 0000_0000
13B0 Clock root access control (CLOCK_ROOT39_AUTHEN) 32 RW 0000_0000
13B4 Clock root access control (CLOCK_ROOT39_AUTHEN_SET) 32 RW 0000_0000
13B8 Clock root access control (CLOCK_ROOT39_AUTHEN_CLR) 32 RW 0000_0000
13BC Clock root access control (CLOCK_ROOT39_AUTHEN_TOG) 32 RW 0000_0000
1400 Clock root control (CLOCK_ROOT40_CONTROL) 32 RW 0000_0000
1404 Clock root control (CLOCK_ROOT40_CONTROL_SET) 32 RW 0000_0000
1408 Clock root control (CLOCK_ROOT40_CONTROL_CLR) 32 RW 0000_0000
140C Clock root control (CLOCK_ROOT40_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1521
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1430 Clock root access control (CLOCK_ROOT40_AUTHEN) 32 RW 0000_0000
1434 Clock root access control (CLOCK_ROOT40_AUTHEN_SET) 32 RW 0000_0000
1438 Clock root access control (CLOCK_ROOT40_AUTHEN_CLR) 32 RW 0000_0000
143C Clock root access control (CLOCK_ROOT40_AUTHEN_TOG) 32 RW 0000_0000
1480 Clock root control (CLOCK_ROOT41_CONTROL) 32 RW 0000_0000
1484 Clock root control (CLOCK_ROOT41_CONTROL_SET) 32 RW 0000_0000
1488 Clock root control (CLOCK_ROOT41_CONTROL_CLR) 32 RW 0000_0000
148C Clock root control (CLOCK_ROOT41_CONTROL_TOG) 32 RW 0000_0000
14B0 Clock root access control (CLOCK_ROOT41_AUTHEN) 32 RW 0000_0000
14B4 Clock root access control (CLOCK_ROOT41_AUTHEN_SET) 32 RW 0000_0000
14B8 Clock root access control (CLOCK_ROOT41_AUTHEN_CLR) 32 RW 0000_0000
14BC Clock root access control (CLOCK_ROOT41_AUTHEN_TOG) 32 RW 0000_0000
1500 Clock root control (CLOCK_ROOT42_CONTROL) 32 RW 0000_0000
1504 Clock root control (CLOCK_ROOT42_CONTROL_SET) 32 RW 0000_0000
1508 Clock root control (CLOCK_ROOT42_CONTROL_CLR) 32 RW 0000_0000
150C Clock root control (CLOCK_ROOT42_CONTROL_TOG) 32 RW 0000_0000
1530 Clock root access control (CLOCK_ROOT42_AUTHEN) 32 RW 0000_0000
1534 Clock root access control (CLOCK_ROOT42_AUTHEN_SET) 32 RW 0000_0000
1538 Clock root access control (CLOCK_ROOT42_AUTHEN_CLR) 32 RW 0000_0000
153C Clock root access control (CLOCK_ROOT42_AUTHEN_TOG) 32 RW 0000_0000
1580 Clock root control (CLOCK_ROOT43_CONTROL) 32 RW 0000_0000
1584 Clock root control (CLOCK_ROOT43_CONTROL_SET) 32 RW 0000_0000
1588 Clock root control (CLOCK_ROOT43_CONTROL_CLR) 32 RW 0000_0000
158C Clock root control (CLOCK_ROOT43_CONTROL_TOG) 32 RW 0000_0000
15B0 Clock root access control (CLOCK_ROOT43_AUTHEN) 32 RW 0000_0000
15B4 Clock root access control (CLOCK_ROOT43_AUTHEN_SET) 32 RW 0000_0000
15B8 Clock root access control (CLOCK_ROOT43_AUTHEN_CLR) 32 RW 0000_0000
15BC Clock root access control (CLOCK_ROOT43_AUTHEN_TOG) 32 RW 0000_0000
1600 Clock root control (CLOCK_ROOT44_CONTROL) 32 RW 0000_0000
1604 Clock root control (CLOCK_ROOT44_CONTROL_SET) 32 RW 0000_0000
1608 Clock root control (CLOCK_ROOT44_CONTROL_CLR) 32 RW 0000_0000
160C Clock root control (CLOCK_ROOT44_CONTROL_TOG) 32 RW 0000_0000
1630 Clock root access control (CLOCK_ROOT44_AUTHEN) 32 RW 0000_0000
1634 Clock root access control (CLOCK_ROOT44_AUTHEN_SET) 32 RW 0000_0000
1638 Clock root access control (CLOCK_ROOT44_AUTHEN_CLR) 32 RW 0000_0000
163C Clock root access control (CLOCK_ROOT44_AUTHEN_TOG) 32 RW 0000_0000
1680 Clock root control (CLOCK_ROOT45_CONTROL) 32 RW 0000_0000
1684 Clock root control (CLOCK_ROOT45_CONTROL_SET) 32 RW 0000_0000
1688 Clock root control (CLOCK_ROOT45_CONTROL_CLR) 32 RW 0000_0000
168C Clock root control (CLOCK_ROOT45_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1522 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
16B0 Clock root access control (CLOCK_ROOT45_AUTHEN) 32 RW 0000_0000
16B4 Clock root access control (CLOCK_ROOT45_AUTHEN_SET) 32 RW 0000_0000
16B8 Clock root access control (CLOCK_ROOT45_AUTHEN_CLR) 32 RW 0000_0000
16BC Clock root access control (CLOCK_ROOT45_AUTHEN_TOG) 32 RW 0000_0000
1700 Clock root control (CLOCK_ROOT46_CONTROL) 32 RW 0000_0000
1704 Clock root control (CLOCK_ROOT46_CONTROL_SET) 32 RW 0000_0000
1708 Clock root control (CLOCK_ROOT46_CONTROL_CLR) 32 RW 0000_0000
170C Clock root control (CLOCK_ROOT46_CONTROL_TOG) 32 RW 0000_0000
1730 Clock root access control (CLOCK_ROOT46_AUTHEN) 32 RW 0000_0000
1734 Clock root access control (CLOCK_ROOT46_AUTHEN_SET) 32 RW 0000_0000
1738 Clock root access control (CLOCK_ROOT46_AUTHEN_CLR) 32 RW 0000_0000
173C Clock root access control (CLOCK_ROOT46_AUTHEN_TOG) 32 RW 0000_0000
1780 Clock root control (CLOCK_ROOT47_CONTROL) 32 RW 0000_0000
1784 Clock root control (CLOCK_ROOT47_CONTROL_SET) 32 RW 0000_0000
1788 Clock root control (CLOCK_ROOT47_CONTROL_CLR) 32 RW 0000_0000
178C Clock root control (CLOCK_ROOT47_CONTROL_TOG) 32 RW 0000_0000
17B0 Clock root access control (CLOCK_ROOT47_AUTHEN) 32 RW 0000_0000
17B4 Clock root access control (CLOCK_ROOT47_AUTHEN_SET) 32 RW 0000_0000
17B8 Clock root access control (CLOCK_ROOT47_AUTHEN_CLR) 32 RW 0000_0000
17BC Clock root access control (CLOCK_ROOT47_AUTHEN_TOG) 32 RW 0000_0000
1800 Clock root control (CLOCK_ROOT48_CONTROL) 32 RW 0000_0000
1804 Clock root control (CLOCK_ROOT48_CONTROL_SET) 32 RW 0000_0000
1808 Clock root control (CLOCK_ROOT48_CONTROL_CLR) 32 RW 0000_0000
180C Clock root control (CLOCK_ROOT48_CONTROL_TOG) 32 RW 0000_0000
1830 Clock root access control (CLOCK_ROOT48_AUTHEN) 32 RW 0000_0000
1834 Clock root access control (CLOCK_ROOT48_AUTHEN_SET) 32 RW 0000_0000
1838 Clock root access control (CLOCK_ROOT48_AUTHEN_CLR) 32 RW 0000_0000
183C Clock root access control (CLOCK_ROOT48_AUTHEN_TOG) 32 RW 0000_0000
1880 Clock root control (CLOCK_ROOT49_CONTROL) 32 RW 0000_0000
1884 Clock root control (CLOCK_ROOT49_CONTROL_SET) 32 RW 0000_0000
1888 Clock root control (CLOCK_ROOT49_CONTROL_CLR) 32 RW 0000_0000
188C Clock root control (CLOCK_ROOT49_CONTROL_TOG) 32 RW 0000_0000
18B0 Clock root access control (CLOCK_ROOT49_AUTHEN) 32 RW 0000_0000
18B4 Clock root access control (CLOCK_ROOT49_AUTHEN_SET) 32 RW 0000_0000
18B8 Clock root access control (CLOCK_ROOT49_AUTHEN_CLR) 32 RW 0000_0000
18BC Clock root access control (CLOCK_ROOT49_AUTHEN_TOG) 32 RW 0000_0000
1900 Clock root control (CLOCK_ROOT50_CONTROL) 32 RW 0000_0000
1904 Clock root control (CLOCK_ROOT50_CONTROL_SET) 32 RW 0000_0000
1908 Clock root control (CLOCK_ROOT50_CONTROL_CLR) 32 RW 0000_0000
190C Clock root control (CLOCK_ROOT50_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1523
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1930 Clock root access control (CLOCK_ROOT50_AUTHEN) 32 RW 0000_0000
1934 Clock root access control (CLOCK_ROOT50_AUTHEN_SET) 32 RW 0000_0000
1938 Clock root access control (CLOCK_ROOT50_AUTHEN_CLR) 32 RW 0000_0000
193C Clock root access control (CLOCK_ROOT50_AUTHEN_TOG) 32 RW 0000_0000
1980 Clock root control (CLOCK_ROOT51_CONTROL) 32 RW 0000_0000
1984 Clock root control (CLOCK_ROOT51_CONTROL_SET) 32 RW 0000_0000
1988 Clock root control (CLOCK_ROOT51_CONTROL_CLR) 32 RW 0000_0000
198C Clock root control (CLOCK_ROOT51_CONTROL_TOG) 32 RW 0000_0000
19B0 Clock root access control (CLOCK_ROOT51_AUTHEN) 32 RW 0000_0000
19B4 Clock root access control (CLOCK_ROOT51_AUTHEN_SET) 32 RW 0000_0000
19B8 Clock root access control (CLOCK_ROOT51_AUTHEN_CLR) 32 RW 0000_0000
19BC Clock root access control (CLOCK_ROOT51_AUTHEN_TOG) 32 RW 0000_0000
1A00 Clock root control (CLOCK_ROOT52_CONTROL) 32 RW 0000_0000
1A04 Clock root control (CLOCK_ROOT52_CONTROL_SET) 32 RW 0000_0000
1A08 Clock root control (CLOCK_ROOT52_CONTROL_CLR) 32 RW 0000_0000
1A0C Clock root control (CLOCK_ROOT52_CONTROL_TOG) 32 RW 0000_0000
1A30 Clock root access control (CLOCK_ROOT52_AUTHEN) 32 RW 0000_0000
1A34 Clock root access control (CLOCK_ROOT52_AUTHEN_SET) 32 RW 0000_0000
1A38 Clock root access control (CLOCK_ROOT52_AUTHEN_CLR) 32 RW 0000_0000
1A3C Clock root access control (CLOCK_ROOT52_AUTHEN_TOG) 32 RW 0000_0000
1A80 Clock root control (CLOCK_ROOT53_CONTROL) 32 RW 0000_0000
1A84 Clock root control (CLOCK_ROOT53_CONTROL_SET) 32 RW 0000_0000
1A88 Clock root control (CLOCK_ROOT53_CONTROL_CLR) 32 RW 0000_0000
1A8C Clock root control (CLOCK_ROOT53_CONTROL_TOG) 32 RW 0000_0000
1AB0 Clock root access control (CLOCK_ROOT53_AUTHEN) 32 RW 0000_0000
1AB4 Clock root access control (CLOCK_ROOT53_AUTHEN_SET) 32 RW 0000_0000
1AB8 Clock root access control (CLOCK_ROOT53_AUTHEN_CLR) 32 RW 0000_0000
1ABC Clock root access control (CLOCK_ROOT53_AUTHEN_TOG) 32 RW 0000_0000
1B00 Clock root control (CLOCK_ROOT54_CONTROL) 32 RW 0000_0000
1B04 Clock root control (CLOCK_ROOT54_CONTROL_SET) 32 RW 0000_0000
1B08 Clock root control (CLOCK_ROOT54_CONTROL_CLR) 32 RW 0000_0000
1B0C Clock root control (CLOCK_ROOT54_CONTROL_TOG) 32 RW 0000_0000
1B30 Clock root access control (CLOCK_ROOT54_AUTHEN) 32 RW 0000_0000
1B34 Clock root access control (CLOCK_ROOT54_AUTHEN_SET) 32 RW 0000_0000
1B38 Clock root access control (CLOCK_ROOT54_AUTHEN_CLR) 32 RW 0000_0000
1B3C Clock root access control (CLOCK_ROOT54_AUTHEN_TOG) 32 RW 0000_0000
1B80 Clock root control (CLOCK_ROOT55_CONTROL) 32 RW 0000_0000
1B84 Clock root control (CLOCK_ROOT55_CONTROL_SET) 32 RW 0000_0000
1B88 Clock root control (CLOCK_ROOT55_CONTROL_CLR) 32 RW 0000_0000
1B8C Clock root control (CLOCK_ROOT55_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1524 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1BB0 Clock root access control (CLOCK_ROOT55_AUTHEN) 32 RW 0000_0000
1BB4 Clock root access control (CLOCK_ROOT55_AUTHEN_SET) 32 RW 0000_0000
1BB8 Clock root access control (CLOCK_ROOT55_AUTHEN_CLR) 32 RW 0000_0000
1BBC Clock root access control (CLOCK_ROOT55_AUTHEN_TOG) 32 RW 0000_0000
1C00 Clock root control (CLOCK_ROOT56_CONTROL) 32 RW 0000_0000
1C04 Clock root control (CLOCK_ROOT56_CONTROL_SET) 32 RW 0000_0000
1C08 Clock root control (CLOCK_ROOT56_CONTROL_CLR) 32 RW 0000_0000
1C0C Clock root control (CLOCK_ROOT56_CONTROL_TOG) 32 RW 0000_0000
1C30 Clock root access control (CLOCK_ROOT56_AUTHEN) 32 RW 0000_0000
1C34 Clock root access control (CLOCK_ROOT56_AUTHEN_SET) 32 RW 0000_0000
1C38 Clock root access control (CLOCK_ROOT56_AUTHEN_CLR) 32 RW 0000_0000
1C3C Clock root access control (CLOCK_ROOT56_AUTHEN_TOG) 32 RW 0000_0000
1C80 Clock root control (CLOCK_ROOT57_CONTROL) 32 RW 0000_0000
1C84 Clock root control (CLOCK_ROOT57_CONTROL_SET) 32 RW 0000_0000
1C88 Clock root control (CLOCK_ROOT57_CONTROL_CLR) 32 RW 0000_0000
1C8C Clock root control (CLOCK_ROOT57_CONTROL_TOG) 32 RW 0000_0000
1CB0 Clock root access control (CLOCK_ROOT57_AUTHEN) 32 RW 0000_0000
1CB4 Clock root access control (CLOCK_ROOT57_AUTHEN_SET) 32 RW 0000_0000
1CB8 Clock root access control (CLOCK_ROOT57_AUTHEN_CLR) 32 RW 0000_0000
1CBC Clock root access control (CLOCK_ROOT57_AUTHEN_TOG) 32 RW 0000_0000
1D00 Clock root control (CLOCK_ROOT58_CONTROL) 32 RW 0000_0000
1D04 Clock root control (CLOCK_ROOT58_CONTROL_SET) 32 RW 0000_0000
1D08 Clock root control (CLOCK_ROOT58_CONTROL_CLR) 32 RW 0000_0000
1D0C Clock root control (CLOCK_ROOT58_CONTROL_TOG) 32 RW 0000_0000
1D30 Clock root access control (CLOCK_ROOT58_AUTHEN) 32 RW 0000_0000
1D34 Clock root access control (CLOCK_ROOT58_AUTHEN_SET) 32 RW 0000_0000
1D38 Clock root access control (CLOCK_ROOT58_AUTHEN_CLR) 32 RW 0000_0000
1D3C Clock root access control (CLOCK_ROOT58_AUTHEN_TOG) 32 RW 0000_0000
1D80 Clock root control (CLOCK_ROOT59_CONTROL) 32 RW 0000_0000
1D84 Clock root control (CLOCK_ROOT59_CONTROL_SET) 32 RW 0000_0000
1D88 Clock root control (CLOCK_ROOT59_CONTROL_CLR) 32 RW 0000_0000
1D8C Clock root control (CLOCK_ROOT59_CONTROL_TOG) 32 RW 0000_0000
1DB0 Clock root access control (CLOCK_ROOT59_AUTHEN) 32 RW 0000_0000
1DB4 Clock root access control (CLOCK_ROOT59_AUTHEN_SET) 32 RW 0000_0000
1DB8 Clock root access control (CLOCK_ROOT59_AUTHEN_CLR) 32 RW 0000_0000
1DBC Clock root access control (CLOCK_ROOT59_AUTHEN_TOG) 32 RW 0000_0000
1E00 Clock root control (CLOCK_ROOT60_CONTROL) 32 RW 0000_0000
1E04 Clock root control (CLOCK_ROOT60_CONTROL_SET) 32 RW 0000_0000
1E08 Clock root control (CLOCK_ROOT60_CONTROL_CLR) 32 RW 0000_0000
1E0C Clock root control (CLOCK_ROOT60_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1525
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1E30 Clock root access control (CLOCK_ROOT60_AUTHEN) 32 RW 0000_0000
1E34 Clock root access control (CLOCK_ROOT60_AUTHEN_SET) 32 RW 0000_0000
1E38 Clock root access control (CLOCK_ROOT60_AUTHEN_CLR) 32 RW 0000_0000
1E3C Clock root access control (CLOCK_ROOT60_AUTHEN_TOG) 32 RW 0000_0000
1E80 Clock root control (CLOCK_ROOT61_CONTROL) 32 RW 0000_0000
1E84 Clock root control (CLOCK_ROOT61_CONTROL_SET) 32 RW 0000_0000
1E88 Clock root control (CLOCK_ROOT61_CONTROL_CLR) 32 RW 0000_0000
1E8C Clock root control (CLOCK_ROOT61_CONTROL_TOG) 32 RW 0000_0000
1EB0 Clock root access control (CLOCK_ROOT61_AUTHEN) 32 RW 0000_0000
1EB4 Clock root access control (CLOCK_ROOT61_AUTHEN_SET) 32 RW 0000_0000
1EB8 Clock root access control (CLOCK_ROOT61_AUTHEN_CLR) 32 RW 0000_0000
1EBC Clock root access control (CLOCK_ROOT61_AUTHEN_TOG) 32 RW 0000_0000
1F00 Clock root control (CLOCK_ROOT62_CONTROL) 32 RW 0000_0000
1F04 Clock root control (CLOCK_ROOT62_CONTROL_SET) 32 RW 0000_0000
1F08 Clock root control (CLOCK_ROOT62_CONTROL_CLR) 32 RW 0000_0000
1F0C Clock root control (CLOCK_ROOT62_CONTROL_TOG) 32 RW 0000_0000
1F30 Clock root access control (CLOCK_ROOT62_AUTHEN) 32 RW 0000_0000
1F34 Clock root access control (CLOCK_ROOT62_AUTHEN_SET) 32 RW 0000_0000
1F38 Clock root access control (CLOCK_ROOT62_AUTHEN_CLR) 32 RW 0000_0000
1F3C Clock root access control (CLOCK_ROOT62_AUTHEN_TOG) 32 RW 0000_0000
1F80 Clock root control (CLOCK_ROOT63_CONTROL) 32 RW 0000_0000
1F84 Clock root control (CLOCK_ROOT63_CONTROL_SET) 32 RW 0000_0000
1F88 Clock root control (CLOCK_ROOT63_CONTROL_CLR) 32 RW 0000_0000
1F8C Clock root control (CLOCK_ROOT63_CONTROL_TOG) 32 RW 0000_0000
1FB0 Clock root access control (CLOCK_ROOT63_AUTHEN) 32 RW 0000_0000
1FB4 Clock root access control (CLOCK_ROOT63_AUTHEN_SET) 32 RW 0000_0000
1FB8 Clock root access control (CLOCK_ROOT63_AUTHEN_CLR) 32 RW 0000_0000
1FBC Clock root access control (CLOCK_ROOT63_AUTHEN_TOG) 32 RW 0000_0000
2000 Clock root control (CLOCK_ROOT64_CONTROL) 32 RW 0000_0000
2004 Clock root control (CLOCK_ROOT64_CONTROL_SET) 32 RW 0000_0000
2008 Clock root control (CLOCK_ROOT64_CONTROL_CLR) 32 RW 0000_0000
200C Clock root control (CLOCK_ROOT64_CONTROL_TOG) 32 RW 0000_0000
2030 Clock root access control (CLOCK_ROOT64_AUTHEN) 32 RW 0000_0000
2034 Clock root access control (CLOCK_ROOT64_AUTHEN_SET) 32 RW 0000_0000
2038 Clock root access control (CLOCK_ROOT64_AUTHEN_CLR) 32 RW 0000_0000
203C Clock root access control (CLOCK_ROOT64_AUTHEN_TOG) 32 RW 0000_0000
2080 Clock root control (CLOCK_ROOT65_CONTROL) 32 RW 0000_0000
2084 Clock root control (CLOCK_ROOT65_CONTROL_SET) 32 RW 0000_0000
2088 Clock root control (CLOCK_ROOT65_CONTROL_CLR) 32 RW 0000_0000
208C Clock root control (CLOCK_ROOT65_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1526 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
20B0 Clock root access control (CLOCK_ROOT65_AUTHEN) 32 RW 0000_0000
20B4 Clock root access control (CLOCK_ROOT65_AUTHEN_SET) 32 RW 0000_0000
20B8 Clock root access control (CLOCK_ROOT65_AUTHEN_CLR) 32 RW 0000_0000
20BC Clock root access control (CLOCK_ROOT65_AUTHEN_TOG) 32 RW 0000_0000
2100 Clock root control (CLOCK_ROOT66_CONTROL) 32 RW 0000_0000
2104 Clock root control (CLOCK_ROOT66_CONTROL_SET) 32 RW 0000_0000
2108 Clock root control (CLOCK_ROOT66_CONTROL_CLR) 32 RW 0000_0000
210C Clock root control (CLOCK_ROOT66_CONTROL_TOG) 32 RW 0000_0000
2130 Clock root access control (CLOCK_ROOT66_AUTHEN) 32 RW 0000_0000
2134 Clock root access control (CLOCK_ROOT66_AUTHEN_SET) 32 RW 0000_0000
2138 Clock root access control (CLOCK_ROOT66_AUTHEN_CLR) 32 RW 0000_0000
213C Clock root access control (CLOCK_ROOT66_AUTHEN_TOG) 32 RW 0000_0000
2180 Clock root control (CLOCK_ROOT67_CONTROL) 32 RW 0000_0000
2184 Clock root control (CLOCK_ROOT67_CONTROL_SET) 32 RW 0000_0000
2188 Clock root control (CLOCK_ROOT67_CONTROL_CLR) 32 RW 0000_0000
218C Clock root control (CLOCK_ROOT67_CONTROL_TOG) 32 RW 0000_0000
21B0 Clock root access control (CLOCK_ROOT67_AUTHEN) 32 RW 0000_0000
21B4 Clock root access control (CLOCK_ROOT67_AUTHEN_SET) 32 RW 0000_0000
21B8 Clock root access control (CLOCK_ROOT67_AUTHEN_CLR) 32 RW 0000_0000
21BC Clock root access control (CLOCK_ROOT67_AUTHEN_TOG) 32 RW 0000_0000
2200 Clock root control (CLOCK_ROOT68_CONTROL) 32 RW 0000_0000
2204 Clock root control (CLOCK_ROOT68_CONTROL_SET) 32 RW 0000_0000
2208 Clock root control (CLOCK_ROOT68_CONTROL_CLR) 32 RW 0000_0000
220C Clock root control (CLOCK_ROOT68_CONTROL_TOG) 32 RW 0000_0000
2230 Clock root access control (CLOCK_ROOT68_AUTHEN) 32 RW 0000_0000
2234 Clock root access control (CLOCK_ROOT68_AUTHEN_SET) 32 RW 0000_0000
2238 Clock root access control (CLOCK_ROOT68_AUTHEN_CLR) 32 RW 0000_0000
223C Clock root access control (CLOCK_ROOT68_AUTHEN_TOG) 32 RW 0000_0000
2280 Clock root control (CLOCK_ROOT69_CONTROL) 32 RW 0000_0000
2284 Clock root control (CLOCK_ROOT69_CONTROL_SET) 32 RW 0000_0000
2288 Clock root control (CLOCK_ROOT69_CONTROL_CLR) 32 RW 0000_0000
228C Clock root control (CLOCK_ROOT69_CONTROL_TOG) 32 RW 0000_0000
22B0 Clock root access control (CLOCK_ROOT69_AUTHEN) 32 RW 0000_0000
22B4 Clock root access control (CLOCK_ROOT69_AUTHEN_SET) 32 RW 0000_0000
22B8 Clock root access control (CLOCK_ROOT69_AUTHEN_CLR) 32 RW 0000_0000
22BC Clock root access control (CLOCK_ROOT69_AUTHEN_TOG) 32 RW 0000_0000
2300 Clock root control (CLOCK_ROOT70_CONTROL) 32 RW 0000_0000
2304 Clock root control (CLOCK_ROOT70_CONTROL_SET) 32 RW 0000_0000
2308 Clock root control (CLOCK_ROOT70_CONTROL_CLR) 32 RW 0000_0000
230C Clock root control (CLOCK_ROOT70_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1527
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
2330 Clock root access control (CLOCK_ROOT70_AUTHEN) 32 RW 0000_0000
2334 Clock root access control (CLOCK_ROOT70_AUTHEN_SET) 32 RW 0000_0000
2338 Clock root access control (CLOCK_ROOT70_AUTHEN_CLR) 32 RW 0000_0000
233C Clock root access control (CLOCK_ROOT70_AUTHEN_TOG) 32 RW 0000_0000
2380 Clock root control (CLOCK_ROOT71_CONTROL) 32 RW 0000_0000
2384 Clock root control (CLOCK_ROOT71_CONTROL_SET) 32 RW 0000_0000
2388 Clock root control (CLOCK_ROOT71_CONTROL_CLR) 32 RW 0000_0000
238C Clock root control (CLOCK_ROOT71_CONTROL_TOG) 32 RW 0000_0000
23B0 Clock root access control (CLOCK_ROOT71_AUTHEN) 32 RW 0000_0000
23B4 Clock root access control (CLOCK_ROOT71_AUTHEN_SET) 32 RW 0000_0000
23B8 Clock root access control (CLOCK_ROOT71_AUTHEN_CLR) 32 RW 0000_0000
23BC Clock root access control (CLOCK_ROOT71_AUTHEN_TOG) 32 RW 0000_0000
2400 Clock root control (CLOCK_ROOT72_CONTROL) 32 RW 0000_0000
2404 Clock root control (CLOCK_ROOT72_CONTROL_SET) 32 RW 0000_0000
2408 Clock root control (CLOCK_ROOT72_CONTROL_CLR) 32 RW 0000_0000
240C Clock root control (CLOCK_ROOT72_CONTROL_TOG) 32 RW 0000_0000
2430 Clock root access control (CLOCK_ROOT72_AUTHEN) 32 RW 0000_0000
2434 Clock root access control (CLOCK_ROOT72_AUTHEN_SET) 32 RW 0000_0000
2438 Clock root access control (CLOCK_ROOT72_AUTHEN_CLR) 32 RW 0000_0000
243C Clock root access control (CLOCK_ROOT72_AUTHEN_TOG) 32 RW 0000_0000
2480 Clock root control (CLOCK_ROOT73_CONTROL) 32 RW 0000_0000
2484 Clock root control (CLOCK_ROOT73_CONTROL_SET) 32 RW 0000_0000
2488 Clock root control (CLOCK_ROOT73_CONTROL_CLR) 32 RW 0000_0000
248C Clock root control (CLOCK_ROOT73_CONTROL_TOG) 32 RW 0000_0000
24B0 Clock root access control (CLOCK_ROOT73_AUTHEN) 32 RW 0000_0000
24B4 Clock root access control (CLOCK_ROOT73_AUTHEN_SET) 32 RW 0000_0000
24B8 Clock root access control (CLOCK_ROOT73_AUTHEN_CLR) 32 RW 0000_0000
24BC Clock root access control (CLOCK_ROOT73_AUTHEN_TOG) 32 RW 0000_0000
2500 Clock root control (CLOCK_ROOT74_CONTROL) 32 RW 0000_0000
2504 Clock root control (CLOCK_ROOT74_CONTROL_SET) 32 RW 0000_0000
2508 Clock root control (CLOCK_ROOT74_CONTROL_CLR) 32 RW 0000_0000
250C Clock root control (CLOCK_ROOT74_CONTROL_TOG) 32 RW 0000_0000
2530 Clock root access control (CLOCK_ROOT74_AUTHEN) 32 RW 0000_0000
2534 Clock root access control (CLOCK_ROOT74_AUTHEN_SET) 32 RW 0000_0000
2538 Clock root access control (CLOCK_ROOT74_AUTHEN_CLR) 32 RW 0000_0000
253C Clock root access control (CLOCK_ROOT74_AUTHEN_TOG) 32 RW 0000_0000
2580 Clock root control (CLOCK_ROOT75_CONTROL) 32 RW 0000_0000
2584 Clock root control (CLOCK_ROOT75_CONTROL_SET) 32 RW 0000_0000
2588 Clock root control (CLOCK_ROOT75_CONTROL_CLR) 32 RW 0000_0000
258C Clock root control (CLOCK_ROOT75_CONTROL_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1528 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
25B0 Clock root access control (CLOCK_ROOT75_AUTHEN) 32 RW 0000_0000
25B4 Clock root access control (CLOCK_ROOT75_AUTHEN_SET) 32 RW 0000_0000
25B8 Clock root access control (CLOCK_ROOT75_AUTHEN_CLR) 32 RW 0000_0000
25BC Clock root access control (CLOCK_ROOT75_AUTHEN_TOG) 32 RW 0000_0000
2600 Clock root control (CLOCK_ROOT76_CONTROL) 32 RW 0000_0000
2604 Clock root control (CLOCK_ROOT76_CONTROL_SET) 32 RW 0000_0000
2608 Clock root control (CLOCK_ROOT76_CONTROL_CLR) 32 RW 0000_0000
260C Clock root control (CLOCK_ROOT76_CONTROL_TOG) 32 RW 0000_0000
2630 Clock root access control (CLOCK_ROOT76_AUTHEN) 32 RW 0000_0000
2634 Clock root access control (CLOCK_ROOT76_AUTHEN_SET) 32 RW 0000_0000
2638 Clock root access control (CLOCK_ROOT76_AUTHEN_CLR) 32 RW 0000_0000
263C Clock root access control (CLOCK_ROOT76_AUTHEN_TOG) 32 RW 0000_0000
2680 Clock root control (CLOCK_ROOT77_CONTROL) 32 RW 0000_0000
2684 Clock root control (CLOCK_ROOT77_CONTROL_SET) 32 RW 0000_0000
2688 Clock root control (CLOCK_ROOT77_CONTROL_CLR) 32 RW 0000_0000
268C Clock root control (CLOCK_ROOT77_CONTROL_TOG) 32 RW 0000_0000
26B0 Clock root access control (CLOCK_ROOT77_AUTHEN) 32 RW 0000_0000
26B4 Clock root access control (CLOCK_ROOT77_AUTHEN_SET) 32 RW 0000_0000
26B8 Clock root access control (CLOCK_ROOT77_AUTHEN_CLR) 32 RW 0000_0000
26BC Clock root access control (CLOCK_ROOT77_AUTHEN_TOG) 32 RW 0000_0000
2700 Clock root control (CLOCK_ROOT78_CONTROL) 32 RW 0000_0000
2704 Clock root control (CLOCK_ROOT78_CONTROL_SET) 32 RW 0000_0000
2708 Clock root control (CLOCK_ROOT78_CONTROL_CLR) 32 RW 0000_0000
270C Clock root control (CLOCK_ROOT78_CONTROL_TOG) 32 RW 0000_0000
2730 Clock root access control (CLOCK_ROOT78_AUTHEN) 32 RW 0000_0000
2734 Clock root access control (CLOCK_ROOT78_AUTHEN_SET) 32 RW 0000_0000
2738 Clock root access control (CLOCK_ROOT78_AUTHEN_CLR) 32 RW 0000_0000
273C Clock root access control (CLOCK_ROOT78_AUTHEN_TOG) 32 RW 0000_0000
4000 Clock group control (CLOCK_GROUP0_CONTROL) 32 RW 0000_0000
4004 Clock group control (CLOCK_GROUP0_CONTROL_SET) 32 RW 0000_0000
4008 Clock group control (CLOCK_GROUP0_CONTROL_CLR) 32 RW 0000_0000
400C Clock group control (CLOCK_GROUP0_CONTROL_TOG) 32 RW 0000_0000
4020 - 40A0 Clock group working status (CLOCK_GROUP0_STATUS0 - 32 RW 0000_0000
CLOCK_GROUP1_STATUS0)
4024 - 40A4 Clock group low power/extend status (CLOCK_GROUP0_STATUS1 - 32 RO 0000_0000
CLOCK_GROUP1_STATUS1)
402C - 40AC Clock group configuration (CLOCK_GROUP0_CONFIG - 32 RO Table 15-6
CLOCK_GROUP1_CONFIG)
4030 Clock group access control (CLOCK_GROUP0_AUTHEN) 32 RW 0000_0000
4034 Clock group access control (CLOCK_GROUP0_AUTHEN_SET) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1529
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4038 Clock group access control (CLOCK_GROUP0_AUTHEN_CLR) 32 RW 0000_0000
403C Clock group access control (CLOCK_GROUP0_AUTHEN_TOG) 32 RW 0000_0000
4040 - 40FC Setpoint setting (CLOCK_GROUP0_SETPOINT0 - 32 RW 0000_0000
CLOCK_GROUP1_SETPOINT15)
4080 Clock group control (CLOCK_GROUP1_CONTROL) 32 RW 0000_0000
4084 Clock group control (CLOCK_GROUP1_CONTROL_SET) 32 RW 0000_0000
4088 Clock group control (CLOCK_GROUP1_CONTROL_CLR) 32 RW 0000_0000
408C Clock group control (CLOCK_GROUP1_CONTROL_TOG) 32 RW 0000_0000
40B0 Clock group access control (CLOCK_GROUP1_AUTHEN) 32 RW 0000_0000
40B4 Clock group access control (CLOCK_GROUP1_AUTHEN_SET) 32 RW 0000_0000
40B8 Clock group access control (CLOCK_GROUP1_AUTHEN_CLR) 32 RW 0000_0000
40BC Clock group access control (CLOCK_GROUP1_AUTHEN_TOG) 32 RW 0000_0000
4800 General Purpose Register (GPR_SHARED0) 32 RW 0000_0000
4804 General Purpose Register (GPR_SHARED0_SET) 32 RW 0000_0000
4808 General Purpose Register (GPR_SHARED0_CLR) 32 RW 0000_0000
480C General Purpose Register (GPR_SHARED0_TOG) 32 RW 0000_0000
4810 GPR access control (GPR_SHARED0_AUTHEN) 32 RW 0000_0000
4814 GPR access control (GPR_SHARED0_AUTHEN_SET) 32 RW 0000_0000
4818 GPR access control (GPR_SHARED0_AUTHEN_CLR) 32 RW 0000_0000
481C GPR access control (GPR_SHARED0_AUTHEN_TOG) 32 RW 0000_0000
4820 General Purpose Register (GPR_SHARED1) 32 RW 0000_0000
4824 General Purpose Register (GPR_SHARED1_SET) 32 RW 0000_0000
4828 General Purpose Register (GPR_SHARED1_CLR) 32 RW 0000_0000
482C General Purpose Register (GPR_SHARED1_TOG) 32 RW 0000_0000
4830 GPR access control (GPR_SHARED1_AUTHEN) 32 RW 0000_0000
4834 GPR access control (GPR_SHARED1_AUTHEN_SET) 32 RW 0000_0000
4838 GPR access control (GPR_SHARED1_AUTHEN_CLR) 32 RW 0000_0000
483C GPR access control (GPR_SHARED1_AUTHEN_TOG) 32 RW 0000_0000
4840 General Purpose Register (GPR_SHARED2) 32 RW 0000_0000
4844 General Purpose Register (GPR_SHARED2_SET) 32 RW 0000_0000
4848 General Purpose Register (GPR_SHARED2_CLR) 32 RW 0000_0000
484C General Purpose Register (GPR_SHARED2_TOG) 32 RW 0000_0000
4850 GPR access control (GPR_SHARED2_AUTHEN) 32 RW 0000_0000
4854 GPR access control (GPR_SHARED2_AUTHEN_SET) 32 RW 0000_0000
4858 GPR access control (GPR_SHARED2_AUTHEN_CLR) 32 RW 0000_0000
485C GPR access control (GPR_SHARED2_AUTHEN_TOG) 32 RW 0000_0000
4860 General Purpose Register (GPR_SHARED3) 32 RW 0000_0000
4864 General Purpose Register (GPR_SHARED3_SET) 32 RW 0000_0000
4868 General Purpose Register (GPR_SHARED3_CLR) 32 RW 0000_0000
486C General Purpose Register (GPR_SHARED3_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1530 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4870 GPR access control (GPR_SHARED3_AUTHEN) 32 RW 0000_0000
4874 GPR access control (GPR_SHARED3_AUTHEN_SET) 32 RW 0000_0000
4878 GPR access control (GPR_SHARED3_AUTHEN_CLR) 32 RW 0000_0000
487C GPR access control (GPR_SHARED3_AUTHEN_TOG) 32 RW 0000_0000
4880 General Purpose Register (GPR_SHARED4) 32 RW 0000_0000
4884 General Purpose Register (GPR_SHARED4_SET) 32 RW 0000_0000
4888 General Purpose Register (GPR_SHARED4_CLR) 32 RW 0000_0000
488C General Purpose Register (GPR_SHARED4_TOG) 32 RW 0000_0000
4890 GPR access control (GPR_SHARED4_AUTHEN) 32 RW 0000_0000
4894 GPR access control (GPR_SHARED4_AUTHEN_SET) 32 RW 0000_0000
4898 GPR access control (GPR_SHARED4_AUTHEN_CLR) 32 RW 0000_0000
489C GPR access control (GPR_SHARED4_AUTHEN_TOG) 32 RW 0000_0000
48A0 General Purpose Register (GPR_SHARED5) 32 RW 0000_0000
48A4 General Purpose Register (GPR_SHARED5_SET) 32 RW 0000_0000
48A8 General Purpose Register (GPR_SHARED5_CLR) 32 RW 0000_0000
48AC General Purpose Register (GPR_SHARED5_TOG) 32 RW 0000_0000
48B0 GPR access control (GPR_SHARED5_AUTHEN) 32 RW 0000_0000
48B4 GPR access control (GPR_SHARED5_AUTHEN_SET) 32 RW 0000_0000
48B8 GPR access control (GPR_SHARED5_AUTHEN_CLR) 32 RW 0000_0000
48BC GPR access control (GPR_SHARED5_AUTHEN_TOG) 32 RW 0000_0000
48C0 General Purpose Register (GPR_SHARED6) 32 RW 0000_0000
48C4 General Purpose Register (GPR_SHARED6_SET) 32 RW 0000_0000
48C8 General Purpose Register (GPR_SHARED6_CLR) 32 RW 0000_0000
48CC General Purpose Register (GPR_SHARED6_TOG) 32 RW 0000_0000
48D0 GPR access control (GPR_SHARED6_AUTHEN) 32 RW 0000_0000
48D4 GPR access control (GPR_SHARED6_AUTHEN_SET) 32 RW 0000_0000
48D8 GPR access control (GPR_SHARED6_AUTHEN_CLR) 32 RW 0000_0000
48DC GPR access control (GPR_SHARED6_AUTHEN_TOG) 32 RW 0000_0000
48E0 General Purpose Register (GPR_SHARED7) 32 RW 0000_0000
48E4 General Purpose Register (GPR_SHARED7_SET) 32 RW 0000_0000
48E8 General Purpose Register (GPR_SHARED7_CLR) 32 RW 0000_0000
48EC General Purpose Register (GPR_SHARED7_TOG) 32 RW 0000_0000
48F0 GPR access control (GPR_SHARED7_AUTHEN) 32 RW 0000_0000
48F4 GPR access control (GPR_SHARED7_AUTHEN_SET) 32 RW 0000_0000
48F8 GPR access control (GPR_SHARED7_AUTHEN_CLR) 32 RW 0000_0000
48FC GPR access control (GPR_SHARED7_AUTHEN_TOG) 32 RW 0000_0000
4C20 General Purpose Register (GPR_PRIVATE1) 32 RW 0000_0000
4C24 General Purpose Register (GPR_PRIVATE1_SET) 32 RW 0000_0000
4C28 General Purpose Register (GPR_PRIVATE1_CLR) 32 RW 0000_0000
4C2C General Purpose Register (GPR_PRIVATE1_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1531
Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4C30 GPR access control (GPR_PRIVATE1_AUTHEN) 32 RW 0000_0000
4C34 GPR access control (GPR_PRIVATE1_AUTHEN_SET) 32 RW 0000_0000
4C38 GPR access control (GPR_PRIVATE1_AUTHEN_CLR) 32 RW 0000_0000
4C3C GPR access control (GPR_PRIVATE1_AUTHEN_TOG) 32 RW 0000_0000
4C40 General Purpose Register (GPR_PRIVATE2) 32 RW 0000_0000
4C44 General Purpose Register (GPR_PRIVATE2_SET) 32 RW 0000_0000
4C48 General Purpose Register (GPR_PRIVATE2_CLR) 32 RW 0000_0000
4C4C General Purpose Register (GPR_PRIVATE2_TOG) 32 RW 0000_0000
4C50 GPR access control (GPR_PRIVATE2_AUTHEN) 32 RW 0000_0000
4C54 GPR access control (GPR_PRIVATE2_AUTHEN_SET) 32 RW 0000_0000
4C58 GPR access control (GPR_PRIVATE2_AUTHEN_CLR) 32 RW 0000_0000
4C5C GPR access control (GPR_PRIVATE2_AUTHEN_TOG) 32 RW 0000_0000
4C60 General Purpose Register (GPR_PRIVATE3) 32 RW 0000_0000
4C64 General Purpose Register (GPR_PRIVATE3_SET) 32 RW 0000_0000
4C68 General Purpose Register (GPR_PRIVATE3_CLR) 32 RW 0000_0000
4C6C General Purpose Register (GPR_PRIVATE3_TOG) 32 RW 0000_0000
4C70 GPR access control (GPR_PRIVATE3_AUTHEN) 32 RW 0000_0000
4C74 GPR access control (GPR_PRIVATE3_AUTHEN_SET) 32 RW 0000_0000
4C78 GPR access control (GPR_PRIVATE3_AUTHEN_CLR) 32 RW 0000_0000
4C7C GPR access control (GPR_PRIVATE3_AUTHEN_TOG) 32 RW 0000_0000
4C80 General Purpose Register (GPR_PRIVATE4) 32 RW 0000_0000
4C84 General Purpose Register (GPR_PRIVATE4_SET) 32 RW 0000_0000
4C88 General Purpose Register (GPR_PRIVATE4_CLR) 32 RW 0000_0000
4C8C General Purpose Register (GPR_PRIVATE4_TOG) 32 RW 0000_0000
4C90 GPR access control (GPR_PRIVATE4_AUTHEN) 32 RW 0000_0000
4C94 GPR access control (GPR_PRIVATE4_AUTHEN_SET) 32 RW 0000_0000
4C98 GPR access control (GPR_PRIVATE4_AUTHEN_CLR) 32 RW 0000_0000
4C9C GPR access control (GPR_PRIVATE4_AUTHEN_TOG) 32 RW 0000_0000
4CA0 General Purpose Register (GPR_PRIVATE5) 32 RW 0000_0000
4CA4 General Purpose Register (GPR_PRIVATE5_SET) 32 RW 0000_0000
4CA8 General Purpose Register (GPR_PRIVATE5_CLR) 32 RW 0000_0000
4CAC General Purpose Register (GPR_PRIVATE5_TOG) 32 RW 0000_0000
4CB0 GPR access control (GPR_PRIVATE5_AUTHEN) 32 RW 0000_0000
4CB4 GPR access control (GPR_PRIVATE5_AUTHEN_SET) 32 RW 0000_0000
4CB8 GPR access control (GPR_PRIVATE5_AUTHEN_CLR) 32 RW 0000_0000
4CBC GPR access control (GPR_PRIVATE5_AUTHEN_TOG) 32 RW 0000_0000
4CC0 General Purpose Register (GPR_PRIVATE6) 32 RW 0000_0000
4CC4 General Purpose Register (GPR_PRIVATE6_SET) 32 RW 0000_0000
4CC8 General Purpose Register (GPR_PRIVATE6_CLR) 32 RW 0000_0000
4CCC General Purpose Register (GPR_PRIVATE6_TOG) 32 RW 0000_0000
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1532 NXP Semiconductors
Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4CD0 GPR access control (GPR_PRIVATE6_AUTHEN) 32 RW 0000_0000
4CD4 GPR access control (GPR_PRIVATE6_AUTHEN_SET) 32 RW 0000_0000
4CD8 GPR access control (GPR_PRIVATE6_AUTHEN_CLR) 32 RW 0000_0000
4CDC GPR access control (GPR_PRIVATE6_AUTHEN_TOG) 32 RW 0000_0000
4CE0 General Purpose Register (GPR_PRIVATE7) 32 RW 0000_0000
4CE4 General Purpose Register (GPR_PRIVATE7_SET) 32 RW 0000_0000
4CE8 General Purpose Register (GPR_PRIVATE7_CLR) 32 RW 0000_0000
4CEC General Purpose Register (GPR_PRIVATE7_TOG) 32 RW 0000_0000
4CF0 GPR access control (GPR_PRIVATE7_AUTHEN) 32 RW 0000_0000
4CF4 GPR access control (GPR_PRIVATE7_AUTHEN_SET) 32 RW 0000_0000
4CF8 GPR access control (GPR_PRIVATE7_AUTHEN_CLR) 32 RW 0000_0000
4CFC GPR access control (GPR_PRIVATE7_AUTHEN_TOG) 32 RW 0000_0000
5000 - 5380 Clock source direct control (OSCPLL0_DIRECT - 32 RW 0000_0001
OSCPLL28_DIRECT)
5004 - 5384 Clock source domain control (OSCPLL0_DOMAIN - 32 RW 0001_0001
OSCPLL28_DOMAIN)
5008 - 5388 Clock source Setpoint setting (OSCPLL0_SETPOINT - 32 RW 0000_0000
OSCPLL28_SETPOINT)
5010 - 5390 Clock source working status (OSCPLL0_STATUS0 - 32 RO 0000_0000
OSCPLL28_STATUS0)
5014 - 5394 Clock source low power status (OSCPLL0_STATUS1 - 32 RO 0000_0000
OSCPLL28_STATUS1)
5018 - 5398 Clock source configuration (OSCPLL0_CONFIG - 32 RO Table 15-7
OSCPLL28_CONFIG)
501C - 539C Clock source access control (OSCPLL0_AUTHEN - 32 RW 0000_0000
OSCPLL28_AUTHEN)
6000 - 7120 LPCG direct control (LPCG0_DIRECT - LPCG137_DIRECT) 32 RW 0000_0001
6004 - 7124 LPCG domain control (LPCG0_DOMAIN - LPCG137_DOMAIN) 32 RW 0001_0001
6010 - 7130 LPCG working status (LPCG0_STATUS0 - LPCG137_STATUS0) 32 RO 0000_0000
6014 - 7134 LPCG low power status (LPCG0_STATUS1 - LPCG137_STATUS1) 32 RO 0000_0000
6018 - 7138 LPCG configuration (LPCG0_CONFIG - LPCG137_CONFIG) 32 RO Table 15-8
601C - 713C LPCG access control (LPCG0_AUTHEN - LPCG137_AUTHEN) 32 RW 0000_0000
6048 - 6608 LPCG Setpoint setting (LPCG2_SETPOINT - LPCG48_SETPOINT) 32 RW 0000_0000
15.9.1.2 Clock root control (CLOCK_ROOT0_CONTROL -
CLOCK_ROOT78_CONTROL)
This register controls clock root generation.
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Memory Map and register definition
15.9.1.2.1 Offset
For a = 0 to 78:
Register Offset Description
CLOCK_ROOTa_CONT 0h + (a × 80h) Clock root control
ROL
CLOCK_ROOTa_CONT 4h + (a × 80h) Writing a 1 to a bit in this register sets the
ROL_SET corresponding bit in CLOCK_ROOTa_CONTROL
CLOCK_ROOTa_CONT 8h + (a × 80h) Writing a 1 to a bit in this register clears the
ROL_CLR corresponding bit in CLOCK_ROOTa_CONTROL
CLOCK_ROOTa_CONT Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
ROL_TOG corresponding bit in CLOCK_ROOTa_CONTROL
15.9.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
Reserved OFF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved MUX DIV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.2.3 Fields
Field Description
31-25 Reserved
—
24 OFF
OFF Shutdown clock root
0 - Turn on clock
1 - Turn off clock
23-16 Reserved
—
15-11 Reserved
—
10-8 Clock multiplexer
MUX Select clock from 8 clock sources.
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Field Description
7-0 Clock divider
DIV Divider selected clock by DIV + 1.
15.9.1.3 Clock root working status (CLOCK_ROOT0_STATUS0 -
CLOCK_ROOT78_STATUS0)
This register shows current clock root running status.
15.9.1.3.1 Offset
For a = 0 to 78:
Register Offset
CLOCK_ROOTa_STATU 20h + (a × 80h)
S0
15.9.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE_FORWARD
UPDATE_REVERS
POWERDOWN
SLICE_BUS
CHANGING
Reserved
Reserved
OFF
R
Y
E
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MUX DIV
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.3.3 Fields
Field Description
31 Internal updating in clock root
Table continues on the next page...
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Memory Map and register definition
Field Description
CHANGING Indication for clock root logic is internal updating. This status is combination of UPDATE_FORWARD,
UPDATE_REVERSE, and SLICE_BUSY.
0 - Clock Status is not updating currently
1 - Clock generation logic is updating currently
30 Internal status synchronization from clock generation logic
UPDATE_REVE Indication for internal status synchronizing to clock generation logic.
RSE
0 - Synchronization not in process
1 - Synchronization in process
29 Internal status synchronization to clock generation logic
UPDATE_FOR Indication for clock status is synchronizing for clock root.
WARD
0 - Synchronization not in process
1 - Synchronization in process
28 Internal updating in generation logic
SLICE_BUSY Indication for clock generation logic is applying new setting.
0 - Clock generation logic is not busy
1 - Clock generation logic is applying the new setting
27 Current clock root POWERDOWN setting
POWERDOWN Current running state of POWERDOWN field for clock root.
0 - Clock root is running
1 - Clock root is Powered Down
26-25 Reserved
—
24 Current clock root OFF setting
OFF Current running state of OFF field for clock root.
0 - Clock is running
1 - Clock is disabled/off
23-16 Reserved
—
15-11 Reserved
—
10-8 Current clock root MUX setting
MUX Current running state of MUX field for clock root.
7-0 Current clock root DIV setting
DIV Current running state of DIV field for clock root.
15.9.1.4 Clock root low power status (CLOCK_ROOT0_STATUS1 -
CLOCK_ROOT78_STATUS1)
This register shows low power status of clock root.
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Chapter 15 Clock Controller Module (CCM)
15.9.1.4.1 Offset
For a = 0 to 78:
Register Offset
CLOCK_ROOTa_STATU 24h + (a × 80h)
S1
15.9.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT_SETPOINT
TARGET_SETPOINT
DOWN_REQUEST
DOWN_DONE
UP_REQUES
UP_DONE
Reserved
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.4.3 Fields
Field Description
31-28 Reserved
—
27 Clock frequency increase finish
UP_DONE Handshake signal with GPC status indicating frequency increase finish.
0 - Frequency increase not completed
1 - Frequency increase completed
26 Clock frequency increase request
UP_REQUEST Handshake signal with GPC status indicating frequency increase is requesting.
0 - Frequency increase not requested
1 - Frequency increase requested
Table continues on the next page...
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Memory Map and register definition
Field Description
25 Clock frequency decrease finish
DOWN_DONE Handshake signal with GPC status indicating frequency decrease finish.
0 - Frequency decrease not completed
1 - Frequency decrease completed
24 Clock frequency decrease request
DOWN_REQUE Handshake signal with GPC status indicating frequency decrease is requesting.
ST
0 - Frequency decrease not requested
1 - Frequency decrease requested
23-20 Current Setpoint
CURRENT_SET This is the Setpoint value the Soc is current working in.
POINT
19-16 Target Setpoint
TARGET_SETP This is the Setpoint value the SoC will switch to
OINT
15-0 Reserved
—
15.9.1.5 Clock root configuration (CLOCK_ROOT0_CONFIG -
CLOCK_ROOT78_CONFIG)
This register shows integration parameters
15.9.1.5.1 Offset
For a = 0 to 78:
Register Offset
CLOCK_ROOTa_CONFI 2Ch + (a × 80h)
G
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Chapter 15 Clock Controller Module (CCM)
15.9.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPOINT_PRESEN
Reserved
Reserved
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 u 0 0 0 0
15.9.1.5.3 Fields
Field Description
31-5 Reserved
—
4 Setpoint present
SETPOINT_PR This bit indicate whether this clock root implement Setpoint control scheme.
ESENT
0 - Setpoint is not implemented.
1 - Setpoint is implemented.
3-0 Reserved
—
15.9.1.6 Clock root access control (CLOCK_ROOT0_AUTHEN -
CLOCK_ROOT78_AUTHEN)
This register that manages clock root access control.
15.9.1.6.1 Offset
For a = 0 to 78:
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Memory Map and register definition
Register Offset Description
CLOCK_ROOTa_AUTHE 30h + (a × 80h) Clock root access control
N
CLOCK_ROOTa_AUTHE 34h + (a × 80h) Writing a 1 to a bit in this register sets the
N_SET corresponding bit in CLOCK_ROOTa_AUTHEN
CLOCK_ROOTa_AUTHE 38h + (a × 80h) Writing a 1 to a bit in this register clears the
N_CLR corresponding bit in CLOCK_ROOTa_AUTHEN
CLOCK_ROOTa_AUTHE 3Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
N_TOG corresponding bit in CLOCK_ROOTa_AUTHEN
15.9.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_MODE
DOMAIN_MODE
LOCK_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.6.3 Fields
Field Description
31-21 Reserved
—
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked
1 - MODE is locked
19-18 Reserved
—
17 Low power and access control by Setpoint
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Chapter 15 Clock Controller Module (CCM)
Field Description
SETPOINT_MO Clock root works in Setpoint controlled Mode
DE
0 - Clock does NOT work in Setpoint Mode
1 - Clock works in Setpoint Mode
16 Low power and access control by domain
DOMAIN_MOD Clock root works in domain controlled mode
E
0 - Clock does NOT work in Domain Mode
1 - Clock works in Domain Mode
15-13 Reserved
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, CLOCK_ROOTx_AUTHEN[WHITE_LIST] cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - Whitelist is not locked
1 - Whitelist is locked
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this clock root. Each field in this field represent for one domain.
Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
0000 - This domain is NOT allowed to change clock
0001 - This domain is allowed to change clock
7-5 Reserved
—
4 Lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked
1 - Trustzone setting is locked
3-2 Reserved
—
1 Non-secure access
TZ_NS This clock root can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode
1 - Can be changed in Non-secure mode
0 User access
TZ_USER This clock root can be changed when CPU is in user mode (in CMx core).
0 - Clock cannot be changed in user mode
1 - Clock can be changed in user mode
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Memory Map and register definition
15.9.1.7 Setpoint setting (CLOCK_ROOT0_SETPOINT0 -
CLOCK_ROOT78_SETPOINT15)
These registers define 16 clock root setting which will take effect when the system
switches to a corresponding Setpoint.
These 16 registers provide clock root generation settings for the Setpoint. Corresponding
settings will be automatically loaded when system low power mode transition takes
place.
The following clock roots support Setpoints:
• M7_CLK_ROOT
• M4_CLK_ROOT
• BUS_CLK_ROOT
• BUS_LPSR_CLK_ROOT
• SEMC_CLK_ROOT
• FLEXSPI1_CLK_ROOT
• FLEXSPI2_CLK_ROOT
• CCM_CLK01_CLK_ROOT
• CCM_CLKO2_CLK_ROOT
15.9.1.7.1 Offset
Register Offset
CLOCK_ROOT0_SETPO 40h
INT0
CLOCK_ROOT0_SETPO 44h
INT1
CLOCK_ROOT0_SETPO 48h
INT2
CLOCK_ROOT0_SETPO 4Ch
INT3
CLOCK_ROOT0_SETPO 50h
INT4
CLOCK_ROOT0_SETPO 54h
INT5
CLOCK_ROOT0_SETPO 58h
INT6
CLOCK_ROOT0_SETPO 5Ch
INT7
CLOCK_ROOT0_SETPO 60h
INT8
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Chapter 15 Clock Controller Module (CCM)
Register Offset
CLOCK_ROOT0_SETPO 64h
INT9
CLOCK_ROOT0_SETPO 68h
INT10
CLOCK_ROOT0_SETPO 6Ch
INT11
CLOCK_ROOT0_SETPO 70h
INT12
CLOCK_ROOT0_SETPO 74h
INT13
CLOCK_ROOT0_SETPO 78h
INT14
CLOCK_ROOT0_SETPO 7Ch
INT15
CLOCK_ROOT1_SETPO C0h
INT0
CLOCK_ROOT1_SETPO C4h
INT1
CLOCK_ROOT1_SETPO C8h
INT2
CLOCK_ROOT1_SETPO CCh
INT3
CLOCK_ROOT1_SETPO D0h
INT4
CLOCK_ROOT1_SETPO D4h
INT5
CLOCK_ROOT1_SETPO D8h
INT6
CLOCK_ROOT1_SETPO DCh
INT7
CLOCK_ROOT1_SETPO E0h
INT8
CLOCK_ROOT1_SETPO E4h
INT9
CLOCK_ROOT1_SETPO E8h
INT10
CLOCK_ROOT1_SETPO ECh
INT11
CLOCK_ROOT1_SETPO F0h
INT12
CLOCK_ROOT1_SETPO F4h
INT13
CLOCK_ROOT1_SETPO F8h
INT14
CLOCK_ROOT1_SETPO FCh
INT15
CLOCK_ROOT2_SETPO 140h
INT0
Table continues on the next page...
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Memory Map and register definition
Register Offset
CLOCK_ROOT2_SETPO 144h
INT1
CLOCK_ROOT2_SETPO 148h
INT2
CLOCK_ROOT2_SETPO 14Ch
INT3
CLOCK_ROOT2_SETPO 150h
INT4
CLOCK_ROOT2_SETPO 154h
INT5
CLOCK_ROOT2_SETPO 158h
INT6
CLOCK_ROOT2_SETPO 15Ch
INT7
CLOCK_ROOT2_SETPO 160h
INT8
CLOCK_ROOT2_SETPO 164h
INT9
CLOCK_ROOT2_SETPO 168h
INT10
CLOCK_ROOT2_SETPO 16Ch
INT11
CLOCK_ROOT2_SETPO 170h
INT12
CLOCK_ROOT2_SETPO 174h
INT13
CLOCK_ROOT2_SETPO 178h
INT14
CLOCK_ROOT2_SETPO 17Ch
INT15
CLOCK_ROOT3_SETPO 1C0h
INT0
CLOCK_ROOT3_SETPO 1C4h
INT1
CLOCK_ROOT3_SETPO 1C8h
INT2
CLOCK_ROOT3_SETPO 1CCh
INT3
CLOCK_ROOT3_SETPO 1D0h
INT4
CLOCK_ROOT3_SETPO 1D4h
INT5
CLOCK_ROOT3_SETPO 1D8h
INT6
CLOCK_ROOT3_SETPO 1DCh
INT7
CLOCK_ROOT3_SETPO 1E0h
INT8
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Chapter 15 Clock Controller Module (CCM)
Register Offset
CLOCK_ROOT3_SETPO 1E4h
INT9
CLOCK_ROOT3_SETPO 1E8h
INT10
CLOCK_ROOT3_SETPO 1ECh
INT11
CLOCK_ROOT3_SETPO 1F0h
INT12
CLOCK_ROOT3_SETPO 1F4h
INT13
CLOCK_ROOT3_SETPO 1F8h
INT14
CLOCK_ROOT3_SETPO 1FCh
INT15
CLOCK_ROOT4_SETPO 240h
INT0
CLOCK_ROOT4_SETPO 244h
INT1
CLOCK_ROOT4_SETPO 248h
INT2
CLOCK_ROOT4_SETPO 24Ch
INT3
CLOCK_ROOT4_SETPO 250h
INT4
CLOCK_ROOT4_SETPO 254h
INT5
CLOCK_ROOT4_SETPO 258h
INT6
CLOCK_ROOT4_SETPO 25Ch
INT7
CLOCK_ROOT4_SETPO 260h
INT8
CLOCK_ROOT4_SETPO 264h
INT9
CLOCK_ROOT4_SETPO 268h
INT10
CLOCK_ROOT4_SETPO 26Ch
INT11
CLOCK_ROOT4_SETPO 270h
INT12
CLOCK_ROOT4_SETPO 274h
INT13
CLOCK_ROOT4_SETPO 278h
INT14
CLOCK_ROOT4_SETPO 27Ch
INT15
CLOCK_ROOT20_SETP A40h
OINT0
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Memory Map and register definition
Register Offset
CLOCK_ROOT20_SETP A44h
OINT1
CLOCK_ROOT20_SETP A48h
OINT2
CLOCK_ROOT20_SETP A4Ch
OINT3
CLOCK_ROOT20_SETP A50h
OINT4
CLOCK_ROOT20_SETP A54h
OINT5
CLOCK_ROOT20_SETP A58h
OINT6
CLOCK_ROOT20_SETP A5Ch
OINT7
CLOCK_ROOT20_SETP A60h
OINT8
CLOCK_ROOT20_SETP A64h
OINT9
CLOCK_ROOT20_SETP A68h
OINT10
CLOCK_ROOT20_SETP A6Ch
OINT11
CLOCK_ROOT20_SETP A70h
OINT12
CLOCK_ROOT20_SETP A74h
OINT13
CLOCK_ROOT20_SETP A78h
OINT14
CLOCK_ROOT20_SETP A7Ch
OINT15
CLOCK_ROOT21_SETP AC0h
OINT0
CLOCK_ROOT21_SETP AC4h
OINT1
CLOCK_ROOT21_SETP AC8h
OINT2
CLOCK_ROOT21_SETP ACCh
OINT3
CLOCK_ROOT21_SETP AD0h
OINT4
CLOCK_ROOT21_SETP AD4h
OINT5
CLOCK_ROOT21_SETP AD8h
OINT6
CLOCK_ROOT21_SETP ADCh
OINT7
CLOCK_ROOT21_SETP AE0h
OINT8
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Chapter 15 Clock Controller Module (CCM)
Register Offset
CLOCK_ROOT21_SETP AE4h
OINT9
CLOCK_ROOT21_SETP AE8h
OINT10
CLOCK_ROOT21_SETP AECh
OINT11
CLOCK_ROOT21_SETP AF0h
OINT12
CLOCK_ROOT21_SETP AF4h
OINT13
CLOCK_ROOT21_SETP AF8h
OINT14
CLOCK_ROOT21_SETP AFCh
OINT15
CLOCK_ROOT77_SETP 26C0h
OINT0
CLOCK_ROOT77_SETP 26C4h
OINT1
CLOCK_ROOT77_SETP 26C8h
OINT2
CLOCK_ROOT77_SETP 26CCh
OINT3
CLOCK_ROOT77_SETP 26D0h
OINT4
CLOCK_ROOT77_SETP 26D4h
OINT5
CLOCK_ROOT77_SETP 26D8h
OINT6
CLOCK_ROOT77_SETP 26DCh
OINT7
CLOCK_ROOT77_SETP 26E0h
OINT8
CLOCK_ROOT77_SETP 26E4h
OINT9
CLOCK_ROOT77_SETP 26E8h
OINT10
CLOCK_ROOT77_SETP 26ECh
OINT11
CLOCK_ROOT77_SETP 26F0h
OINT12
CLOCK_ROOT77_SETP 26F4h
OINT13
CLOCK_ROOT77_SETP 26F8h
OINT14
CLOCK_ROOT77_SETP 26FCh
OINT15
CLOCK_ROOT78_SETP 2740h
OINT0
Table continues on the next page...
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Memory Map and register definition
Register Offset
CLOCK_ROOT78_SETP 2744h
OINT1
CLOCK_ROOT78_SETP 2748h
OINT2
CLOCK_ROOT78_SETP 274Ch
OINT3
CLOCK_ROOT78_SETP 2750h
OINT4
CLOCK_ROOT78_SETP 2754h
OINT5
CLOCK_ROOT78_SETP 2758h
OINT6
CLOCK_ROOT78_SETP 275Ch
OINT7
CLOCK_ROOT78_SETP 2760h
OINT8
CLOCK_ROOT78_SETP 2764h
OINT9
CLOCK_ROOT78_SETP 2768h
OINT10
CLOCK_ROOT78_SETP 276Ch
OINT11
CLOCK_ROOT78_SETP 2770h
OINT12
CLOCK_ROOT78_SETP 2774h
OINT13
CLOCK_ROOT78_SETP 2778h
OINT14
CLOCK_ROOT78_SETP 277Ch
OINT15
15.9.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GRADE Reserved OFF Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved MUX DIV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 15 Clock Controller Module (CCM)
15.9.1.7.3 Fields
Field Description
31-28 Grade
GRADE Indicate speed grade for each Setpoint setting.
This value MUST be set to make Setpoint work properly. Values will be used CCM internally to determine
clock frequency relation ship between Setpoint settings and generate proper sequence. Smaller value
means higher clock speed.
27-25 Reserved
—
24 OFF
OFF OFF value in Setpoint
0 - ON
1 - OFF
23-11 Reserved
—
10-8 Clock multiplexer
MUX MUX value in Setpoint.
7-0 Clock divider
DIV DIV value in Setpoint.
15.9.1.8 Clock group control (CLOCK_GROUP0_CONTROL -
CLOCK_GROUP1_CONTROL)
This register controls synchronous clock group clocks generation.
15.9.1.8.1 Offset
For a = 0 to 1:
Register Offset Description
CLOCK_GROUPa_CON 4000h + (a × 80h) Clock group control
TROL
CLOCK_GROUPa_CON 4004h + (a × 80h) Writing a 1 to a bit in this register sets the
TROL_SET corresponding bit in CLOCK_GROUPa_CONTROL
CLOCK_GROUPa_CON 4008h + (a × 80h) Writing a 1 to a bit in this register clears the
TROL_CLR corresponding bit in CLOCK_GROUPa_CONTROL
CLOCK_GROUPa_CON 400Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
TROL_TOG corresponding bit in CLOCK_GROUPa_CONTROL
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15.9.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved OFF RSTDIV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DIV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.8.3 Fields
Field Description
31-25 Reserved
—
24 OFF
OFF Shutdown all clocks in clock group
0 - Clock is running
1 - Turn off clock
23-16 Clock group global restart count
RSTDIV Clock group will restart when this divider overflows. This field must be common multiple of all dividers.
15-4 Reserved
—
3-0 Clock divider0
DIV0 Divider clock root by DIV0 + 1.
15.9.1.9 Clock group working status (CLOCK_GROUP0_STATUS0 -
CLOCK_GROUP1_STATUS0)
15.9.1.9.1 Offset
Register Offset
CLOCK_GROUP0_STAT 4020h
US0
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Chapter 15 Clock Controller Module (CCM)
Register Offset
CLOCK_GROUP1_STAT 40A0h
US0
15.9.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDATE_FORWARD
UPDATE_REVERS
POWERDOWN
SLICE_BUS
CHANGING
Reserved
RSTDIV
R
OFF
Y
E
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DIV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.9.3 Fields
Field Description
31 Internal updating in clock group
CHANGING Indication for clock group logic is internal updating. This status is combination of UPDATE_FORWARD,
UPDATE_REVERSE, and SLICE_BUSY.
0 - Clock root is not updating currently
1 - Clock root logic is updating currently
30 Internal status synchronization from clock generation logic
UPDATE_REVE Indication for internal status synchronizing to clock generation logic.
RSE
0 - Synchronization not in process
1 - Synchronization in process
29 Internal status synchronization to clock generation logic
UPDATE_FOR Indication for clock status is synchronizing fro clock generation logic.
WARD
0 - Synchronization not in process
1 - Synchronization in process
28 Internal updating in generation logic
SLICE_BUSY Indication for clock generation logic is applying new setting.
Table continues on the next page...
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Memory Map and register definition
Field Description
0 - Clock generation logic is not busy
1 - Clock generation logic is applying the new setting
27 Current clock root POWERDOWN setting
POWERDOWN Current running state of POWERDOWN field for clock root.
0 - Clock root is running
1 - Clock root is Powered Down
26-25 Reserved
—
24 OFF
OFF Current running state of OFF field for clock group.
0 - Clock is running.
1 - Turn off clock.
23-16 Clock divider
RSTDIV Current running state of RSTDIV field for clock group.
15-4 Reserved
—
3-0 Clock divider
DIV0 Current running state of DIV0 field for clock group.
15.9.1.10 Clock group low power/extend status
(CLOCK_GROUP0_STATUS1 - CLOCK_GROUP1_STATUS1)
15.9.1.10.1 Offset
Register Offset
CLOCK_GROUP0_STAT 4024h
US1
CLOCK_GROUP1_STAT 40A4h
US1
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Chapter 15 Clock Controller Module (CCM)
15.9.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT_SETPOINT
TARGET_SETPOINT
DOWN_REQUEST
DOWN_DONE
UP_REQUES
UP_DONE
Reserved
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.10.3 Fields
Field Description
31-28 Reserved
—
27 Clock frequency increase complete
UP_DONE Handshake signal with GPC status indicating frequency increase is complete.
0 - Handshake signal with GPC status indicating frequency increase is not complete
1 - Handshake signal with GPC status indicating frequency increase is complete
26 Clock frequency increase request
UP_REQUEST Handshake signal with GPC status indicating frequency increase is requested.
0 - No handshake signal is not requested
1 - Handshake signal with GPC status indicating frequency increase is requested
25 Clock frequency decrease complete
DOWN_DONE Handshake signal with GPC status indicating frequency decrease is complete.
0 - Handshake signal with GPC status indicating frequency decrease is not complete
1 - Handshake signal with GPC status indicating frequency decrease is complete
24 Clock frequency decrease request
DOWN_REQUE 0 - No handshake signal is not requested
ST
1 - Handshake signal with GPC status indicating frequency decrease is requested
23-20 Current Setpoint
CURRENT_SET This is the Setpoint value the Soc is current working in
POINT
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Memory Map and register definition
Field Description
19-16 Next Setpoint to change to
TARGET_SETP This is the Setpoint value the SoC will switch to
OINT
15-0 Reserved
—
15.9.1.11 Clock group configuration (CLOCK_GROUP0_CONFIG -
CLOCK_GROUP1_CONFIG)
This register shows integration parameters.
15.9.1.11.1 Offset
Register Offset
CLOCK_GROUP0_CON 402Ch
FIG
CLOCK_GROUP1_CON 40ACh
FIG
15.9.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPOINT_PRESEN
Reserved
Reserved
R
T
W
Reset u u u u u u u u u u u u u u u u
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Chapter 15 Clock Controller Module (CCM)
15.9.1.11.3 Fields
Field Description
31-5 Reserved
—
4 Setpoint present
SETPOINT_PR This bit indicate whether this clock root implement Setpoint control scheme.
ESENT
0 - Setpoint is not implemented.
1 - Setpoint is implemented.
3-0 Reserved
—
15.9.1.12 Clock group access control (CLOCK_GROUP0_AUTHEN -
CLOCK_GROUP1_AUTHEN)
This register manages clock group access control.
15.9.1.12.1 Offset
For a = 0 to 1:
Register Offset Description
CLOCK_GROUPa_AUT 4030h + (a × 80h) Clock group access control
HEN
CLOCK_GROUPa_AUT 4034h + (a × 80h) Writing a 1 to a bit in this register sets the
HEN_SET corresponding bit in CLOCK_GROUPa_AUTHEN
CLOCK_GROUPa_AUT 4038h + (a × 80h) Writing a 1 to a bit in this register clears the
HEN_CLR corresponding bit in CLOCK_GROUPa_AUTHEN
CLOCK_GROUPa_AUT 403Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
HEN_TOG corresponding bit in CLOCK_GROUPa_AUTHEN
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15.9.1.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_MODE
DOMAIN_MODE
LOCK_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.12.3 Fields
Field Description
31-21 Reserved
—
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19-18 Reserved
—
17 Low power and access control by Setpoint
SETPOINT_MO Clock group works in Setpoint controlled Mode.
DE
16 Low power and access control by domain
DOMAIN_MOD Clock group works in Domain controlled Mode.
E
0 - Clock does not work in Domain Mode.
1 - Clock works in Domain Mode.
15-13 Reserved
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, CLOCK_GROUPx_AUTHEN[WHITE_LIST] cannot be
changed. Once this bit is set, it cannot be cleared, until next system reset.
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Chapter 15 Clock Controller Module (CCM)
Field Description
0 - Whitelist is not locked.
1 - Whitelist is locked.
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this clock root. Each field in this field represent for one domain.
Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
7-5 Reserved
—
4 Lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This clock root can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This clock group can be changed when CPU is in user mode (in CMx core).
0 - Clock cannot be changed in user mode.
1 - Clock can be changed in user mode.
15.9.1.13 Setpoint setting (CLOCK_GROUP0_SETPOINT0 -
CLOCK_GROUP1_SETPOINT15)
Register that provide clock root generation setting for Setpoint.
Corresponding setting will be automatically loaded when system low power mode shift.
15.9.1.13.1 Offset
For a = 0 to 1; c = 0 to 15:
Register Offset
CLOCK_GROUPa_SETP 4040h + (a × 80h) + (c × 4h)
OINTc
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15.9.1.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GRADE Reserved OFF RSTDIV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DIV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.13.3 Fields
Field Description
31-28 Grade
GRADE Indicate speed grade for each Setpoint setting.
This value MUST be set to make Setpoint work properly. Values will be used CCM internally to determine
clock frequency relation ship between Setpoint settings and generate proper sequence. Smaller value
means higher clock speed.
27-25 Reserved
—
24 OFF
OFF Shutdown all locks in clock group.
0 - Clock is running.
1 - Turn off clock.
23-16 Clock group global restart count
RSTDIV Clock group will restart when this divider overflows. This field must be common multiple of all dividers.
15-4 Reserved
—
3-0 Clock divider
DIV0 Divider selected clock by DIV + 1.
0000 - Direct output.
0001 - Divide by 2.
0010 - Divide by 3.
0011 - Divide by 4.
1111 - Divide by 16.
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Chapter 15 Clock Controller Module (CCM)
15.9.1.14 General Purpose Register (GPR_SHARED0 -
GPR_SHARED7)
These registers do not have any dedicated functions. They can be set by the user
15.9.1.14.1 Offset
For a = 0 to 7:
Register Offset Description
GPR_SHAREDa 4800h + (a × 20h) General Purpose Register
GPR_SHAREDa_SET 4804h + (a × 20h) Writing a 1 to a bit in this register sets the
corresponding bit in GPR_SHAREDa
GPR_SHAREDa_CLR 4808h + (a × 20h) Writing a 1 to a bit in this register clears the
corresponding bit in GPR_SHAREDa
GPR_SHAREDa_TOG 480Ch + (a × 20h) Writing a 1 to a bit in this register toggles the
corresponding bit in GPR_SHAREDa
15.9.1.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.14.3 Fields
Field Description
31-0 GP register
GPR This register is shared for all CPU domains.
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15.9.1.15 GPR access control (GPR_SHARED0_AUTHEN -
GPR_SHARED7_AUTHEN)
This register manages GPR access control.
15.9.1.15.1 Offset
For a = 0 to 7:
Register Offset Description
GPR_SHAREDa_AUTHE 4810h + (a × 20h) GPR access control
N
GPR_SHAREDa_AUTHE 4814h + (a × 20h) Writing a 1 to a bit in this register sets the
N_SET corresponding bit in GPR_SHAREDa_AUTHEN
GPR_SHAREDa_AUTHE 4818h + (a × 20h) Writing a 1 to a bit in this register clears the
N_CLR corresponding bit in GPR_SHAREDa_AUTHEN
GPR_SHAREDa_AUTHE 481Ch + (a × 20h) Writing a 1 to a bit in this register toggles the
N_TOG corresponding bit in GPR_SHAREDa_AUTHEN
15.9.1.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN_MODE
LOCK_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.15.3 Fields
Field Description
31-21 Reserved
—
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Chapter 15 Clock Controller Module (CCM)
Field Description
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19-17 Reserved
—
16 Low power and access control by domain
DOMAIN_MOD Register works in Domain controlled Mode.
E
0 - Clock does NOT work in Domain Mode.
1 - Clock works in Domain Mode.
15-13 Reserved
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, GPR_SHAREDx_AUTHEN[WHITE_LIST] cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - Whitelist is not locked.
1 - Whitelist is locked.
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this register. Each field in this field represent for one domain.
Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
0000 - This domain is NOT allowed to change clock.
0001 - This domain is allowed to change clock.
7-5 Reserved
—
4 Lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This register can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This register can be changed when CPU is in user mode (in CMx core).
0 - Clock cannot be changed in user mode.
1 - Clock can be changed in user mode.
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15.9.1.16 General Purpose Register (GPR_PRIVATE1 -
GPR_PRIVATE7)
These registers is general purpose register.
15.9.1.16.1 Offset
For a = 1 to 7:
Register Offset Description
GPR_PRIVATEa 4C00h + (a × 20h) General Purpose Register
GPR_PRIVATEa_SET 4C04h + (a × 20h) Writing a 1 to a bit in this register sets the
corresponding bit in GPR_PRIVATEa
GPR_PRIVATEa_CLR 4C08h + (a × 20h) Writing a 1 to a bit in this register clears the
corresponding bit in GPR_PRIVATEa
GPR_PRIVATEa_TOG 4C0Ch + (a × 20h) Writing a 1 to a bit in this register toggles the
corresponding bit in GPR_PRIVATEa
15.9.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.16.3 Fields
Field Description
31-0 GP register
GPR General purpose register. This register has dedicate bits for each domain.
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Chapter 15 Clock Controller Module (CCM)
15.9.1.17 GPR access control (GPR_PRIVATE1_AUTHEN -
GPR_PRIVATE7_AUTHEN)
This register that manages clock root access control.
15.9.1.17.1 Offset
For a = 1 to 7:
Register Offset Description
GPR_PRIVATEa_AUTH 4C10h + (a × 20h) GPR access control
EN
GPR_PRIVATEa_AUTH 4C14h + (a × 20h) Writing a 1 to a bit in this register sets the
EN_SET corresponding bit in GPR_PRIVATEa_AUTHEN
GPR_PRIVATEa_AUTH 4C18h + (a × 20h) Writing a 1 to a bit in this register clears the
EN_CLR corresponding bit in GPR_PRIVATEa_AUTHEN
GPR_PRIVATEa_AUTH 4C1Ch + (a × 20h) Writing a 1 to a bit in this register toggles the
EN_TOG corresponding bit in GPR_PRIVATEa_AUTHEN
15.9.1.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN_MODE
LOCK_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.17.3 Fields
Field Description
31-21 Reserved
—
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Field Description
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19-17 Reserved
—
16 Low power and access control by Domain
DOMAIN_MOD Register works in Domain controlled Mode.
E
0 - Clock does NOT work in Domain Mode.
1 - Clock works in Domain Mode.
15-13 Reserved
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, GPR_PRIVATEx_AUTHEN[WHITE_LIST] cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - Whitelist is not locked.
1 - Whitelist is locked.
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this register. Each field in this field represent for one domain.
Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
0000 - This domain is NOT allowed to change clock.
0001 - This domain is allowed to change clock.
7-5 Reserved
—
4 Lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This register can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This register can be changed when CPU is in user mode (in CMx core).
0 - Clock cannot be changed in user mode.
1 - Clock can be changed in user mode.
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Chapter 15 Clock Controller Module (CCM)
15.9.1.18 Clock source direct control (OSCPLL0_DIRECT -
OSCPLL28_DIRECT)
This register controls clock source on and off when clock source works in Unassigned
Mode and Domain Mode.
15.9.1.18.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_DIRECT 5000h + (a × 20h)
15.9.1.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
15.9.1.18.3 Fields
Field Description
31-1 Reserved
—
0 turn on clock source
ON This bit controls clock source.
0 - OSCPLL is OFF
1 - OSCPLL is ON
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15.9.1.19 Clock source domain control (OSCPLL0_DOMAIN -
OSCPLL28_DOMAIN)
This register controls clock source on and off when Clock source works in CPU Low
Power Mode.
During CPULPM mode, write to bit field OSCPLLn_DOMAIN[LEVEL], and during
Unassigned mode, write to OSCPLLn_DOMAIN[LEVELx], where x = 0,1,2 or 3. See
the table below for more details.
Table 15-7. CCM Mode and access types
CCM Mode/ Unassigned Mode CPU Low Power Mode Other Modes
Access Read Write Read Write Read Write
LEVEL Y N Y Y Y N
LEVEL0 Y Y Y N Y N
LEVEL1 Y Y Y N Y N
LEVEL2 Y Y Y N Y N
LEVEL3 Y Y Y N Y N
15.9.1.19.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_DOMAIN 5004h + (a × 20h)
15.9.1.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
Reserved
Reserved
Reserved
LEVEL
LEVEL
LEVEL
LEVEL
W
3
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved LEVEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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15.9.1.19.3 Fields
Field Description
31 Reserved
—
30-28 Depend level
LEVEL3 Depend level of this clock source for DOMAIN3.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
27 Reserved
—
26-24 Depend level
LEVEL2 Depend level of this clock source for DOMAIN2.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
23 Reserved
—
22-20 Depend level
LEVEL1 Depend level of this clock source for DOMAIN1.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
19 Reserved
—
18-16 Dependence level
LEVEL0 Dependence level of this clock source for DOMAIN0
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
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Field Description
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
15-3 Reserved
—
2-0 Current dependence level
LEVEL Dependence level of this clock source for the current accessing domain
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
15.9.1.20 Clock source Setpoint setting (OSCPLL0_SETPOINT -
OSCPLL28_SETPOINT)
This register defines 16 Setpoint values when clock source works in Setpoint Mode.
15.9.1.20.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_SETPOINT 5008h + (a × 20h)
15.9.1.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STANDBY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SETPOINT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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15.9.1.20.3 Fields
Field Description
31-16 Standby
STANDBY This field defines 16 Setpoint standby values. Bit0~Bit15 hold value for Setpoint 0~16 standby
respectively.
A bitfield value of 0 implies the OSC or PLL will be shutdown during standby.
A bitfield value of 1 represent OSC or PLL will keep Setpoint setting during standby.
15-0 Setpoint
SETPOINT This field defines 16 Setpoint values. Bit0~Bit15 hold value for Setpoint 0~16 respectively.
A bitfield value of 0 implies OSC or PLL will be shutdown in this Setpoint.
A bitfield value of 1 implies OSC or PLL will be turn on in this Setpoint.
15.9.1.21 Clock source working status (OSCPLL0_STATUS0 -
OSCPLL28_STATUS0)
This register shows current clock source running status.
15.9.1.21.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_STATUS0 5010h + (a × 20h)
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15.9.1.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IN_US
R
0
0
E
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN_ENABLE
ACTIVE_DOMAIN
STATUS_LATE
STATUS_EARL
ON
R
0
Y
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.21.3 Fields
Field Description
31-29 Reserved
—
28 In use
IN_USE This status bit indicates whether the clock source is being used by active clock roots
0 - Clock source is not being used by clock roots
1 - Clock source is being used by clock roots
27-16 Reserved
—
15-12 Enable status from each domain
DOMAIN_ENAB Enable status from domains, each bit represent one domain.
LE
0000 - No domain request
0001 - Request from Domain0
0010 - Request from Domain1
0011 - Request from Domain0 and Domain1
0100 - Request from Domain2
0101 - Request from Domain0 and Domain2
0110 - Request from Domain1 and Domain2
0111 - Request from Domain0, Domain1 and Domain 2
1000 - Request from Domain3
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Field Description
1001 - Request from Domain0 and Domain3
1010 - Request from Domain1 and Domain3
1011 - Request from Domain2 and Domain3
1100 - Request from Domain0, Domain 1, and Domain3
1101 - Request from Domain0, Domain 2, and Domain3
1110 - Request from Domain1, Domain 2, and Domain3
1111 - Request from all domains
11-8 Domains that own this clock source
ACTIVE_DOMAI Domains that own this clock source according to Whitelist.
N
0000 - Clock not owned by any domain
0001 - Clock owned by Domain0
0010 - Clock owned by Domain1
0011 - Clock owned by Domain0 and Domain1
0100 - Clock owned by Domain2
0101 - Clock owned by Domain0 and Domain2
0110 - Clock owned by Domain1 and Domain2
0111 - Clock owned by Domain0, Domain1 and Domain 2
1000 - Clock owned by Domain3
1001 - Clock owned by Domain0 and Domain3
1010 - Clock owned by Domain1 and Domain3
1011 - Clock owned by Domain2 and Domain3
1100 - Clock owned by Domain0, Domain 1, and Domain3
1101 - Clock owned by Domain0, Domain 2, and Domain3
1110 - Clock owned by Domain1, Domain 2, and Domain3
1111 - Clock owned by all domains
7-6 Reserved
—
5 Clock source ready
STATUS_LATE This status bit indicating clock source is ready to use.
0 - Clock source is not ready to use
1 - Clock source is ready to use
4 Clock source active
STATUS_EARL This status bit indicating clock source is active.
Y
0 - Clock source is not active
1 - Clock source is active
3-1 Reserved
—
0 Clock source current state
ON Clock source running status
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Memory Map and register definition
Field Description
0 - Clock source is OFF
1 - Clock source is ON
15.9.1.22 Clock source low power status (OSCPLL0_STATUS1 -
OSCPLL28_STATUS1)
This register shows low power status of clock source.
NOTE
The CPU0-3 references are to the CPU domain assignment, not
the number of supported CPU platforms. Each CPU platform
can be assigned to any domain, including the same domain.
15.9.1.22.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_STATUS1 5014h + (a × 20h)
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Chapter 15 Clock Controller Module (CCM)
15.9.1.22.2 Diagram
Bits 31
STANDBY_OUT_REQUEST 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_ON_REQUEST
SETPOINT_OFF_REQUES
STANDBY_IN_REQUEST
SETPOINT_OFF_DONE
STANDBY_OUT_DONE
CURRENT_SETPOINT
SETPOINT_ON_DONE
TARGET_SETPOINT
STANDBY_IN_DONE
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU3_MODE_REQUEST
CPU2_MODE_REQUEST
CPU1_MODE_REQUEST
CPU0_MODE_REQUEST
CPU3_MODE_DONE
CPU2_MODE_DONE
CPU1_MODE_DONE
CPU0_MODE_DONE
CPU3_MODE
CPU2_MODE
CPU1_MODE
CPU0_MODE
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.22.3 Fields
Field Description
31 Clock gate turn on request from GPC standby
STANDBY_OUT Status bit indication clock gate is requested to turned on from GPC.
_REQUEST
0 - No request
1 - Clock gate requested to be turned on
30 Clock gate turn on finish from GPC standby
STANDBY_OUT Status bit indication clock gate is requested to turned on from GPC.
_DONE
0 - Request to turn on Clock gate is not complete
1 - Request to turn on Clock gate is complete
29 Clock source turn off finish from GPC standby
STANDBY_IN_ Status bit indication clock source is turned off according to GPC request.
DONE
0 - Clock source is not turned off
1 - Clock source is turned off
Table continues on the next page...
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Memory Map and register definition
Field Description
28 Clock gate turn off request from GPC standby
STANDBY_IN_ Status bit indication clock gate is requested to turned off from GPC.
REQUEST
0 - No request
1 - Clock gate requested to be turned off
27 Clock gate turn on finish from GPC Setpoint
SETPOINT_ON Status bit indication clock gate is requested to turned on from GPC.
_DONE
0 - No request
1 - Request to turn on clock gate
26 Clock gate turn on request from GPC Setpoint
SETPOINT_ON Status bit indication clock gate is requested to turned on from GPC.
_REQUEST
0 - No request
1 - Clock gate requested to be turned on
25 Clock source turn off finish from GPC Setpoint
SETPOINT_OF Status bit indication clock source is turned off according to GPC request.
F_DONE
0 - Clock source is not turned off
1 - Clock source is turned off
24 Clock gate turn off request from GPC Setpoint
SETPOINT_OF Status bit indication clock gate is requested to turned off from GPC.
F_REQUEST
0 - No request
1 - Clock gate requested to be turned off
23-20 Current Setpoint
CURRENT_SET This is the Setpoint value the Soc is current working in
POINT
19-16 Next Setpoint to change to
TARGET_SETP This is the Setpoint value the SoC will switch to
OINT
15 Domain3 Low Power Mode task done
CPU3_MODE_ Domain3 response signal status to GPC to indicate clock was gated-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
14 Domain3 request enter Low Power Mode
CPU3_MODE_ Domain3 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
13-12 Domain3 Low Power Mode
CPU3_MODE Domain3 will enter in Low Power Mode.
00 - Run
01 - Wait
10 - Stop
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Chapter 15 Clock Controller Module (CCM)
Field Description
11 - Suspend
11 Domain2 Low Power Mode task done
CPU2_MODE_ Domain2 response signal status to GPC to indicate clock was gate-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
10 Domain2 request enter Low Power Mode
CPU2_MODE_ Domain2 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
9-8 Domain2 Low Power Mode
CPU2_MODE Domain2 will enter in Low Power Mode.
00 - Run
01 - Wait
10 - Stop
11 - Suspend
7 Domain1 Low Power Mode task done
CPU1_MODE_ Domain1 response signal status to GPC to indicate clock was gated-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
6 Domain1 request enter Low Power Mode
CPU1_MODE_ Domain1 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
5-4 Domain1 Low Power Mode
CPU1_MODE Domain1 will enter in Low Power Mode
00 - Run
01 - Wait
10 - Stop
11 - Suspend
3 Domain0 Low Power Mode task done
CPU0_MODE_ Domain0 response signal status to GPC to indicate clock was gate-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
2 Domain0 request enter Low Power Mode
CPU0_MODE_ Domain0 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
Table continues on the next page...
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Memory Map and register definition
Field Description
1-0 Domain0 Low Power Mode
CPU0_MODE Domain0 will enter in Low Power Mode
00 - Run
01 - Wait
10 - Stop
11 - Suspend
15.9.1.23 Clock source configuration (OSCPLL0_CONFIG -
OSCPLL28_CONFIG)
This register shows integration parameters.
15.9.1.23.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_CONFIG 5018h + (a × 20h)
15.9.1.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOMODE_PRESENT
SETPOINT_PRESEN
Reserved
Reserved
Reserved
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 u 0 0 u 0
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Chapter 15 Clock Controller Module (CCM)
15.9.1.23.3 Fields
Field Description
31-5 Reserved
—
4 Setpoint present
SETPOINT_PR This bit indicate whether this clock source implement Setpoint control scheme.
ESENT
0 - Setpoint is not implemented.
1 - Setpoint is implemented.
3-2 Reserved
—
1 Automode Present
AUTOMODE_P 0 - Not present
RESENT
1 - Present
0 Reserved
—
15.9.1.24 Clock source access control (OSCPLL0_AUTHEN -
OSCPLL28_AUTHEN)
This register that manages clock source access control.
NOTE
SETPOINT_MODE, DOMAIN_MODE, and CPULPM cannot
be set to '1' at the same time.
15.9.1.24.1 Offset
For a = 0 to 28:
Register Offset
OSCPLLa_AUTHEN 501Ch + (a × 20h)
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15.9.1.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_MODE
DOMAIN_MODE
LOCK_MODE
CPULPM
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.24.3 Fields
Field Description
31-21 Reserved
—
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19 Reserved
—
18 CPU Low Power Mode
CPULPM PLL works in CPU Low Power Mode
0 - PLL does not function in Low power Mode
1 - PLL functions in Low Power Mode
17 LPCG works in Setpoint controlled Mode.
SETPOINT_MO Clock source works in Setpoint controlled Mode.
DE
16 Low power and access control by domain
DOMAIN_MOD Clock source works in Domain controlled Mode.
E
0 - Clock does not work in Domain Mode.
1 - Clock works in Domain Mode.
15-13 Reserved
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Chapter 15 Clock Controller Module (CCM)
Field Description
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, OSCPLLx_AUTHEN[WHITE_LIST] cannot be changed. Once
this bit is set, it cannot be cleared, until next system reset.
0 - Whitelist is not locked.
1 - Whitelist is locked.
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this clock source. Each field in this field represent for one
domain. Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
7-5 Reserved
—
4 lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This clock source can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This clock source can be changed when CPU is in user mode (in CMx core).
0 - Clock cannot be changed in user mode.
1 - Clock can be changed in user mode.
15.9.1.25 LPCG direct control (LPCG0_DIRECT - LPCG137_DIRECT)
This register controls LPCG on and off when LPCG works in Unassigned Mode and
Domain Mode.
15.9.1.25.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_DIRECT 6000h + (a × 20h)
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15.9.1.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved ON
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
15.9.1.25.3 Fields
Field Description
31-1 Reserved
—
0 LPCG on
ON This bit controls LPCG.
0 - LPCG is OFF.
1 - LPCG is ON.
15.9.1.26 LPCG domain control (LPCG0_DOMAIN -
LPCG137_DOMAIN)
This register controls LPCG on and off when LPCG works in CPU Low Power Mode.
During CPULPM mode, write to bit field LPCGn_DOMAIN[LEVEL], and during
Unassigned mode, write to LPCGn_DOMAIN[LEVELx], where x = 0,1,2 or 3. See the
table below for more details.
Table 15-8. CCM Mode and access types
CCM Mode/ Unassigned Mode CPU Low Power Mode Other Modes
Access Read Write Read Write Read Write
LEVEL Y N Y Y Y N
LEVEL0 Y Y Y N Y N
LEVEL1 Y Y Y N Y N
LEVEL2 Y Y Y N Y N
LEVEL3 Y Y Y N Y N
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Chapter 15 Clock Controller Module (CCM)
15.9.1.26.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_DOMAIN 6004h + (a × 20h)
15.9.1.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
Reserved
Reserved
Reserved
LEVEL
LEVEL
LEVEL
LEVEL
W
3
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved LEVEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
15.9.1.26.3 Fields
Field Description
31 Reserved
—
30-28 Depend level
LEVEL3 Depend level of this LPCG for DOMAIN3.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
27 Reserved
—
26-24 Depend level
LEVEL2 Depend level of this LPCG for DOMAIN2.
Table continues on the next page...
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Memory Map and register definition
Field Description
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
23 Reserved
—
22-20 Depend level
LEVEL1 Depend level of this LPCG for DOMAIN1.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
19 Reserved
—
18-16 Depend level
LEVEL0 Depend level of this LPCG for DOMAIN0.
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
15-3 Reserved
—
2-0 Current dependence level
LEVEL Dependence level of this clock source for the current accessing domain
000 - This clock source is not needed in any mode, and can be turned off
001 - This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
010 - This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
011 - This clock source is needed in RUN, WAIT and STOP mode
100 - This clock source is always on in any mode (including SUSPEND)
101, 110, 111 - Reserved
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Chapter 15 Clock Controller Module (CCM)
15.9.1.27 LPCG working status (LPCG0_STATUS0 -
LPCG137_STATUS0)
This register shows current LPCG running status.
15.9.1.27.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_STATUS0 6010h + (a × 20h)
15.9.1.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN_ENABLE
ACTIVE_DOMAIN
ON
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.27.3 Fields
Field Description
31-16 Reserved
—
15-12 Enable status from each domain
DOMAIN_ENAB Enable status from domains, each bit represent one domain.
LE
0000 - No domain request
0001 - Request from Domain0
0010 - Request from Domain1
0011 - Request from Domain0 and Domain1
Table continues on the next page...
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Memory Map and register definition
Field Description
0100 - Request from Domain2
0101 - Request from Domain0 and Domain2
0110 - Request from Domain1 and Domain2
0111 - Request from Domain0, Domain1 and Domain 2
1000 - Request from Domain3
1001 - Request from Domain0 and Domain3
1010 - Request from Domain1 and Domain3
1011 - Request from Domain2 and Domain3
1100 - Request from Domain0, Domain 1, and Domain3
1101 - Request from Domain0, Domain 2, and Domain3
1110 - Request from Domain1, Domain 2, and Domain3
1111 - Request from all domains
11-8 Domains that own this clock gate
ACTIVE_DOMAI Domains that own this clock gate according to Whitelist.
N
0000 - Clock not owned by any domain
0001 - Clock owned by Domain0
0010 - Clock owned by Domain1
0011 - Clock owned by Domain0 and Domain1
0100 - Clock owned by Domain2
0101 - Clock owned by Domain0 and Domain2
0110 - Clock owned by Domain1 and Domain2
0111 - Clock owned by Domain0, Domain1 and Domain 2
1000 - Clock owned by Domain3
1001 - Clock owned by Domain0 and Domain3
1010 - Clock owned by Domain1 and Domain3
1011 - Clock owned by Domain2 and Domain3
1100 - Clock owned by Domain0, Domain 1, and Domain3
1101 - Clock owned by Domain0, Domain 2, and Domain3
1110 - Clock owned by Domain1, Domain 2, and Domain3
1111 - Clock owned by all domains
7-1 Reserved
—
0 LPCG current state
ON LPCG running status.
0 - LPCG is OFF.
1 - LPCG is ON.
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Chapter 15 Clock Controller Module (CCM)
15.9.1.28 LPCG low power status (LPCG0_STATUS1 -
LPCG137_STATUS1)
This register shows low power status of LPCG.
NOTE
The CPU0-3 references are to the CPU domain assignment, not
the number of supported CPU platforms. Each CPU platform
can be assigned to any domain, including the same domain.
15.9.1.28.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_STATUS1 6014h + (a × 20h)
15.9.1.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_ON_REQUEST
SETPOINT_OFF_REQUES
SETPOINT_OFF_DONE
CURRENT_SETPOINT
SETPOINT_ON_DONE
TARGET_SETPOINT
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU3_MODE_REQUEST
CPU2_MODE_REQUEST
CPU1_MODE_REQUEST
CPU0_MODE_REQUEST
CPU3_MODE_DONE
CPU2_MODE_DONE
CPU1_MODE_DONE
CPU0_MODE_DONE
CPU3_MODE
CPU2_MODE
CPU1_MODE
CPU0_MODE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory Map and register definition
15.9.1.28.3 Fields
Field Description
31-28 Reserved
—
27 Clock gate turn on finish from GPC Setpoint
SETPOINT_ON Status bit indication clock gate is turned on according to GPC request.
_DONE
0 - Clock gate is not turned on
1 - Clock gate is turned on
26 Clock gate turn on request from GPC Setpoint
SETPOINT_ON Status bit indication clock gate is requested to turned on from GPC.
_REQUEST
0 - No request
1 - Clock gate requested to be turned on
25 Clock gate turn off finish from GPC Setpoint
SETPOINT_OF Status bit indication clock gate is turned off according to GPC request.
F_DONE
0 - Clock gate is not turned off
1 - Clock gate is turned off
24 Clock gate turn off request from GPC Setpoint
SETPOINT_OF Status bit indication clock gate is requested to turned off from GPC.
F_REQUEST
0 - No request
1 - Clock gate requested to be turned off
23-20 Current Setpoint
CURRENT_SET This is the Setpoint value the Soc is current working in
POINT
19-16 Next Setpoint to change to
TARGET_SETP This is the Setpoint value the SoC will switch to
OINT
15 Domain3 Low Power Mode task done
CPU3_MODE_ Domain3 response signal status to GPC to indicate clock was gate-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
14 Domain3 request enter Low Power Mode
CPU3_MODE_ Domain3 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
13-12 Domain3 Low Power Mode
CPU3_MODE Domain3 will enter in Low Power Mode.
00 - Run
01 - Wait
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Chapter 15 Clock Controller Module (CCM)
Field Description
10 - Stop
11 - Suspend
11 Domain2 Low Power Mode task done
CPU2_MODE_ Domain2 response signal status to GPC to indicate clock was gate-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
10 Domain2 request enter Low Power Mode
CPU2_MODE_ Domain2 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
9-8 Domain2 Low Power Mode
CPU2_MODE Domain2 will enter in Low Power Mode
00 - Run
01 - Wait
10 - Stop
11 - Suspend
7 Domain1 Low Power Mode task done
CPU1_MODE_ Domain1 response signal status to GPC to indicate clock was gate-off if needed to enter Low Power
DONE Mode
0 - Clock is not gated
1 - Clock is gated-off
6 Domain1 request enter Low Power Mode
CPU1_MODE_ Domain1 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
5-4 Domain1 Low Power Mode
CPU1_MODE Domain1 will enter in Low Power Mode
00 - Run
01 - Wait
10 - Stop
11 - Suspend
3 Domain0 Low Power Mode task done
CPU0_MODE_ Domain0 response signal status to GPC to indicate clock was gate-off to enter Low Power Mode
DONE
0 - Clock is not gated
1 - Clock is gated-off
2 Domain0 request enter Low Power Mode
CPU0_MODE_ Domain0 request signal status to enter Low Power Mode
REQUEST
0 - No request
1 - Request from domain to enter Low Power Mode
Table continues on the next page...
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Memory Map and register definition
Field Description
1-0 Domain0 Low Power Mode
CPU0_MODE Domain0 will enter in Low Power Mode
00 - Run
01 - Wait
10 - Stop
11 - Suspend
15.9.1.29 LPCG configuration (LPCG0_CONFIG - LPCG137_CONFIG)
This register shows integration parameters.
15.9.1.29.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_CONFIG 6018h + (a × 20h)
15.9.1.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPOINT_PRESEN
Reserved
Reserved
R
T
W
Reset u u u u u u u u u u u u u u u u
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Chapter 15 Clock Controller Module (CCM)
15.9.1.29.3 Fields
Field Description
31-5 Reserved
—
4 Setpoint present
SETPOINT_PR This bit indicate whether this clock root implement Setpoint control scheme.
ESENT
0 - Setpoint is not implemented.
1 - Setpoint is implemented.
3-0 Reserved
—
15.9.1.30 LPCG access control (LPCG0_AUTHEN -
LPCG137_AUTHEN)
This register that manages LPCG access control.
NOTE
SETPOINT_MODE, DOMAIN_MODE, and CPULPM cannot
be set to '1' at the same time.
15.9.1.30.1 Offset
For a = 0 to 137:
Register Offset
LPCGa_AUTHEN 601Ch + (a × 20h)
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15.9.1.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPOINT_MODE
0
DOMAIN_MODE
LOCK_MODE
CPULPM
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.30.3 Fields
Field Description
31-21 Reserved
—
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, bits 16-20 cannot be changed.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19 Reserved
—
18 CPU Low Power Mode
CPULPM LPCG works in CPU Low Power Mode
0 - LPCG is not functioning in Low power Mode
1 - LPCG is functioning in Low Power Mode
17 Low power and access control by Setpoint
SETPOINT_MO 0 - LPCG is not functioning in Setpoint controlled Mode
DE
1 - LPCG is functioning in Setpoint controlled Mode
16 Low power and access control by domain
DOMAIN_MOD LPCG works in Domain controlled Mode.
E
0 - Clock does not work in Domain Mode
1 - Clock works in Domain Mode
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Chapter 15 Clock Controller Module (CCM)
Field Description
15-13 Reserved
—
12 Lock Whitelist
LOCK_LIST This bit lock Whitelist. When this bit is set, LPCGx_AUTHEN[WHITE_LIST] cannot be changed. Once
this bit is set, it cannot be cleared, until next system reset.
0 - Whitelist is not locked.
1 - Whitelist is locked.
11-8 Whitelist
WHITE_LIST Domains that on the Whitelist can change this clock root. Each field in this field represent for one domain.
Bit8~Bit11 represent for DOMAIN0~DOMAIN3 respectively.
7-5 Reserved
—
4 lock truszone setting
LOCK_TZ This bit lock Trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This LPCG can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This LPCG can be changed when CPU is in user mode (in CMx core).
0 - LPCG cannot be changed in user mode.
1 - LPCG can be changed in user mode.
15.9.1.31 LPCG Setpoint setting (LPCG2_SETPOINT -
LPCG48_SETPOINT)
This register defines 16 Setpoint values when LPCG works in Setpoint Mode.
15.9.1.31.1 Offset
Register Offset
LPCG2_SETPOINT 6048h
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Memory Map and register definition
Register Offset
LPCG3_SETPOINT 6068h
LPCG4_SETPOINT 6088h
LPCG5_SETPOINT 60A8h
LPCG6_SETPOINT 60C8h
LPCG7_SETPOINT 60E8h
LPCG8_SETPOINT 6108h
LPCG9_SETPOINT 6128h
LPCG10_SETPOINT 6148h
LPCG11_SETPOINT 6168h
LPCG12_SETPOINT 6188h
LPCG14_SETPOINT 61C8h
LPCG15_SETPOINT 61E8h
LPCG16_SETPOINT 6208h
LPCG17_SETPOINT 6228h
LPCG18_SETPOINT 6248h
LPCG19_SETPOINT 6268h
LPCG24_SETPOINT 6308h
LPCG25_SETPOINT 6328h
LPCG26_SETPOINT 6348h
LPCG27_SETPOINT 6368h
LPCG28_SETPOINT 6388h
LPCG29_SETPOINT 63A8h
LPCG30_SETPOINT 63C8h
LPCG31_SETPOINT 63E8h
LPCG32_SETPOINT 6408h
LPCG33_SETPOINT 6428h
LPCG34_SETPOINT 6448h
LPCG35_SETPOINT 6468h
LPCG36_SETPOINT 6488h
LPCG37_SETPOINT 64A8h
LPCG38_SETPOINT 64C8h
LPCG39_SETPOINT 64E8h
LPCG40_SETPOINT 6508h
LPCG43_SETPOINT 6568h
LPCG44_SETPOINT 6588h
LPCG45_SETPOINT 65A8h
LPCG46_SETPOINT 65C8h
LPCG47_SETPOINT 65E8h
LPCG48_SETPOINT 6608h
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Chapter 15 Clock Controller Module (CCM)
15.9.1.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STANDBY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SETPOINT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.1.31.3 Fields
Field Description
31-16 Standby
STANDBY This field defines 16 Setpoint standby values. Bit0~Bit15 hold value for Setpoint 0~16 standby
respectively.
A bitfield value of 0 implies the LPCG will be shutdown during standby.
A bitfield value of 1 represent LPCG will keep Setpoint setting during standby.
15-0 Setpoints
SETPOINT This field defines 16 Setpoint values. Bit0~Bit15 hold value for Setpoint 0~16 respectively.
A value of 0 implies the clock is off in Setpoint Mode
A value of 1 implies the clock is on in Setpoint Mode
15.9.2 CCM_OBS register descriptions
15.9.2.1 D_IP_IMXRT_CCM_OBS_LN28FDSOI memory map
CCM_OBS base address: 4015_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Observe control (OBSERVE0_CONTROL) 32 RW 0000_0000
4 Observe control (OBSERVE0_CONTROL_SET) 32 RW 0000_0000
8 Observe control (OBSERVE0_CONTROL_CLR) 32 RW 0000_0000
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
C Observe control (OBSERVE0_CONTROL_TOG) 32 RW 0000_0000
20 Observe status (OBSERVE0_STATUS0) 32 RO 0000_0000
30 Observe access control (OBSERVE0_AUTHEN) 32 RW 0000_0000
34 Observe access control (OBSERVE0_AUTHEN_SET) 32 RW 0000_0000
38 Observe access control (OBSERVE0_AUTHEN_CLR) 32 RW 0000_0000
3C Observe access control (OBSERVE0_AUTHEN_TOG) 32 RW 0000_0000
40 Current frequency detected (OBSERVE0_FREQUENCY_CURRENT) 32 RO 0000_0000
44 Minimum frequency detected (OBSERVE0_FREQUENCY_MIN) 32 RO FFFF_FFC0
48 Maximum frequency detected (OBSERVE0_FREQUENCY_MAX) 32 RO 0000_0000
80 Observe control (OBSERVE1_CONTROL) 32 RW 0000_0000
84 Observe control (OBSERVE1_CONTROL_SET) 32 RW 0000_0000
88 Observe control (OBSERVE1_CONTROL_CLR) 32 RW 0000_0000
8C Observe control (OBSERVE1_CONTROL_TOG) 32 RW 0000_0000
A0 Observe status (OBSERVE1_STATUS0) 32 RO 0000_0000
B0 Observe access control (OBSERVE1_AUTHEN) 32 RW 0000_0000
B4 Observe access control (OBSERVE1_AUTHEN_SET) 32 RW 0000_0000
B8 Observe access control (OBSERVE1_AUTHEN_CLR) 32 RW 0000_0000
BC Observe access control (OBSERVE1_AUTHEN_TOG) 32 RW 0000_0000
C0 Current frequency detected (OBSERVE1_FREQUENCY_CURRENT) 32 RO 0000_0000
C4 Minimum frequency detected (OBSERVE1_FREQUENCY_MIN) 32 RO FFFF_FFC0
C8 Maximum frequency detected (OBSERVE1_FREQUENCY_MAX) 32 RO 0000_0000
100 Observe control (OBSERVE2_CONTROL) 32 RW 0000_0000
104 Observe control (OBSERVE2_CONTROL_SET) 32 RW 0000_0000
108 Observe control (OBSERVE2_CONTROL_CLR) 32 RW 0000_0000
10C Observe control (OBSERVE2_CONTROL_TOG) 32 RW 0000_0000
120 Observe status (OBSERVE2_STATUS0) 32 RO 0000_0000
130 Observe access control (OBSERVE2_AUTHEN) 32 RW 0000_0000
134 Observe access control (OBSERVE2_AUTHEN_SET) 32 RW 0000_0000
138 Observe access control (OBSERVE2_AUTHEN_CLR) 32 RW 0000_0000
13C Observe access control (OBSERVE2_AUTHEN_TOG) 32 RW 0000_0000
140 Current frequency detected (OBSERVE2_FREQUENCY_CURRENT) 32 RO 0000_0000
144 Minimum frequency detected (OBSERVE2_FREQUENCY_MIN) 32 RO FFFF_FFC0
148 Maximum frequency detected (OBSERVE2_FREQUENCY_MAX) 32 RO 0000_0000
180 Observe control (OBSERVE3_CONTROL) 32 RW 0000_0000
184 Observe control (OBSERVE3_CONTROL_SET) 32 RW 0000_0000
188 Observe control (OBSERVE3_CONTROL_CLR) 32 RW 0000_0000
18C Observe control (OBSERVE3_CONTROL_TOG) 32 RW 0000_0000
1A0 Observe status (OBSERVE3_STATUS0) 32 RO 0000_0000
1B0 Observe access control (OBSERVE3_AUTHEN) 32 RW 0000_0000
1B4 Observe access control (OBSERVE3_AUTHEN_SET) 32 RW 0000_0000
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Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1B8 Observe access control (OBSERVE3_AUTHEN_CLR) 32 RW 0000_0000
1BC Observe access control (OBSERVE3_AUTHEN_TOG) 32 RW 0000_0000
1C0 Current frequency detected (OBSERVE3_FREQUENCY_CURRENT) 32 RO 0000_0000
1C4 Minimum frequency detected (OBSERVE3_FREQUENCY_MIN) 32 RO FFFF_FFC0
1C8 Maximum frequency detected (OBSERVE3_FREQUENCY_MAX) 32 RO 0000_0000
200 Observe control (OBSERVE4_CONTROL) 32 RW 0000_0000
204 Observe control (OBSERVE4_CONTROL_SET) 32 RW 0000_0000
208 Observe control (OBSERVE4_CONTROL_CLR) 32 RW 0000_0000
20C Observe control (OBSERVE4_CONTROL_TOG) 32 RW 0000_0000
220 Observe status (OBSERVE4_STATUS0) 32 RO 0000_0000
230 Observe access control (OBSERVE4_AUTHEN) 32 RW 0000_0000
234 Observe access control (OBSERVE4_AUTHEN_SET) 32 RW 0000_0000
238 Observe access control (OBSERVE4_AUTHEN_CLR) 32 RW 0000_0000
23C Observe access control (OBSERVE4_AUTHEN_TOG) 32 RW 0000_0000
240 Current frequency detected (OBSERVE4_FREQUENCY_CURRENT) 32 RO 0000_0000
244 Minimum frequency detected (OBSERVE4_FREQUENCY_MIN) 32 RO FFFF_FFC0
248 Maximum frequency detected (OBSERVE4_FREQUENCY_MAX) 32 RO 0000_0000
280 Observe control (OBSERVE5_CONTROL) 32 RW 0000_0000
284 Observe control (OBSERVE5_CONTROL_SET) 32 RW 0000_0000
288 Observe control (OBSERVE5_CONTROL_CLR) 32 RW 0000_0000
28C Observe control (OBSERVE5_CONTROL_TOG) 32 RW 0000_0000
2A0 Observe status (OBSERVE5_STATUS0) 32 RO 0000_0000
2B0 Observe access control (OBSERVE5_AUTHEN) 32 RW 0000_0000
2B4 Observe access control (OBSERVE5_AUTHEN_SET) 32 RW 0000_0000
2B8 Observe access control (OBSERVE5_AUTHEN_CLR) 32 RW 0000_0000
2BC Observe access control (OBSERVE5_AUTHEN_TOG) 32 RW 0000_0000
2C0 Current frequency detected (OBSERVE5_FREQUENCY_CURRENT) 32 RO 0000_0000
2C4 Minimum frequency detected (OBSERVE5_FREQUENCY_MIN) 32 RO FFFF_FFC0
2C8 Maximum frequency detected (OBSERVE5_FREQUENCY_MAX) 32 RO 0000_0000
15.9.2.2 Observe control (OBSERVE0_CONTROL -
OBSERVE5_CONTROL)
Register that control observe.
15.9.2.2.1 Offset
For a = 0 to 5:
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Memory Map and register definition
Register Offset Description
OBSERVEa_CONTROL 0h + (a × 80h) Observe control
OBSERVEa_CONTROL_ 4h + (a × 80h) Writing a 1 to a bit in this register sets the
SET corresponding bit in OBSERVEa_CONTROL
OBSERVEa_CONTROL_ 8h + (a × 80h) Writing a 1 to a bit in this register clears the
CLR corresponding bit in OBSERVEa_CONTROL
OBSERVEa_CONTROL_ Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
TOG corresponding bit in OBSERVEa_CONTROL
15.9.2.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved OFF DIVIDE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
SELEC
RESE
RAW
INV
W
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.2.2.3 Fields
Field Description
31-25 Reserved
—
24 Turn off
OFF Turn off slice to save power.
0 - observe slice is on
1 - observe slice is off
23-16 Divider for observe signal
DIVIDE Divider before measurement or send out to IO. Divider by DIVIDE+1.
NOTE: If divider selected, first several toggles may not be observed. Divider is typically be used when
observe signal is a continuous clock.
15 Reset observe divider
RESET A change from 0 to 1 will reset the divider.
0 - No reset
1 - Reset observe divider
14 Reserved
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Chapter 15 Clock Controller Module (CCM)
Field Description
—
13 Invert
INV Invert input signal phase.
0 - Clock phase remain same.
1 - Invert clock phase before measurement or send to IO.
12 Observe raw signal
RAW Select from raw signal and divided signal.
0 - Select divided signal.
1 - Select raw signal.
11-9 Reserved
—
8-0 Observe signal selector
SELECT Selector that controls which observe signals will be selected and observed.
Target SELECT index Slice Number
M7_CLK_ROOT 128 4
M4_CLK_ROOT 129 0
BUS_CLK_ROOT 130 2
BUS_LPSR_CLK_ROOT 131 0
SEMC_CLK_ROOT 132 2
CSSYS_CLK_ROOT 133 2
CSTRACE_CLK_ROOT 134 2
M4_SYSTICK_CLK_ROOT 135 0
M7_SYSTICK_CLK_ROOT 136 2
ADC1_CLK_ROOT 137 2
ADC2_CLK_ROOT 138 2
ACMP_CLK_ROOT 139 2
FLEXIO1_CLK_ROOT 140 2
FLEXIO2_CLK_ROOT 141 2
GPT1_CLK_ROOT 142 2
GPT2_CLK_ROOT 143 2
GPT3_CLK_ROOT 144 2
GPT4_CLK_ROOT 145 2
GPT5_CLK_ROOT 146 2
GPT6_CLK_ROOT 147 2
FLEXSPI1_CLK_ROOT 148 2
FLEXSPI2_CLK_ROOT 149 2
CAN1_CLK_ROOT 150 2
CAN2_CLK_ROOT 151 2
CAN3_CLK_ROOT 152 0
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Memory Map and register definition
Field Description
Target SELECT index Slice Number
LPUART1_CLK_ROOT 153 2
LPUART2_CLK_ROOT 154 2
LPUART3_CLK_ROOT 155 2
LPUART4_CLK_ROOT 156 2
LPUART5_CLK_ROOT 157 2
LPUART6_CLK_ROOT 158 2
LPUART7_CLK_ROOT 159 2
LPUART8_CLK_ROOT 160 2
LPUART9_CLK_ROOT 161 2
LPUART10_CLK_ROOT 162 2
LPUART11_CLK_ROOT 163 0
LPUART12_CLK_ROOT 164 0
LPI2C1_CLK_ROOT 165 2
LPI2C2_CLK_ROOT 166 2
LPI2C3_CLK_ROOT 167 2
LPI2C4_CLK_ROOT 168 2
LPI2C5_CLK_ROOT 169 0
LPI2C6_CLK_ROOT 170 0
LPSPI1_CLK_ROOT 171 2
LPSPI2_CLK_ROOT 172 2
LPSPI3_CLK_ROOT 173 2
LPSPI4_CLK_ROOT 174 2
LPSPI5_CLK_ROOT 175 0
LPSPI6_CLK_ROOT 176 0
EMV1_CLK_ROOT 177 2
EMV2_CLK_ROOT 178 2
ENET1_CLK_ROOT 179 2
ENET2_CLK_ROOT 180 2
ENET_QOS_CLK_ROOT 181 2
ENET_25M_CLK_ROOT 182 2
ENET_TIMER1_CLK_ROOT 183 2
ENET_TIMER2_CLK_ROOT 184 2
ENET_TIMER3_CLK_ROOT 185 2
USDHC1_CLK_ROOT 186 2
USDHC2_CLK_ROOT 187 2
ASRC_CLK_ROOT 188 2
MQS_CLK_ROOT 189 2
MIC_CLK_ROOT 190 0
SPDIF_CLK_ROOT 191 2
SAI1_CLK_ROOT 192 2
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Chapter 15 Clock Controller Module (CCM)
Field Description
Target SELECT index Slice Number
SAI2_CLK_ROOT 193 2
SAI3_CLK_ROOT 194 2
SAI4_CLK_ROOT 195 0
GPU2D_CLK_ROOT 196 2
ELCDIF_CLK_ROOT 197 2
LCDIFV2_CLK_ROOT 198 2
MIPI_REF_CLK_ROOT 199 2
MIPI_ESC_CLK_ROOT 200 2
CSI2_CLK_ROOT 201 2
CSI2_ESC_CLK_ROOT 202 2
CSI2_UI_CLK_ROOT 203 2
CSI_CLK_ROOT 204 2
CCM_CKO1_CLK_ROOT 205 0
CCM_CKO2_CLK_ROOT 206 2
CM7_CORE_STCLKEN 207 4
CCM_FLEXRAM_CLK_ROOT 208 4
MIPI_DSI_TXESC 209 2
MIPI_DSI_RXESC 210 2
OSC_RC_16M 224 0
OSC_RC_48M 225 0
OSC_RC_48M_DIV2 226 0
OSC_RC_400M 227 0
OSC_24M_OUT 229 0
PLL_ARM_OUT 231 2
SYS_PLL2_OUT 233 2
SYS_PLL2_PFD0 234 2
SYS_PLL2_PFD1 235 2
SYS_PLL2_PFD2 236 2
SYS_PLL2_PFD3 237 2
SYS_PLL3_OUT 239 2
SYS_PLL3_DIV2 240 2
SYS_PLL3_PFD0 241 2
SYS_PLL3_PFD1 242 2
SYS_PLL3_PFD2 243 2
SYS_PLL3_PFD3 244 2
SYS_PLL1_OUT 246 2
SYS_PLL1_DIV2 247 2
SYS_PLL1_DIV5 248 2
PLL_AUDIO_OUT 250 2
PLL_VIDEO_OUT 252 2
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Memory Map and register definition
Field Description
15.9.2.3 Observe status (OBSERVE0_STATUS0 -
OBSERVE5_STATUS0)
15.9.2.3.1 Offset
Register Offset
OBSERVE0_STATUS0 20h
OBSERVE1_STATUS0 A0h
OBSERVE2_STATUS0 120h
OBSERVE3_STATUS0 1A0h
OBSERVE4_STATUS0 220h
OBSERVE5_STATUS0 2A0h
15.9.2.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVIDE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OFF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SELEC
RESE
RAW
Reserved
Reserved
INV
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.2.3.3 Fields
Field Description
31 Reserved
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Chapter 15 Clock Controller Module (CCM)
Field Description
—
30 Reserved
—
29 Reserved
—
28 Reserved
—
27 Reserved
—
26-25 Reserved
—
24 Turn off slice
OFF 0 - observe slice is on
1 - observe slice is off
23-16 Divide value status. The clock will be divided by DIVIDE + 1.
DIVIDE
15 Reset state
RESET 0 - Observe divider is not in reset state
1 - Observe divider is in reset state
14 Reserved
—
13 Polarity of the observe target
INV 0 - Polarity is not inverted
1 - Polarity of the observe target is inverted
12 Observe raw signal
RAW 0 - Divided signal is selected
1 - Raw signal is selected
11-9 Reserved
—
8-0 Select value
SELECT
Target SELECT index Slice Number
M7_CLK_ROOT 128 4
M4_CLK_ROOT 129 0
BUS_CLK_ROOT 130 2
BUS_LPSR_CLK_ROOT 131 0
SEMC_CLK_ROOT 132 2
CSSYS_CLK_ROOT 133 2
CSTRACE_CLK_ROOT 134 2
M4_SYSTICK_CLK_ROOT 135 0
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Memory Map and register definition
Field Description
Target SELECT index Slice Number
M7_SYSTICK_CLK_ROOT 136 2
ADC1_CLK_ROOT 137 2
ADC2_CLK_ROOT 138 2
ACMP_CLK_ROOT 139 2
FLEXIO1_CLK_ROOT 140 2
FLEXIO2_CLK_ROOT 141 2
GPT1_CLK_ROOT 142 2
GPT2_CLK_ROOT 143 2
GPT3_CLK_ROOT 144 2
GPT4_CLK_ROOT 145 2
GPT5_CLK_ROOT 146 2
GPT6_CLK_ROOT 147 2
FLEXSPI1_CLK_ROOT 148 2
FLEXSPI2_CLK_ROOT 149 2
CAN1_CLK_ROOT 150 2
CAN2_CLK_ROOT 151 2
CAN3_CLK_ROOT 152 0
LPUART1_CLK_ROOT 153 2
LPUART2_CLK_ROOT 154 2
LPUART3_CLK_ROOT 155 2
LPUART4_CLK_ROOT 156 2
LPUART5_CLK_ROOT 157 2
LPUART6_CLK_ROOT 158 2
LPUART7_CLK_ROOT 159 2
LPUART8_CLK_ROOT 160 2
LPUART9_CLK_ROOT 161 2
LPUART10_CLK_ROOT 162 2
LPUART11_CLK_ROOT 163 0
LPUART12_CLK_ROOT 164 0
LPI2C1_CLK_ROOT 165 2
LPI2C2_CLK_ROOT 166 2
LPI2C3_CLK_ROOT 167 2
LPI2C4_CLK_ROOT 168 2
LPI2C5_CLK_ROOT 169 0
LPI2C6_CLK_ROOT 170 0
LPSPI1_CLK_ROOT 171 2
LPSPI2_CLK_ROOT 172 2
LPSPI3_CLK_ROOT 173 2
LPSPI4_CLK_ROOT 174 2
LPSPI5_CLK_ROOT 175 0
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Chapter 15 Clock Controller Module (CCM)
Field Description
Target SELECT index Slice Number
LPSPI6_CLK_ROOT 176 0
EMV1_CLK_ROOT 177 2
EMV2_CLK_ROOT 178 2
ENET1_CLK_ROOT 179 2
ENET2_CLK_ROOT 180 2
ENET_QOS_CLK_ROOT 181 2
ENET_25M_CLK_ROOT 182 2
ENET_TIMER1_CLK_ROOT 183 2
ENET_TIMER2_CLK_ROOT 184 2
ENET_TIMER3_CLK_ROOT 185 2
USDHC1_CLK_ROOT 186 2
USDHC2_CLK_ROOT 187 2
ASRC_CLK_ROOT 188 2
MQS_CLK_ROOT 189 2
MIC_CLK_ROOT 190 0
SPDIF_CLK_ROOT 191 2
SAI1_CLK_ROOT 192 2
SAI2_CLK_ROOT 193 2
SAI3_CLK_ROOT 194 2
SAI4_CLK_ROOT 195 0
GPU2D_CLK_ROOT 196 2
ELCDIF_CLK_ROOT 197 2
LCDIFV2_CLK_ROOT 198 2
MIPI_REF_CLK_ROOT 199 2
MIPI_ESC_CLK_ROOT 200 2
CSI2_CLK_ROOT 201 2
CSI2_ESC_CLK_ROOT 202 2
CSI2_UI_CLK_ROOT 203 2
CSI_CLK_ROOT 204 2
CCM_CKO1_CLK_ROOT 205 0
CCM_CKO2_CLK_ROOT 206 2
CM7_CORE_STCLKEN 207 4
CCM_FLEXRAM_CLK_ROOT 208 4
MIPI_DSI_TXESC 209 2
MIPI_DSI_RXESC 210 2
OSC_RC_16M 224 0
OSC_RC_48M 225 0
OSC_RC_48M_DIV2 226 0
OSC_RC_400M 227 0
OSC_24M_OUT 229 0
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Memory Map and register definition
Field Description
Target SELECT index Slice Number
PLL_ARM_OUT 231 2
SYS_PLL2_OUT 233 2
SYS_PLL2_PFD0 234 2
SYS_PLL2_PFD1 235 2
SYS_PLL2_PFD2 236 2
SYS_PLL2_PFD3 237 2
SYS_PLL3_OUT 239 2
SYS_PLL3_DIV2 240 2
SYS_PLL3_PFD0 241 2
SYS_PLL3_PFD1 242 2
SYS_PLL3_PFD2 243 2
SYS_PLL3_PFD3 244 2
SYS_PLL1_OUT 246 2
SYS_PLL1_DIV2 247 2
SYS_PLL1_DIV5 248 2
PLL_AUDIO_OUT 250 2
PLL_VIDEO_OUT 252 2
15.9.2.4 Observe access control (OBSERVE0_AUTHEN -
OBSERVE5_AUTHEN)
This register that manages observe access control.
15.9.2.4.1 Offset
For a = 0 to 5:
Register Offset Description
OBSERVEa_AUTHEN 30h + (a × 80h) Observe access control
OBSERVEa_AUTHEN_S 34h + (a × 80h) Writing a 1 to a bit in this register sets the
ET corresponding bit in OBSERVEa_AUTHEN
OBSERVEa_AUTHEN_C 38h + (a × 80h) Writing a 1 to a bit in this register clears the
LR corresponding bit in OBSERVEa_AUTHEN
OBSERVEa_AUTHEN_T 3Ch + (a × 80h) Writing a 1 to a bit in this register toggles the
OG corresponding bit in OBSERVEa_AUTHEN
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Chapter 15 Clock Controller Module (CCM)
15.9.2.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN_MODE
LOCK_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WHITE_LIST
LOCK_LIST
LOCK_TZ
Reserved
Reserved
Reserved
TZ_USE
TZ_NS
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.2.4.3 Fields
Field Description
31-21 Reserved
—
20 Lock low power and access mode
LOCK_MODE This bit lock low power and access control mode. When this bit is set, DOMAIN_MODE cannot change.
Once this bit is set, it cannot be cleared, until next system reset.
0 - MODE is not locked.
1 - MODE is locked.
19-17 Reserved
—
16 Low power and access control by domain
DOMAIN_MOD Observe works in domain controlled mode.
E
0 - Clock does not work in domain mode.
1 - Clock works in domain mode.
15-13 Reserved
—
12 Lock white list
LOCK_LIST This bit lock white list. When this bit is set, WHITE_LIST cannot be changed. Once this bit is set, it cannot
be cleared, until next system reset.
0 - White list is not locked.
1 - White list is locked.
11-8 White list
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Memory Map and register definition
Field Description
WHITE_LIST Domains that on the white list can change this observe. Each field in this field represent for one domain.
Bit8~Bit12 represent for DOMAIN0~DOMAIN3 respectively.
0000 - No domain can change.
0001 - Domain 0 can change.
0010 - Domain 1 can change.
0011 - Domain 0 and domain 1 can change.
0100 - Domain 2 can change.
1111 - All domain can change.
7-5 Reserved
—
4 Lock truszone setting
LOCK_TZ This bit lock trustzone setting. When this bit is set, TRUSTZONE_USER and
TRUSTZONE_NONSECURE cannot be changed. Once this bit is set, it cannot be cleared, until next
system reset.
0 - Trustzone setting is not locked.
1 - Trustzone setting is locked.
3-2 Reserved
—
1 Non-secure access
TZ_NS This observe can be changed when CPU is in Non-secure mode.
0 - Cannot be changed in Non-secure mode.
1 - Can be changed in Non-secure mode.
0 User access
TZ_USER This observe can be changed when CPU is in user mode.
0 - Clock cannot be changed in user mode.
1 - Clock can be changed in user mode.
15.9.2.5 Current frequency detected
(OBSERVE0_FREQUENCY_CURRENT -
OBSERVE5_FREQUENCY_CURRENT)
This register shows the current frequency detected since last update or reset. After the
measurement begins, wait for 20ms before reading this register.
NOTE
Frequency related measurement requires 32K crystal clock.
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15.9.2.5.1 Offset
Register Offset
OBSERVE0_FREQUEN 40h
CY_CURRENT
OBSERVE1_FREQUEN C0h
CY_CURRENT
OBSERVE2_FREQUEN 140h
CY_CURRENT
OBSERVE3_FREQUEN 1C0h
CY_CURRENT
OBSERVE4_FREQUEN 240h
CY_CURRENT
OBSERVE5_FREQUEN 2C0h
CY_CURRENT
15.9.2.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FREQUENCY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FREQUENCY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.2.5.3 Fields
Field Description
31-0 Frequency
FREQUENCY Current frequency of observed signal in Hz.
15.9.2.6 Minimum frequency detected
(OBSERVE0_FREQUENCY_MIN -
OBSERVE5_FREQUENCY_MIN)
This register shows the minimum frequency detected since last update or reset. After the
measurement begins, wait for 20ms before reading this register.
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15.9.2.6.1 Offset
Register Offset
OBSERVE0_FREQUEN 44h
CY_MIN
OBSERVE1_FREQUEN C4h
CY_MIN
OBSERVE2_FREQUEN 144h
CY_MIN
OBSERVE3_FREQUEN 1C4h
CY_MIN
OBSERVE4_FREQUEN 244h
CY_MIN
OBSERVE5_FREQUEN 2C4h
CY_MIN
15.9.2.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FREQUENCY
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FREQUENCY
W
Reset 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
15.9.2.6.3 Fields
Field Description
31-0 Frequency
FREQUENCY Minimum frequency of observed signal in Hz.
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Chapter 15 Clock Controller Module (CCM)
15.9.2.7 Maximum frequency detected
(OBSERVE0_FREQUENCY_MAX -
OBSERVE5_FREQUENCY_MAX)
This register shows the maximum frequency detected since last update or reset. After the
measurement begins, wait for 20ms before reading this register.
15.9.2.7.1 Offset
Register Offset
OBSERVE0_FREQUEN 48h
CY_MAX
OBSERVE1_FREQUEN C8h
CY_MAX
OBSERVE2_FREQUEN 148h
CY_MAX
OBSERVE3_FREQUEN 1C8h
CY_MAX
OBSERVE4_FREQUEN 248h
CY_MAX
OBSERVE5_FREQUEN 2C8h
CY_MAX
15.9.2.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R FREQUENCY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FREQUENCY
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.2.7.3 Fields
Field Description
31-0 Frequency
FREQUENCY Maximum frequency of observed signal in Hz.
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15.9.3 MISC register descriptions
15.9.3.1 Miscellaneous Registers memory map
For details on how to program these registers, refer to Analog IP (AI) Interface.
misc base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
800 Chip Silicon Version Register (MISC_DIFPROG) 32 RO 0011_70B0
820 VDDSOC_AI_CTRL_REGISTER (VDDSOC_AI_CTRL) 32 RW 0000_0000
830 VDDSOC_AI_WDATA_REGISTER (VDDSOC_AI_WDATA) 32 RW 0000_0000
840 VDDSOC_AI_RDATA_REGISTER (VDDSOC_AI_RDATA) 32 RO 0000_0000
850 VDDSOC2PLL_AI_CTRL_1G_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_CTRL_1G)
860 VDDSOC2PLL_AI_WDATA_1G_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_WDATA_1G)
870 VDDSOC2PLL_AI_RDATA_1G_REGISTER 32 RO 0000_0000
(VDDSOC2PLL_AI_RDATA_1G)
880 VDDSOC_AI_CTRL_AUDIO_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_CTRL_AUDIO)
890 VDDSOC_AI_WDATA_AUDIO_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_WDATA_AUDIO)
8A0 VDDSOC2PLL_AI_RDATA_REGISTER 32 RO 0000_0000
(VDDSOC2PLL_AI_RDATA_AUDIO)
8B0 VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_CTRL_VIDEO)
8C0 VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER 32 RW 0000_0000
(VDDSOC2PLL_AI_WDATA_VIDEO)
8D0 VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER 32 RO 0000_0000
(VDDSOC2PLL_AI_RDATA_VIDEO)
8E0 VDDSOC_AI_CTRL_REGISTER (VDDLPSR_AI_CTRL) 32 RW 0000_0000
8F0 VDDLPSR_AI_WDATA_REGISTER (VDDLPSR_AI_WDATA) 32 RW 0000_0000
900 VDDLPSR_AI_RDATA_REFTOP_REGISTER 32 RO 0000_0000
(VDDLPSR_AI_RDATA_REFTOP)
910 VDDLPSR_AI_RDATA_TMPSNS_REGISTER 32 RO 0000_0000
(VDDLPSR_AI_RDATA_TMPSNS)
920 VDDLPSR_AI400M_CTRL_REGISTER (VDDLPSR_AI400M_CTRL) 32 RW 0000_0000
930 VDDLPSR_AI400M_WDATA_REGISTER 32 RW 0000_0000
(VDDLPSR_AI400M_WDATA)
940 VDDLPSR_AI400M_RDATA_REGISTER 32 RO 0000_0000
(VDDLPSR_AI400M_RDATA)
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Chapter 15 Clock Controller Module (CCM)
15.9.3.2 Chip Silicon Version Register (MISC_DIFPROG)
Chip Silicon Version Register
15.9.3.2.1 Offset
Register Offset
MISC_DIFPROG 800h
15.9.3.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CHIPID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHIPID
W
Reset 0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0
15.9.3.2.3 Fields
Field Description
31-0 Chip ID
CHIPID
15.9.3.3 VDDSOC_AI_CTRL_REGISTER (VDDSOC_AI_CTRL)
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15.9.3.3.1 Offset
Register Offset
VDDSOC_AI_CTRL 820h
15.9.3.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDSOC_AIRWB
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved VDDSOC_AI_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.3.3 Fields
Field Description
31-24 Always set to zero (0).
— Always set to zero (0).
23-17 Reserved
—
16 VDDSOC_AIRWB
VDDSOC_AIRW Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
B
15-8 Always set to zero (0).
— Always set to zero (0).
7-0 VDDSOC_AI_ADDR
VDDSOC_AI_A Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
DDR
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15.9.3.4 VDDSOC_AI_WDATA_REGISTER (VDDSOC_AI_WDATA)
15.9.3.4.1 Offset
Register Offset
VDDSOC_AI_WDATA 830h
15.9.3.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDSOC_AI_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDSOC_AI_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.4.3 Fields
Field Description
31-0 VDDSOC_AI_WDATA
VDDSOC_AI_W Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
DATA
15.9.3.5 VDDSOC_AI_RDATA_REGISTER (VDDSOC_AI_RDATA)
15.9.3.5.1 Offset
Register Offset
VDDSOC_AI_RDATA 840h
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15.9.3.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDSOC_AI_RDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDSOC_AI_RDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.5.3 Fields
Field Description
31-0 VDDSOC_AI_RDATA
VDDSOC_AI_R Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
DATA
15.9.3.6 VDDSOC2PLL_AI_CTRL_1G_REGISTER
(VDDSOC2PLL_AI_CTRL_1G)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.6.1 Offset
Register Offset
VDDSOC2PLL_AI_CTRL 850h
_1G
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15.9.3.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDSOC2PLL_AIRWB_1G
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDSOC2PLL_AITOGGLE_DONE_1G
VDDSOC2PLL_AITOGGLE_1G
VDDSOC2PLL_AIADDR_1G
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.6.3 Fields
Field Description
31-24 Reserved
—
23-17 Reserved
—
16 VDDSOC2PLL_AIRWB_1G
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AIRWB_1G
15-10 Reserved
—
9 VDDSOC2PLL_AITOGGLE_DONE_1G
Table continues on the next page...
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Field Description
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description..
AITOGGLE_DO
NE_1G
8 VDDSOC2PLL_AITOGGLE_1G
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description..
AITOGGLE_1G
7-0 VDDSOC2PLL_AIADDR_1G
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AIADDR_1G
15.9.3.7 VDDSOC2PLL_AI_WDATA_1G_REGISTER
(VDDSOC2PLL_AI_WDATA_1G)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.7.1 Offset
Register Offset
VDDSOC2PLL_AI_WDA 860h
TA_1G
15.9.3.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDSOC2PLL_AI_WDATA_1G
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDSOC2PLL_AI_WDATA_1G
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.7.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_WDATA_1G
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Field Description
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_WDATA_1G
15.9.3.8 VDDSOC2PLL_AI_RDATA_1G_REGISTER
(VDDSOC2PLL_AI_RDATA_1G)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.8.1 Offset
Register Offset
VDDSOC2PLL_AI_RDAT 870h
A_1G
15.9.3.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDSOC2PLL_AI_RDATA_1G
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDSOC2PLL_AI_RDATA_1G
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.8.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_RDATA_1G
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_RDATA_1G
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15.9.3.9 VDDSOC_AI_CTRL_AUDIO_REGISTER
(VDDSOC2PLL_AI_CTRL_AUDIO)
15.9.3.9.1 Offset
Register Offset
VDDSOC2PLL_AI_CTRL 880h
_AUDIO
15.9.3.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDSOC2PLL_AIRWB_AUDIO
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDSOC2PLL_AITOGGLE_DONE_AUDIO
VDDSOC2PLL_AITOGGLE_AUDIO
VDDSOC2PLL_AI_ADDR_AUDIO
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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15.9.3.9.3 Fields
Field Description
31-24 Always set to zero (0).
— Always set to zero (0).
23-17 Reserved
—
16 VDDSOC_AIRWB
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AIRWB_AUDIO
15-10 Always set to zero (0).
— Always set to zero (0).
9 VDDSOC2PLL_AITOGGLE_DONE_AUDIO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description..
AITOGGLE_DO
NE_AUDIO
8 VDDSOC2PLL_AITOGGLE_AUDIO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AITOGGLE_AU
DIO
7-0 VDDSOC2PLL_AI_ADDR_AUDIO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_ADDR_AUDI
O
15.9.3.10 VDDSOC_AI_WDATA_AUDIO_REGISTER
(VDDSOC2PLL_AI_WDATA_AUDIO)
15.9.3.10.1 Offset
Register Offset
VDDSOC2PLL_AI_WDA 890h
TA_AUDIO
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15.9.3.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDSOC2PLL_AI_WDATA_AUDIO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDSOC2PLL_AI_WDATA_AUDIO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.10.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_WDATA_AUDIO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_WDATA_AU
DIO
15.9.3.11 VDDSOC2PLL_AI_RDATA_REGISTER
(VDDSOC2PLL_AI_RDATA_AUDIO)
15.9.3.11.1 Offset
Register Offset
VDDSOC2PLL_AI_RDAT 8A0h
A_AUDIO
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15.9.3.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDSOC2PLL_AI_RDATA_AUDIO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDSOC2PLL_AI_RDATA_AUDIO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.11.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_RDATA_AUDIO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_RDATA_AU
DIO
15.9.3.12 VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER
(VDDSOC2PLL_AI_CTRL_VIDEO)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.12.1 Offset
Register Offset
VDDSOC2PLL_AI_CTRL 8B0h
_VIDEO
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15.9.3.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDSOC2PLL_AIRWB_VIDEO
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 VDDSOC2PLL_AITOGGLE_DONE_VIDEO 9 8 7 6 5 4 3 2 1 0
VDDSOC2PLL_AITOGGLE_VIDEO
VDDSOC2PLL_AIADDR_VIDEO
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.12.3 Fields
Field Description
31-24 Reserved
—
23-17 Reserved
—
16 VDDSOC2PLL_AIRWB_VIDEO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AIRWB_VIDEO
15-10 Reserved
Table continues on the next page...
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Chapter 15 Clock Controller Module (CCM)
Field Description
—
9 VDDSOC2PLL_AITOGGLE_DONE_VIDEO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AITOGGLE_DO
NE_VIDEO
8 VDDSOC2PLL_AITOGGLE_VIDEO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AITOGGLE_VID
EO
7-0 VDDSOC2PLL_AIADDR_VIDEO
VDDSOC2PLL_ VDDSOC2PLL_AIADDR_VIDEO
AIADDR_VIDEO
15.9.3.13 VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER
(VDDSOC2PLL_AI_WDATA_VIDEO)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.13.1 Offset
Register Offset
VDDSOC2PLL_AI_WDA 8C0h
TA_VIDEO
15.9.3.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDSOC2PLL_AI_WDATA_VIDEO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDSOC2PLL_AI_WDATA_VIDEO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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15.9.3.13.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_WDATA_VIDEO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description..
AI_WDATA_VID
EO
15.9.3.14 VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER
(VDDSOC2PLL_AI_RDATA_VIDEO)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.14.1 Offset
Register Offset
VDDSOC2PLL_AI_RDAT 8D0h
A_VIDEO
15.9.3.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDSOC2PLL_AI_RDATA_VIDEO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDSOC2PLL_AI_RDATA_VIDEO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.14.3 Fields
Field Description
31-0 VDDSOC2PLL_AI_RDATA_VIDEO
VDDSOC2PLL_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
AI_RDATA_VID
EO
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15.9.3.15 VDDSOC_AI_CTRL_REGISTER (VDDLPSR_AI_CTRL)
15.9.3.15.1 Offset
Register Offset
VDDLPSR_AI_CTRL 8E0h
15.9.3.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDLPSR_AIRWB
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved VDDLPSR_AI_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.15.3 Fields
Field Description
31-24 Always set to zero (0).
— Always set to zero (0).
23-17 Reserved
—
16 VDDLPSR_AIRWB
VDDLPSR_AIR Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
WB
15-8 Always set to zero (0).
— Always set to zero (0).
Table continues on the next page...
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Field Description
7-0 VDDLPSR_AI_ADDR
VDDLPSR_AI_A Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
DDR
15.9.3.16 VDDLPSR_AI_WDATA_REGISTER (VDDLPSR_AI_WDATA)
15.9.3.16.1 Offset
Register Offset
VDDLPSR_AI_WDATA 8F0h
15.9.3.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDLPSR_AI_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDLPSR_AI_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.16.3 Fields
Field Description
31-0 VDD_LPSR_AI_WDATA
VDDLPSR_AI_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
WDATA
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15.9.3.17 VDDLPSR_AI_RDATA_REFTOP_REGISTER
(VDDLPSR_AI_RDATA_REFTOP)
15.9.3.17.1 Offset
Register Offset
VDDLPSR_AI_RDATA_R 900h
EFTOP
15.9.3.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDLPSR_AI_RDATA_REFTOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDLPSR_AI_RDATA_REFTOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.17.3 Fields
Field Description
31-0 VDDLPSR_AI_RDATA_REFTOP
VDDLPSR_AI_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
RDATA_REFTO
P
15.9.3.18 VDDLPSR_AI_RDATA_TMPSNS_REGISTER
(VDDLPSR_AI_RDATA_TMPSNS)
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15.9.3.18.1 Offset
Register Offset
VDDLPSR_AI_RDATA_T 910h
MPSNS
15.9.3.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDLPSR_AI_RDATA_TMPSNS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDLPSR_AI_RDATA_TMPSNS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.18.3 Fields
Field Description
31-0 VDDLPSR_AI_RDATA_TMPSNS
VDDLPSR_AI_ Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
RDATA_TMPSN
S
15.9.3.19 VDDLPSR_AI400M_CTRL_REGISTER
(VDDLPSR_AI400M_CTRL)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.19.1 Offset
Register Offset
VDDLPSR_AI400M_CTR 920h
L
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15.9.3.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDDLPSR_AI400M_RWB
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDLPSR_AITOGGLE_DONE_400M
VDDLPSR_AITOGGLE_400M
VDDLPSR_AI400M_ADDR
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.19.3 Fields
Field Description
31-24 Reserved
—
23-17 Reserved
—
16 VDDLPSR_AI400M_RWB
VDDLPSR_AI40 Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
0M_RWB
15-10 Reserved
—
9 VDDLPSR_AITOGGLE_DONE_400M
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Field Description
VDDLPSR_AIT Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
OGGLE_DONE
_400M
8 VDDLPSR_AITOGGLE_400M
VDDLPSR_AIT Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
OGGLE_400M
7-0 VDDLPSR_AI400M_ADDR
VDDLPSR_AI40 Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
0M_ADDR
15.9.3.20 VDDLPSR_AI400M_WDATA_REGISTER
(VDDLPSR_AI400M_WDATA)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.20.1 Offset
Register Offset
VDDLPSR_AI400M_WD 930h
ATA
15.9.3.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VDDLPSR_AI400M_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VDDLPSR_AI400M_WDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.20.3 Fields
Field Description
31-0 VDDLPSR_AI400M_WDATA
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Field Description
VDDLPSR_AI40 Please refer to 'Analog IP (AI) Interface' topic for the detailed description.
0M_WDATA
15.9.3.21 VDDLPSR_AI400M_RDATA_REGISTER
(VDDLPSR_AI400M_RDATA)
Please refer to 'Analog IP (AI) Interface' topic for the detailed description. It should
follow the sequence provided.
15.9.3.21.1 Offset
Register Offset
VDDLPSR_AI400M_RDA 940h
TA
15.9.3.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VDDLPSR_AI400M_RDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VDDLPSR_AI400M_RDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.3.21.3 Fields
Field Description
31-0 VDDLPSR_AI400M_RDATA
VDDLPSR_AI40 Please refer to 'Analog IP (AI) Interface' topic for the detailed description..
0M_RDATA
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15.9.4 PLL register descriptions
15.9.4.1 PLL memory map
pll base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
200 ARM_PLL_CTRL_REGISTER (ARM_PLL_CTRL) 32 RW 4000_00A6
210 SYS_PLL3_CTRL_REGISTER (SYS_PLL3_CTRL) 32 RW 4000_0003
220 SYS_PLL3_UPDATE_REGISTER (SYS_PLL3_UPDATE) 32 RW 0000_0000
230 SYS_PLL3_PFD_REGISTER (SYS_PLL3_PFD) 32 RW 8CA0_918D
240 SYS_PLL2_CTRL_REGISTER (SYS_PLL2_CTRL) 32 RW 4000_0000
250 SYS_PLL2_UPDATE_REGISTER (SYS_PLL2_UPDATE) 32 RW 0000_0000
260 SYS_PLL2_SS_REGISTER (SYS_PLL2_SS) 32 RW 0000_0000
270 SYS_PLL2_PFD_REGISTER (SYS_PLL2_PFD) 32 RW A098_909B
2A0 SYS_PLL2_MFD_REGISTER (SYS_PLL2_MFD) 32 RW 0FFF_FFFF
2B0 SYS_PLL1_SS_REGISTER (SYS_PLL1_SS) 32 RW 0000_0000
2C0 SYS_PLL1_CTRL_REGISTER (SYS_PLL1_CTRL) 32 RW 0000_4000
2D0 SYS_PLL1_DENOMINATOR_REGISTER 32 RW 2FFF_FFFE
(SYS_PLL1_DENOMINATOR)
2E0 SYS_PLL1_NUMERATOR_REGISTER (SYS_PLL1_NUMERATOR) 32 RW 1FFF_FFFF
2F0 SYS_PLL1_DIV_SELECT_REGISTER (SYS_PLL1_DIV_SELECT) 32 RW 0000_001D
300 PLL_AUDIO_CTRL_REGISTER (PLL_AUDIO_CTRL) 32 RW 0000_4000
310 PLL_AUDIO_SS_REGISTER (PLL_AUDIO_SS) 32 RW 0000_0000
320 PLL_AUDIO_DENOMINATOR_REGISTER 32 RW 2FFF_FFFE
(PLL_AUDIO_DENOMINATOR)
330 PLL_AUDIO_NUMERATOR_REGISTER 32 RW 1FFF_FFFF
(PLL_AUDIO_NUMERATOR)
340 PLL_AUDIO_DIV_SELECT_REGISTER 32 RW 0000_0029
(PLL_AUDIO_DIV_SELECT)
350 PLL_VIDEO_CTRL_REGISTER (PLL_VIDEO_CTRL) 32 RW 0000_4000
360 PLL_VIDEO_SS_REGISTER (PLL_VIDEO_SS) 32 RW 0000_0000
370 PLL_VIDEO_DENOMINATOR_REGISTER 32 RW 2FFF_FFFE
(PLL_VIDEO_DENOMINATOR)
380 PLL_VIDEO_NUMERATOR_REGISTER 32 RW 1FFF_FFFF
(PLL_VIDEO_NUMERATOR)
390 PLL_VIDEO_DIV_SELECT_REGISTER (PLL_VIDEO_DIV_SELECT) 32 RW 0000_0029
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Chapter 15 Clock Controller Module (CCM)
15.9.4.2 ARM_PLL_CTRL_REGISTER (ARM_PLL_CTRL)
ARM_PLL control register
The control register provides control for the ARM PLL.
15.9.4.2.1 Offset
Register Offset
ARM_PLL_CTRL 200h
15.9.4.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARM_PLL_STABLE
ARM_PLL_CONTROL_MODE
ARM_PLL_GATE
POST_DIV_SEL
R
Reserved
Reserved
Reserved
Reserved
Reserved
BYPAS
S
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HOLD_RING_OFF
POST_DIV_SEL
ENABLE_CLK
POWERUP
DIV_SELEC
Reserved
W
T
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0
15.9.4.2.3 Fields
Field Description
31 pll_arm_control_mode
ARM_PLL_CON Enable mode
TROL_MODE
0 - Software Mode (Default)
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Field Description
1 - GPC Mode
30 ARM_PLL_GATE
ARM_PLL_GAT default value is 1'b1
E
0 - Clock is not gated
1 - Clock is gated
29 ARM_PLL_STABLE
ARM_PLL_STA The stable indicate bit. Normally in Software mode, after the power up and enable sequence for arm pll,
BLE arm pll will not be in stable state immediately. This bit is used by software to monitor the locking status for
arm pll. GPC mode do not need to take care of this bit. Hardware will handle it automatically.
0 - ARM PLL is not stable
1 - ARM PLL is stable
28-22 Always set to zero (0).
— Always set to zero (0).
21 Reserved
—
20 Reserved
—
19 Reserved
—
18 Reserved
—
17 Bypass the pll.
BYPASS Bypass the pll enable bit. This bit could be used to bypass the PLL output to the source of reference clock
0 - Function mode
1 - Bypass Mode
16-15 POST_DIV_SEL
POST_DIV_SEL 00 - Divide by 2
01 - Divide by 4
10 - Divide by 8
11 - Divide by 1
14 Enable the clock output.
ENABLE_CLK Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Disable the clock
1 - Enable the clock
13 Powers up the PLL.
POWERUP Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Power down the PLL
1 - Power Up the PLL
12 PLL Start up initialization
This field should be set to 1 every time during PLL lock, and cleared after a certain delay.
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Chapter 15 Clock Controller Module (CCM)
Field Description
HOLD_RING_O Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
FF
0 - Normal operation
1 - Initialize PLL start up
11-8 Reserved
—
7-0 DIV_SELECT
DIV_SELECT This field controls the pll loop divider. Valid range for divider value: 104-208.
Fout = Fin * div_select/2.0
15.9.4.3 SYS_PLL3_CTRL_REGISTER (SYS_PLL3_CTRL)
The control register provides control for the 480 PLL.
15.9.4.3.1 Offset
Register Offset
SYS_PLL3_CTRL 210h
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15.9.4.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYS_PLL3_STABL
SYS_PLL3_DIV2_CONTROL_MODE
SYS_PLL3_CONTROL_MODE
R
SYS_PLL3_GAT
POWERUP
Reserved
Reserved
Reserved
BYPAS
E
S
E
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HOLD_RING_OFF
SYS_PLL3_DIV2
ENABLE_CLK
PLL_REG_E
Reserved
Reserved
Reserved
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
15.9.4.3.3 Fields
Field Description
31 SYS_PLL3_control_mode
SYS_PLL3_CO Enable mode
NTROL_MODE
0 - Software Mode (Default)
1 - GPC Mode
30 SYS_PLL3_GATE
SYS_PLL3_GA default value is 1'b1
TE
0 - Clock is not gated
1 - Clock is gated
29 SYS_PLL3_STABLE
SYS_PLL3_STA The stable indicate bit. Normally in Software mode, after the power up and enable sequence for
BLE SYS_PLL3, arm pll will not be in stable state immediately. This bit is used by software to monitor the
locking status for SYS_PLL3.
28 SYS_PLL3_DIV2_CONTROL_MODE
Enable mode
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Chapter 15 Clock Controller Module (CCM)
Field Description
SYS_PLL3_DIV 0 - Software Mode (Default)
2_CONTROL_M
1 - GPC Mode
ODE
27-22 Always set to zero (0).
— Always set to zero (0).
21 Powers up the PLL.
POWERUP Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Power down the PLL
1 - Power Up the PLL
20-18 Reserved
—
17 Reserved
—
16 BYPASS
BYPASS Bypass the pll enable bit. This bit could be used to bypass the PLL output to the source of reference clock
0 - Function mode
1 - Bypass Mode
15-14 Reserved
—
13 Enable the clock output.
ENABLE_CLK Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Disable the clock
1 - Enable the clock
12 Reserved
—
11 PLL Start up initialization
HOLD_RING_O This field should be set to 1 every time during PLL lock, and cleared after a certain delay.
FF
Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Normal operation
1 - Initialize PLL start up
10-7 Reserved
—
6-5 Reserved
—
4 Enable Internal PLL Regulator
PLL_REG_EN Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
3 SYS PLL3 DIV2 gate
SYS_PLL3_DIV Enable SYS_PLL3_DIV2 clock which is sourced from SYS_PLL3
2
0 : disable
1 : enable
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Field Description
2-0 Reserved
—
15.9.4.4 SYS_PLL3_UPDATE_REGISTER (SYS_PLL3_UPDATE)
The control register provides control for the 480 PLL.
15.9.4.4.1 Offset
Register Offset
SYS_PLL3_UPDATE 220h
15.9.4.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PFD3_CONTROL_MODE
PDF2_CONTROL_MODE
PFD1_CONTROL_MODE
PFD0_CONTROL_MODE
PFD3_UPDATE
PFD2_UPDATE
PFD1_UPDATE
PFD0_UPDATE
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.4.3 Fields
Field Description
31-10 Always set to zero (0).
— Always set to zero (0).
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Chapter 15 Clock Controller Module (CCM)
Field Description
9 Reserved
—
8 pfd3_control_mode
PFD3_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
7 pdf2_control_mode
PDF2_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
6 pfd1_control_mode
PFD1_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
5 pfd0_control_mode
PFD0_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
4 PFD3_UPDATE
PFD3_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
3 PFD2_OVERRIDE
PFD2_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
2 PFD1_OVERRIDE
PFD1_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
1 PFD0_OVERRIDE
PFD0_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
0 Reserved
—
15.9.4.5 SYS_PLL3_PFD_REGISTER (SYS_PLL3_PFD)
This register contains the numerator of SYS PLL3 fractional loop divider.
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15.9.4.5.1 Offset
Register Offset
SYS_PLL3_PFD 230h
15.9.4.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFD3_STABLE
PFD2_STABLE
PFD3_DIV1_CLKGATE
PFD2_DIV1_CLKGATE
PFD3_FRAC
PFD2_FRAC
R
Reset 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFD1_STABLE
PFD0_STABLE
PFD1_DIV1_CLKGATE
PFD0_DIV1_CLKGATE
PFD1_FRAC
PFD0_FRAC
R
Reset 1 0 0 1 0 0 0 1 1 0 0 0 1 1 0 1
15.9.4.5.3 Fields
Field Description
31 PFD3_DIV1_CLKGATE
PFD3_DIV1_CL 0 - ref_pfd3 fractional divider clock is enabled
KGATE
1 - Fractional divider clock (reference ref_pfd3) is off (power savings)
30 PFD3_STABLE
PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
29-24 PFD3_FRAC
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Chapter 15 Clock Controller Module (CCM)
Field Description
PFD3_FRAC This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD3_FRAC where
PFD3_FRAC is in the range 13-35.
NOTE: The PFD value can be set to 12, however the lowest recommended setting for PFD is 13.
23 PFD2_DIV1_CLKGATE
PFD2_DIV1_CL 0 - ref_pfd2 fractional divider clock is enabled
KGATE
1 - Fractional divider clock (reference ref_pfd2) is off (power savings)
22 PFD2_STABLE
PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
21-16 PFD2_FRAC
PFD2_FRAC This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD2_FRAC where
PFD2_FRAC is in the range 13-35.
15 PFD1_DIV1_CLKGATE
PFD1_DIV1_CL 0 - ref_pfd1 fractional divider clock is enabled
KGATE
1 - Fractional divider clock (reference ref_pfd1) is off (power savings)
14 PFD1_STABLE
PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
13-8 PFD1_FRAC
PFD1_FRAC This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD1_FRAC where
PFD1_FRAC is in the range 13-35.
7 PFD0_DIV1_CLKGATE
PFD0_DIV1_CL 0 - ref_pfd0 fractional divider clock is enabled
KGATE
1 - Fractional divider clock (reference ref_pfd0) is off (power savings
6 PFD0_STABLE
PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
5-0 PFD0_FRAC
PFD0_FRAC This field controls the fractional divide value. The resulting frequency shall be 480*18/PFD0_FRAC where
PFD0_FRAC is in the range 13-35.
15.9.4.6 SYS_PLL2_CTRL_REGISTER (SYS_PLL2_CTRL)
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The control register provides control for the SYS_PLL2
15.9.4.6.1 Offset
Register Offset
SYS_PLL2_CTRL 240h
15.9.4.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYS_PLL2_CONTROL_MODE
SYS_PLL2_STABL
PLL_DDR_OVERRIDE
PFD_OFFSET_E
SYS_PLL2_GAT
DITHER_ENABL
R
POWERUP
Reserved
Reserved
BYPAS
E
S
E
E
W
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HOLD_RING_OFF
ENABLE_CLK
PLL_REG_E
Reserved
Reserved
Reserved
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.6.3 Fields
Field Description
31 SYS_PLL2_control_mode
SYS_PLL2_CO SYS_PLL2 has two mode to for enable. One is software mode, the other is GPC mode(Setpoint).
NTROL_MODE
0 - Software Mode (Default)
1 - GPC Mode
30 SYS_PLL2_GATE
SYS_PLL2_GA default value is 1'b1
TE
0 - Clock is not gated
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Chapter 15 Clock Controller Module (CCM)
Field Description
1 - Clock is gated
29 SYS_PLL2_STABLE
SYS_PLL2_STA The stable indicate bit. Normally in Software mode, after the power up and enable sequence for
BLE SYS_PLL2, ARM_PLL will not be in stable state immediately. This bit is used by software to monitor the
locking status for SYS_PLL2.
28-24 Always set to zero (0).
— Always set to zero (0).
23 Powers up the PLL.
POWERUP Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Power down the PLL
1 - Power Up the PLL
22-20 Always set to zero (0).
— Always set to zero (0).
19 PLL_DDR_OVERRIDE
PLL_DDR_OVE The OVERRIDE bit allows the clock control module to automatically override portions of the register.
RRIDE
PLL_DDR_OVERRIDE = 0x0: ENABLE_CLK bits and the POWERDOWN bit controlled by this register.
PLL_DDR_OVERRIDE = 0x1: CCM based hardware bits override the ENABLE_CLK bits and the
POWERDOWN bit in this register.
18 PFD_OFFSET_EN
PFD_OFFSET_ Enables an offset in the phase frequency detector.
EN
17 DITHER_ENABLE
DITHER_ENAB Enables dither in the fractional modulator calculation.
LE
0 - Disable Dither
1 - Enable Dither
16 Bypass the pll.
BYPASS Control bit to Bypass the pll to the reference clock
0 - Function mode
1 - Bypass Mode
15-14 Reserved
—
13 Enable the clock output.
ENABLE_CLK Enable the clock output.
0 - Disable the clock
1 - Enable the clock
12 Reserved
—
11 PLL Start up initialization
HOLD_RING_O This field should be set to 1 every time during PLL lock, and cleared after a certain delay.
FF
Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
0 - Normal operation
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Field Description
1 - Initialize PLL start up
10-7 Reserved
—
6-4 Reserved
—
3 Enable Internal PLL Regulator
PLL_REG_EN Please refer to PLL Enable Sequence for more details on how to use this bit during the PLL enablement.
2-0 Reserved
—
15.9.4.7 SYS_PLL2_UPDATE_REGISTER (SYS_PLL2_UPDATE)
SYS_PLL2 PFD control register
The control register provides control for the 528 PLL.
15.9.4.7.1 Offset
Register Offset
SYS_PLL2_UPDATE 250h
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Chapter 15 Clock Controller Module (CCM)
15.9.4.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFD3_CONTROL_MODE
PFD2_CONTROL_MODE
PFD1_CONTROL_MODE
PFD0_CONTROL_MODE
PFD3_UPDATE
PFD2_UPDATE
PFD1_UPDATE
PFD0_UPDATE
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.7.3 Fields
Field Description
31-10 Always set to zero (0).
— Always set to zero (0).
9 Reserved
—
8 pfd3_control_mode
PFD3_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
7 pfd2_control_mode
PFD2_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
6 pfd1_control_mode
PFD1_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
5 pfd0_control_mode
PFD0_CONTRO Enable mode
L_MODE
0 - Software Mode (Default)
1 - GPC Mode
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Memory Map and register definition
Field Description
4 PFD3_UPDATE
PFD3_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
3 PFD2_UPDATE
PFD2_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
2 PFD1_UPDATE
PFD1_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
1 PFD0_UPDATE
PFD0_UPDATE PFD update
This bit is used to update the pfd value. Toggle it will make the update function.
0 Reserved
—
15.9.4.8 SYS_PLL2_SS_REGISTER (SYS_PLL2_SS)
This register contains the SYS PLL2 spread spectrum controls
Refer to Spread Spectrum Parameters for more details.
15.9.4.8.1 Offset
Register Offset
SYS_PLL2_SS 260h
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15.9.4.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABL
STE
W
P
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.8.3 Fields
Field Description
31-16 STOP
STOP Frequency change = stop/MFD*24MHz.
15 ENABLE
ENABLE This bit enables the spread spectrum modulation
0 - Disable Spread Spectrum. In this setting, the values for STEP and STOP are ignored
1 - Enable Spread Spectrum
14-0 STEP
STEP The max frequency change = step/MFD*24MHz.
15.9.4.9 SYS_PLL2_PFD_REGISTER (SYS_PLL2_PFD)
SYS_PLL2 fractional loop divider
This register contains the numerator of DDR PLL fractional loop divider.
15.9.4.9.1 Offset
Register Offset
SYS_PLL2_PFD 270h
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15.9.4.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFD3_STABLE
PFD2_STABLE
PFD3_DIV1_CLKGATE
PFD2_DIV1_CLKGATE
PFD3_FRAC
PFD2_FRAC
R
Reset 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFD1_STABLE
PFD0_STABLE
PFD1_DIV1_CLKGATE
PFD0_DIV1_CLKGATE
PFD1_FRAC
PFD0_FRAC
R
Reset 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1
15.9.4.9.3 Fields
Field Description
31 PFD3_DIV1_CLKGATE
PFD3_DIV1_CL If set to 1, the 3rd fractional divider clock (reference ref_pfd3) is off (power savings). 0: ref_pfd3 fractional
KGATE divider clock is enabled.
30 PFD3_STABLE
PFD3_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
29-24 PFD3_FRAC
PFD3_FRAC This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD3_FRAC where
PFD3_FRAC is in the range 13-35.
23 PFD2_DIV1_CLKGATE
PFD2_DIV1_CL If set to 1, the 2 fractional divider clock (reference ref_pfd2) is off (power savings). 0: ref_pfd2 fractional
KGATE divider clock is enabled.
22 PFD2_STABLE
PFD2_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
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Field Description
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
21-16 PFD2_FRAC
PFD2_FRAC This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD2_FRAC where
PFD2_FRAC is in the range 13-35.
15 PFD1_DIV1_CLKGATE
PFD1_DIV1_CL If set to 1, the 1 fractional divider clock (reference ref_pfd1) is off (power savings). 0: ref_pfd1 fractional
KGATE divider clock is enabled.
14 PFD1_STABLE
PFD1_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
13-8 PFD1_FRAC
PFD1_FRAC This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD1_FRAC where
PFD1_FRAC is in the range 13-35.
7 PFD0_DIV1_CLKGATE
PFD0_DIV1_CL If set to 1, the 0 fractional divider clock (reference ref_pfd0) is off (power savings). 0: ref_pfd0 fractional
KGATE divider clock is enabled.
6 PFD0_STABLE
PFD0_STABLE This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit,
program the new value, and when this bit inverts, the phase divider clock output is stable. Note that the
value will not invert when the fractional divider is taken out of or placed into clock-gated state.
5-0 PFD0_FRAC
PFD0_FRAC This field controls the fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where
PFD0_FRAC is in the range 13-35.
15.9.4.10 SYS_PLL2_MFD_REGISTER (SYS_PLL2_MFD)
Spread Spectrum Frequency Range is calculated as follows: Range = (STOP/MFD) *
Fref
15.9.4.10.1 Offset
Register Offset
SYS_PLL2_MFD 2A0h
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15.9.4.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
MFD
W
Reset 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MFD
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15.9.4.10.3 Fields
Field Description
31-30 Reserved
—
29-0 Denominator
MFD Refer to Programming Guidelines for more details.
15.9.4.11 SYS_PLL1_SS_REGISTER (SYS_PLL1_SS)
This register contains the 1G PLL spread spectrum controls
Refer to Spread Spectrum Parameters for more details.
15.9.4.11.1 Offset
Register Offset
SYS_PLL1_SS 2B0h
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15.9.4.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABL
STE
W
P
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.11.3 Fields
Field Description
31-16 STOP
STOP Frequency change = stop/MFD*24MHz.
15 ENABLE
ENABLE This bit enables the spread spectrum modulation
0 - Disable Spread Spectrum. In this setting, the values for STEP and STOP are ignored
1 - Enable Spread Spectrum
14-0 STEP
STEP The max frequency change = step/MFD*24MHz.
15.9.4.12 SYS_PLL1_CTRL_REGISTER (SYS_PLL1_CTRL)
The control register provides control for the 1G PLL.
15.9.4.12.1 Offset
Register Offset
SYS_PLL1_CTRL 2C0h
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15.9.4.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYS_PLL1_AI_BUS
SYS_PLL1_STABL
SYS_PLL1_DIV2_CONTROL_MODE
SYS_PLL1_DIV5_CONTROL_MODE
SYS_PLL1_CONTROL_MODE
SYS_PLL1_DIV5
SYS_PLL1_DIV2
Reserved
Reserved
E
Y
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SYS_PLL1_GAT
ENABLE_CLK
Reserved
Reserved
W
E
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.12.3 Fields
Field Description
31 SYS_PLL1_CONTROL_MODE
SYS_PLL1_CO Enable mode
NTROL_MODE
0 - Software Mode (Default)
1 - GPC Mode
30 SYS_PLL1_AI_BUSY
SYS_PLL1_AI_ For this AI bridge register field, this bit is used along with AI bus. Function is for AI busy monitor. There
BUSY will be a detail description on how to use it. For debug purpose. Reserved.
29 SYS_PLL1_STABLE
SYS_PLL1_STA SYS_PLL1_STABLE
BLE
Normally in Software mode, after the power up and enable sequence for pll, arm pll will not be in stable
state immediately. This bit is used by software to monitor the locking status for pll. GPC mode do not
need to take care of this bit. Hardware will handle it automatically.
28 SYS_PLL1_DIV2_CONTROL_MODE
SYS_PLL1_DIV Enable mode
2_CONTROL_M
0 - Software Mode (Default)
ODE
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Field Description
1 - GPC Mode
27 SYS_PLL1_DIV5_CONTROL_MODE
SYS_PLL1_DIV Enable mode
5_CONTROL_M
0 - Software Mode (Default)
ODE
1 - GPC Mode
26 SYS_PLL1_DIV5
SYS_PLL1_DIV SYS_PLL1_DIV5 The PLL 1g has the source which is DIV5 by the actual frequency of PLL 1G, this bit
5 control of the enable of this divider.
25 SYS_PLL1_DIV2
SYS_PLL1_DIV The PLL 1g has the source which is DIV2 by the actual frequency of PLL 1G, this bit control of the enable
2 of this divider.
24 Reserved
—
23-15 Reserved
—
14 SYS_PLL1_GATE
SYS_PLL1_GA SYS_PLL1_GATE There is a gate in top level to gate the pll output for power saving purpose,this field it
TE to control this gate.
0 - No gate
1 - Gate the output
13 ENABLE_CLK
ENABLE_CLK Enable the clock output.
This field is used to align the software mode and GPC mode. The usage of this bit is to describe the last
PLL mode(enable or disable) before entering GPC mode. User need to make sure the pll state is
matching first Setpoint will be entered.
12-0 Reserved
—
15.9.4.13 SYS_PLL1_DENOMINATOR_REGISTER
(SYS_PLL1_DENOMINATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
Output frequency=Fref∗(MFI+MFN/MFD)
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15.9.4.13.1 Offset
Register Offset
SYS_PLL1_DENOMINAT 2D0h
OR
15.9.4.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
DENOM
Reset 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DENOM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
15.9.4.13.3 Fields
Field Description
31-30 Reserved
—
29-0 DENOM
DENOM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.14 SYS_PLL1_NUMERATOR_REGISTER
(SYS_PLL1_NUMERATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
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15.9.4.14.1 Offset
Register Offset
SYS_PLL1_NUMERATO 2E0h
R
15.9.4.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
NUM
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NUM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15.9.4.14.3 Fields
Field Description
31-30 Reserved
—
29-0 NUM
NUM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.15 SYS_PLL1_DIV_SELECT_REGISTER
(SYS_PLL1_DIV_SELECT)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
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15.9.4.15.1 Offset
Register Offset
SYS_PLL1_DIV_SELEC 2F0h
T
15.9.4.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DIV_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
15.9.4.15.3 Fields
Field Description
31-7 Reserved
—
6-0 DIV_SELECT
DIV_SELECT As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.16 PLL_AUDIO_CTRL_REGISTER (PLL_AUDIO_CTRL)
PLL_AUDIO_control_register
The control register provides control for the AUDIO PLL.
15.9.4.16.1 Offset
Register Offset
PLL_AUDIO_CTRL 300h
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15.9.4.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_AUDIO_AI_BUSY
PLL_AUDIO_STABLE
PLL_AUDIO_CONTROL_MODE
R
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PLL_AUDIO_GATE
ENABLE_CLK
Reserved
Reserved
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.16.3 Fields
Field Description
31 pll_audio_control_mode
PLL_AUDIO_C Enable mode
ONTROL_MOD
0 - Software Mode (Default)
E
1 - GPC Mode
30 pll_audio_ai_busy
PLL_AUDIO_AI For this AI bridge register field, this bit is used along with AI bus. Function is for AI busy monitor. there will
_BUSY be a detail description on how to use it. For debug purpose. Reserved.
29 PLL_AUDIO_STABLE
PLL_AUDIO_ST PLL_AUDIO_STABLE
ABLE
Normally in Software mode, after the power up and enable sequence for pll, arm pll will not be in stable
state immediately. This bit is used by software to monitor the locking status for pll. GPC mode do not
need to take care of this bit. Harfware will handle it automaticly.
28-25 Always set to zero (0).
— Always set to zero (0).
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Field Description
24 Reserved
—
23-15 Reserved
—
14 PLL_AUDIO_GATE
PLL_AUDIO_G PLL_AUDIO_GATE
ATE
There is a gate in top level to gate the pll output for power saving purpose,this field it to control this gate.
0 - No gate
1 - Gate the output
13 ENABLE_CLK
ENABLE_CLK Enable the clock output.
This field is used to align the software mode and GPC mode. The usage of this bit is to describe the last
PLL mode(enable or disable) before entering GPC mode. User need to make sure the pll state is
matching first Setpoint will be entered.
12-0 Reserved
—
15.9.4.17 PLL_AUDIO_SS_REGISTER (PLL_AUDIO_SS)
This register contains the AUDIO PLL spread spectrum controls
Refer to Spread Spectrum Parameters for more details.
15.9.4.17.1 Offset
Register Offset
PLL_AUDIO_SS 310h
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15.9.4.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABL
STE
W
P
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.17.3 Fields
Field Description
31-16 STOP
STOP Frequency change = stop/MFD*24MHz.
15 ENABLE
ENABLE This bit enables the spread spectrum modulation
0 - Disable Spread Spectrum. In this setting, the values for STEP and STOP are ignored
1 - Enable Spread Spectrum
14-0 STEP
STEP The max frequency change = step/MFD*24MHz.
15.9.4.18 PLL_AUDIO_DENOMINATOR_REGISTER
(PLL_AUDIO_DENOMINATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.18.1 Offset
Register Offset
PLL_AUDIO_DENOMINA 320h
TOR
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15.9.4.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
DENOM
W
Reset 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DENOM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
15.9.4.18.3 Fields
Field Description
31-30 Reserved
—
29-0 DENOM
DENOM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.19 PLL_AUDIO_NUMERATOR_REGISTER
(PLL_AUDIO_NUMERATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.19.1 Offset
Register Offset
PLL_AUDIO_NUMERAT 330h
OR
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15.9.4.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
NUM
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NUM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15.9.4.19.3 Fields
Field Description
31-30 Reserved
—
29-0 NUM
NUM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.20 PLL_AUDIO_DIV_SELECT_REGISTER
(PLL_AUDIO_DIV_SELECT)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.20.1 Offset
Register Offset
PLL_AUDIO_DIV_SELE 340h
CT
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15.9.4.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved PLL_AUDIO_DIV_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
15.9.4.20.3 Fields
Field Description
31-7 Reserved
—
6-0 PLL_AUDIO_DIV_SELECT
PLL_AUDIO_DI As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
V_SELECT And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.21 PLL_VIDEO_CTRL_REGISTER (PLL_VIDEO_CTRL)
The control register provides control for the VIDEO PLL.
15.9.4.21.1 Offset
Register Offset
PLL_VIDEO_CTRL 350h
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15.9.4.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_VIDEO_AI_BUSY
PLL_VIDEO_STABLE
PLL_VIDEO_CONTROL_MODE
PLL_VIDEO_COUNTER_CLR
R
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PLL_VIDEO_GATE
ENABLE_CLK
Reserved
Reserved
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.21.3 Fields
Field Description
31 pll_video_control_mode
PLL_VIDEO_C Enable mode
ONTROL_MOD
0 - Software Mode (Default)
E
1 - GPC Mode
30 pll_video_ai_busy
PLL_VIDEO_AI For this AI bridge register field, this bit is used along with AI bus. Function is for AI busy monitor.there will
_BUSY be a detail description on how to use it. For debug purpose. Reserved.
29 PLL_VIDEO_STABLE
PLL_VIDEO_ST PLL_VIDEO_STABLE
ABLE
Normally in Software mode, after the power up and enable sequence for pll, arm pll will not be in stable
state immediately. This bit is used by software to monitor the locking status for pll. GPC mode do not
need to take care of this bit. Harfware will handle it automaticly.
28-25 Always set to zero (0).
— Always set to zero (0).
24 pll_video_counter_clr
reserved
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Field Description
PLL_VIDEO_C
OUNTER_CLR
23-15 Reserved
—
14 PLL_VIDEO_GATE
PLL_VIDEO_GA PLL_VIDEO_GATE
TE
There is a gate in top level to gate the pll output for power saving purpose,this field it to control this gate.
0 - No gate
1 - Gate the output
13 ENABLE_CLK
ENABLE_CLK Enable the clock output.
This field is used to align the software mode and GPC mode. The usage of this bit is to describe the last
PLL mode(enable or disable) before entering GPC mode. User need to make sure the pll state is
matching first Setpoint will be entered.
12-0 Reserved
—
15.9.4.22 PLL_VIDEO_SS_REGISTER (PLL_VIDEO_SS)
This register contains the VIDEO PLL spread spectrum controls
Refer to Spread Spectrum Parameters for more details.
15.9.4.22.1 Offset
Register Offset
PLL_VIDEO_SS 360h
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15.9.4.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABL
STE
W
P
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.4.22.3 Fields
Field Description
31-16 STOP
STOP Frequency change = stop/MFD*24MHz.
15 ENABLE
ENABLE This bit enables the spread spectrum modulation
0 - Disable Spread Spectrum. In this setting, the values for STEP and STOP are ignored
1 - Enable Spread Spectrum
14-0 STEP
STEP .The max frequency change = step/MFD*24MHz.
15.9.4.23 PLL_VIDEO_DENOMINATOR_REGISTER
(PLL_VIDEO_DENOMINATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.23.1 Offset
Register Offset
PLL_VIDEO_DENOMINA 370h
TOR
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15.9.4.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
DENOM
W
Reset 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DENOM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
15.9.4.23.3 Fields
Field Description
31-30 Reserved
—
29-0 DENOM
DENOM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.24 PLL_VIDEO_NUMERATOR_REGISTER
(PLL_VIDEO_NUMERATOR)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.24.1 Offset
Register Offset
PLL_VIDEO_NUMERAT 380h
OR
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15.9.4.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
NUM
W
Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NUM
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15.9.4.24.3 Fields
Field Description
31-30 Reserved
—
29-0 NUM
NUM As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.4.25 PLL_VIDEO_DIV_SELECT_REGISTER
(PLL_VIDEO_DIV_SELECT)
As this AI interface PLL is used both in Software mode and GPC mode. This field is an
entry to GPC mode for the corresponding field.
15.9.4.25.1 Offset
Register Offset
PLL_VIDEO_DIV_SELE 390h
CT
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15.9.4.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved DIV_SELECT
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
15.9.4.25.3 Fields
Field Description
31-7 Reserved
—
6-0 DIV_SELECT
DIV_SELECT As this is AI interface PLL, there will be two modes support for this PLL, software mode and GPC mode.
And this file is providing the entry to the corresponding field in GPC mode.
15.9.5 Fractional PLL register descriptions
NOTE
The CCM Fractional PLL registers are accessed through the
Analog IP (AI) Interface.
15.9.5.1 FRACTIONAL_PLL memory map
frac_pll base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Fractional PLL Control Register (CTRL0) 32 RW 0000_0000
4 Fractional PLL Control Register (CTRL0_SET) 32 RW 0000_0000
8 Fractional PLL Control Register (CTRL0_CLR) 32 RW 0000_0000
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Chapter 15 Clock Controller Module (CCM)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
C Fractional PLL Control Register (CTRL0_TOG) 32 RW 0000_0000
10 Fractional PLL Spread Spectrum Control Register 32 RW 0000_0000
(SPREAD_SPECTRUM)
14 Fractional PLL Spread Spectrum Control Register 32 RW 0000_0000
(SPREAD_SPECTRUM_SET)
18 Fractional PLL Spread Spectrum Control Register 32 RW 0000_0000
(SPREAD_SPECTRUM_CLR)
1C Fractional PLL Spread Spectrum Control Register 32 RW 0000_0000
(SPREAD_SPECTRUM_TOG)
20 Fractional PLL Numerator Control Register (NUMERATOR) 32 RW 0000_0000
24 Fractional PLL Numerator Control Register (NUMERATOR_SET) 32 RW 0000_0000
28 Fractional PLL Numerator Control Register (NUMERATOR_CLR) 32 RW 0000_0000
2C Fractional PLL Numerator Control Register (NUMERATOR_TOG) 32 RW 0000_0000
30 Fractional PLL Denominator Control Register (DENOMINATOR) 32 RW 0000_0000
34 Fractional PLL Denominator Control Register 32 RW 0000_0000
(DENOMINATOR_SET)
38 Fractional PLL Denominator Control Register 32 RW 0000_0000
(DENOMINATOR_CLR)
3C Fractional PLL Denominator Control Register 32 RW 0000_0000
(DENOMINATOR_TOG)
15.9.5.2 Fractional PLL Control Register (CTRL0)
This register contains fractional pll control registers.
15.9.5.2.1 Offset
Register Offset Description
CTRL0 0h Fractional PLL Control Register
CTRL0_SET 4h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL0
CTRL0_CLR 8h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL0
CTRL0_TOG Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL0
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15.9.5.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POST_DIV_SEL
BIAS_SELEC
PLL_REG_E
BIAS_TRIM
DITHER_E
Reserved
Reserved
Reserved
Reserved
BYPAS
W
S
N
N
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HOLD_RING_OFF
ENABLE_ALT
POWERUP
DIV_SELEC
Reserved
Reserved
ENABL
W
E
T
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.5.2.3 Fields
Field Description
31-30 Reserved
—
29 BIAS_SELECT
BIAS_SELECT Selects which input bias current is expected by the PLL.
0 - Used in SoCs with a bias current of 10uA
1 - Used in SoCs with a bias current of 2uA
28 Reserved
—
27-25 Post Divide Select
POST_DIV_SEL Fractional PLL Post Divider Select (glitchless clock mux)
000 - Divide by 1
001 - Divide by 2
010 - Divide by 4
011 - Divide by 8
100 - Divide by 16
101 - Divide by 32
24-23 Reserved
—
22 PLL_REG_EN
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Chapter 15 Clock Controller Module (CCM)
Field Description
PLL_REG_EN Enables the internal PLL regulator.
21-19 BIAS_TRIM
BIAS_TRIM Not currently used.
18 Reserved
—
17 DITHER_EN
DITHER_EN Enables dither in the fractional modulator calculation.
0 - Disable Dither
1 - Enable Dither
16 BYPASS
BYPASS Byapss the PLL. Output is the PLL reference clock source
0 - No Bypass
1 - Bypass the PLL
15 ENABLE
ENABLE 0 - Disable the clock output
1 - Enable the clock output
14 POWERUP
POWERUP 0 - Power down the PLL
1 - Power Up the PLL
13 PLL Start up initialization
HOLD_RING_O This field should be set to 1 every time during PLL lock, and cleared after a certain delay.
FF
0 - Normal operation
1 - Initialize PLL start up
12-9 Reserved
—
8 ENABLE_ALT
ENABLE_ALT 0 - Disable the alternate clock output
1 - Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
7 Reserved
—
6-0 DIV_SELECT
DIV_SELECT This field controls the pll loop divider. Valid range for DIV_SELECT divider value: 27-54 decimal.
15.9.5.3 Fractional PLL Spread Spectrum Control Register
(SPREAD_SPECTRUM)
This register contains fractional pll spread spectrum control registers.
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15.9.5.3.1 Offset
Register Offset Description
SPREAD_SPECTRUM 10h Fractional PLL Spread Spectrum Control Register
SPREAD_SPECTRUM_ 14h Writing a 1 to a bit in this register sets the
SET corresponding bit in SPREAD_SPECTRUM
SPREAD_SPECTRUM_ 18h Writing a 1 to a bit in this register clears the
CLR corresponding bit in SPREAD_SPECTRUM
SPREAD_SPECTRUM_T 1Ch Writing a 1 to a bit in this register toggles the
OG corresponding bit in SPREAD_SPECTRUM
15.9.5.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
STOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ENABL
STE
W
P
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.5.3.3 Fields
Field Description
31-16 Stop
STOP Spread Spectrum Stop Register. Frequency change = step/MFD*24MHz.
15 Enable
ENABLE This bit enables the spread spectrum modulation.
14-0 Step
STEP Spread Spectrum Step The max frequency change = stop/MFD*24MHz.
15.9.5.4 Fractional PLL Numerator Control Register (NUMERATOR)
This register contains fractional pll numerator control registers.
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15.9.5.4.1 Offset
Register Offset Description
NUMERATOR 20h Fractional PLL Numerator Control Register
NUMERATOR_SET 24h Writing a 1 to a bit in this register sets the
corresponding bit in NUMERATOR
NUMERATOR_CLR 28h Writing a 1 to a bit in this register clears the
corresponding bit in NUMERATOR
NUMERATOR_TOG 2Ch Writing a 1 to a bit in this register toggles the
corresponding bit in NUMERATOR
15.9.5.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
NUM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NUM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.5.4.3 Fields
Field Description
31-30 Reserved
—
29-0 Numerator
NUM Numerator of PLL Fractional Loop Divider. Signed number.
15.9.5.5 Fractional PLL Denominator Control Register
(DENOMINATOR)
This register contains fractional pll denominator control registers.
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15.9.5.5.1 Offset
Register Offset Description
DENOMINATOR 30h Fractional PLL Denominator Control Register
DENOMINATOR_SET 34h Writing a 1 to a bit in this register sets the
corresponding bit in DENOMINATOR
DENOMINATOR_CLR 38h Writing a 1 to a bit in this register clears the
corresponding bit in DENOMINATOR
DENOMINATOR_TOG 3Ch Writing a 1 to a bit in this register toggles the
corresponding bit in DENOMINATOR
15.9.5.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
DENOM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DENOM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15.9.5.5.3 Fields
Field Description
31-30 Reserved
—
29-0 Denominator
DENOM Denominator of Fractional Loop Divider. Unsigned number.
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Chapter 16
Crystal Oscillator (XTALOSC)
16.1 Chip-specific XTALOSC information
Table 16-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
16.2 Overview
This block details the function and control of the oscillators on the chip.
This chip contains two Crystal Oscillators for clock generation - 24MHz, and 32KHz. In
addition, it also contains four RC oscillators - 48MHz, 32KHz, 16MHz, and 400MHz.
16.2.1 Block Diagram
The Crystal Oscillator block diagram is shown below.
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Functional Description
XTALI XTALO
R fb
Crystal
CL CL
C L load capacitance
R fb feedback resistor
Figure 16-1. Block diagram
The Rfb resistor is used in high gain mode. It is not used in low power mode.
16.3 Functional Description
This section details the oscillator clock sources to the chip.
16.3.1 Crystal Oscillators
The XTALOSC has two external crystal oscillators:
• 24MHz XTAL oscillator
• Primary clock source for all PLLs that generate the clocks for the CPU, Bus, and
high-speed interfaces.
• This clock source can be bypassed by the user, and replaced with another
external clock source.
• 32KHz XTAL oscillator
• Primary clock source for RTC as well as low-speed clock source for CCM/SRC/
GPC.
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Chapter 16 Crystal Oscillator (XTALOSC)
16.3.1.1 Bypass configuration (24MHz XTAL oscillator)
If it is desired to drive the chip with an external clock source, then it should be connected
to XTALI and OSC_24M_CTRL[BYPASS_EN] should be set to 1. XTALO should be
left externally floating.
16.3.2 RC Oscillators
The XTALOSC is supported by RC Oscillators (RCOSC). This chip has four RCOSC:
• 48MHz RC oscillator
• Generates the 24MHz clock source for the chip during start-up when the external
24MHz crystal is not ready.
• Alternative 24MHz clock source in low power mode when the crystal oscillator
is turned off, or in system which does not have any crystal oscillator.
• 32KHz RC oscillator
• 32KHz clock source for the chip during start-up when the external 32KHz
crystal is not ready.
• Alternative 32KHz clock source when the external 32KHz crystal oscillator is
not stable, or in system which does not have any crystal oscillator.
• 16MHz RC oscillator
• Clock source in low power mode.
• 400MHz RC oscillator
• Clock source during chip boot up before PLL is enabled or in low-power mode
when PLL is turned off.
NOTE
• The switch from external 32KHz XTALOSC to internal
32KHz RCOSC is controlled by hardware and occurs
automatically when the system detects a loss of 32KHz
crystal clock.
• To properly switch between 24MHz XTAL and 48MHz
internal RC, ensure the PLL is powered down before the
switch. After switching the clock, power up PLL.
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Functional Description
16.3.3 Analog IP (AI) Interface
The chip has various analog IP and components that are controlled via an AI interface.
The AI control registers are used to indirectly program the analog components on the AI
bus. The following table shows the AI interface registers relative to their respective
analog components and power domains.
Power Domain Analog Component AI Registers
SOC2PLL SYS_PLL1 (1G) VDDSOC2PLL_AI_CTRL_1G
AUDIO_PLL VDDSOC2PLL_AI_WDATA_1G
VIDEO_PLL VDDSOC2PLL_AI_RDATA_1G
VDDSOC2PLL_AI_CTRL_AUDIO
VDDSOC2PLL_AI_WDATA_AUDIO
VDDSOC2PLL_AI_RDATA_AUDIO
VDDSOC2PLL_AI_CTRL_VIDEO
VDDSOC2PLL_AI_WDATA_VIDEO
VDDSOC2PLL_AI_RDATA_VIDEO
SOC PHY LDO VDDSOC_AI_CTRL
VDDSOC_AI_WDATA
VDDSOC_AI_RDATA
PMU_LDO_PLL
LPSR Bandgap VDDLPSR_AI_CTRL
Tempsensor VDDLPSR_AI_WDATA
RCOSC_400M VDDLPSR_AI_RDATA_REFTOP
PMU_REF_CTRL
VDDLPSR_AI400M_CTRL
VDDLPSR_AI400M_WDATA
VDDLPSR_AI400M_RDATA
VDDLPSR_AI_RDATA_TMPSNS
Follow the steps below to perform register accesses through the AI interface.
Steps to perform a write operation of an analog component's AI interface:
1. Write *AI_CTRL register
• Set RWB value to 0
• Set ADDR value to the analog component's relative AI control register to be
accessed
2. Write *AI_WDATA
• Set Data[31:0] value to the analog component's relative AI control register value
to be written
3. Write *CTRL IP Toggle
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Chapter 16 Crystal Oscillator (XTALOSC)
• Set TOGGLE value to 1 in the bit position for the respective analog component.
The toggle will initiate the write sequence.
Steps to perform a read operation of an analog component's AI interface:
1. Write *AI_CTRL register
• Set RWB value to 1
• Set ADDR value to the analog component's relative AI control register to be
accessed
2. Write *CTRL IP Toggle
• Set TOGGLE value to 1 in the bit position for the respective analog component.
The toggle will initiate the read sequence
3. Read *CTRL
• Poll this register until the respective analog component's busy bit is low,
indicating the read transaction has completed.
4. Read *AI_RDATA
• Read Data[31:0]. The contents of the Read Data register is the value of the
analog component's respective AI register's contents.
NOTE
Varying IP will have a corresponding identical toggle bit
NOTE
For PLL operations, follow the PLL enable sequence first.
16.4 External Signals
The table found here describes the external signals of XTALOSC:
Table 16-2. XTALOSC External Signals
Signal Description Pad Mode Direction
RTC_XTALI Real-time clock crystal RTC_XTALI No muxing I
oscillator input
RTC_XTALO Real-time clock crystal RTC_XTALO No muxing O
oscillator output
XTALI Crystal oscillator input XTALI No muxing I
signal
XTALO Crystal oscillator output XTALO No muxing O
signal
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Memory Map and register definition
16.5 Memory Map and register definition
This section includes the module memory map and detailed descriptions of all registers.
NOTE
For related IPS Domain Slot control, please see IPS Domain
Registers in Power Management Unit (PMU) chapter.
16.5.1 OSC register descriptions
16.5.1.1 OSC memory map
osc base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
10 48MHz RCOSC Control Register (OSC_48M_CTRL) 32 RW 0179_01F2
20 24MHz OSC Control Register (OSC_24M_CTRL) 32 RW 0000_0080
40 400MHz RCOSC Control0 Register (OSC_400M_CTRL0) 32 RW 0000_0000
50 400MHz RCOSC Control1 Register (OSC_400M_CTRL1) 32 RW 0000_0001
60 400MHz RCOSC Control2 Register (OSC_400M_CTRL2) 32 RW 0000_0000
C0 16MHz RCOSC Control Register (OSC_16M_CTRL) 32 RW 0000_0007
16.5.1.2 48MHzRCOSC Control Register (OSC_48M_CTRL)
This register is used to control the 48MHz RC oscillator.
16.5.1.2.1 Offset
Register Offset
OSC_48M_CTRL 10h
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16.5.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RC_48M_DIV2_CONTROL_MODE
RC_48M_CONTROL_MODE
RC_48M_DIV2_EN
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
TEN
W
Reset 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0
16.5.1.2.3 Fields
Field Description
31 48MHzRCOSC Control Mode
RC_48M_CONT This field selects between GPC mode and Software mode
ROL_MODE
0 - Software mode (default)
1 - GPC mode (Setpoint)
30 RCOSC_48M_DIV2 Control Mode
RC_48M_DIV2_ This field selects between GPC mode and Software mode
CONTROL_MO
0 - Software mode (default)
DE
1 - GPC mode (Setpoint)
29-25 Always set to zero
—
24 RCOSC_48M_DIV2 Enable
RC_48M_DIV2_ This field enables/disables the 24MHz clock sourced from 48MHz RCOSC
EN
0 - Disable
1 - Enable
23-2 Reserved
—
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Field Description
1 48MHzRCOSC Enable
TEN This field powers up or powers down the 48MHz RCOSC
0 - Power down
1 - Power up
0 Reserved
—
16.5.1.3 24MHz OSC Control Register (OSC_24M_CTRL)
This register is used to control the 24MHz Oscillator.
16.5.1.3.1 Offset
Register Offset
OSC_24M_CTRL 20h
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Chapter 16 Crystal Oscillator (XTALOSC)
16.5.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSC_24M_STABLE
OSC_24M_CONTROL_MODE
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSC_COMP_MODE
OSC_24M_GATE
BYPASS_CLK
BYPASS_E
Reserved
Reserved
OSC_E
LP_E
W
N
N
N
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
16.5.1.3.3 Fields
Field Description
31 24MHz OSC Control Mode
OSC_24M_CON This field selects between GPC mode and Software mode
TROL_MODE
0 - Software mode (default)
1 - GPC mode (Setpoint)
30 24MHz OSC Stable
OSC_24M_STA This field indicates whether 24MHzOSC is stable (24MHz OSC will not be stable the time it is enabled)
BLE
0 - Not Stable
1 - Stable
29-8 Always set to zero
—
7 24MHz OSC Gate Control
OSC_24M_GAT This field gates the 24MHz OSC output for saving power
E
0 - Not Gated
1 - Gated
6-5 Reserved
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Field Description
—
4 24MHzOSC Enable
OSC_EN This field enables the 24MHz XTALOSC
0 - Disable
1 - Enable
3 24MHz OSC Comparator Mode
OSC_COMP_M This field selects the ac-coupling comparator operation-mode
ODE
0 - Single-ended mode (default)
1 - Differential mode (test mode)
2 24MH OSC Low-Power Mode Enable
LP_EN 0 - High Gain mode (HP)
1 - Low-power mode (LP)
1 24MHz OSC Bypass Enable
BYPASS_EN Enable signal for external bypass clock (mostly connect to XTAL directly in SOC level). Users can use
this filed to enable an external source of XTAL.
0 - Disable
1 - Enable
0 24MHz OSC Bypass Clock
BYPASS_CLK External Bypass Clock from pad (1.8v)
16.5.1.4 400MHz RCOSC Control0 Register (OSC_400M_CTRL0)
16.5.1.4.1 Offset
Register Offset
OSC_400M_CTRL0 40h
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Chapter 16 Crystal Oscillator (XTALOSC)
16.5.1.4.2 Diagram
Bits 31
OSC400M_AI_BUSY 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.1.4.3 Fields
Field Description
31 400MHz OSC AI BUSY
OSC400M_AI_B This field is associated with AI busy monitor function in AI bus. Please see 'Analog IP (AI) Interface' topic
USY for more details.
30-0 Always set to zero
—
16.5.1.5 400MHz RCOSC Control1 Register (OSC_400M_CTRL1)
This register provides the controls for clock gate, power down, and 400MHz RCOSC
mode selects.
16.5.1.5.1 Offset
Register Offset
OSC_400M_CTRL1 50h
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16.5.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RC_400M_CONTROL_MODE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKGATE_400MEG
Reserved
Reserved
Reserved
PWD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
16.5.1.5.3 Fields
Field Description
31 rc_400m_control_mode
RC_400M_CON This field selects between GPC mode and Software mode
TROL_MODE
0 - Software mode (default)
1 - GPC mode (Setpoint)
30-12 Always set to zero
—
11-3 Always set to zero
—
2 Reserved
—
1 Clock gate control for 400MHz RCOSC
CLKGATE_400 0 - Not Gated
MEG
1 - Gated
0 Power down control for 400MHz RCOSC
PWD 400MHz RCOSC can be powered down directly with this bit. There is no need to follow AI bus sequence
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Chapter 16 Crystal Oscillator (XTALOSC)
Field Description
0 - No Power down
1 - Power down
16.5.1.6 400MHz RCOSC Control2 Register (OSC_400M_CTRL2)
This register provides the OSC tune value and clock enable control used for HW mode.
16.5.1.6.1 Offset
Register Offset
OSC_400M_CTRL2 60h
16.5.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
OSC_TUNE_VAL Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE_CLK
TUNE_BYP
Reserved
Reserved
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.1.6.3 Fields
Field Description
31-24 Oscillator Tune Value
OSC_TUNE_VA These bits determine the frequency of oscillator when tuning is not enabled. Frequency varies with PVT.
L
0 - Lowest frequency
255 - Highest frequency
23-15 Always set to zero
—
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Memory Map and register definition
Field Description
14-12 Always set to zero
—
11 Always set to zero
—
10 Bypass tuning logic
TUNE_BYP 0 - Use the output of tuning logic to run the oscillator
1 - Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
9-8 Always set to zero
—
7-1 Always set to zero
—
0 Clock enable
ENABLE_CLK This bit is used for the switching between Software mode and GPC mode. ENABLE_CLK is to indicate
the GPC mode, the last Software mode RC400M state. It must be programed correspondingly.
0 - Clock is disabled before entering GPC mode
1 - Clock is enabled before entering GPC mode
16.5.1.7 16MHz RCOSC Control Register (OSC_16M_CTRL)
This register is used to control the 16MHz RC oscillator.
NOTE
The EN_IRC4M16M bit is used to disable/kill the output clocks
while keeping the oscillator working. The oscillator should be
disabled before powering it down.
16.5.1.7.1 Offset
Register Offset
OSC_16M_CTRL C0h
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16.5.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RC_16M_CONTROL_MODE
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOURCE_SEL_16M
EN_POWER_SAV
EN_IRC4M16M
Reserved
Reserved
Reserved
Reserved
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
16.5.1.7.3 Fields
Field Description
31 Control Mode for 16MHz Oscillator
RC_16M_CONT This field selects between GPC mode and Software mode
ROL_MODE
0 - Software mode (default)
1 - GPC mode (Setpoint)
30 Reserved
—
29-9 Always set to zero
—
8 Source select
SOURCE_SEL_ This is the source select for 16MHz RC Oscillator. The user can select between the 16MHz RCOSC or
16M 24MHz OSC.
0 - 16MHz Oscillator
1 - 24MHz Oscillator
7-4 Reserved
—
3 Power Save Enable
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Field Description
EN_POWER_S Enable the power save mode function at 16MHz
AVE
0 - Disable
1 - Enable
2 Reserved
-
1 Enable Clock Output
EN_IRC4M16M This field enables clock output for 16MHz RCOSC (rc4m_en_irc4M16M_1p8v)
0 - Disable
1 - Enable
0 Reserved
—
16.5.2 OSC_RC_400M register descriptions
16.5.2.1 OSC_RC_400M memory map
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Control Register 0 (CTRL0) 32 RW 0000_0000
4 Control Register 0 (CTRL0_SET) 32 RW 0000_0000
8 Control Register 0 (CTRL0_CLR) 32 RW 0000_0000
C Control Register 0 (CTRL0_TOG) 32 RW 0000_0000
10 Control Register 1 (CTRL1) 32 RW 0000_0000
14 Control Register 1 (CTRL1_SET) 32 RW 0000_0000
18 Control Register 1 (CTRL1_CLR) 32 RW 0000_0000
1C Control Register 1 (CTRL1_TOG) 32 RW 0000_0000
20 Control Register 2 (CTRL2) 32 RW 0000_0000
24 Control Register 2 (CTRL2_SET) 32 RW 0000_0000
28 Control Register 2 (CTRL2_CLR) 32 RW 0000_0000
2C Control Register 2 (CTRL2_TOG) 32 RW 0000_0000
30 Control Register 3 (CTRL3) 32 RW 0000_0000
34 Control Register 3 (CTRL3_SET) 32 RW 0000_0000
38 Control Register 3 (CTRL3_CLR) 32 RW 0000_0000
3C Control Register 3 (CTRL3_TOG) 32 RW 0000_0000
50 Status Register 0 (STAT0) 32 RO 0000_0000
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
54 Status Register 0 (STAT0_SET) 32 RO 0000_0000
58 Status Register 0 (STAT0_CLR) 32 RO 0000_0000
5C Status Register 0 (STAT0_TOG) 32 RO 0000_0000
60 Status Register 1 (STAT1) 32 RO 0000_0000
64 Status Register 1 (STAT1_SET) 32 RO 0000_0000
68 Status Register 1 (STAT1_CLR) 32 RO 0000_0000
6C Status Register 1 (STAT1_TOG) 32 RO 0000_0000
70 Status Register 2 (STAT2) 32 RO 0000_0000
74 Status Register 2 (STAT2_SET) 32 RO 0000_0000
78 Status Register 2 (STAT2_CLR) 32 RO 0000_0000
7C Status Register 2 (STAT2_TOG) 32 RO 0000_0000
16.5.2.2 Control Register 0 (CTRL0)
This register contains analog control bits.
16.5.2.2.1 Offset
Register Offset Description
CTRL0 0h Control Register 0
CTRL0_SET 4h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL0
CTRL0_CLR 8h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL0
CTRL0_TOG Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL0
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16.5.2.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_CLK_DIV
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.2.3 Fields
Field Description
31-30 Reserved
—
29-24 Divide value for ref_clk to generate slow_clk (used inside this IP)
REF_CLK_DIV 0: divide by 1
1-63: corresponding division by 1-63.
The recommended divide value is 24.
23-0 Reserved
— This read-only field is reserved and always has the value 0.
16.5.2.3 Control Register 1 (CTRL1)
This register contains analog control bits.
16.5.2.3.1 Offset
Register Offset Description
CTRL1 10h Control Register 1
CTRL1_SET 14h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL1
CTRL1_CLR 18h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL1
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Register Offset Description
CTRL1_TOG 1Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL1
16.5.2.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TARGET_COUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved HYST_PLUS Reserved HYST_MINUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.3.3 Fields
Field Description
31-16 Target count for the fast clock
TARGET_COU This field is used to set the desired target for the fast clock (osc_out_400m). Value in no. of clock cycles
NT of the fast_clk (osc_out_400m) per divided ref_clk.
15-12 Reserved
— This read-only field is reserved and always has the value 0.
11-8 Positive hysteresis value for the tuned clock
HYST_PLUS Set this value after the clock is tuned. Value in no. of clock cycles of the fast clock(osc_out_400m).
7-4 Reserved
—
3-0 Negative hysteresis value for the tuned clock
HYST_MINUS Set this value after the clock is tuned. Value in no. of clock cycles of the fast clock(osc_out_400m).
16.5.2.4 Control Register 2 (CTRL2)
This register contains analog control bits.
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16.5.2.4.1 Offset
Register Offset Description
CTRL2 20h Control Register 2
CTRL2_SET 24h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL2
CTRL2_CLR 28h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL2
CTRL2_TOG 2Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL2
16.5.2.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
OSC_TUNE_VAL Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TUNE_START
TUNE_BYP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TUNE_E
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.4.3 Fields
Field Description
31-24 Program the oscillator frequency
OSC_TUNE_VA These bits determine the frequency of oscillator when tuning is not enabled
L
Frequency varies with PVT.
0 - Lowest frequency.
255 - Highest frequency.
23-15 Reserved
—
14 Start/Stop tuning
TUNE_START 0 - Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL
1 - Start tuning
13 Reserved
— This read-only field is reserved and always has the value 0.
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Field Description
12 Freeze/Unfreeze the tuning value
TUNE_EN 0 - Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value
1 - Unfreezes and continues the tuning operation
11 Reserved
— This read-only field is reserved and always has the value 0.
10 Bypass the tuning logic
TUNE_BYP 0 - Use the output of tuning logic to run the oscillator
1 - Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
9 Reserved
— This read-only field is reserved and always has the value 0.
8 Reserved
—
7-0 Reserved
— This read-only field is reserved and always has the value 0.
16.5.2.5 Control Register 3 (CTRL3)
This register contains analog control bits.
16.5.2.5.1 Offset
Register Offset Description
CTRL3 30h Control Register 3
CTRL3_SET 34h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL3
CTRL3_CLR 38h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL3
CTRL3_TOG 3Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL3
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16.5.2.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
COUNT_1M_CLK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX_1M_CLK
EN_1M_CLK
Reserved
Reserved
Reserved
CLR_ER
W
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.5.3 Fields
Field Description
31-16 Count for the locked clk_1m_out
COUNT_1M_CL This bit field is used to set the desired target for the locked clk_1m_out. Value in no. of clock cycles of the
K fast_clk (osc_out_400m) per divided ref_clk.
NOTE: This value should be 4 to 8 counts less than CTRL1[TARGET_COUNT] -
CTRL1[HYST_MINUS].
15-11 Reserved
— This read-only field is reserved and always has the value 0.
10 Select free/locked 1MHz output
MUX_1M_CLK 0 - Select free-running 1MHz to be put out on clk_1m_out
1 - Select locked 1MHz to be put out on clk_1m_out
9 Reserved
— This read-only field is reserved and always has the value 0.
8 Enable 1MHz output Clock
EN_1M_CLK Though the name is EN_1M_CLK, it's function is inverted in analog to make this clock enabled by default.
This clock is used to keep time.
0 - Enable the output (clk_1m_out)
1 - Disable the output (clk_1m_out)
7-1 Reserved
—
0 Clear the error flag CLK1M_ERR
CLR_ERR 0 - No effect
1 - Clears the error flag CLK1M_ERR in status register STAT0
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Chapter 16 Crystal Oscillator (XTALOSC)
16.5.2.6 Status Register 0 (STAT0)
This register contains analog status bits.
16.5.2.6.1 Offset
Register Offset Description
STAT0 50h Status Register 0
STAT0_SET 54h Writing a 1 to a bit in this register sets the
corresponding bit in STAT0
STAT0_CLR 58h Writing a 1 to a bit in this register clears the
corresponding bit in STAT0
STAT0_TOG 5Ch Writing a 1 to a bit in this register toggles the
corresponding bit in STAT0
16.5.2.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK1M_ERR
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.6.3 Fields
Field Description
31-1 Reserved
— This read-only field is reserved and always has the value 0.
0 Error flag for clk_1m_locked
CLK1M_ERR Flag indicates that the count_1m count wasn't reached within one divided ref_clk period.
0 - No effect
1 - The count value has been reached within one divided ref_clk period
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16.5.2.7 Status Register 1 (STAT1)
This register contains analog status bits.
16.5.2.7.1 Offset
Register Offset Description
STAT1 60h Status Register 1
STAT1_SET 64h Writing a 1 to a bit in this register sets the
corresponding bit in STAT1
STAT1_CLR 68h Writing a 1 to a bit in this register clears the
corresponding bit in STAT1
STAT1_TOG 6Ch Writing a 1 to a bit in this register toggles the
corresponding bit in STAT1
16.5.2.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CURR_COUNT_VAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.7.3 Fields
Field Description
31-16 Current count for the fast clock
CURR_COUNT This field holds the current count during the tuning process. This value converges to TARGET_COUNT
_VAL as tuning progresses.
15-0 Reserved
— This read-only field is reserved and always has the value 0.
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Chapter 16 Crystal Oscillator (XTALOSC)
16.5.2.8 Status Register 2 (STAT2)
This register contains analog status bits.
16.5.2.8.1 Offset
Register Offset Description
STAT2 70h Status Register 2
STAT2_SET 74h Writing a 1 to a bit in this register sets the
corresponding bit in STAT2
STAT2_CLR 78h Writing a 1 to a bit in this register clears the
corresponding bit in STAT2
STAT2_TOG 7Ch Writing a 1 to a bit in this register toggles the
corresponding bit in STAT2
16.5.2.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CURR_OSC_TUNE_VAL
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16.5.2.8.3 Fields
Field Description
31-24 Current tuning value used by oscillator
CURR_OSC_TU This bit field holds the current OSC_TUNE_VAL value which is being used by the oscillator. This value
NE_VAL changes as the tuning progresses.
23-0 Reserved
— This read-only field is reserved and always has the value 0.
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Chapter 17
Power Management Unit (PMU)
17.1 Chip-specific PMU information
Table 17-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
17.2 Overview
The Power Management Unit (PMU) is designed to simplify the external power interface.
17.2.1 Block Diagram
The power architecture of the chip is illustrated in the figure below, which shows the
typical use case of a single 3.3V power supply and a coin cell battery. Depending on the
application, different power supply schemes can apply (e.g. DCDC bypassed).
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Functional Description
3.3V
DCDC_IN
DCDC_ANA
DCDC
DCDC_DIG
VDDA_1P8_IN
VDDA_SOC_IN
SOC Domain LPSR Domain
VDD_LPSR_IN
Cortex-M7 LDO_LPSR_ANA
32KB I$ 32KB D$ VDD_LPSR_ANA
512KB TCM
USB, Ethernet, LDO_LPSR_DIG
SD/eMMC, Audio VDD_LPSR_DIG
LCD, CSI, Temperature
PXP, GC355 Sensor
SOC (AlwaysON) RC OSCs
Cortex-M4
LDO_PLL PLLs 16KB D$ 16KB I$
VDDA_1P0 256KB TCM
eFuse
VDDA_MIPI_1P8
VDDA_MIPI_1P0 MIPI PHY LPSR
Peripherals
VDDA_USB_1P8
VDDA_USB_3P3 USB PHY x2
GPIO PADs NVCC_LPSR
VDDA_ADC_3P3 ADC x2
VDDA_ADC_1P8
DAC SNVS Domain VDD_SNVS_IN Coin
LDO_SNVS_ANA
VDD_SNVS_ANA
Cell
ACMP x4
NVCC_EMC1 GPIO PADs 4KB RAM LDO_SNVS_DIG
NVCC_EMC2 VDD_SNVS_DIG
GPIO PADs
NVCC_GPIO GPIO PADs DryICE
NVCC_DISP1 GPIO PADs 32KHz XTAL
NVCC_DISP2 GPIO PADs 32KHz RC OSC
NVCC_SD1 GPIO PADs SNVS LP
NVCC_SD2 GPIO PADs GPIO PADs NVCC_SNVS
Figure 17-1. Power System Overview
17.2.2 Features
The PMU has the following components integrated for power management:
• One DCDC to generate core power supply, with dynamic voltage scaling capability
• LDOs to generate power for internal logics
• Multiple Power Switches for sophisticated power mode management
17.3 Functional Description
The PMU operations are detailed in the sections below.
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Chapter 17 Power Management Unit (PMU)
17.3.1 Well-Bias configuration
The well-bias configuration is shown below. The NWELL is an adaptive, quiescent
consumption, negative voltage output, switched regulator. The PWELL is an adaptive,
quiescent consumption, positive voltage tracker, switched regulator. The NWELL and
PWELL regulators are biased together, as either FBB or RBB, not both at the same time.
Both regulators are connected to RVT and LVT transistors.
• For low-voltage threshold (LVT), FBB is supported. It provides enhanced SoC core
performance at a cost of higher leakage.
• For regular-voltage threshold (RVT), RBB is supported. It reduces SoC core
consumption with lower leakage.
When the system enters low-power mode, it normally decreases the power supply
voltage, then turns on RBB. The VDDA_SOC_IN and VDD_LPSR_ANA supplies need
to be settled before the well-bias regulator is turned on (WB_EN). Both supplies need to
be settled for FBB as well.
LDO_LPSR_ANA
VDD_LPSR_ANA
LVT
PWELL wbias pwr
switch
CM7
REGULATOR
LDO_LSPR_DIG
VDD_LPSR_DIG RVT RBB
wbias pwr
Well-bias switch
OR LPSR
Control
RVT RBB
DCDC_DIG wbias pwr
DCDC NWELL SOC
VDDA_SOC_IN switch
REGULATOR
MU_BIAS_CTRL2[WB_PWR_SW_EN_1P8]
MU_BIAS_CTRL[WB_VDD_SEL_1P8]
PMU_BIAS_CTRL2[WB_EN] MU_BIAS_CTRL[WB_CFG_1P8]
MU_BIAS_CTRL2[WB_OK]
Figure 17-2. Well-Biasing Block Diagram
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Functional Description
NOTE
The VDD selection (WB_VDD_SEL_1P8) depends on whether
SoC RBB or LPSR RBB is set. This selection needs to be done
before enabling well-bias.
17.3.1.1 Body Biasing (BB)
Forward Body Biasing (FBB) and Reverse Body Biasing (RBB) areis implemented to
boost performance and reduce power. The implementation of BB in each power domain
are listed below:
• FBB is implemented in Cortex-M7 Platform to achieve higher performance
• RBB is implemented in LPSR and SoC power domains to reduce power consumption
in low-power modes
FBB
FBB
Charge Wbias PWR Cortex-M7
Cortex-M7
Charge Pump Wbias PWRSW
Pump SW Platform
Platform
RBB
RBB
Wbias PWR
Wbias PWRSW OR LPSR
LPSRMIX
SW
RBB
RBB
Wbias PWR SoC
Wbias PWRSW SoC
SW WAKEUPMIX
Figure 17-3. Body Biasing Diagram
NOTE
Software must ensure that FBB and RBB are not enabled
simultaneously, only one can be used at a time.
17.3.2 Control Mode
The PMU supports two control modes that can be configured by x_CONTROL_MODE
fields. These two modes are Sofware control mode and Hardware control mode.
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Chapter 17 Power Management Unit (PMU)
• The Software control mode enables LDOs, switches, and bandgap to be fully
configured by registers.
• The Hardware control mode enables the ON/OFF of the LDOs, LDO bypass
switches, and bandgap to be configured by GPC Setpoints. The voltage of
LPSR_DIG and operation modes of LDOs (lp_mode), are also configured by GPC
Setpoints. The other settings remain unchanged.
The following table shows the functions controlled by GPC:
Table 17-2. Functions controlled by GPC
IP ON/OFF Operation Tracking Mode Bypass Mode Standby Mode Voltage
Control Mode (Switch ON/ (Low Power Control
OFF) Mode)
LDO_PLL Y - - - Y -
LPSR_ANA - HP/LP Y Y HP/LP -
LPSR_DIG - HP/LP Y Y HP/LP Y
REFTOP Y - - - Y -
(Bandgap)
FBB_M7 Y - - - Y -
RBB_SOC Y - - - Y -
RBB_LPSR Y - - - Y -
Each time there is a change in Setpoint, there will be two steps of requests - voltage down
and voltage up. The new target is compared with the current setting to check if the
voltage change should happen at each step. When there is a Setpoint change request, the
'done' signals will be generated until all the settings have been changed. When there is a
standby in request, the acknowledge signal will be held high until the set modules are put
into low-power mode. When there is standby out request, the acknowledge signal will
held high until the modules are brought back from low power mode.
17.3.2.1 ON/OFF Control Mode
• The ON/OFF control for LDOs:
• When LDO_x_CONTROL_MODE = 0 (Software control mode)
LD0_x_ENABLE controls the ON/OFF
• When LDO_x_CONTROL_MODE = 1 (Hardware / GPC control mode) system
is in Setpoint n, and LDO_x_ENABLE_SP[ON_OFF_SETPOINTn] controls the
ON/OFF
• Biasing ON/OFF:
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Functional Description
• When yBB_x_CONTROL_MODE = 0 (Software control mode)
yBB_x_ENABLE controls the ON/OFF of the Biasing Circuit
• When yBB_x_CONTROL_MODE = 1 (Hardware / GPC control mode) system
is in Setpoint n, and yBB_x_ENABLE_SP[ON_OFF_SETPOINTn] controls the
ON/OFF of the biasing circuit
• Bandgap ON/OFF Control:
• When REF_CONTROL_MODE = 0 (Software control mode) REF_ENABLE
controls the ON/OFF of the bandgap
• When REF_CONTROL_MODE = 1 (Hardware / GPC control mode) system is
in Setpoint n, and BANDGAP_ENABLE_SP[ON_OFF_SETPOINTn] controls
the ON/OFF of the bandgap
NOTE
Software mode supports flexible control, but care and
consideration should be followed in regards to analog
dependecies and power structure sequences. In GPC mode,
everything is handled precisely by hardware.
17.3.2.2 Low Power Control Mode
GPC will wait for an acknowledgement to be asserted before it continues to the next step.
When standby sequence is initiated, GPC will wait for another acknowledgement to be
asserted before it continues to the next step. When standby exit sequence is completed,
LDO enters the low-power mode based on the following condition:
• When LDO_x_CONTROL_MODE = 0 (Software control mode),
LDO_x_LP_MODE register is set
• When LDO_x_CONTROL_MODE = 1 (Hardware / GPC control mode) system is in
Setpoint n, and LDO_x_LP_MODE_SP[LP_MODE_SETPOINTn] is set to 1
The LDOs can also enter low power mode based on following condition:
• When LDO_x_CONTROL_MODE = 0 (Software control mode) standby_request
signal is asserted, and LDO_x_STBY_EN register is set to 1 (0 by default)
• When LDO_x_CONTROL_MODE = 1 (Hardware / GPC control mode)
standby_request signal is asserted, and system in Setpoint n, and
LDO_x_STBY_EN_SP[LP_MODE_SETPOINT] is set to 1
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Chapter 17 Power Management Unit (PMU)
17.3.2.3 Tracking Mode
This mode is supported on LDO_LPSR_ANA and LDO_LPSR_DIG domains. When
enabled on LDO_LPSR_DIG, it's output will track the VDD_SOC to confirm that the
LPSR_DIG voltage is same as the VDD_SOC when bypass mode is enabled. When
enabled on LDO_LPSR_ANA, its output will track the VDDA_1P8 to confirm the
LPSR_ANA voltage is same as the VDDA_1P8 when bypass mode is enabled.
17.3.2.4 Bypass Mode
When bypass mode is enabled on LDO_LPSR_DIG, it's output will be shorted with
VDD_SOC, and the LPSR_DIG domain will be supplied by DCDC_DIG. When bypass
mode is enabled on LDO_LPSR_ANA, it's output will be shorted with VDDA_1P8, and
the LPSR_ANA domain will be supplied by DCDC_ANA.
NOTE
When tracking is enabled, force low power mode to disable.
Tracking enable should happen before bypass enable and
Tracking disable should happen after bypass disable.
17.3.2.5 Setpoint Change Sequence
The following sequence should be followed to change the LDO_DIG voltage setpoint
(Voltage Down):
• The Setpoint voltage down request is asserted by GPC
• The current Setpoint setting is captured, after detecting the rising edge offset point of
voltage down request
• The current LDO voltage is compared with the new setting
• If the new setting is lower, the new settings are applied. If the new setting is higher,
the request is ignored.
• The setpoint voltage down done signal is asserted
The following sequence should be followed to change the LDO_DIG voltage setpoint
(Voltage Up):
• The setpoint voltage up request is asserted by GPC
• The current Setpoint setting after detecting the rising edge offset point of voltage up
request
• The current LDO voltage is compared with the new setting
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External Signals
• If the new setting is higher, the new settings are applied. If the new setting is lower,
the request is ignored.
• The setpoint voltage up done signal is asserted
17.3.2.6 Well Bias Enable Sequence
The following sequence should be followed to enable Well Bias:
• Set well bias setting(voltage, LVT/RVT)
• PMU_BIAS_CTRL[1] is set to 1 (NWELL is configured to supply and LVT
CORE,FBB)
• PMU_BIAS_CTRL[12] is set to 1 to enable FBB correctly
• All the other bits are set to 0
• Turn on CM7 FBB switch, and well bias (must be executed in the same step)
• PMU_BIAS_CTRL2[WB_EN] is set to 1
• PMU_BIAS_CTRL2[WB_PWR_SW_EN_1P8] is set to 1
• All other bits set to 0
• Check the PMU_BIAS_CTRL2[WB_OK] bit to confirm Well Bias is stable
17.3.3 Clocks
The PMU doesn't have any relevant application clock sources.
17.4 External Signals
Please see the supply contact assignments in the datasheet for more information.
17.5 Memory Map and register definition
This section includes the PMU module memory map and detailed descriptions of all
registers.
17.5.1 PMU register descriptions
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Chapter 17 Power Management Unit (PMU)
17.5.1.1 PMU memory map
PMU base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
500 PMU_LDO_PLL_REGISTER (PMU_LDO_PLL) 32 RW 0000_0001
550 PMU_BIAS_CTRL_REGISTER (PMU_BIAS_CTRL) 32 RW 0000_0000
560 PMU_BIAS_CTRL2_REGISTER (PMU_BIAS_CTRL2) 32 RW 0000_0000
570 PMU_REF_CTRL_REGISTER (PMU_REF_CTRL) 32 RW 0000_0000
580 PMU_POWER_DETECT_CTRL_REGISTER (PMU_POWER_DE 32 RW 0000_0000
TECT_CTRL)
600 LDO_PLL_ENABLE_SP_REGISTER (LDO_PLL_ENABLE_SP) 32 RW 0000_0000
610 LDO_LPSR_ANA_ENABLE_SP_REGISTER (LDO_LPSR_ANA_ 32 RW 0000_0000
ENABLE_SP)
620 LDO_LPSR_ANA_LP_MODE_SP_REGISTER (LDO_LPSR_ANA_ 32 RW 0000_0000
LP_MODE_SP)
630 LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER (LDO_LPSR_ 32 RW 0000_0000
ANA_TRACKING_EN_SP)
640 LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER (LDO_LPSR_ANA 32 RW 0000_0000
_BYPASS_EN_SP)
650 LDO_LPSR_ANA_STBY_EN_SP_REGISTER (LDO_LPSR_ANA_ 32 RW 0000_0000
STBY_EN_SP)
660 LDO_LPSR_DIG_ENABLE_SP_REGISTER (LDO_LPSR_DIG_ENA 32 RW 0000_0000
BLE_SP)
670 LDO_LPSR_DIG_TRG_SP0_REGISTER (LDO_LPSR_DIG_TRG_ 32 RW 0000_0000
SP0)
680 LDO_LPSR_DIG_TRG_SP1_REGISTER (LDO_LPSR_DIG_TRG_ 32 RW 0000_0000
SP1)
690 LDO_LPSR_DIG_TRG_SP2_REGISTER (LDO_LPSR_DIG_TRG_ 32 RW 0000_0000
SP2)
6A0 LDO_LPSR_DIG_TRG_SP3_REGISTER (LDO_LPSR_DIG_TRG_ 32 RW 0000_0000
SP3)
6B0 LDO_LPSR_DIG_LP_MODE_SP_REGISTER (LDO_LPSR_DIG_ 32 RW 0000_0000
LP_MODE_SP)
6C0 LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER (LDO_LPSR_ 32 RW 0000_0000
DIG_TRACKING_EN_SP)
6D0 LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER (LDO_LPSR_DIG_ 32 RW 0000_0000
BYPASS_EN_SP)
6E0 LDO_LPSR_DIG_STBY_EN_SP_REGISTER (LDO_LPSR_DIG_ 32 RW 0000_0000
STBY_EN_SP)
6F0 BANDGAP_ENABLE_SP_REGISTER (BANDGAP_ENABLE_SP) 32 RW 0000_0000
700 FBB_M7_ENABLE_SP_REGISTER (FBB_M7_ENABLE_SP) 32 RW 0000_0000
710 RBB_SOC_ENABLE_SP_REGISTER (RBB_SOC_ENABLE_SP) 32 RW 0000_0000
720 RBB_LPSR_ENABLE_SP_REGISTER (RBB_LPSR_ENABLE_SP) 32 RW 0000_0000
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
730 BANDGAP_STBY_EN_SP_REGISTER (BANDGAP_STBY_EN_SP) 32 RW 0000_0000
740 PLL_LDO_STBY_EN_SP_REGISTER (PLL_LDO_STBY_EN_SP) 32 RW 0000_0000
750 FBB_M7_STBY_EN_SP_REGISTER (FBB_M7_STBY_EN_SP) 32 RW 0000_0000
760 RBB_SOC_STBY_EN_SP_REGISTER (RBB_SOC_STBY_EN_SP) 32 RW 0000_0000
770 RBB_LPSR_STBY_EN_SP_REGISTER (RBB_LPSR_STBY_EN_ 32 RW 0000_0000
SP)
780 FBB_M7_CONFIGURE_REGISTER (FBB_M7_CONFIGURE) 32 RW 0000_2F11
790 RBB_LPSR_CONFIGURE_REGISTER (RBB_LPSR_CONFIGURE) 32 RW 0000_3022
7A0 RBB_SOC_CONFIGURE_REGISTER (RBB_SOC_CONFIGURE) 32 RW 0000_0044
7B0 REFTOP_OTP_TRIM_VALUE_REGISTER (REFTOP_OTP_TRIM_ 32 RO 0000_0000
VALUE)
7D0 LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER (LPSR_1P8_LDO 32 RO 0000_0000
_OTP_TRIM_VALUE)
17.5.1.2 PMU_LDO_PLL_REGISTER (PMU_LDO_PLL)
PMU_LDO_PLL_Regulator_Control_Register
This register defines the control and status bits for PLL regulator. This regulator is
designed to power the digital portions of the analog cells
17.5.1.2.1 Offset
Register Offset
PMU_LDO_PLL 500h
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Chapter 17 Power Management Unit (PMU)
17.5.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDO_PLL_AI_BUSY
LDO_PLL_AI_TOGGLE
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDO_PLL_CONTROL_MODE
LDO_PLL_ENABLE
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
17.5.1.2.3 Fields
Field Description
31 Reserved
—
30 ldo_pll_busy
LDO_PLL_AI_B For this AI bridge register field, there will be a detail description on how to use it.
USY
29-17 Reserved
— Always set to zero (0).
16 ldo_pll_ai_toggle
LDO_PLL_AI_T For this AI bridge register field, there will be a detail description on how to use it.
OGGLE
15-13 Reserved
— Always set to zero (0).
12-2 Reserved
—
1 LDO_PLL_CONTROL_MODE
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Memory Map and register definition
Field Description
LDO_PLL_CON LDO_PLL has two mode to for enable. One is software mode, the other is GPC mode(Setpoint).
TROL_MODE LDO_PLL_CONTROL_MODE select
0 - Software control mode
1 - Hardware / GPC control mode
0 LDO_PLL_ENABLE
LDO_PLL_ENA The usage of this bit is for software mode switching to gpc mode: If the Setpoint 0 is ldo_pll on : set this
BLE ldo_pll_enable to default state 1. Else the Setpoint 0 is ldo_pll off : set this ldo_pll_enable to state 0. After
the mode switched to gpc mode, keep this bit as it is should be fine.
17.5.1.3 PMU_BIAS_CTRL_REGISTER (PMU_BIAS_CTRL)
PMU_Well_BIAS_Control_Register
This register defines functions for wb bias.
17.5.1.3.1 Offset
Register Offset
PMU_BIAS_CTRL 550h
17.5.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WB_VDD_SEL_1P8
WB_CFG_1P8
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.3.3 Fields
Field Description
31-28 Reserved
—
27-24 Reserved
—
23-15 Reserved
—
14 wb_vdd_sel_1p8
WB_VDD_SEL_ Well bias VDD selector 1P8. There are two power sources (LPSR_DIG_LDO or DCDC).
1P8
NOTE: This selection depends on which RBB is working, SOC RBB (DCDC) or LPSR RBB
(LPSR_DIG_LDO). This select bit needs to be done before enabling wbias
0 - VDD_LV1 supplies the power stage and NWELL sampler (LPSR_DIG_LDO)
1 - VDD_LV2 supplies the power stage and NWELL sampler (DCDC)
13 Reserved
—
12-0 wb_cfg_1p8
WB_CFG_1P8 Well Bias Configuration 1P8.
For bit 0 :
• 0 PWELL and NWELL is turned on when wb_en_1p8 is set;
• 1 PWELL regulator is turned on only when wb_en_1p8 is set. NWELL is kept disabled.
For bit 1 : Body bias
• 0 NWELL is configured to supply and RVT CORE - RBB.
• 1 NWELL is configured to supply and LVT CORE - FBB.
For bit 2-4 : Select size of bias area
• 000 Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C
• 001 Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C
• 010 Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C
• 011 Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C
• 100 Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C
• 101 Imax = 45uA; Areamax-RVT = 0.15mm2 at 125C
• 110 Imax = 30uA; Areamax-RVT = 1.0mm2 at 125C
• 111 Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C
For bit 5 : Adaptive function
• 1 Adaptive frequency disabled. Frequency determined by wb_cfg_1p8[8:6].
• 0 Frequency change after each half cycle Minimum frequency determined by wb_cfg_1p8[8:6]
For bit 6-8 : Oscillator bits
• 000 typical frequency = osc_freq/128
• 001 typical frequency = osc_freq/64
• 010 typical frequency = osc_freq/32
• 011 typical frequency =osc_freq/16
• 100 typical frequency = osc_freq/8
• 110 typical frequency = osc_freq/2
• 111 typical frequency = oscillator Frequency (osc_freq)
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Memory Map and register definition
Field Description
For bit 9 : TRIM BUS. It is used to set an internal adaptive configuration. It configures the adaptive clock
source. The options are: 1) the oscillator clock 2) clock synchronous with the Charge Pump clock. These
2 signals have the same frequency, but delayed one to other. It determines if the adaptive control signal
changes the frequency in the same or in the next oscillator cycle.
• 0 The option is the oscillator clock
• 1 The option is clock synchronous with the Charge Pump clock
For bit 10 - 11 : TRIM BUS
• 00 no frequency reduction
• 01 30% frequency reduction due to cap. increment.
• 10 40% frequency reduction due to cap. increment.
• 11 50% frequency reduction due to cap. increment.
For bit 12 :
• 1 Pull down option is enabled.
• 0 Pull down option is disabled.
17.5.1.4 PMU_BIAS_CTRL2_REGISTER (PMU_BIAS_CTRL2)
Well Bias IP control register
This register defines the test mode function for wb bias.
17.5.1.4.1 Offset
Register Offset
PMU_BIAS_CTRL2 560h
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Chapter 17 Power Management Unit (PMU)
17.5.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBB_LPSR_CONTROL_MODE
WB_TST_DIG_OUT
RBB_SOC_CONTROL_MODE
FBB_M7_CONTROL_MODE
WB_OK
R
WB_ADJ_1P8
Reserved
WB_E
N
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WB_PWR_SW_EN_1P8
WB_ADJ_1P8
WB_TST_MD
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.4.3 Fields
Field Description
31-27 Reserved
— Always set to zero (0).
26 Digital Output pin.
WB_OK Turn on/off acknowledge bit from regulator
25 Digital output
WB_TST_DIG_ For test purposes
OUT
24 wb_en
WB_EN
23 RBB_LPSR_CONTROL_MODE
RBB_LPSR_CO 0 - Software control mode
NTROL_MODE
1 - Hardware / GPC control mode
22 RBB_SOC_CONTROL_MODE
0 - Software control mode
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Memory Map and register definition
Field Description
RBB_SOC_CO 1 - Hardware / GPC control mode
NTROL_MODE
21 FBB_M7_CONTROL_MODE
FBB_M7_CONT 0 - Software control mode
ROL_MODE
1 - Hardware / GPC control mode
20-13 wb_adj_1p8
WB_ADJ_1P8 Well Bias Adjustment 1P8. The bit values detailed below is a representation of bits 0 - 3 : TRIM BUS, and
bits 4 - 7.
00000000 - Cref= 0fF Cspl= 0fF DeltaC= 0fF
00000001 - Cref= 0fF Cspl= 30fF DeltaC= -30fF
00000010 - Cref= 0fF Cspl= 43fF DeltaC= -43fF
00000011 - Cref= 0fF Cspl= 62fF DeltaC=-62fF
00000100 - Cref= 0fF Cspl=105fF DeltaC=-105fF
00000101 - Cref= 30fF Cspl= 0fF DeltaC= 30fF
00000110 - Cref= 30fF Cspl= 43fF DeltaC= -12fF
00000111 - Cref= 30fF Cspl=105fF DeltaC= -75fF
00001000 - Cref= 43fF Cspl= 0fF DeltaC= 43fF
00001001 - Cref= 43fF Cspl= 30fF DeltaC= 13fF
00001010 - Cref= 43fF Cspl= 62fF DeltaC= -19fF
00001011 - Cref= 62fF Cspl= 0fF DeltaC= 62fF
00001100 - Cref= 62fF Cspl= 43fF DeltaC= 19fF
00001101 - Cref=105fF Cspl= 0fF DeltaC= 105fF
00001110 - Cref=105fF Cspl=30fF DeltaC= 75fF
00001111 - Cref=0fF Cspl=0fF DeltaC= 0fF
12-10 MODSEL_wb_tst_md_1p8
WB_PWR_SW_ Power switch enable
EN_1P8
This is a PWR_SW_EN, that is a module selection. Setting these bits will connect the NWELL/PWELL to
back-biasing power supplies (0 - not connected, 1 - connected).
Each bit represents one configuration.
bit [0] represents FBB M7
bit [1] represents RBB LPSR
bit [2] RBB SOC + LPSR
NOTE: Only one bit can be 1 at the same time.
001 - NWELL/PWELL FBB is connected to CM7
010 - NWELL/PWELL RBB is connected to LPSR
100 - NWELL/PWELL RBB is connected to SOC.
9-1 TMOD_wb_tst_md_1p8
WB_TST_MD TMOD Test modes inside the module
0 Reserved
— Always set to zero (0).
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Chapter 17 Power Management Unit (PMU)
17.5.1.5 PMU_REF_CTRL_REGISTER (PMU_REF_CTRL)
Anadig_Reference_Analog_Control_and_Status_Control_Register
17.5.1.5.1 Offset
Register Offset
PMU_REF_CTRL 570h
17.5.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_PLL_VOL_REF_BUFFE
REF_AI_BUS
REF_CONTROL_MODE
R
REF_AI_TOGGL
REF_ENABL
Reserved
Y
E
W
E
R
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.5.3 Fields
Field Description
31-5 Reserved
— Always set to zero (0).
4 en_pll_vol_ref_buffer
EN_PLL_VOL_ This control bit enables or disables the reference voltage for the PLLs.
REF_BUFFER
3 REF_CONTROL_MODE
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Memory Map and register definition
Field Description
REF_CONTROL SW/HW control mode for reftop
_MODE
0 - Software control mode
1 - Hardware / GPC control mode
2 REF_ENABLE
REF_ENABLE The usage of this bit is for software mode switching to gpc mode: If the Setpoint 0 is bandgap on: set this
ref_enable to default state 0. Else the Setpoint 0 is bandgap off: set this ref_enable to state 1. After the
mode switched to gpc mode, keep this bit as it is should be fine. It is recommended to let software handle
all the possible cases.
1 ref_ai_busy
REF_AI_BUSY ref_ai_busy
0 ref_ai_toggle
REF_AI_TOGG ref_ai_toggle
LE
17.5.1.6 PMU_POWER_DETECT_CTRL_REGISTER (PMU_POWER_
DETECT_CTRL)
This register will be deleted in next release except ckgb bit
17.5.1.6.1 Offset
Register Offset
PMU_POWER_DETECT 580h
_CTRL
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Chapter 17 Power Management Unit (PMU)
17.5.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGB_LPSR1P0
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.6.3 Fields
Field Description
31-16 Reserved
—
15-9 Reserved
—
8 ckgb_lpsr1p0
CKGB_LPSR1P PHY LDO isolation control bit. This bit is used during PHY LDO ON/OFF sequence. This bit is for
0 software usage. In GPC mode, it will automatically be handled by hardware.
7-0 Reserved
—
17.5.1.7 LDO_PLL_ENABLE_SP_REGISTER (LDO_PLL_ENABLE_SP)
LDO_PLL Setpoint enable and disable register
17.5.1.7.1 Offset
Register Offset
LDO_PLL_ENABLE_SP 600h
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Memory Map and register definition
17.5.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.7.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
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Chapter 17 Power Management Unit (PMU)
Field Description
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
17.5.1.8 LDO_LPSR_ANA_ENABLE_SP_REGISTER (LDO_LPSR_ANA
_ENABLE_SP)
LDO_LPSR_ANA LDO, the ON/OFF control did not show the responsibility of LDO
ON/OFF, it is the combination usage for bypass function. The setting should be aligned
with BYPASS. When LDO bypass enable , ***_ENABLE_SP - 1'b1,
***_TRACKING_EN_SP - 1'b1, ***_BYPASS_EN_SP - 1'b1.
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Memory Map and register definition
17.5.1.8.1 Offset
Register Offset
LDO_LPSR_ANA_ENA 610h
BLE_SP
17.5.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.8.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
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Chapter 17 Power Management Unit (PMU)
Field Description
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
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Memory Map and register definition
17.5.1.9 LDO_LPSR_ANA_LP_MODE_SP_REGISTER (LDO_LPSR_
ANA_LP_MODE_SP)
LDO_LPSR_ANA high_power mode and low_power mode SP register
17.5.1.9.1 Offset
Register Offset
LDO_LPSR_ANA_LP_ 620h
MODE_SP
17.5.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LP_MODE_SETPONIT15
LP_MODE_SETPONIT14
LP_MODE_SETPONIT13
LP_MODE_SETPONIT12
LP_MODE_SETPONIT11
LP_MODE_SETPONIT10
LP_MODE_SETPONIT9
LP_MODE_SETPONIT8
LP_MODE_SETPONIT7
LP_MODE_SETPONIT6
LP_MODE_SETPONIT5
LP_MODE_SETPONIT4
LP_MODE_SETPONIT3
LP_MODE_SETPONIT2
LP_MODE_SETPOINT1
LP_MODE_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.9.3 Fields
Field Description
31-16 Reserved
—
15 LP_MODE_SETPOINT15
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT15
1 - HP mode in certain Setpoint
14 LP_MODE_SETPOINT14
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT14
1 - HP mode in certain Setpoint
13 LP_MODE_SETPOINT13
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT13
1 - HP mode in certain Setpoint
12 LP_MODE_SETPOINT12
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT12
1 - HP mode in certain Setpoint
11 LP_MODE_SETPOINT11
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT11
1 - HP mode in certain Setpoint
10 LP_MODE_SETPOINT10
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT10
1 - HP mode in certain Setpoint
9 LP_MODE_SETPOINT9
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT9
1 - HP mode in certain Setpoint
8 LP_MODE_SETPOINT8
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT8
1 - HP mode in certain Setpoint
7 LP_MODE_SETPOINT7
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT7
1 - HP mode in certain Setpoint
6 LP_MODE_SETPOINT6
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT6
1 - HP mode in certain Setpoint
5 LP_MODE_SETPOINT5
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT5
1 - HP mode in certain Setpoint
4 LP_MODE_SETPOINT4
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT4
1 - HP mode in certain Setpoint
3 LP_MODE_SETPOINT3
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT3
1 - HP mode in certain Setpoint
2 LP_MODE_SETPOINT2
LP_MODE_SET 0 - LP mode in certain Setpoint
PONIT2
1 - HP mode in certain Setpoint
1 LP_MODE_SETPOINT1
Table continues on the next page...
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Memory Map and register definition
Field Description
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT1
1 - HP mode in certain Setpoint
0 LP_MODE_SETPOINT0
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT0
1 - HP mode in certain Setpoint
17.5.1.10 LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER (LDO_
LPSR_ANA_TRACKING_EN_SP)
LDO_LPSR_ANA tracking mode sp enable register
17.5.1.10.1 Offset
Register Offset
LDO_LPSR_ANA_TRA 630h
CKING_EN_SP
17.5.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TRACKING_EN_SETPOINT15
TRACKING_EN_SETPOINT14
TRACKING_EN_SETPOINT13
TRACKING_EN_SETPOINT12
TRACKING_EN_SETPOINT11
TRACKING_EN_SETPOINT10
TRACKING_EN_SETPOINT9
TRACKING_EN_SETPOINT8
TRACKING_EN_SETPOINT7
TRACKING_EN_SETPOINT6
TRACKING_EN_SETPOINT5
TRACKING_EN_SETPOINT4
TRACKING_EN_SETPOINT3
TRACKING_EN_SETPOINT2
TRACKING_EN_SETPOINT1
TRACKING_EN_SETPOINT0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.10.3 Fields
Field Description
31-16 Reserved
—
15 TRACKING_EN_SETPOINT15
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT15
1 - Tracking mode is enabled in certain Setpoint
14 TRACKING_EN_SETPOINT14
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT14
1 - Tracking mode is enabled in certain Setpoint
13 TRACKING_EN_SETPOINT13
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT13
1 - Tracking mode is enabled in certain Setpoint
12 TRACKING_EN_SETPOINT12
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT12
1 - Tracking mode is enabled in certain Setpoint
11 TRACKING_EN_SETPOINT11
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT11
1 - Tracking mode is enabled in certain Setpoint
10 TRACKING_EN_SETPOINT10
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT10
1 - Tracking mode is enabled in certain Setpoint
9 TRACKING_EN_SETPOINT9
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT9
1 - Tracking mode is enabled in certain Setpoint
8 TRACKING_EN_SETPOINT8
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT8
1 - Tracking mode is enabled in certain Setpoint
7 TRACKING_EN_SETPOINT7
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT7
1 - Tracking mode is enabled in certain Setpoint
6 TRACKING_EN_SETPOINT6
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT6
1 - Tracking mode is enabled in certain Setpoint
5 TRACKING_EN_SETPOINT5
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT5
1 - Tracking mode is enabled in certain Setpoint
4 TRACKING_EN_SETPOINT4
0 - Tracking mode is disabled in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
TRACKING_EN 1 - Tracking mode is enabled in certain Setpoint
_SETPOINT4
3 TRACKING_EN_SETPOINT3
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT3
1 - Tracking mode is enabled in certain Setpoint
2 TRACKING_EN_SETPOINT2
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT2
1 - Tracking mode is enabled in certain Setpoint
1 TRACKING_EN_SETPOINT1
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT1
1 - Tracking mode is enabled in certain Setpoint
0 TRACKING_EN_SETPOINT0
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT0
1 - Tracking mode is enabled in certain Setpoint
17.5.1.11 LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER (LDO_LPSR
_ANA_BYPASS_EN_SP)
LDO_LPSR_ANA bypass mode sp enable register
17.5.1.11.1 Offset
Register Offset
LDO_LPSR_ANA_BYP 640h
ASS_EN_SP
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Chapter 17 Power Management Unit (PMU)
17.5.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BYPASS_EN_SETPOINT15
BYPASS_EN_SETPOINT14
BYPASS_EN_SETPOINT13
BYPASS_EN_SETPOINT12
BYPASS_EN_SETPOINT11
BYPASS_EN_SETPOINT10
BYPASS_EN_SETPOINT9
BYPASS_EN_SETPOINT8
BYPASS_EN_SETPOINT7
BYPASS_EN_SETPOINT6
BYPASS_EN_SETPOINT5
BYPASS_EN_SETPOINT4
BYPASS_EN_SETPOINT3
BYPASS_EN_SETPOINT2
BYPASS_EN_SETPOINT1
BYPASS_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.11.3 Fields
Field Description
31-16 Reserved
—
15 BYPASS_EN_SETPOINT15
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT15
1 - Bypass mode is enabled in certain Setpoint
14 BYPASS_EN_SETPOINT14
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT14
1 - Bypass mode is enabled in certain Setpoint
13 BYPASS_EN_SETPOINT13
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT13
1 - Bypass mode is enabled in certain Setpoint
12 BYPASS_EN_SETPOINT12
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT12
1 - Bypass mode is enabled in certain Setpoint
11 BYPASS_EN_SETPOINT11
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT11
1 - Bypass mode is enabled in certain Setpoint
10 BYPASS_EN_SETPOINT10
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT10
1 - Bypass mode is enabled in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
9 BYPASS_EN_SETPOINT9
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT9
1 - Bypass mode is enabled in certain Setpoint
8 BYPASS_EN_SETPOINT
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT8
1 - Bypass mode is enabled in certain Setpoint
7 BYPASS_EN_SETPOINT7
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT7
1 - Bypass mode is enabled in certain Setpoint
6 BYPASS_EN_SETPOINT6
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT6
1 - Bypass mode is enabled in certain Setpoint
5 BYPASS_EN_SETPOINT5
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT5
1 - Bypass mode is enabled in certain Setpoint
4 BYPASS_EN_SETPOINT4
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT4
1 - Bypass mode is enabled in certain Setpoint
3 BYPASS_EN_SETPOINT3
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT3
1 - Bypass mode is enabled in certain Setpoint
2 BYPASS_EN_SETPOINT2
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT2
1 - Bypass mode is enabled in certain Setpoint
1 BYPASS_EN_SETPOINT1
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT1
1 - Bypass mode is enabled in certain Setpoint
0 BYPASS_EN_SETPOINT0
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT0
1 - Bypass mode is enabled in certain Setpoint
17.5.1.12 LDO_LPSR_ANA_STBY_EN_SP_REGISTER (LDO_LPSR_
ANA_STBY_EN_SP)
LDO_LPSR_ANA STBY MODE enable sp register stby mode represent HP/LP mode
transist.
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Chapter 17 Power Management Unit (PMU)
17.5.1.12.1 Offset
Register Offset
LDO_LPSR_ANA_STB 650h
Y_EN_SP
17.5.1.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.12.3 Fields
Field Description
31-16 Reserved
—
15 STBY_EN_SETPOINT15
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 STBY_EN_SETPOINT14
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 STBY_EN_SETPOINT13
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 STBY_EN_SETPOINT12
0 - STANDBY mode is disabled
Table continues on the next page...
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Memory Map and register definition
Field Description
STBY_EN_SET 1 - STANDBY mode is enabled
POINT12
11 STBY_EN_SETPOINT11
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 STBY_EN_SETPOINT10
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
9 STBY_EN_SETPOINT9
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 STBY_EN_SETPOINT8
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 STBY_EN_SETPOINT7
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 STBY_EN_SETPOINT6
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 STBY_EN_SETPOINT5
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 STBY_EN_SETPOINT4
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 STBY_EN_SETPOINT3
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 STBY_EN_SETPOINT2
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 STBY_EN_SETPOINT1
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 STBY_EN_SETPOINT0
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
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Chapter 17 Power Management Unit (PMU)
17.5.1.13 LDO_LPSR_DIG_ENABLE_SP_REGISTER (LDO_LPSR_DIG
_ENABLE_SP)
LDO_LPSR_ANA LDO, the ON/OFF control did not show the responsibility of LDO
ON/OFF, it is the combination usage for bypass function. The setting should be aligned
with BYPASS. When LDO bypass enable , ***_ENABLE_SP - 1'b1,
***_TRACKING_EN_SP - 1'b1, ***_BYPASS_EN_SP - 1'b1.
17.5.1.13.1 Offset
Register Offset
LDO_LPSR_DIG_ENA 660h
BLE_SP
17.5.1.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.13.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
0 - ON in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
ON_OFF_SETP 1 - OFF in certain Setpoint
OINT15
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
0 - ON in certain Setpoint
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
ON_OFF_SETP 1 - OFF in certain Setpoint
OINT2
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
17.5.1.14 LDO_LPSR_DIG_TRG_SP0_REGISTER (LDO_LPSR_DIG_
TRG_SP0)
This register store the lpsr_dig voltage step which will be performed during GPC mode.
17.5.1.14.1 Offset
Register Offset
LDO_LPSR_DIG_TRG_ 670h
SP0
17.5.1.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VOLTAGE_SETPOINT3 VOLTAGE_SETPOINT2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VOLTAGE_SETPOINT1 VOLTAGE_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.14.3 Fields
Field Description
31-24 VOLTAGE_SETPOINT3
This field store the voltage step will be performed during identical Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
VOLTAGE_SET
POINT3
23-16 VOLTAGE_SETPOINT2
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT2
15-8 VOLTAGE_SETPOINT1
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT1
7-0 VOLTAGE_SETPOINT0
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT0
17.5.1.15 LDO_LPSR_DIG_TRG_SP1_REGISTER (LDO_LPSR_DIG_
TRG_SP1)
This register store the lpsr_dig voltage step which will be performed during GPC mode.
17.5.1.15.1 Offset
Register Offset
LDO_LPSR_DIG_TRG_ 680h
SP1
17.5.1.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VOLTAGE_SETPOINT7 VOLTAGE_SETPOINT6
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VOLTAGE_SETPOINT5 VOLTAGE_SETPOINT4
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.15.3 Fields
Field Description
31-24 VOLTAGE_SETPOINT7
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT7
23-16 VOLTAGE_SETPOINT6
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT6
15-8 VOLTAGE_SETPOINT5
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT5
7-0 VOLTAGE_SETPOINT4
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT4
17.5.1.16 LDO_LPSR_DIG_TRG_SP2_REGISTER (LDO_LPSR_DIG_
TRG_SP2)
This register store the lpsr_dig voltage step which will be performed during GPC mode.
17.5.1.16.1 Offset
Register Offset
LDO_LPSR_DIG_TRG_ 690h
SP2
17.5.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VOLTAGE_SETPOINT11 VOLTAGE_SETPOINT10
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VOLTAGE_SETPOINT9 VOLTAGE_SETPOINT8
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Memory Map and register definition
17.5.1.16.3 Fields
Field Description
31-24 VOLTAGE_SETPOINT11
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT11
23-16 VOLTAGE_SETPOINT10
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT10
15-8 VOLTAGE_SETPOINT9
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT9
7-0 VOLTAGE_SETPOINT8
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT8
17.5.1.17 LDO_LPSR_DIG_TRG_SP3_REGISTER (LDO_LPSR_DIG_
TRG_SP3)
This register store the lpsr_dig voltage step which will be performed during GPC mode.
17.5.1.17.1 Offset
Register Offset
LDO_LPSR_DIG_TRG_ 6A0h
SP3
17.5.1.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VOLTAGE_SETPOINT15 VOLTAGE_SETPOINT14
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VOLTAGE_SETPOINT13 VOLTAGE_SETPOINT12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.17.3 Fields
Field Description
31-24 VOLTAGE_SETPOINT15
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT15
23-16 VOLTAGE_SETPOINT14
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT14
15-8 VOLTAGE_SETPOINT13
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT13
7-0 VOLTAGE_SETPOINT12
VOLTAGE_SET This field store the voltage step will be performed during identical Setpoint
POINT12
17.5.1.18 LDO_LPSR_DIG_LP_MODE_SP_REGISTER (LDO_LPSR_
DIG_LP_MODE_SP)
This register provide the entry to the LP mode configure in GPC mode
17.5.1.18.1 Offset
Register Offset
LDO_LPSR_DIG_LP_ 6B0h
MODE_SP
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NXP Semiconductors 1739
Memory Map and register definition
17.5.1.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LP_MODE_SETPOINT15
LP_MODE_SETPOINT14
LP_MODE_SETPOINT13
LP_MODE_SETPOINT12
LP_MODE_SETPOINT11
LP_MODE_SETPOINT10
LP_MODE_SETPOINT9
LP_MODE_SETPOINT8
LP_MODE_SETPOINT7
LP_MODE_SETPOINT6
LP_MODE_SETPOINT5
LP_MODE_SETPOINT4
LP_MODE_SETPOINT3
LP_MODE_SETPOINT2
LP_MODE_SETPOINT1
LP_MODE_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.18.3 Fields
Field Description
31-16 Reserved
—
15 LP_MODE_SETPOINT15
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT15
1 - HP mode in certain Setpoint
14 LP_MODE_SETPOINT14
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT14
1 - HP mode in certain Setpoint
13 LP_MODE_SETPOINT13
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT13
1 - HP mode in certain Setpoint
12 LP_MODE_SETPOINT12
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT12
1 - HP mode in certain Setpoint
11 LP_MODE_SETPOINT11
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT11
1 - HP mode in certain Setpoint
10 LP_MODE_SETPOINT10
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT10
1 - HP mode in certain Setpoint
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
9 LP_MODE_SETPOINT9
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT9
1 - HP mode in certain Setpoint
8 LP_MODE_SETPOINT8
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT8
1 - HP mode in certain Setpoint
7 LP_MODE_SETPOINT7
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT7
1 - HP mode in certain Setpoint
6 LP_MODE_SETPOINT6
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT6
1 - HP mode in certain Setpoint
5 LP_MODE_SETPOINT5
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT5
1 - HP mode in certain Setpoint
4 LP_MODE_SETPOINT4
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT4
1 - HP mode in certain Setpoint
3 LP_MODE_SETPOINT3
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT3
1 - HP mode in certain Setpoint
2 LP_MODE_SETPOINT2
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT2
1 - HP mode in certain Setpoint
1 LP_MODE_SETPOINT1
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT1
1 - HP mode in certain Setpoint
0 LP_MODE_SETPOINT0
LP_MODE_SET 0 - LP mode in certain Setpoint
POINT0
1 - HP mode in certain Setpoint
17.5.1.19 LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER (LDO_
LPSR_DIG_TRACKING_EN_SP)
This register provide the entry to the tracking mode configure in GPC mode
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Memory Map and register definition
17.5.1.19.1 Offset
Register Offset
LDO_LPSR_DIG_TRA 6C0h
CKING_EN_SP
17.5.1.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TRACKING_EN_SETPOINT15
TRACKING_EN_SETPOINT14
TRACKING_EN_SETPOINT13
TRACKING_EN_SETPOINT12
TRACKING_EN_SETPOINT11
TRACKING_EN_SETPOINT10
TRACKING_EN_SETPOINT9
TRACKING_EN_SETPOINT8
TRACKING_EN_SETPOINT7
TRACKING_EN_SETPOINT6
TRACKING_EN_SETPOINT5
TRACKING_EN_SETPOINT4
TRACKING_EN_SETPOINT3
TRACKING_EN_SETPOINT2
TRACKING_EN_SETPOINT1
TRACKING_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.19.3 Fields
Field Description
31-16 Reserved
—
15 TRACKING_EN_SETPOINT15
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT15
1 - Tracking mode is enabled in certain Setpoint
14 TRACKING_EN_SETPOINT14
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT14
1 - Tracking mode is enabled in certain Setpoint
13 TRACKING_EN_SETPOINT13
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT13
1 - Tracking mode is enabled in certain Setpoint
12 TRACKING_EN_SETPOINT12
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT12
1 - Tracking mode is enabled in certain Setpoint
11 TRACKING_EN_SETPOINT11
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT11
1 - Tracking mode is enabled in certain Setpoint
10 TRACKING_EN_SETPOINT10
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT10
1 - Tracking mode is enabled in certain Setpoint
9 TRACKING_EN_SETPOINT9
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT9
1 - Tracking mode is enabled in certain Setpoint
8 TRACKING_EN_SETPOINT8
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT8
1 - Tracking mode is enabled in certain Setpoint
7 TRACKING_EN_SETPOINT7
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT7
1 - Tracking mode is enabled in certain Setpoint
6 TRACKING_EN_SETPOINT6
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT6
1 - Tracking mode is enabled in certain Setpoint
5 TRACKING_EN_SETPOINT5
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT5
1 - Tracking mode is enabled in certain Setpoint
4 TRACKING_EN_SETPOINT4
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT4
1 - Tracking mode is enabled in certain Setpoint
3 TRACKING_EN_SETPOINT3
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT3
1 - Tracking mode is enabled in certain Setpoint
2 TRACKING_EN_SETPOINT2
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT2
1 - Tracking mode is enabled in certain Setpoint
1 TRACKING_EN_SETPOINT1
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT1
1 - Tracking mode is enabled in certain Setpoint
0 TRACKING_EN_SETPOINT0
TRACKING_EN 0 - Tracking mode is disabled in certain Setpoint
_SETPOINT0
1 - Tracking mode is enabled in certain Setpoint
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Memory Map and register definition
17.5.1.20 LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER (LDO_LPSR_
DIG_BYPASS_EN_SP)
This register provide the entry to the bypass_en configure in GPC mode
17.5.1.20.1 Offset
Register Offset
LDO_LPSR_DIG_BYP 6D0h
ASS_EN_SP
17.5.1.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BYPASS_EN_SETPOINT15
BYPASS_EN_SETPOINT14
BYPASS_EN_SETPOINT13
BYPASS_EN_SETPOINT12
BYPASS_EN_SETPOINT11
BYPASS_EN_SETPOINT10
BYPASS_EN_SETPOINT9
BYPASS_EN_SETPOINT8
BYPASS_EN_SETPOINT7
BYPASS_EN_SETPOINT6
BYPASS_EN_SETPOINT5
BYPASS_EN_SETPOINT4
BYPASS_EN_SETPOINT3
BYPASS_EN_SETPOINT2
BYPASS_EN_SETPOINT1
BYPASS_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.20.3 Fields
Field Description
31-16 Reserved
—
15 BYPASS_EN_SETPOINT15
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT15
1 - Bypass mode is enabled in certain Setpoint
14 BYPASS_EN_SETPOINT14
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT14
1 - Bypass mode is enabled in certain Setpoint
13 BYPASS_EN_SETPOINT13
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT13
1 - Bypass mode is enabled in certain Setpoint
12 BYPASS_EN_SETPOINT12
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT12
1 - Bypass mode is enabled in certain Setpoint
11 BYPASS_EN_SETPOINT11
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT11
1 - Bypass mode is enabled in certain Setpoint
10 BYPASS_EN_SETPOINT10
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT10
1 - Bypass mode is enabled in certain Setpoint
9 BYPASS_EN_SETPOINT9
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT9
1 - Bypass mode is enabled in certain Setpoint
8 BYPASS_EN_SETPOINT8
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT8
1 - Bypass mode is enabled in certain Setpoint
7 BYPASS_EN_SETPOINT7
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT7
1 - Bypass mode is enabled in certain Setpoint
6 BYPASS_EN_SETPOINT6
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT6
1 - Bypass mode is enabled in certain Setpoint
5 BYPASS_EN_SETPOINT5
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT5
1 - Bypass mode is enabled in certain Setpoint
4 BYPASS_EN_SETPOINT4
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT4
1 - Bypass mode is enabled in certain Setpoint
3 BYPASS_EN_SETPOINT3
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT3
1 - Bypass mode is enabled in certain Setpoint
2 BYPASS_EN_SETPOINT2
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT2
1 - Bypass mode is enabled in certain Setpoint
1 BYPASS_EN_SETPOINT1
Table continues on the next page...
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Memory Map and register definition
Field Description
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT1
1 - Bypass mode is enabled in certain Setpoint
0 BYPASS_EN_SETPOINT0
BYPASS_EN_S 0 - Bypass mode is disabled in certain Setpoint
ETPOINT0
1 - Bypass mode is enabled in certain Setpoint
17.5.1.21 LDO_LPSR_DIG_STBY_EN_SP_REGISTER (LDO_LPSR_
DIG_STBY_EN_SP)
This register provide the entry to the standby configure in GPC mode
17.5.1.21.1 Offset
Register Offset
LDO_LPSR_DIG_STBY_ 6E0h
EN_SP
17.5.1.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.21.3 Fields
Field Description
31-16 Reserved
—
15 STBY_EN_SETPOINT15
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 STBY_EN_SETPOINT14
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 STBY_EN_SETPOINT13
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 STBY_EN_SETPOINT12
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
11 STBY_EN_SETPOINT11
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 STBY_EN_SETPOINT10
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
9 STBY_EN_SETPOINT9
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 STBY_EN_SETPOINT8
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 STBY_EN_SETPOINT7
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 STBY_EN_SETPOINT6
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 STBY_EN_SETPOINT5
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 STBY_EN_SETPOINT4
0 - STANDBY mode is disabled
Table continues on the next page...
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Memory Map and register definition
Field Description
STBY_EN_SET 1 - STANDBY mode is enabled
POINT4
3 STBY_EN_SETPOINT3
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 STBY_EN_SETPOINT2
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 STBY_EN_SETPOINT1
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 STBY_EN_SETPOINT0
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
17.5.1.22 BANDGAP_ENABLE_SP_REGISTER (BANDGAP_ENABLE_
SP)
BANDGAP, ON/OFF control register
17.5.1.22.1 Offset
Register Offset
BANDGAP_ENABLE_SP 6F0h
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Chapter 17 Power Management Unit (PMU)
17.5.1.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.22.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
17.5.1.23 FBB_M7_ENABLE_SP_REGISTER (FBB_M7_ENABLE_SP)
FBB M7, ON/OFF control register
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Chapter 17 Power Management Unit (PMU)
17.5.1.23.1 Offset
Register Offset
FBB_M7_ENABLE_SP 700h
17.5.1.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.23.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
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Chapter 17 Power Management Unit (PMU)
17.5.1.24 RBB_SOC_ENABLE_SP_REGISTER (RBB_SOC_ENABLE_
SP)
Wellbias control SOC represent SOC + LPSR in the Setpoint definition table. No matter
it is SW or GPC mode. SOC domain + LPSR domain , ON/OFF control register
17.5.1.24.1 Offset
Register Offset
RBB_SOC_ENABLE_SP 710h
17.5.1.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.24.3 Fields
Field Description
31-16 Reserved
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
Table continues on the next page...
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Memory Map and register definition
Field Description
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
17.5.1.25 RBB_LPSR_ENABLE_SP_REGISTER (RBB_LPSR_ENA
BLE_SP)
RBB LPSR, ON/OFF control register
17.5.1.25.1 Offset
Register Offset
RBB_LPSR_ENABLE_ 720h
SP
17.5.1.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ON_OFF_SETPOINT15
ON_OFF_SETPOINT14
ON_OFF_SETPOINT13
ON_OFF_SETPOINT12
ON_OFF_SETPOINT11
ON_OFF_SETPOINT10
ON_OFF_SETPOINT9
ON_OFF_SETPOINT8
ON_OFF_SETPOINT7
ON_OFF_SETPOINT6
ON_OFF_SETPOINT5
ON_OFF_SETPOINT4
ON_OFF_SETPOINT3
ON_OFF_SETPOINT2
ON_OFF_SETPOINT1
ON_OFF_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.25.3 Fields
Field Description
31-16 Reserved
Table continues on the next page...
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NXP Semiconductors 1755
Memory Map and register definition
Field Description
—
15 ON_OFF_SETPOINT15
ON_OFF_SETP 0 - ON in certain Setpoint
OINT15
1 - OFF in certain Setpoint
14 ON_OFF_SETPOINT14
ON_OFF_SETP 0 - ON in certain Setpoint
OINT14
1 - OFF in certain Setpoint
13 ON_OFF_SETPOINT13
ON_OFF_SETP 0 - ON in certain Setpoint
OINT13
1 - OFF in certain Setpoint
12 ON_OFF_SETPOINT12
ON_OFF_SETP 0 - ON in certain Setpoint
OINT12
1 - OFF in certain Setpoint
11 ON_OFF_SETPOINT11
ON_OFF_SETP 0 - ON in certain Setpoint
OINT11
1 - OFF in certain Setpoint
10 ON_OFF_SETPOINT10
ON_OFF_SETP 0 - ON in certain Setpoint
OINT10
1 - OFF in certain Setpoint
9 ON_OFF_SETPOINT9
ON_OFF_SETP 0 - ON in certain Setpoint
OINT9
1 - OFF in certain Setpoint
8 ON_OFF_SETPOINT8
ON_OFF_SETP 0 - ON in certain Setpoint
OINT8
1 - OFF in certain Setpoint
7 ON_OFF_SETPOINT7
ON_OFF_SETP 0 - ON in certain Setpoint
OINT7
1 - OFF in certain Setpoint
6 ON_OFF_SETPOINT6
ON_OFF_SETP 0 - ON in certain Setpoint
OINT6
1 - OFF in certain Setpoint
5 ON_OFF_SETPOINT5
ON_OFF_SETP 0 - ON in certain Setpoint
OINT5
1 - OFF in certain Setpoint
4 ON_OFF_SETPOINT4
ON_OFF_SETP 0 - ON in certain Setpoint
OINT4
1 - OFF in certain Setpoint
3 ON_OFF_SETPOINT3
ON_OFF_SETP 0 - ON in certain Setpoint
OINT3
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
1 - OFF in certain Setpoint
2 ON_OFF_SETPOINT2
ON_OFF_SETP 0 - ON in certain Setpoint
OINT2
1 - OFF in certain Setpoint
1 ON_OFF_SETPOINT1
ON_OFF_SETP 0 - ON in certain Setpoint
OINT1
1 - OFF in certain Setpoint
0 ON_OFF_SETPOINT0
ON_OFF_SETP 0 - ON in certain Setpoint
OINT0
1 - OFF in certain Setpoint
17.5.1.26 BANDGAP_STBY_EN_SP_REGISTER (BANDGAP_STBY_
EN_SP)
BANDGAP STBY MODE enable sp register stby mode represent ON/OFF mode
transist.
17.5.1.26.1 Offset
Register Offset
BANDGAP_STBY_EN_ 730h
SP
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Memory Map and register definition
17.5.1.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.26.3 Fields
Field Description
31-16 Reserved
—
15 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
11 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
9 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 STBY_EN_SETPOINT
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
17.5.1.27 PLL_LDO_STBY_EN_SP_REGISTER (PLL_LDO_STBY_EN_
SP)
PLL_LDO STBY MODE enable sp register stby mode represent ON/OFF mode transist.
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Memory Map and register definition
17.5.1.27.1 Offset
Register Offset
PLL_LDO_STBY_EN_SP 740h
17.5.1.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.27.3 Fields
Field Description
31-16 Reserved
—
15 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
11 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
9 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
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Memory Map and register definition
17.5.1.28 FBB_M7_STBY_EN_SP_REGISTER (FBB_M7_STBY_EN_S
P)
FBB_M7 STBY MODE enable sp register stby mode represent ON/OFF mode transist.
17.5.1.28.1 Offset
Register Offset
FBB_M7_STBY_EN_SP 750h
17.5.1.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.28.3 Fields
Field Description
31-16 Reserved
—
15 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 Standy mode
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
11 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
9 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 Standy mode
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Memory Map and register definition
Field Description
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
17.5.1.29 RBB_SOC_STBY_EN_SP_REGISTER (RBB_SOC_STBY_
EN_SP)
SOC domain + LPSR domain RBB_SOC STBY MODE enable sp register stby mode
represent ON/OFF mode transist.
17.5.1.29.1 Offset
Register Offset
RBB_SOC_STBY_EN_ 760h
SP
17.5.1.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.29.3 Fields
Field Description
31-16 Reserved
Table continues on the next page...
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Chapter 17 Power Management Unit (PMU)
Field Description
—
15 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
11 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
9 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
Table continues on the next page...
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Memory Map and register definition
Field Description
1 - STANDBY mode is enabled
2 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
17.5.1.30 RBB_LPSR_STBY_EN_SP_REGISTER (RBB_LPSR_STBY_
EN_SP)
RBB_LPSR STBY MODE enable sp register stby mode represent ON/OFF mode
transist.
17.5.1.30.1 Offset
Register Offset
RBB_LPSR_STBY_EN_ 770h
SP
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Chapter 17 Power Management Unit (PMU)
17.5.1.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STBY_EN_SETPOINT15
STBY_EN_SETPOINT14
STBY_EN_SETPOINT13
STBY_EN_SETPOINT12
STBY_EN_SETPOINT11
STBY_EN_SETPOINT10
STBY_EN_SETPOINT9
STBY_EN_SETPOINT8
STBY_EN_SETPOINT7
STBY_EN_SETPOINT6
STBY_EN_SETPOINT5
STBY_EN_SETPOINT4
STBY_EN_SETPOINT3
STBY_EN_SETPOINT2
STBY_EN_SETPOINT1
STBY_EN_SETPOINT0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.30.3 Fields
Field Description
31-16 Reserved
—
15 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT15
1 - STANDBY mode is enabled
14 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT14
1 - STANDBY mode is enabled
13 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT13
1 - STANDBY mode is enabled
12 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT12
1 - STANDBY mode is enabled
11 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT11
1 - STANDBY mode is enabled
10 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT10
1 - STANDBY mode is enabled
Table continues on the next page...
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Memory Map and register definition
Field Description
9 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT9
1 - STANDBY mode is enabled
8 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT8
1 - STANDBY mode is enabled
7 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT7
1 - STANDBY mode is enabled
6 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT6
1 - STANDBY mode is enabled
5 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT5
1 - STANDBY mode is enabled
4 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT4
1 - STANDBY mode is enabled
3 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT3
1 - STANDBY mode is enabled
2 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT2
1 - STANDBY mode is enabled
1 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT1
1 - STANDBY mode is enabled
0 Standy mode
STBY_EN_SET 0 - STANDBY mode is disabled
POINT0
1 - STANDBY mode is enabled
17.5.1.31 FBB_M7_CONFIGURE_REGISTER (FBB_M7_CONFIGURE)
This register is used in GPC mode to make selection of BIAS configure function.
Software and Hardware (GPC) mode
• WB_EN : Wellbias Enable
• WB_CFG_1P8[1] -
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Chapter 17 Power Management Unit (PMU)
• 0 : RBB
• 1 : FBB
• WB_PWR_SW_EN_1P8 -
• [0] FBB M7
• [1] RBB LPSR
• [2] RBB SOG
• WBB_VDD_SEL - LPSR_DIG_LDO or DCDC
• WB_CFG_1P8[4:2] - Select size of of bias area.
• WB_CFG_1P8[5] - Adaptive function
• WB_CFG_1P8[8:6] - Oscillator bits
17.5.1.31.1 Offset
Register Offset
FBB_M7_CONFIGURE 780h
17.5.1.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
REGULATOR_STRENGTH
OSCILLATOR_BITS
WB_CFG_NW
WB_CFG_PW
Reserved
Reset 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 1
17.5.1.31.3 Fields
Field Description
31-14 Reserved
—
Table continues on the next page...
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Memory Map and register definition
Field Description
13-11 regulator_strength
REGULATOR_S This field is used in GPC mode to select regulator_strength. The hardware and software mode settings
TRENGTH are the same. See WB_CFG_1P8[4:2] for details.
10-8 oscillator_bits
OSCILLATOR_ This field is used in GPC mode to select size of oscillator bits. The hardware and software mode settings
BITS are the same. See WB_CFG_1P8[8:6] for details.
7-4 wb_cfg_nw
WB_CFG_NW This field is used in GPC mode and it takes control of Software mode NWELL Output Voltage Range
Selection defined by WB_NW_LVL_1P8. RBB function enabled; valid range is 0000 ~ 1000.
3-0 wb_cfg_pw
WB_CFG_PW This field is used in GPC mode and it takes control of Software mode PWELL Output Voltage Range
Selection defined by WB_PW_LVL_1P8. Valid range is 0000 ~ 1000.
17.5.1.32 RBB_LPSR_CONFIGURE_REGISTER (RBB_LPSR_CON
FIGURE)
This register is used in GPC mode to make selection of BIAS configure function.
Software and Hardware (GPC) mode
• WB_EN : Wellbias Enable
• WB_CFG_1P8[1] -
• 0 : RBB
• 1 : FBB
• WB_PWR_SW_EN_1P8 -
• [0] FBB M7
• [1] RBB LPSR
• [2] RBB SOG
• WBB_VDD_SEL - LPSR_DIG_LDO or DCDC
• WB_CFG_1P8[4:2] - Select size of of bias area.
• WB_CFG_1P8[5] - Adaptive function
• WB_CFG_1P8[8:6] - Oscillator bits
17.5.1.32.1 Offset
Register Offset
RBB_LPSR_CONFIGU 790h
RE
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Chapter 17 Power Management Unit (PMU)
17.5.1.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
REGULATOR_STRENGTH
OSCILLATOR_BITS
WB_CFG_NW
WB_CFG_PW
Reserved
Reset 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0
17.5.1.32.3 Fields
Field Description
31-14 Reserved
—
13-11 regulator_strength
REGULATOR_S This field is used in GPC mode to select regulator_strength. The hardware and software mode settings
TRENGTH are the same. See WB_CFG_1P8[4:2] for details.
10-8 oscillator_bits
OSCILLATOR_ This field is used in GPC mode to select size of oscillator bits. The hardware and software mode settings
BITS are the same. See WB_CFG_1P8[8:6] for details.
7-4 wb_cfg_nw
WB_CFG_NW This field is used in GPC mode and it takes control of Software mode NWELL Output Voltage Range
Selection defined by WB_NW_LVL_1P8. RBB function enabled; valid range is 0000 ~ 1000.
3-0 wb_cfg_pw
WB_CFG_PW This field is used in GPC mode and it takes control of Software mode PWELL Output Voltage Range
Selection defined by WB_PW_LVL_1P8. Valid range is 0000 ~ 1000.
17.5.1.33 RBB_SOC_CONFIGURE_REGISTER (RBB_SOC_CONF
IGURE)
This register is used in GPC mode to make selection of BIAS configure function.
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Memory Map and register definition
Software and Hardware (GPC) mode
• WB_EN : Wellbias Enable
• WB_CFG_1P8[1] -
• 0 : RBB
• 1 : FBB
• WB_PWR_SW_EN_1P8 -
• [0] FBB M7
• [1] RBB LPSR
• [2] RBB SOG
• WBB_VDD_SEL - LPSR_DIG_LDO or DCDC
• WB_CFG_1P8[4:2] - Select size of of bias area.
• WB_CFG_1P8[5] - Adaptive function
• WB_CFG_1P8[8:6] - Oscillator bits
17.5.1.33.1 Offset
Register Offset
RBB_SOC_CONFIGURE 7A0h
17.5.1.33.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
REGULATOR_STRENGTH
OSCILLATOR_BITS
WB_CFG_NW
WB_CFG_PW
Reserved
Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0
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Chapter 17 Power Management Unit (PMU)
17.5.1.33.3 Fields
Field Description
31-14 Reserved
—
13-11 regulator_strength
REGULATOR_S This field is used in GPC mode to select regulator_strength. The hardware and software mode settings
TRENGTH are the same. See WB_CFG_1P8[4:2] for details.
10-8 oscillator_bits
OSCILLATOR_ This field is used in GPC mode to select size of oscillator bits. The hardware and software mode settings
BITS are the same. See WB_CFG_1P8[8:6] for details.
7-4 wb_cfg_nw
WB_CFG_NW This field is used in GPC mode and it takes control of Software mode NWELL Output Voltage Range
Selection defined by WB_NW_LVL_1P8. RBB function enabled; valid range is 0000 ~ 1000.
3-0 wb_cfg_pw
WB_CFG_PW This field is used in GPC mode and it takes control of Software mode PWELL Output Voltage Range
Selection defined by WB_PW_LVL_1P8. Valid range is 0000 ~ 1000.
17.5.1.34 REFTOP_OTP_TRIM_VALUE_REGISTER (REFTOP_OTP_T
RIM_VALUE)
This is the control for TRIM bus control. For ANATOP, this is the source from software
register inside ANATOP.
17.5.1.34.1 Offset
Register Offset
REFTOP_OTP_TRIM_ 7B0h
VALUE
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17.5.1.34.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFTOP_IBZTCADJ
REFTOP_TRIM_EN
REFTOP_VBGADJ
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.34.3 Fields
Field Description
31-7 Reserved
—
6 REFTOP_TRIM_EN
REFTOP_TRIM This is the control for TRIM bus control. For ANATOP, this is the source from software register inside
_EN ANATOP.
5-3 REFTOP_VBGADJ
REFTOP_VBGA This is the control for TRIM bus control. For ANATOP, this is the source from software register inside
DJ ANATOP.
2-0 REFTOP_IBZTCADJ
REFTOP_IBZT This is the control for TRIM bus control. For ANATOP, this is the source from software register inside
CADJ ANATOP.
17.5.1.35 LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER (LPSR_
1P8_LDO_OTP_TRIM_VALUE)
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Chapter 17 Power Management Unit (PMU)
17.5.1.35.1 Offset
Register Offset
LPSR_1P8_LDO_OTP_ 7D0h
TRIM_VALUE
17.5.1.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPSR_LDO_1P8_TRIM_EN
LPSR_LDO_1P8_TRIM
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17.5.1.35.3 Fields
Field Description
31-3 Reserved
—
2 LPSR_LDO_1P8_TRIM_EN
LPSR_LDO_1P This is the control for TRIM bus control. For ANATOP, this is the source from software register inside
8_TRIM_EN ANATOP.
1-0 LPSR_LDO_1P8_TRIM
LPSR_LDO_1P This is the control for TRIM bus control. For ANATOP, this is the source from software register inside
8_TRIM ANATOP.
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Memory Map and register definition
17.5.2 PMU_LDO_SNVS register descriptions
17.5.2.1 LDO_SNVS memory map
ANADIG base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
510 PMU_LDO_LPSR_ANA_REGISTER (PMU_LDO_LPSR_ANA) 32 RW 0000_0108
520 PMU_LDO_LPSR_DIG_2_REGISTER (PMU_LDO_LPSR_DIG_2) 32 RW 0000_0002
530 PMU_LDO_LPSR_DIG_REGISTER (PMU_LDO_LPSR_DIG) 32 RW 0130_1C05
17.5.2.2 PMU_LDO_LPSR_ANA_REGISTER (PMU_LDO_LPSR_ANA)
PMU_LDO_LPSR_ANA_Regulator_Control_Register
This register defines the control and status bits for LDO_LPSR_ANA regulator. This
regulator is designed to power the digital portions of the analog cells
17.5.2.2.1 Offset
Register Offset
PMU_LDO_LPSR_ANA 510h
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Chapter 17 Power Management Unit (PMU)
17.5.2.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PULL_DOWN_20UA_EN
TRACK_MODE_EN
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALWAYS_4MA_PULLDOWN_EN
LPSR_ANA_CONTROL_MODE
PULL_DOWN_2MA_EN
BYPASS_MODE_EN
STANDBY_EN
REG_DISABL
REG_LP_E
Reserved
Reserved
Reserved
Reserved
W
N
E
Reset 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0
17.5.2.2.3 Fields
Field Description
31-21 Reserved
— Always set to zero (0).
20 pull_down_20ua_en
PULL_DOWN_2 High: enable 20uA loading to prevent the overshoot.
0UA_EN
19 Track Mode Enable
TRACK_MODE This bit lets the power switch enter a preparation stage that allows power supply switching between LDO
_EN and DCDC. This bit should be set before the power supply switch and cleared after power switch is
complete. This bit is used during software mode.
0 - Normal use
1 - Switch preparation
18-11 Reserved
— Always set to zero (0).
10-9 Reserved
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Memory Map and register definition
Field Description
— Always set to zero (0).
8 always_4ma_pulldown_en
ALWAYS_4MA_ High: enable 4mA loading to prevent the big voltage drop when a sharp loading coming.It's recommend
PULLDOWN_E to set this bit to high under the reset, and set it to low under the normal use case.
N
7 Reserved
— Always set to zero (0).
6 standby_en
STANDBY_EN This is the standby mode for LDO_LPSR_ANA
5 bypass_mode_en
BYPASS_MOD Work together with track_mode_enable to ensure the LDO_1P8 can be bypassed by DCDC_1P8 well.
E_EN
This the bypass mode for lpsr_ana
4 LPSR_ANA_CONTROL_MODE
LPSR_ANA_CO LPSR_ANA_CONTROL_MODE
NTROL_MODE
This bit is the mode select between software mode and GPC mode.
0 - SW Control. Software control mode
1 - HW Control. Hardware / GPC control mode
3 pull_down_2ma_en
PULL_DOWN_2 High: enable 2mA loading to prevent the overshoot.
MA_EN
2 reg_disable
REG_DISABLE high: disable the output of "vreg_1p8"
1 Reserved
—
0 reg_lp_en
REG_LP_EN High: enable the low-power mode of the ldo
17.5.2.3 PMU_LDO_LPSR_DIG_2_REGISTER
(PMU_LDO_LPSR_DIG_2)
PMU_LDO_LPSR_DIG_2_Regulator_Control Register
This register defines the control and status bits for LDO_LPSR_DIG regulator. This
regulator is designed to power the digital portions of the analog cells
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Chapter 17 Power Management Unit (PMU)
17.5.2.3.1 Offset
Register Offset
PMU_LDO_LPSR_DIG_2 520h
17.5.2.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VOLTAGE_STEP_INC
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
17.5.2.3.3 Fields
Field Description
31-2 Reserved
— Always set to zero (0).
1-0 voltage_step_inc
VOLTAGE_STE voltage_step_time for lpsr_dig 0x00:15us 0x01:25us 0x10:50us 0x11:100us
P_INC
17.5.2.4 PMU_LDO_LPSR_DIG_REGISTER (PMU_LDO_LPSR_DIG)
PMU_LDO_LPSR_DIG_Regulator_Control_Register
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17.5.2.4.1 Offset
Register Offset
PMU_LDO_LPSR_DIG 530h
17.5.2.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VOLTAGE_SELECT
TRACKING_MODE
BYPASS_MODE
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPSR_DIG_CONTROL_MODE
STANDBY_EN
Reserved
Reserved
Reserved
REG_E
W
N
Reset 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1
17.5.2.4.3 Fields
Field Description
31-25 Reserved
— Always set to zero (0).
24-20 VOLTAGE_SELECT
VOLTAGE_SEL VOLTAGE SELECT for LPSR_DIG
ECT
For lpsr_dig voltage switch to different voltage
In SW mode, software is responsible to take care of the stepping time.
In HW mode, hardware is responsible to take care of the stepping time.
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Chapter 17 Power Management Unit (PMU)
Field Description
During the mode transistion, in case the lpsr_dig voltage is out of table, software is responsible to take
care of the stepping time (i.e. mode transist), software calculates the steps difference multiply the
stepping requirement, after the voltage is stable. GPC mode transistion is allowed. The values below are
the stable voltage with the range in parentheses (e.g. Stable Voltage (Range)V).
00000 - Stable Voltage (range). 0.631 (+0.039)V
00001 - Stable Voltage (range). 0.65 (+0.041)V
00010 - Stable Voltage (range). 0.67 (+0.041)V
00011 - Stable Voltage (range). 0.689 (+0.043)V
00100 - Stable Voltage (range). 0.709 (+0.044)V
00101 - Stable Voltage (range). 0.728 (+0.045)V
00110 - Stable Voltage (range). 0.748 (+0.046)V
00111 - Stable Voltage (range). 0.767 (+0.047)V
01000 - Stable Voltage (range). 0.786 (+0.049)V
01001 - Stable Voltage (range). 0.806 (+0.05)V
01010 - Stable Voltage (range). 0.825 (+0.051)V
01011 - Stable Voltage (range). 0.845 (+0.052)V
01100 - Stable Voltage (range). 0.864 (+0.054)V
01101 - Stable Voltage (range). 0.883 (+0.055)V
01110 - Stable Voltage (range). 0.903 (+0.056)V
01111 - Stable Voltage (range). 0.922 (+0.057)V
10000 - Stable Voltage (range). 0.942 (+0.058)V
10001 - Stable Voltage (range). 0.961 (+0.06)V
10010 - Stable Voltage (range). 0.981 (+0.06)V
10011 - Stable Voltage (range). 1 (+0.062)V
10100 - Stable Voltage (range). 1.019 (+0.063)V
10101 - Stable Voltage (range). 1.039 (+0.064)V
10110 - Stable Voltage (range). 1.058 (+0.066)V
10111 - Stable Voltage (range). 1.078 (+0.066)V
11000 - Stable Voltage (range). 1.097 (+0.068)V
11001 - Stable Voltage (range). 1.117 (+0.069)V
11010 - Stable Voltage (range). 1.136 (+0.07)V
11011 - Stable Voltage (range). 1.155 (+0.072)V
11100 - Stable Voltage (range). 1.175 (+0.072)V
11101 - Stable Voltage (range). 1.194 (+0.074)V
11110 - Stable Voltage (range). 1.214 (+0.075)V
11111 - Stable Voltage (range). 1.233 (+0.076)V
19 Reserved
— Always set to zero (0).
18 bypass_mode
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Memory Map and register definition
Field Description
BYPASS_MOD bypass_mode This mode is defined by ANALOG IP, and this bit is software mode control bit to enter this
E bypass mode or not.
17 tracking_mode
TRACKING_MO tracking_mode. This mode is defined by ANALOG IP, and this bit is software mode control bit to enter this
DE tracking mode or not.
16-7 Reserved
— Always set to zero (0).
6 standby_en
STANDBY_EN standby_en There is Standby mode defined in SOC, this bit is about whether to enter standby mode for
lpsr_dig
5 LPSR_DIG_CONTROL_MODE
LPSR_DIG_CO lpsr_dig_control_mode For LPSR DIG there is two mode for operation, one is software mode, the other is
NTROL_MODE GPC mode.
0 - SW Control. Software control mode
1 - HW Control. Hardware / GPC control mode
4-3 Reserved
— Always set to zero (0).
2 ENABLE_ILIMIT
REG_EN Control bit to enable the current-limit circuitry in the regulator.
1-0 Reserved
— Always set to zero (0).
17.5.3 PMU_LDO_SNVS_DIG register descriptions
17.5.3.1 LDO_SNVS_DIG memory map
PMU_LDO_SNVS_DIG base address: 40C8_4000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
540 PMU_LDO_SNVS_DIG_REGISTER (PMU_LDO_SNVS_DIG) 32 RW 0000_0001
17.5.3.2 PMU_LDO_SNVS_DIG_REGISTER (PMU_LDO_SNVS_DIG)
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Chapter 17 Power Management Unit (PMU)
PMU_LDO_SNVS_DIG
This register defines the control and status bits for LDO_SNVS regulator. This regulator
is designed to power the digital portions of the analog cells
17.5.3.2.1 Offset
Register Offset
PMU_LDO_SNVS_DIG 540h
17.5.3.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEST_OVERRID
REG_LP_E
Reserved
REG_E
W
N
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
17.5.3.2.3 Fields
Field Description
31-3 Reserved
— Always set to zero (0).
2 REG_EN
REG_EN Control bit to enable the LDO or not.
1 test_override
TEST_OVERRI test_override
DE
0 REG_LP_EN
REG_LP_EN reg_lp_en, LDO power mode control. LP mode ; HP mode. Defined by identical LDO.
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17.5.4 IPS Domain register descriptions
17.5.4.1 IPS_DOMAIN memory map
IPS Domain base address: 40C8_7C00h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Slot Control Register (SLOT0_CTRL) 32 RW 0000_000F
10 Slot Control Register (SLOT1_CTRL) 32 RW 0000_000F
20 Slot Control Register (SLOT2_CTRL) 32 RW 0000_000F
30 Slot Control Register (SLOT3_CTRL) 32 RW 0000_000F
40 Slot Control Register (SLOT4_CTRL) 32 RW 0000_000F
50 Slot Control Register (SLOT5_CTRL) 32 RW 0000_000F
60 Slot Control Register (SLOT6_CTRL) 32 RW 0000_000F
70 Slot Control Register (SLOT7_CTRL) 32 RW 0000_000F
80 Slot Control Register (SLOT8_CTRL) 32 RW 0000_000F
90 Slot Control Register (SLOT9_CTRL) 32 RW 0000_000F
A0 Slot Control Register (SLOT10_CTRL) 32 RW 0000_000F
B0 Slot Control Register (SLOT11_CTRL) 32 RW 0000_000F
C0 Slot Control Register (SLOT12_CTRL) 32 RW 0000_000F
D0 Slot Control Register (SLOT13_CTRL) 32 RW 0000_000F
E0 Slot Control Register (SLOT14_CTRL) 32 RW 0000_000F
F0 Slot Control Register (SLOT15_CTRL) 32 RW 0000_000F
100 Slot Control Register (SLOT16_CTRL) 32 RW 0000_000F
110 Slot Control Register (SLOT17_CTRL) 32 RW 0000_000F
120 Slot Control Register (SLOT18_CTRL) 32 RW 0000_000F
130 Slot Control Register (SLOT19_CTRL) 32 RW 0000_000F
140 Slot Control Register (SLOT20_CTRL) 32 RW 0000_000F
150 Slot Control Register (SLOT21_CTRL) 32 RW 0000_000F
160 Slot Control Register (SLOT22_CTRL) 32 RW 0000_000F
170 Slot Control Register (SLOT23_CTRL) 32 RW 0000_000F
180 Slot Control Register (SLOT24_CTRL) 32 RW 0000_000F
190 Slot Control Register (SLOT25_CTRL) 32 RW 0000_000F
1A0 Slot Control Register (SLOT26_CTRL) 32 RW 0000_000F
1B0 Slot Control Register (SLOT27_CTRL) 32 RW 0000_000F
1C0 Slot Control Register (SLOT28_CTRL) 32 RW 0000_000F
1D0 Slot Control Register (SLOT29_CTRL) 32 RW 0000_000F
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Chapter 17 Power Management Unit (PMU)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
1E0 Slot Control Register (SLOT30_CTRL) 32 RW 0000_000F
1F0 Slot Control Register (SLOT31_CTRL) 32 RW 0000_000F
200 Slot Control Register (SLOT32_CTRL) 32 RW 0000_000F
210 Slot Control Register (SLOT33_CTRL) 32 RW 0000_000F
220 Slot Control Register (SLOT34_CTRL) 32 RW 0000_000F
230 Slot Control Register (SLOT35_CTRL) 32 RW 0000_000F
240 Slot Control Register (SLOT36_CTRL) 32 RW 0000_000F
250 Slot Control Register (SLOT37_CTRL) 32 RW 0000_000F
17.5.4.2 Slot Control Register (SLOT0_CTRL - SLOT37_CTRL)
Table 17-3. Slot Assignments
Slot Number Assignment
0 ANATOP_CTRL
1 48M
2 24M
3 400M
4 16M
5 OSC TRIM
6 PLL_ARM
7 SYS_PLL3 (480 PLL)
8 SYS_PLL2 (528 PLL)
9 SYS_PLL1 (1G PLL)
10 PLL_AUDIO
11 PLL_VIDEO
12 TEMPSENSOR
13 ANAMUX
14 PWRDET
15 TEMPSENSOR_OTP
16 PWR_OTP
17 PLL_LDO
18 LPSR_ANA
19 LPSR_DIG
20 SNVS_DIG
21 BIAS
22 BANDGAP
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Table 17-3. Slot Assignments (continued)
Slot Number Assignment
23 CKGB
24 SET_POINT
25 BANDGAP_OTP
26 WB_OTP
27 LPSR_ANA_OTP
28 MISC
29 LVDS
30 AI_SOC
31 AI_1G
32 AI_AUDIO
33 AI_VIDEO
34 AI_LPSR
35 AI_TMPSNS
36 AI_400M
37 AI_400M
17.5.4.2.1 Offset
For n = 0 to 37:
Register Offset
SLOTn_CTRL 0h + (n × 10h)
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Chapter 17 Power Management Unit (PMU)
17.5.4.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALLOW_NONSECURE
LOCK_CONTROL
ALLOW_USER
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKED_DOMAIN_ID
DOMAIN_LOCK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
17.5.4.2.3 Fields
Field Description
31 Lock control of this slot
LOCK_CONTR 0 - Do not lock the control register of this slot
OL
1 - Lock the control register of this slot
30-18 Reserved
—
17 Allow user write access to this domain control register or domain register
ALLOW_USER 0 - Do not allow user write access
1 - Allow user write access
16 Allow non-secure write access to this domain control register or domain register
ALLOW_NONS 0 - Do not allow non-secure write access
ECURE
1 - Allow non-secure write access
15 Lock domain ID of this slot
DOMAIN_LOCK 0 - Do not lock the domain ID
1 - Lock the domain ID
14-4 Reserved
—
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Memory Map and register definition
Field Description
3-0 Domain ID of the slot to be locked
LOCKED_DOM Domain id3~0 maps to bit3~0.
AIN_ID
It indicates whether related domain can write to domain register or not.
1'b1 indicates domain write access is allowed. while domain id is locked, only related domain can write to
bit31 and bit17~16
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Chapter 18
PHY LDO (PHY_LDO)
18.1 Chip-specific PHY LDO information
Table 18-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
18.2 Overview
The PHY LDO creates a regulated 1.0V output voltage for digital PHYs from an external
1.8V source. The PHY LDO is controlled through the AI interface.
18.2.1 Features
The PHY LDO has the following featurest:
• Analog 200 mA linear regulator
• 1.8V +/- 10% VDD external input
• 1.0V output
• Programmable adjustment in 0.25mV steps (0.6V to 1.375V)
• AI Interface
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18.3 Memory Map and register definition
This section includes the PHY LDO module memory map and detailed descriptions of all
registers.
NOTE
For related IPS Domain Slot control, please see IPS Domain
Registers in Power Management Unit (PMU) chapter.
18.3.1 register descriptions
18.3.1.1 PHY LDO Memory Map
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Analog Control Register CTRL0 (CTRL0) 32 RW 0000_0000
4 Analog Control Register CTRL0 (CTRL0_SET) 32 RW 0000_0000
8 Analog Control Register CTRL0 (CTRL0_CLR) 32 RW 0000_0000
C Analog Control Register CTRL0 (CTRL0_TOG) 32 RW 0000_0000
50 Analog Status Register STAT0 (STAT0) 32 RO 0000_0000
54 Analog Status Register STAT0 (STAT0_SET) 32 RO 0000_0000
58 Analog Status Register STAT0 (STAT0_CLR) 32 RO 0000_0000
5C Analog Status Register STAT0 (STAT0_TOG) 32 RO 0000_0000
18.3.1.2 Analog Control Register CTRL0 (CTRL0)
This register contains analog control bits.
18.3.1.2.1 Offset
Register Offset Description
CTRL0 0h Analog Control Register CTRL0
CTRL0_SET 4h Writing a 1 to a bit in this register sets the
corresponding bit in CTRL0
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Chapter 18 PHY LDO (PHY_LDO)
Register Offset Description
CTRL0_CLR 8h Writing a 1 to a bit in this register clears the
corresponding bit in CTRL0
CTRL0_TOG Ch Writing a 1 to a bit in this register toggles the
corresponding bit in CTRL0
18.3.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINREG_PWRUPLOAD_DIS
LINREG_OUTPUT_TRG
LINREG_PHY_ISO_B
LINREG_ILIMIT_EN
LINREG_E
Reserved
Reserved
Reserved
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.3.1.2.3 Fields
Field Description
31-16 Reserved
— This read-only field is reserved and always has the value 0.
15 Isolation control for attached PHY load
LINREG_PHY_I This control bit is to be used by the system controller to isolate the attached PHY load when the LinReg is
SO_B powered down. During a power-up event of the regulator it is expected that this control signal is set high
at least 100us after the main regulator is enabled. During a power-down event of the regulator it is
expected that this control signal is set low before the main regulator is disabled/power-down.
14-12 Reserved
— This read-only field is reserved and always has the value 0.
11-9 Reserved
— This read-only field is reserved and always has the value 0.
8-4 LinReg output voltage target setting
LINREG_OUTP LinReg output voltage target setting. The nominal voltage step per code is 25mV. Setting the output
UT_TRG voltage beyond the technology reliability limit is not recommended.
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Memory Map and register definition
Field Description
00000 - Set output voltage to x.xV
10000 - Sets output voltage to 1.0V
11111 - Set output voltage to x.xV
3 Reserved
— This read-only field is reserved and always has the value 0.
2 LinReg current-limit enable
LINREG_ILIMIT LinReg current-limit enable. Setting this bit will enable the current-limiter in the regulator.
_EN
1 LinReg power-up load disable
LINREG_PWRU LinReg power-up load disable control bit.
PLOAD_DIS
0 - Internal pull-down enabled
1 - Internal pull-down disabled
0 LinrReg master enable
LINREG_EN LinReg master enable. Setting this bit will enable the regulator.
18.3.1.3 Analog Status Register STAT0 (STAT0)
This register contains analog status bits.
18.3.1.3.1 Offset
Register Offset Description
STAT0 50h Analog Status Register STAT0
STAT0_SET 54h Writing a 1 to a bit in this register sets the
corresponding bit in STAT0
STAT0_CLR 58h Writing a 1 to a bit in this register clears the
corresponding bit in STAT0
STAT0_TOG 5Ch Writing a 1 to a bit in this register toggles the
corresponding bit in STAT0
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Chapter 18 PHY LDO (PHY_LDO)
18.3.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R LINREG_STAT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18.3.1.3.3 Fields
Field Description
31-4 Reserved
— This read-only field is reserved and always has the value 0.
3-0 LinReg Status Bits
LINREG_STAT LinReg status bits
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Memory Map and register definition
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Chapter 19
General Power Controller (GPC)
19.1 Chip-specific General Power Controller (GPC)
information
Table 19-1. Reference links to related information
Topic Related module(s) Reference
System memory map - System Memory Map
Clocking CCM Clock Management
Clock Control Module (CCM)
Power management PMU Power Management
Power Management Unit
Signal multiplexing IOMUX External Signals and Pin Multiplexing
IOMUX
Interrupts, DMA Events - Interrupts, DMA Events and XBAR Assignments
and XBAR Assignments
19.2 Overview
The General Power Controller (GPC) is the centralized power controller, which controls
the power mode of the processor(s). The GPC takes the Wait For Interrupt (WFI) signal
from CPU platforms, and wakeup events from peripherals, to determine the power mode
based on the GPC power management policy. The GPC can also control the power mode
transition.
19.2.1 Block diagram
The GPC block consists of the following sub-modules:
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Overview
• CPU Mode Control (CMC): It contains CPU mode controllers, one for each CPU
platform. They control CPU mode of CPU platforms and their private resources.
• UPI CM Mapping (UPI): The connection between CMC and CPU platform is
directly hard-wired, but CPU platform can be assigned to any domain in the system.
So this block is used to map CPU mode control signals into the correct domain.
• Setpoint Control (SPC): This controls Setpoint status and transition of system
resources.
• Standby Control (SBC): It indicates which resource controllers go in and out from
standby mode
The figure below shows the block diagram of the General Power Controller.
UPI Control
UPI
HANDSHAKE
CPU_MODE
n
IRQ
n CMCn SBC SBC Control
WFI
SPC
SPC Control
Figure 19-1. GPC block diagram
19.2.2 Features
The GPC includes the following features:
• Standby management
• Domain access control
• Controllable steps of sleep and wakeup sequence
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Chapter 19 General Power Controller (GPC)
19.3 Functional description
The following sections describe functional details of the GPC module.
19.3.1 CPU Mode Control (CMC)
The CPU mode is a power mode of the CPU platform. The following are the four CPU
modes:
Table 19-2. CPU Modes
CPU Mode Description
RUN The CPU core is active and running under normal operation. All the blocks inside the
CPU platform can be accessed when needed. The state of private resources are fully
controlled by software configuration.
WAIT The CPU is in WFI/WFE state, but can to get back to RUN mode with very short
latency. In typical applications, the CPU will enter WAIT mode whenever there is no
active thread running. In WAIT mode, the clock to the CPU core is gated off, the cache
is clock gated, and the TCM is still active since there are other modules, such as DMA,
that still needs access to it.
STOP The CPU is in WFI/WFE state, and does not require an extremely short exit time. In
STOP mode, the clocks to the CPU core, Cache, and TCM are all gated off. The clocks
to the bus and peripherals are also gated off. This is the lowest power consumption
mode without losing the state of the peripheral. When exiting from STOP mode, there is
no need to re-initialize the peripherals.
SUSPEND Entering SUSPEND mode is for lowest power consumption, and exit time is not critical.
In SUSPEND mode, CPU, Cache, and peripherals are all power gated. The biggest
difference between SUSPEND and STOP mode is the peripherals will be power gated.
Because the peripherals are power gated, entering SUSPEND mode requires the CPU
to save the state of the peripherals. When exiting from SUSPEND mode, the CPU
needs to restore these states.
CPU Mode transitions happen when the following events occur:
• Sleep Event: CPU enters sleep state with WFI/WFE instruction
• Wakeup Event: Any unmasked IRQ wakeup
On a Sleep Event, the CPU has the option to enter WAIT/STOP/SUSPEND mode, or stay
in RUN mode. The transition to WAIT/STOP/SUSPEND is called the sleep sequence,
and the next state is configured by CM_MODE_CTRL[CPU_MODE_TARGET].
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Functional description
When CPU is in WAIT/STOP/SUSPEND mode, a wakeup request can wake the CPU,
and bring it back to RUN mode. This is transition is called the wakeup sequence. The
CM_IRQ_WAKEUP_MASK_n register selects which IRQs can wakeup the CPU
platform. There are also non-IRQ requests, which can wakeup the CPU. These non-IRQ
requests are configured by the CM_NON_IRQ_WAKEUP_MASK register.
During a CPU mode transition, the GPC communicates with the system resource
controllers by sending the target CPU mode and transition step. Please see the UPI
interface for more detials.
If a resource is set as private to a single CPU platform, the resource's power state will
change with the CPU platform's mode. If a resource is set as shared by multiple CPU
platforms, the resource controller needs to look at all the current modes of the CPU
platforms to determine the power state of the resource.
19.3.2 Setpoint Control (SPC)
The GPC supports 16 Setpoints. Setpoints are implemented to configure the power state
of Public Resources. Public Resources are system-level resources that aren't owned or
controlled by any of the CPU platforms.
During Setpoint transition, GPC communicates with system resource controllers through
the Unified Power Management Interface (UPI). Setpoint transition is triggered by a
request from any of the CPU platforms. The triggers include the following events:
• CPU Sleep Event
• A sleep event triggers a CPU mode transition, and CPU platform also requests a
Setpoint transition after CPU mode transition completes. The field
CM_SP_CTRL[CPU_SP_SLEEP_EN] controls whether Setpoint transition will
be triggered, and the field CM_SP_CTRL[CPU_SP_SLEEP] controls which
Setpoint the CMC want to transfer to.
• CPU Wakeup Event
• An unmasked wakeup event triggers a CPU mode transition, and CPU platform
requests for a Setpoint transition before CPU mode transition starts. The field
CM_SP_CTRL[CPU_SP_WAKEUP_EN] controls whether Setpoint transition
will be triggered, and the fields CM_SP_CTRL[CPU_SP_WAKEUP] and
CM_SP_CTRL[CPU_SP_WAKEUP_SEL] control which set point the CMC
want to transfer to.
• Software
• CPU platform is in RUN mode and the SW running on the CPU core makes a
write operation to CMC register CPU_SP_RUN_EN to request for a Setpoint
transition. Register CPU_SP_RUN controls which Setpoint the CMC want to
transfer to.
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Chapter 19 General Power Controller (GPC)
With CPU Mode and Setpoint defined properly, the Power Mode of a system is defined
as a combination of the CPU Mode and Setpoint.
19.3.3 System Setpoint management
The SPC receives a Setpoint change request from CMCs, it then determines the Setpoint
of the system, and manages the transition sequence. When a CMC Setpoint request is
accepted, the Setpoint value can then be read from SPC SP_ACCEPTED_CPUn register.
If multiple CPU platforms want to enter different Setpoints, the SPC needs to calculate
the final target Setpoint. There is a mapping table between each Setpoint of a CPU
platform and the Setpoint, which it can accept. For example, CPU1 requests the system to
transit to Setpoint 7 after it transits into STOP mode. CPU1 must provide a Setpoint list
to show which Setpoints are also allowed besides SP-7. This is configured by the CMC
CM_SPx_MAPPING Register. Below are examples of Setpoint list configurations:
• If CPU1_SP7_MAPPING register is set to 16’b00000000_10011111, CPU1 requests
system to transition to SP-7 (bit 7), but also allows transitions to SP-0,1,2,3,4 (bits 0
to 4).
• If CPU0_SP4_MAPPING register is set to 16’b00000000_00010000, CPU0 has
requested the system to transit to SP-4 after STOP.
In the SPC, the SP_SYS_STAT[SYS_SP_ALLOWED] field will be the ANDed result of
allowed Setpoints from all CMCs. If all bits in SP_SYS_STAT[SYS_SP_ALLOWED] is
0, it means there are no Setpoints allowed by both platforms. This would be an invalid
state, and there should be no Setpoint transition in this condition. GPC should generate an
error IRQ. Below is an example of allowed Setpoint configuration:
• If SP_SYS_STAT[SYS_SP_ALLOWED] is 16’b00000000_00010000, it means
only SP-4 is allowed. The system should transit to this Setpoint.
The calculated Setpoint number can be read at SPC CM_SP_STAT[CPU_SP_TARGET]
register.
If more than one bit in SP_SYS_STAT[SYS_SP_ALLOWED] is set to 1, the Setpoint
will be picked based on the following rules:
• If the allowed Setpoints match only one SP_CPU_REQ[SP_ACCEPTED_CPUn],
this Setpoint will be used as SPC CM_SP_STAT[CPU_SP_TARGET]
• If the allowed Setpoints match more than one
SP_CPU_REQ[SP_ACCEPTED_CPUn], the matched Setpoint with highest priority
will be used as SPC CM_SP_STAT[CPU_SP_TARGET]
• If the allowed Setpoints do not match any of the
SP_CPU_REQ[SP_ACCEPTED_CPUn], the CM_SP_STAT[CPU_SP_TARGET]
will be the allowed Setpoint with highest priority
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Functional description
NOTE
The priority settings are set in the SPC
SP_PRIORITY_x[SYS_SPn_PRIORITY] register
configuration.
19.3.4 Standby Control (SBC)
Standby mode is a low-power mode that has distinguishing settings outside of CPU mode
and Setpoint mode. Standby mode is related to state of all CPU platforms and has a much
shorter transition time than Setpoint.
The CMC can send a standby request to SBC. The fields
CM_STBY_CTRL[STBY_WAIT], CM_STBY_CTRL[STBY_STOP], and
CM_STBY_CTRL[STBY_SUSPEND] will determine if the chip enters into Standby
mode when the CPU enters WAIT mode, STOP mode, or SUSPEND mode respectively.
The SBC maintains the system standby status, and only when all CPU platforms send
standby request, can the system enter into Standby mode. If a CPU is disabled by FUSE,
GPC considers it in Standby mode by default.
19.3.5 Unified power management interface (UPI)
GPC does not control the state of the resource directly. During power mode transition, it
communicates with the resource controllers through the UPI (Unified Power management
Interface) to accomplish the power mode transition.
Handshake Method:
Figure 19-2. Handshake
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Chapter 19 General Power Controller (GPC)
19.3.6 Low Power Sequence
19.3.6.1 CPU mode transition flow
Each CMC has a state machine to control the sequence of CPU mode transition.
When CMC receives a sleep request from CPU platform, it starts the sleep sequence, it
cannot be broken by wakeup request until finishing SLEEP_POWER request. In
SLEEP_SP step, the SPC runs set point transition flow. In SLEEP_STBY step, the SBC
runs standby transition flow. After the sleep sequence finishes, the CMC stays at
IDLE_SLEEP and waits for a wakeup event to start wakeup sequence, which is showed
in the left part of the diagram.
DIRECT_SP
WAKEUP_LPCG SLEEP_LPCG
WAKEUP_PLL WAKEUP_SSAR SLEEP_SSAR SLEEP_PLL
IDLE_RUN
WAKEUP_ISO SLEEP_ISO
IDLE_SLEEP
WAKEUP_RESET SLEEP_RESET
WAKEUP_SP SLEEP_SP
WAKEUP_POWER SLEEP_POWER
DIRECT_SP SLEEP_STBY
Figure 19-3. CPU Mode Transition Flow
19.3.6.2 Setpoint transition flow
The SPC has a state machine to control the sequence of Setpoint transition.
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Functional description
The SPC state machine starts after it receives a Setpoint change request from CMC. SPC
uses one state to calculate whether or not it needs to change Setpoint based on all CMC
status. If the calculated result is YES, the Setpoint transition sequence starts. This
sequence cannot be broken by a wakeup request.
The Setpoint transition sequence contains both a sleep sequence and a wakeup sequence,
because GPC doesn't know whether a Setpoint transition is a wakeup or sleep sequence.
GPC sends all step requests by sequence, and the system resource controller determines
which request need be processed.
SSAR_RESTORE SSAR_SAVE
LPCG_ON LPCG_OFF
IDLE
GROUP_UP SP_CALCULATE GROUP_DOWN
ROOT_ON ROOT_DOWN
PLL_OSC_ON PLL_OSC_OFF
ISO_OFF DCDC_UP DCDC_DOWN ISO_ON
RST_LATE RST_EARLY
POWER_ON LDO_POST LDO_PRE POWER_OFF
BIAS_ON
BG_PLDO_ON BG_PLDO_OFF BIAS_OFF
Figure 19-4. Setpoint Transition Flow
19.3.6.3 Standby transition flow
The SBC state machine starts when CMC sends a standby request, it looks at all CMC
standby status, if any CPU platform is not in sleep mode or not allow standby, this
standby request will be refused. The standby_in sequence can be broken after any step
complete because of wakeup time requirement.
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Chapter 19 General Power Controller (GPC)
PLL_OSC_IN PLDO_IN LDO_IN PMIC_IN
LPCG_IN BIAS_IN BANDGAP_IN DCDC_IN
REFUSE IDLE STANDBY
LPCG_OUT BIAS_OUT BANDGAP_OUT DCDC_OUT
PLL_OSC_OUT PLDO_OUT LDO_OUT PMIC_OUT
Figure 19-5. Standby transition flow
19.3.6.4 Step Control
For each step of transition, there is a control register to adjust the step duration. The
CM_SLEEP_SSAR_CTRL[STEP_CNT] field is to set the delay count number.
The STEP_CNT[CNT_MODE] field is to select count mode. Please see register
definition for details.
The STEP_CNT[DISABLE] field to used to disable the step so that no request is sent out
in this transition step. There is also a read only counter to record the time when step
response is received.
19.3.7 System Domain
19.3.7.1 Domain assignment
Each CPU platform and the CMC connected to it can be assigned to the same domain.
Based on the domain assignment, a mapping mechanism between CPU platform and
system domain is implemented inside GPC.
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Functional description
RDC
CPU0 power mode
REQ Domain_0 power mode
CPU0 CMC0
CPU1 power mode Domain_1 power mode
CPU1 CMC1
. . .
. . .
. . .
CPUn power mode Domain_n power mode
CPUn CMCn
Figure 19-6. Domain Assignement
When more than one CMC is assigned to the same domain, a two stage priority selects
which CMC can control the domain’s UPI output. The first stage checks for the
master_cpu flag from CMC. The master_cpu flag is enabled by register
CM_MISC[MASTER_CPU]. The CMC with the master_cpu flag owns the Domain UPI
output. If all or none of the CPUs own the master_cpu flag, the second stage priority
assigns Domain UPI output to the lower indexed CMC.
19.3.7.2 Register Access Permissions
The GPC register access is controlled by the following registers and bitfields:
• CM_AUTHEN_CTRL register for CMC access permission
• SP_AUTHEN_CTRL register for SPC and SBC access permission.
• CM_AUTHEN_CTRL[WHITE_LIST] field configures which Domain IDs can write
to the registers.
• x_AUTHEN_CTRL[USER] and x_AUTHEN_CTRL[NONSECURE] fields are used
to set the privilege and security permission.
• CM_AUTHEN_CTRL[LOCK_CFG] locks configuration fields and should only be
set at initialization.
19.3.8 Clocks
This section describes the clocks for the GPC module.
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Chapter 19 General Power Controller (GPC)
Table 19-3. Clocks
Clock Description
ipg_clk Main GPC clock. This clock originates from RCOSC and can be turned off by setting
SP_ROSC_CTRL[SP_ALLOW_ROSC_OFF] when the system is in a Setpoint, which
allows shutting of the RCOSC. After transitioning into Standby mode, the GPC will shut
off the RCOSC.
32k_clk 32 kHz clock used to wakeup GPC and RCOSC. The 32 kHz clock isn't needed by
ipg_clk since they are fully asynchronous
19.3.9 Interrupts
The interrupt inputs of CMC0 and CMC1 are independent and the same as the CPU
platforms they are connected to. Each CMC has up to 256 IRQ input to wake up the core
or system.
The following are the types of interrupts the GPC can generate:
• CM_INT_CTRL[SP_REQ_NOT_ALLOWED_SLEEP_INT]: Setpoint target is not
allowed by MODE_MAPPING
• CM_INT_CTRL[SP_REQ_NOT_ALLOWED_WAKEUP_INT]: The wakeup
Setpoint target is not allowed by RUN_MODE_MAPPING
• CM_INT_CTRL[SP_REQ_NOT_ALLOWED_SOFT_INT]: The software Setpoint
target is not allowed by RUN_MODE_MAPPING
• SP_INT_CTRL[NO_ALLOWED_SP_INT]: No allowed Setpoint target for all
CMCs
NOTE
All the interrupts share one pin, users need to check above
registers to find out which violation occurs.
19.4 External Signals
There are no external signals pinned out for the GPC.
19.5 Initialization
See Low Power Sequence for low power entry and exit flow and considerations.
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Memory Map and register definition
19.5.1 CPU Sleep Hold
There is a certain delay between the time the core falls asleep and when the core clock
stops. If a wakeup IRQ appears inside this delay window, the core will process the IRQ
and awake, but the GPC sleep sequence is still shutting off the core clock. Since the sleep
sequence is not interruptable, this scenario may lead to unpredictable behavior.
To avoid this scenario, a CPU Sleep Hold is implemented to hold the core in the sleep
state until the sleep sequence is finished. The GPC will then send a signal to release the
core. The CM_MISC[SLEEP_HOLD_EN] field is used to enable this function.
The core clock can also be gated by a WFI event without any GPC sequence. The GPC
uses a signal to clear this gate when a wakeup trigger occurs.
19.6 Memory Map and register definition
This section includes the GPC module memory map and detailed descriptions of all
registers.
19.6.1 GPC_CPU register descriptions
19.6.1.1 gpc_cpu_ctrl memory map
GPC_CPU_MODE_CTRL_0 base address: 40C0_0000h
GPC_CPU_MODE_CTRL_1 base address: 40C0_0800h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4 CM Authentication Control (CM_AUTHEN_CTRL) 32 RW 0000_0F00
8 CM Interrupt Control (CM_INT_CTRL) 32 RW 0000_0007
C Miscellaneous (CM_MISC) 32 RW 0000_0006
10 CPU mode control (CM_MODE_CTRL) 32 RW 0000_0000
14 CM CPU mode Status (CM_MODE_STAT) 32 RO 0000_0000
100 CM IRQ0~31 wakeup mask (CM_IRQ_WAKEUP_MASK_0) 32 RW 0000_0000
104 CM IRQ32~63 wakeup mask (CM_IRQ_WAKEUP_MASK_1) 32 RW 0000_0000
108 CM IRQ64~95 wakeup mask (CM_IRQ_WAKEUP_MASK_2) 32 RW 0000_0000
10C CM IRQ96~127 wakeup mask (CM_IRQ_WAKEUP_MASK_3) 32 RW 0000_0000
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
110 CM IRQ128~159 wakeup mask (CM_IRQ_WAKEUP_MASK_4) 32 RW 0000_0000
114 CM IRQ160~191 wakeup mask (CM_IRQ_WAKEUP_MASK_5) 32 RW 0000_0000
118 CM IRQ192~223 wakeup mask (CM_IRQ_WAKEUP_MASK_6) 32 RW 0000_0000
11C CM IRQ224~255 wakeup mask (CM_IRQ_WAKEUP_MASK_7) 32 RW 0000_0000
140 CM non-irq wakeup mask (CM_NON_IRQ_WAKEUP_MASK) 32 RW 0000_0001
150 CM IRQ0~31 wakeup status (CM_IRQ_WAKEUP_STAT_0) 32 RO 0000_0000
154 CM IRQ32~63 wakeup status (CM_IRQ_WAKEUP_STAT_1) 32 RO 0000_0000
158 CM IRQ64~95 wakeup status (CM_IRQ_WAKEUP_STAT_2) 32 RO 0000_0000
15C CM IRQ96~127 wakeup status (CM_IRQ_WAKEUP_STAT_3) 32 RO 0000_0000
160 CM IRQ128~159 wakeup status (CM_IRQ_WAKEUP_STAT_4) 32 RO 0000_0000
164 CM IRQ160~191 wakeup status (CM_IRQ_WAKEUP_STAT_5) 32 RO 0000_0000
168 CM IRQ192~223 wakeup status (CM_IRQ_WAKEUP_STAT_6) 32 RO 0000_0000
16C CM IRQ224~255 wakeup status (CM_IRQ_WAKEUP_STAT_7) 32 RO 0000_0000
190 CM non-irq wakeup status (CM_NON_IRQ_WAKEUP_STAT) 32 RO 0000_0000
200 CM sleep SSAR control (CM_SLEEP_SSAR_CTRL) 32 RW 0000_0004
208 CM sleep LPCG control (CM_SLEEP_LPCG_CTRL) 32 RW 0000_0004
210 CM sleep PLL control (CM_SLEEP_PLL_CTRL) 32 RW 0000_0004
218 CM sleep isolation control (CM_SLEEP_ISO_CTRL) 32 RW 0000_0004
220 CM sleep reset control (CM_SLEEP_RESET_CTRL) 32 RW 0000_0004
228 CM sleep power control (CM_SLEEP_POWER_CTRL) 32 RW 0000_0004
290 CM wakeup power control (CM_WAKEUP_POWER_CTRL) 32 RW 0000_0004
298 CM wakeup reset control (CM_WAKEUP_RESET_CTRL) 32 RW 0000_0004
2A0 CM wakeup isolation control (CM_WAKEUP_ISO_CTRL) 32 RW 0000_0004
2A8 CM wakeup PLL control (CM_WAKEUP_PLL_CTRL) 32 RW 0000_0004
2B0 CM wakeup LPCG control (CM_WAKEUP_LPCG_CTRL) 32 RW 0000_0004
2B8 CM wakeup SSAR control (CM_WAKEUP_SSAR_CTRL) 32 RW 0000_0004
300 CM Setpoint Control (CM_SP_CTRL) 32 RW 0000_0000
304 CM Setpoint Status (CM_SP_STAT) 32 RO 0000_0000
310 CM Run Mode Setpoint Allowed (CM_RUN_MODE_MAPPING) 32 RW 0000_FFFF
314 CM Wait Mode Setpoint Allowed (CM_WAIT_MODE_MAPPING) 32 RW 0000_FFFF
318 CM Stop Mode Setpoint Allowed (CM_STOP_MODE_MAPPING) 32 RW 0000_FFFF
31C CM Suspend Mode Setpoint Allowed 32 RW 0000_FFFF
(CM_SUSPEND_MODE_MAPPING)
320 CM Setpoint 0 Mapping (CM_SP0_MAPPING) 32 RW 0000_FFFF
324 CM Setpoint 1 Mapping (CM_SP1_MAPPING) 32 RW 0000_FFFF
328 CM Setpoint 2 Mapping (CM_SP2_MAPPING) 32 RW 0000_FFFF
32C CM Setpoint 3 Mapping (CM_SP3_MAPPING) 32 RW 0000_FFFF
330 CM Setpoint 4 Mapping (CM_SP4_MAPPING) 32 RW 0000_FFFF
334 CM Setpoint 5 Mapping (CM_SP5_MAPPING) 32 RW 0000_FFFF
338 CM Setpoint 6 Mapping (CM_SP6_MAPPING) 32 RW 0000_FFFF
Table continues on the next page...
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Memory Map and register definition
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
33C CM Setpoint 7 Mapping (CM_SP7_MAPPING) 32 RW 0000_FFFF
340 CM Setpoint 8 Mapping (CM_SP8_MAPPING) 32 RW 0000_FFFF
344 CM Setpoint 9 Mapping (CM_SP9_MAPPING) 32 RW 0000_FFFF
348 CM Setpoint 10 Mapping (CM_SP10_MAPPING) 32 RW 0000_FFFF
34C CM Setpoint 11 Mapping (CM_SP11_MAPPING) 32 RW 0000_FFFF
350 CM Setpoint 12 Mapping (CM_SP12_MAPPING) 32 RW 0000_FFFF
354 CM Setpoint 13 Mapping (CM_SP13_MAPPING) 32 RW 0000_FFFF
358 CM Setpoint 14 Mapping (CM_SP14_MAPPING) 32 RW 0000_FFFF
35C CM Setpoint 15 Mapping (CM_SP15_MAPPING) 32 RW 0000_FFFF
380 CM standby control (CM_STBY_CTRL) 32 RW 0000_0000
19.6.1.2 CM Authentication Control (CM_AUTHEN_CTRL)
Authentication control for CMC
19.6.1.2.1 Offset
Register Offset
CM_AUTHEN_CTRL 4h
19.6.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LOCK_CFG
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOCK_SETTING
WHITE_LIST
LOCK_LIST
NONSECUR
Reserved
Reserved
Reserved
USE
W
R
E
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
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Chapter 19 General Power Controller (GPC)
19.6.1.2.3 Fields
Field Description
31-21 Reserved
—
20 Configuration lock
LOCK_CFG this field is write once and can lock value of low power configuration fields. Unlocked by System Reset.
19-13 Reserved
—
12 White list lock
LOCK_LIST this field is write once and can lock value of WHITE_LIST field
11-8 Domain ID white list
WHITE_LIST when bit setting to 1, the corresponding domain ID can access CPU mode control registers. bit[0] for
Domain 0, bit[1] for Domain 1, bit[2] for Domain 2, and bit[3] for Domain 3. Muliple bits with a value of 1 is
permitted.
7-5 Reserved
—
4 Lock NONSECURE and USER
LOCK_SETTIN this field is write once and can lock value of USER and NONSECURE field
G
3-2 Reserved
—
1 Allow non-secure mode access
NONSECURE 0 - Allow only secure mode to access CPU mode control registers
1 - Allow both secure and non-secure mode to access CPU mode control registers
0 Allow user mode access
USER 0 - Allow only privilege mode to access CPU mode control registers
1 - Allow both privilege and user mode to access CPU mode control registers
19.6.1.3 CM Interrupt Control (CM_INT_CTRL)
19.6.1.3.1 Offset
Register Offset
CM_INT_CTRL 8h
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19.6.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C SP_REQ_NOT_ALLOWED_WAKEUP_INT
SP_REQ_NOT_ALLOWED_SLEEP_INT
SP_REQ_NOT_ALLOWED_SOFT_INT
R
Reserved
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN
SP_REQ_NOT_ALLOWED_SLEEP_INT_EN
SP_REQ_NOT_ALLOWED_SOFT_INT_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
19.6.1.3.3 Fields
Field Description
31-19 Reserved
—
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
18 sp_req_not_allowed_for_soft interrupt status and clear register
SP_REQ_NOT_ when writing a "1" to CPU_SP_RUN_EN to trigger a software Setpoint transition request, if the target
ALLOWED_SO Setpoint in CPU_SP_RUN is not allowed by CM_RUN_MODE_MAPPING, this interrupt asserts.
FT_INT
17 sp_req_not_allowed_for_wakeup interrupt status and clear register
SP_REQ_NOT_ for wakeup sequence, if the target Setpoint is not allowed by CM_RUN_MODE_MAPPING, this interrupt
ALLOWED_WA asserts. The target Setpoint is determined by CPU_SP_WAKEUP_EN, CPU_SP_WAKEUP_SEL,
KEUP_INT CPU_SP_WAKEUP and CPU_SP_CURRENT
16 sp_req_not_allowed_for_sleep interrupt status and clear register
SP_REQ_NOT_ during sleep sequence, if the target Setpoint is not allowed by CM_X_MODE_MAPPING, this interrupt
ALLOWED_SLE asserts. The "X" is inside WAIT, STOP and SUSPEND, which is determined by CPU_MODE_TARGET.
EP_INT The target Setpoint is determined by CPU_SP_SLEEP if CPU_SP_SLEEP_EN set, and is determined by
CPU_SP_CURRENT if CPU_SP_SLEEP_EN unset
15-3 Reserved
—
2 sp_req_not_allowed_for_soft interrupt enable
SP_REQ_NOT_ See SP_REQ_NOT_ALLOWED_SOFT_INT for more information.
ALLOWED_SO
0 - Interrupt disable
FT_INT_EN
1 - Interrupt enable
1 sp_req_not_allowed_for_wakeup interrupt enable
SP_REQ_NOT_ See SP_REQ_NOT_ALLOWED_WAKEUP_INT for more information.
ALLOWED_WA
0 - Interrupt disable
KEUP_INT_EN
1 - Interrupt enable
0 sp_req_not_allowed_for_sleep interrupt enable
SP_REQ_NOT_ See SP_REQ_NOT_ALLOWED_SLEEP_INT for more information.
ALLOWED_SLE
0 - Interrupt disable
EP_INT_EN
1 - Interrupt enable
19.6.1.4 Miscellaneous (CM_MISC)
Miscellaneous register
19.6.1.4.1 Offset
Register Offset
CM_MISC Ch
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19.6.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP_HOLD_STA
SLEEP_HOLD_E
MASTER_CPU
NMI_STAT
Reserved
Reserved
R
N
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
19.6.1.4.3 Fields
Field Description
31-5 Reserved
—
4 Master CPU
MASTER_CPU Indicate this CPU is a master CPU inside the domain, when mux the UPI domain output, the master CPU
is selected if more than one CPU is assigned to same domain. Locked by LOCK_CFG field
3 Reserved
—
2 Status of cpu_sleep_hold_ack_b
SLEEP_HOLD_
STAT
1 Allow cpu_sleep_hold_req assert during CPU low power status
SLEEP_HOLD_ 0 - Disable cpu_sleep_hold_req
EN
1 - Allow cpu_sleep_hold_req assert during CPU low power status
0 Non-masked interrupt status
NMI_STAT 0 - NMI is not asserting
1 - NMI is asserting
19.6.1.5 CPU mode control (CM_MODE_CTRL)
CPU mode control register
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Chapter 19 General Power Controller (GPC)
19.6.1.5.1 Offset
Register Offset
CM_MODE_CTRL 10h
19.6.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_MODE_TARGET
Reserved
Reserved
WFE_E
W
N
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.5.3 Fields
Field Description
31-5 Reserved
—
4 WFE assertion can be sleep event
WFE_EN 0 - WFE assertion can not trigger low power
1 - WFE assertion can trigger low power
3-2 Reserved
—
1-0 The CPU mode the CPU platform should transit to on next sleep event
CPU_MODE_T Important: Core MUST re-configure this field EACH TIME before entering sleep
ARGET
00 - Stay in RUN mode
01 - Transit to WAIT mode
10 - Transit to STOP mode
11 - Transit to SUSPEND mode
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19.6.1.6 CM CPU mode Status (CM_MODE_STAT)
19.6.1.6.1 Offset
Register Offset
CM_MODE_STAT 14h
19.6.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_MODE_PREVIOUS
CPU_MODE_CURRENT
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.6.3 Fields
Field Description
31-29 Reserved
—
28-24 Reserved
—
23-19 Reserved
—
18-16 Reserved
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
—
15-11 Reserved
—
10-8 Reserved
—
7-4 Reserved
—
3-2 Previous CPU mode
CPU_MODE_P 00 - CPU was previously in RUN mode
REVIOUS
01 - CPU was previously in WAIT mode
10 - CPU was previously in STOP mode
11 - CPU was previously in SUSPEND mode
1-0 Current CPU mode
CPU_MODE_C 00 - CPU is currently in RUN mode
URRENT
01 - CPU is currently in WAIT mode
10 - CPU is currently in STOP mode
11 - CPU is currently in SUSPEND mode
19.6.1.7 CM IRQ0~31 wakeup mask (CM_IRQ_WAKEUP_MASK_0)
IRQ0~31 mask register
19.6.1.7.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 100h
SK_0
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19.6.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_0_31
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_0_31
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.7.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_0_31
19.6.1.8 CM IRQ32~63 wakeup mask (CM_IRQ_WAKEUP_MASK_1)
IRQ32~63 mask register
19.6.1.8.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 104h
SK_1
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Chapter 19 General Power Controller (GPC)
19.6.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_32_63
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_32_63
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.8.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_32_63
19.6.1.9 CM IRQ64~95 wakeup mask (CM_IRQ_WAKEUP_MASK_2)
IRQ64~95 mask register
19.6.1.9.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 108h
SK_2
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19.6.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_64_95
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_64_95
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.9.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_64_95
19.6.1.10 CM IRQ96~127 wakeup mask (CM_IRQ_WAKEUP_MASK_3)
IRQ96~127 mask register
19.6.1.10.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 10Ch
SK_3
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Chapter 19 General Power Controller (GPC)
19.6.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_96_127
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_96_127
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.10.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_96_127
19.6.1.11 CM IRQ128~159 wakeup mask
(CM_IRQ_WAKEUP_MASK_4)
IRQ128~159 mask register
19.6.1.11.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 110h
SK_4
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19.6.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_128_159
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_128_159
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.11.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_128_159
19.6.1.12 CM IRQ160~191 wakeup mask
(CM_IRQ_WAKEUP_MASK_5)
IRQ160~191 mask register
19.6.1.12.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 114h
SK_5
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Chapter 19 General Power Controller (GPC)
19.6.1.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_160_191
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_160_191
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.12.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_160_191
19.6.1.13 CM IRQ192~223 wakeup mask
(CM_IRQ_WAKEUP_MASK_6)
IRQ192~223 mask register
19.6.1.13.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 118h
SK_6
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19.6.1.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_192_223
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_192_223
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.13.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_192_223
19.6.1.14 CM IRQ224~255 wakeup mask
(CM_IRQ_WAKEUP_MASK_7)
IRQ224~255 mask register
19.6.1.14.1 Offset
Register Offset
CM_IRQ_WAKEUP_MA 11Ch
SK_7
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Chapter 19 General Power Controller (GPC)
19.6.1.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
IRQ_WAKEUP_MASK_224_255
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ_WAKEUP_MASK_224_255
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.14.3 Fields
Field Description
31-0 "1" means the IRQ cannot wakeup CPU platform
IRQ_WAKEUP_
MASK_224_255
19.6.1.15 CM non-irq wakeup mask (CM_NON_IRQ_WAKEUP_MASK)
This register is used to mask wakeup events which are not interrupt
19.6.1.15.1 Offset
Register Offset
CM_NON_IRQ_WAKEU 140h
P_MASK
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19.6.1.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBUG_WAKEUP_MASK
EVENT_WAKEUP_MASK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
19.6.1.15.3 Fields
Field Description
31-2 Reserved
—
1 "1" means the debug_wakeup_request cannot wakeup CPU platform
DEBUG_WAKE
UP_MASK
0 There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup
source.
EVENT_WAKE
UP_MASK 1 - The event cannot wakeup CPU platform
19.6.1.16 CM IRQ0~31 wakeup status (CM_IRQ_WAKEUP_STAT_0)
Interrupt status
19.6.1.16.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 150h
T_0
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Chapter 19 General Power Controller (GPC)
19.6.1.16.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_0_31
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_0_31
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.16.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_0_31
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.17 CM IRQ32~63 wakeup status (CM_IRQ_WAKEUP_STAT_1)
Interrupt status
19.6.1.17.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 154h
T_1
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19.6.1.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_32_63
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_32_63
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.17.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_32_63
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.18 CM IRQ64~95 wakeup status (CM_IRQ_WAKEUP_STAT_2)
Interrupt status
19.6.1.18.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 158h
T_2
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Chapter 19 General Power Controller (GPC)
19.6.1.18.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_64_95
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_64_95
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.18.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_64_95
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.19 CM IRQ96~127 wakeup status (CM_IRQ_WAKEUP_STAT_3)
Interrupt status
19.6.1.19.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 15Ch
T_3
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19.6.1.19.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_96_127
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_96_127
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.19.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_96_127
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.20 CM IRQ128~159 wakeup status
(CM_IRQ_WAKEUP_STAT_4)
Interrupt status
19.6.1.20.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 160h
T_4
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Chapter 19 General Power Controller (GPC)
19.6.1.20.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_128_159
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_128_159
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.20.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_128_159
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.21 CM IRQ160~191 wakeup status
(CM_IRQ_WAKEUP_STAT_5)
Interrupt status
19.6.1.21.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 164h
T_5
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19.6.1.21.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_160_191
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_160_191
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.21.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_160_191
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.22 CM IRQ192~223 wakeup status
(CM_IRQ_WAKEUP_STAT_6)
Interrupt status
19.6.1.22.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 168h
T_6
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Chapter 19 General Power Controller (GPC)
19.6.1.22.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_STAT_192_223
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_STAT_192_223
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.22.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
STAT_192_223
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.23 CM IRQ224~255 wakeup status
(CM_IRQ_WAKEUP_STAT_7)
Interrupt status
19.6.1.23.1 Offset
Register Offset
CM_IRQ_WAKEUP_STA 16Ch
T_7
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19.6.1.23.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IRQ_WAKEUP_MASK_224_255
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IRQ_WAKEUP_MASK_224_255
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.23.3 Fields
Field Description
31-0 IRQ status
IRQ_WAKEUP_ 00000000000000000000000000000000 - None. No pending interrupts
MASK_224_255
00000000000000000000000000000001 - Valid. A valid interrupt is pending
19.6.1.24 CM non-irq wakeup status (CM_NON_IRQ_WAKEUP_STAT)
Wakeup event status
19.6.1.24.1 Offset
Register Offset
CM_NON_IRQ_WAKEU 190h
P_STAT
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Chapter 19 General Power Controller (GPC)
19.6.1.24.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEBUG_WAKEUP_STAT
EVENT_WAKEUP_STAT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.24.3 Fields
Field Description
31-2 Reserved
—
1 Debug wakeup status
DEBUG_WAKE
UP_STAT
0 Event wakeup status
EVENT_WAKE 1 - Interrupt is asserting (pending)
UP_STAT
19.6.1.25 CM sleep SSAR control (CM_SLEEP_SSAR_CTRL)
Locked by LOCK_CFG field.
19.6.1.25.1 Offset
Register Offset
CM_SLEEP_SSAR_CTR 200h
L
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19.6.1.25.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.25.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE.
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.26 CM sleep LPCG control (CM_SLEEP_LPCG_CTRL)
Locked by LOCK_CFG field.
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Chapter 19 General Power Controller (GPC)
19.6.1.26.1 Offset
Register Offset
CM_SLEEP_LPCG_CTR 208h
L
19.6.1.26.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.26.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
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Memory Map and register definition
19.6.1.27 CM sleep PLL control (CM_SLEEP_PLL_CTRL)
Locked by LOCK_CFG field.
19.6.1.27.1 Offset
Register Offset
CM_SLEEP_PLL_CTRL 210h
19.6.1.27.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.27.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.28 CM sleep isolation control (CM_SLEEP_ISO_CTRL)
Locked by LOCK_CFG field.
19.6.1.28.1 Offset
Register Offset
CM_SLEEP_ISO_CTRL 218h
19.6.1.28.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.28.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
Table continues on the next page...
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Memory Map and register definition
Field Description
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.29 CM sleep reset control (CM_SLEEP_RESET_CTRL)
Locked by LOCK_CFG field.
19.6.1.29.1 Offset
Register Offset
CM_SLEEP_RESET_CT 220h
RL
19.6.1.29.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
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Chapter 19 General Power Controller (GPC)
19.6.1.29.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.30 CM sleep power control (CM_SLEEP_POWER_CTRL)
Locked by LOCK_CFG field.
19.6.1.30.1 Offset
Register Offset
CM_SLEEP_POWER_C 228h
TRL
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19.6.1.30.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.30.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.31 CM wakeup power control (CM_WAKEUP_POWER_CTRL)
Locked by LOCK_CFG field.
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Chapter 19 General Power Controller (GPC)
19.6.1.31.1 Offset
Register Offset
CM_WAKEUP_POWER_ 290h
CTRL
19.6.1.31.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.31.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
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19.6.1.32 CM wakeup reset control (CM_WAKEUP_RESET_CTRL)
Locked by LOCK_CFG field.
19.6.1.32.1 Offset
Register Offset
CM_WAKEUP_RESET_ 298h
CTRL
19.6.1.32.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.32.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.33 CM wakeup isolation control (CM_WAKEUP_ISO_CTRL)
Locked by LOCK_CFG field.
19.6.1.33.1 Offset
Register Offset
CM_WAKEUP_ISO_CTR 2A0h
L
19.6.1.33.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.33.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
Table continues on the next page...
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Memory Map and register definition
Field Description
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.34 CM wakeup PLL control (CM_WAKEUP_PLL_CTRL)
Locked by LOCK_CFG field.
19.6.1.34.1 Offset
Register Offset
CM_WAKEUP_PLL_CTR 2A8h
L
19.6.1.34.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
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Chapter 19 General Power Controller (GPC)
19.6.1.34.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.35 CM wakeup LPCG control (CM_WAKEUP_LPCG_CTRL)
Locked by LOCK_CFG field.
19.6.1.35.1 Offset
Register Offset
CM_WAKEUP_LPCG_C 2B0h
TRL
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19.6.1.35.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.35.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.1.36 CM wakeup SSAR control (CM_WAKEUP_SSAR_CTRL)
Locked by LOCK_CFG field.
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Chapter 19 General Power Controller (GPC)
19.6.1.36.1 Offset
Register Offset
CM_WAKEUP_SSAR_C 2B8h
TRL
19.6.1.36.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.1.36.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
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Memory Map and register definition
19.6.1.37 CM Setpoint Control (CM_SP_CTRL)
Setpoint control register.
19.6.1.37.1 Offset
Register Offset
CM_SP_CTRL 300h
19.6.1.37.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP_WAKEUP_EN
CPU_SP_WAKEUP_SE
CPU_SP_SLEEP_E
CPU_SP_WAKEUP
CPU_SP_RUN_E
CPU_SP_SLEE
CPU_SP_RUN
W
P
N
N
L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.37.3 Fields
Field Description
31-16 Reserved
—
15 Select the Setpoint transiton on the next CPU platform wakeup sequence
CPU_SP_WAK 0 - Request SP transition to CPU_SP_WAKEUP
EUP_SEL
1 - Request SP transition to the Setpoint when the sleep event happens, which is captured in
CPU_SP_PREVIOUS
14-11 The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence
CPU_SP_WAK
EUP
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
10 1 means enable Setpoint transition on next CPU platform wakeup sequence
CPU_SP_WAK
EUP_EN
9-6 The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence
CPU_SP_SLEE
P
5 1 means enable Setpoint transition on next CPU platform sleep sequence
CPU_SP_SLEE
P_EN
4-1 The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set
CPU_SP_RUN
0 Request a Setpoint transition when this bit is set
CPU_SP_RUN_ Write 1 will trigger Setpoint transition. The field is read as 1 until transition complete.
EN
19.6.1.38 CM Setpoint Status (CM_SP_STAT)
19.6.1.38.1 Offset
Register Offset
CM_SP_STAT 304h
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19.6.1.38.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_SP_PREVIOUS
CPU_SP_TARGET
CPU_SP_CURREN
Reserved
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.38.3 Fields
Field Description
31-16 Reserved
—
15-12 Reserved
—
11-8 The requested Setpoint from the CPU platform
CPU_SP_TARG 0000 - Setpoint 0
ET
0001 - Setpoint 1
...
1111 - Setpoint 15
7-4 The previous Setpoint of the system
CPU_SP_PREV 0000 - Setpoint 0
IOUS
0001 - Setpoint 1
...
1111 - Setpoint 15
3-0 The current Setpoint of the system
CPU_SP_CURR 0000 - Setpoint 0
ENT
0001 - Setpoint 1
...
1111 - Setpoint 15
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Chapter 19 General Power Controller (GPC)
19.6.1.39 CM Run Mode Setpoint Allowed
(CM_RUN_MODE_MAPPING)
Allowed setpoint list for CPU RUN mode
19.6.1.39.1 Offset
Register Offset
CM_RUN_MODE_MAPP 310h
ING
19.6.1.39.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_RUN_MODE_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.39.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by
LOCK_CFG field
CPU_RUN_MO
DE_MAPPING
19.6.1.40 CM Wait Mode Setpoint Allowed
(CM_WAIT_MODE_MAPPING)
Allowed setpoint list for CPU WAIT mode
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19.6.1.40.1 Offset
Register Offset
CM_WAIT_MODE_MAP 314h
PING
19.6.1.40.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_WAIT_MODE_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.40.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked
by LOCK_CFG
CPU_WAIT_MO
DE_MAPPING
19.6.1.41 CM Stop Mode Setpoint Allowed
(CM_STOP_MODE_MAPPING)
Allowed setpoint list for CPU STOP mode
19.6.1.41.1 Offset
Register Offset
CM_STOP_MODE_MAP 318h
PING
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Chapter 19 General Power Controller (GPC)
19.6.1.41.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_STOP_MODE_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.41.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked
by LOCK_CFG
CPU_STOP_M
ODE_MAPPING
19.6.1.42 CM Suspend Mode Setpoint Allowed
(CM_SUSPEND_MODE_MAPPING)
Allowed setpoint list for CPU SUSPEND mode
19.6.1.42.1 Offset
Register Offset
CM_SUSPEND_MODE_ 31Ch
MAPPING
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19.6.1.42.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SUSPEND_MODE_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.42.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint,
locked by LOCK_CFG
CPU_SUSPEN
D_MODE_MAP
PING
19.6.1.43 CM Setpoint 0 Mapping (CM_SP0_MAPPING)
Allowed setpoint list for setpoint0 target
19.6.1.43.1 Offset
Register Offset
CM_SP0_MAPPING 320h
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Chapter 19 General Power Controller (GPC)
19.6.1.43.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP0_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.43.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP0_MAP
PING
19.6.1.44 CM Setpoint 1 Mapping (CM_SP1_MAPPING)
Allowed setpoint list for setpoint1 target
19.6.1.44.1 Offset
Register Offset
CM_SP1_MAPPING 324h
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19.6.1.44.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP1_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.44.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP1_MAP
PING
19.6.1.45 CM Setpoint 2 Mapping (CM_SP2_MAPPING)
Allowed setpoint list for setpoint2 target
19.6.1.45.1 Offset
Register Offset
CM_SP2_MAPPING 328h
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Chapter 19 General Power Controller (GPC)
19.6.1.45.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP2_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.45.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP2_MAP
PING
19.6.1.46 CM Setpoint 3 Mapping (CM_SP3_MAPPING)
Allowed setpoint list for setpoint3 target
19.6.1.46.1 Offset
Register Offset
CM_SP3_MAPPING 32Ch
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19.6.1.46.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP3_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.46.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP3_MAP
PING
19.6.1.47 CM Setpoint 4 Mapping (CM_SP4_MAPPING)
Allowed setpoint list for setpoint4 target
19.6.1.47.1 Offset
Register Offset
CM_SP4_MAPPING 330h
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19.6.1.47.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP4_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.47.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP4_MAP
PING
19.6.1.48 CM Setpoint 5 Mapping (CM_SP5_MAPPING)
Allowed setpoint list for setpoint5 target
19.6.1.48.1 Offset
Register Offset
CM_SP5_MAPPING 334h
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19.6.1.48.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP5_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.48.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP5_MAP
PING
19.6.1.49 CM Setpoint 6 Mapping (CM_SP6_MAPPING)
Allowed setpoint list for setpoint6 target
19.6.1.49.1 Offset
Register Offset
CM_SP6_MAPPING 338h
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19.6.1.49.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP6_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.49.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP6_MAP
PING
19.6.1.50 CM Setpoint 7 Mapping (CM_SP7_MAPPING)
Allowed setpoint list for setpoint7 target
19.6.1.50.1 Offset
Register Offset
CM_SP7_MAPPING 33Ch
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19.6.1.50.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP7_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.50.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP7_MAP
PING
19.6.1.51 CM Setpoint 8 Mapping (CM_SP8_MAPPING)
Allowed setpoint list for setpoint8 target
19.6.1.51.1 Offset
Register Offset
CM_SP8_MAPPING 340h
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19.6.1.51.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP8_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.51.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP8_MAP
PING
19.6.1.52 CM Setpoint 9 Mapping (CM_SP9_MAPPING)
Allowed setpoint list for setpoint9 target
19.6.1.52.1 Offset
Register Offset
CM_SP9_MAPPING 344h
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19.6.1.52.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP9_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.52.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP9_MAP
PING
19.6.1.53 CM Setpoint 10 Mapping (CM_SP10_MAPPING)
Allowed setpoint list for setpoint10 target
19.6.1.53.1 Offset
Register Offset
CM_SP10_MAPPING 348h
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19.6.1.53.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP10_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.53.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP10_MA
PPING
19.6.1.54 CM Setpoint 11 Mapping (CM_SP11_MAPPING)
Allowed setpoint list for setpoint11 target
19.6.1.54.1 Offset
Register Offset
CM_SP11_MAPPING 34Ch
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19.6.1.54.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP11_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.54.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP11_MA
PPING
19.6.1.55 CM Setpoint 12 Mapping (CM_SP12_MAPPING)
Allowed setpoint list for setpoint12 target
19.6.1.55.1 Offset
Register Offset
CM_SP12_MAPPING 350h
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19.6.1.55.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP12_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.55.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP12_MA
PPING
19.6.1.56 CM Setpoint 13 Mapping (CM_SP13_MAPPING)
Allowed setpoint list for setpoint13 target
19.6.1.56.1 Offset
Register Offset
CM_SP13_MAPPING 354h
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19.6.1.56.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP13_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.56.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP13_MA
PPING
19.6.1.57 CM Setpoint 14 Mapping (CM_SP14_MAPPING)
Allowed setpoint list for setpoint14 target
19.6.1.57.1 Offset
Register Offset
CM_SP14_MAPPING 358h
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Chapter 19 General Power Controller (GPC)
19.6.1.57.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP14_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.57.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP14_MA
PPING
19.6.1.58 CM Setpoint 15 Mapping (CM_SP15_MAPPING)
Allowed setpoint list for setpoint15 target
19.6.1.58.1 Offset
Register Offset
CM_SP15_MAPPING 35Ch
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19.6.1.58.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CPU_SP15_MAPPING
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.1.58.3 Fields
Field Description
31-16 Reserved
—
15-0 Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
CPU_SP15_MA
PPING
19.6.1.59 CM standby control (CM_STBY_CTRL)
Standby control register
19.6.1.59.1 Offset
Register Offset
CM_STBY_CTRL 380h
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Chapter 19 General Power Controller (GPC)
19.6.1.59.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STBY_WAKEUP_BUSY
STBY_SLEEP_BUS
Reserved
Y
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STBY_SUSPEN
STBY_WAIT
STBY_STO
Reserved
P
D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.1.59.3 Fields
Field Description
31-18 Reserved
—
17 Indicate the CPU is busy exiting standby mode.
STBY_WAKEU
P_BUSY
16 Indicate the CPU is busy entering standby mode.
STBY_SLEEP_
BUSY
15-3 Reserved
—
2 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG
field.
STBY_SUSPEN
D
1 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field.
STBY_STOP
0 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field.
STBY_WAIT
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19.6.2 GPC_SP register descriptions
19.6.2.1 gpc_sp_ctrl memory map
GPC_SET_POINT_CTRL base address: 40C0_2000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4 SP Authentication Control (SP_AUTHEN_CTRL) 32 RW 0000_0F00
8 SP Interrupt Control (SP_INT_CTRL) 32 RW 0000_0001
10 CPU SP Request (SP_CPU_REQ) 32 RO 0000_0000
14 SP System Status (SP_SYS_STAT) 32 RO 0000_FFFF
1C SP ROSC Control (SP_ROSC_CTRL) 32 RW 0000_0000
40 SP0~7 Priority (SP_PRIORITY_0_7) 32 RW 7654_3210
44 SP8~15 Priority (SP_PRIORITY_8_15) 32 RW FEDC_BA98
100 SP SSAR save control (SP_SSAR_SAVE_CTRL) 32 RW 0000_0004
110 SP LPCG off control (SP_LPCG_OFF_CTRL) 32 RW 0000_0004
120 SP group down control (SP_GROUP_DOWN_CTRL) 32 RW 0000_0004
130 SP root down control (SP_ROOT_DOWN_CTRL) 32 RW 0000_0004
140 SP PLL off control (SP_PLL_OFF_CTRL) 32 RW 0000_0004
150 SP ISO on control (SP_ISO_ON_CTRL) 32 RW 0000_0004
160 SP reset early control (SP_RESET_EARLY_CTRL) 32 RW 0000_0004
170 SP power off control (SP_POWER_OFF_CTRL) 32 RW 0000_0004
180 SP bias off control (SP_BIAS_OFF_CTRL) 32 RW 0000_0004
190 SP bandgap and PLL_LDO off control (SP_BG_PLDO_OFF_CTRL) 32 RW 0000_0004
1A0 SP LDO pre control (SP_LDO_PRE_CTRL) 32 RW 0000_0004
1B0 SP DCDC down control (SP_DCDC_DOWN_CTRL) 32 RW 0000_0004
200 SP DCDC up control (SP_DCDC_UP_CTRL) 32 RW 0000_0004
210 SP LDO post control (SP_LDO_POST_CTRL) 32 RW 0000_0004
220 SP bandgap and PLL_LDO on control (SP_BG_PLDO_ON_CTRL) 32 RW 0000_0004
230 SP bias on control (SP_BIAS_ON_CTRL) 32 RW 0000_0004
240 SP power on control (SP_POWER_ON_CTRL) 32 RW 0000_0004
250 SP reset late control (SP_RESET_LATE_CTRL) 32 RW 0000_0004
260 SP ISO off control (SP_ISO_OFF_CTRL) 32 RW 0000_0004
270 SP PLL on control (SP_PLL_ON_CTRL) 32 RW 0000_0004
280 SP root up control (SP_ROOT_UP_CTRL) 32 RW 0000_0004
290 SP group up control (SP_GROUP_UP_CTRL) 32 RW 0000_0004
2A0 SP LPCG on control (SP_LPCG_ON_CTRL) 32 RW 0000_0004
2B0 SP SSAR restore control (SP_SSAR_RESTORE_CTRL) 32 RW 0000_0004
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Chapter 19 General Power Controller (GPC)
19.6.2.2 SP Authentication Control (SP_AUTHEN_CTRL)
Authentication control of setpoint controller
19.6.2.2.1 Offset
Register Offset
SP_AUTHEN_CTRL 4h
19.6.2.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK_CFG
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LOCK_SETTING
WHITE_LIST
LOCK_LIST
NONSECUR
Reserved
Reserved
Reserved
USE
W
R
E
Reset 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
19.6.2.2.3 Fields
Field Description
31-21 Reserved
—
20 Configuration lock
LOCK_CFG this field is write once and can lock value of low power configuration fields
19-13 Reserved
—
12 White list lock
LOCK_LIST this field is write once and can lock value of WHITE_LIST field
Table continues on the next page...
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Field Description
11-8 Domain ID white list
WHITE_LIST when bit setting to 1, the corresponding domain ID can access CPU mode control registers
7-5 Reserved
—
4 Lock NONSECURE and USER
LOCK_SETTIN this field is write once and can lock value of USER and NONSECURE field
G
3-2 Reserved
—
1 Allow non-secure mode access
NONSECURE 0 - Allow only secure mode to access setpoint control registers
1 - Allow both secure and non-secure mode to access setpoint control registers
0 Allow user mode access
USER 0 - Allow only privilege mode to access setpoint control registers
1 - Allow both privilege and user mode to access setpoint control registers
19.6.2.3 SP Interrupt Control (SP_INT_CTRL)
Setpoint controller interrupt control register
19.6.2.3.1 Offset
Register Offset
SP_INT_CTRL 8h
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Chapter 19 General Power Controller (GPC)
19.6.2.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C NO_ALLOWED_SP_INT
NO_ALLOWED_SP_INT_EN
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
19.6.2.3.3 Fields
Field Description
31-2 Reserved
—
1 no_allowed_set_point interrupt
NO_ALLOWED if the calculation result shows there is not any setpoint value can be allowed by all the CPU mode
_SP_INT controller, this interrupt happens
0 no_allowed_set_point interrupt enable
NO_ALLOWED 1 means enable to assert interrupt when no_allowed_set_point happens
_SP_INT_EN
19.6.2.4 CPU SP Request (SP_CPU_REQ)
19.6.2.4.1 Offset
Register Offset
SP_CPU_REQ 10h
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19.6.2.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SP_ACCEPTED_CPU3
SP_ACCEPTED_CPU2
SP_ACCEPTED_CPU1
SP_ACCEPTED_CPU0
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SP_REQ_CPU3 SP_REQ_CPU2 SP_REQ_CPU1 SP_REQ_CPU0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.2.4.3 Fields
Field Description
31-28 CPU3 Setpoint accepted by SP controller
SP_ACCEPTED 0000 - Setpoint 0
_CPU3
0001 - Setpoint 1
...
1111 - Setpoint 15
27-24 CPU2 Setpoint accepted by SP controller
SP_ACCEPTED 0000 - Setpoint 0
_CPU2
0001 - Setpoint 1
...
1111 - Setpoint 15
23-20 CPU1 Setpoint accepted by SP controller
SP_ACCEPTED 0000 - Setpoint 0
_CPU1
0001 - Setpoint 1
...
1111 - Setpoint 15
19-16 CPU0 Setpoint accepted by SP controller
SP_ACCEPTED 0000 - Setpoint 0
_CPU0
0001 - Setpoint 1
...
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
1111 - Setpoint 15
15-12 Setpoint requested by CPU3
SP_REQ_CPU3 0000 - Setpoint 0
0001 - Setpoint 1
...
1111 - Setpoint 15
11-8 Setpoint requested by CPU2
SP_REQ_CPU2 0000 - Setpoint 0
0001 - Setpoint 1
...
1111 - Setpoint 15
7-4 Setpoint requested by CPU1
SP_REQ_CPU1 0000 - Setpoint 0
0001 - Setpoint 1
...
1111 - Setpoint 15
3-0 Setpoint requested by CPU0
SP_REQ_CPU0 0000 - Setpoint 0
0001 - Setpoint 1
...
1111 - Setpoint 15
19.6.2.5 SP System Status (SP_SYS_STAT)
.
19.6.2.5.1 Offset
Register Offset
SP_SYS_STAT 14h
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19.6.2.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYS_SP_PREVIOU
SYS_SP_CURREN
SYS_SP_TARGE
Reserved
T
T
S
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R SYS_SP_ALLOWED
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19.6.2.5.3 Fields
Field Description
31-28 Reserved
—
27-24 Previous Setpoint, only valid when not SP trans busy
SYS_SP_PREVI 0000 - Setpoint 0
OUS
0001 - Setpoint 1
...
1111 - Setpoint 15
23-20 Current Setpoint, only valid when not SP trans busy
SYS_SP_CURR 0000 - Setpoint 0
ENT
0001 - Setpoint 1
...
1111 - Setpoint 15
19-16 The Setpoint chosen as the target setpoint
SYS_SP_TARG 0000 - Setpoint 0
ET
0001 - Setpoint 1
...
1111 - Setpoint 15
15-0 Allowed Setpoints by all current CPU Setpoint requests
SYS_SP_ALLO This field is the ANDed result of allowed Setpoints from all CMCs. If all bits are 0, there are no Setpoints,
WED and no Setpoint transitions are allowed. See System Setpoint Management topic for more information.
Bit 0: Setpoint 0 is allowed
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Chapter 19 General Power Controller (GPC)
Field Description
Bit 1: Setpoint 1 is allowed
...
Bit 15: Setpoint 15 is allowed
19.6.2.6 SP ROSC Control (SP_ROSC_CTRL)
On-chip oscillator control register
19.6.2.6.1 Offset
Register Offset
SP_ROSC_CTRL 1Ch
19.6.2.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SP_ALLOW_ROSC_OFF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
19.6.2.6.3 Fields
Field Description
31-16 Reserved
—
15-0 Allow shutting off the ROSC
SP_ALLOW_RO ROSC is the main clock source of GPC when system is in a selected Setpoint. Locked by LOCK_CFG
SC_OFF field. Each bit represents a Setpoint index.
1b1 - Allows Shutting off RCOSC at the Setpoint index.
1b0 - Does not allow shutting off RCOSC at the Setpoint index.
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19.6.2.7 SP0~7 Priority (SP_PRIORITY_0_7)
Larger number means higher priority, locked by LOCK_CFG field
19.6.2.7.1 Offset
Register Offset
SP_PRIORITY_0_7 40h
19.6.2.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SYS_SP7_PRIORIT
SYS_SP6_PRIORIT
SYS_SP5_PRIORIT
SYS_SP4_PRIORIT
W
Y
Y
Reset 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SYS_SP3_PRIORIT
SYS_SP2_PRIORIT
SYS_SP1_PRIORIT
SYS_SP0_PRIORIT
W
Y
Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0
19.6.2.7.3 Fields
Field Description
31-28 priority of Setpoint 7
SYS_SP7_PRIO
RITY
27-24 priority of Setpoint 6
SYS_SP6_PRIO
RITY
Table continues on the next page...
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Chapter 19 General Power Controller (GPC)
Field Description
23-20 priority of Setpoint 5
SYS_SP5_PRIO
RITY
19-16 priority of Setpoint 4
SYS_SP4_PRIO
RITY
15-12 priority of Setpoint 3
SYS_SP3_PRIO
RITY
11-8 priority of Setpoint 2
SYS_SP2_PRIO
RITY
7-4 priority of Setpoint 1
SYS_SP1_PRIO
RITY
3-0 priority of Setpoint 0
SYS_SP0_PRIO
RITY
19.6.2.8 SP8~15 Priority (SP_PRIORITY_8_15)
Larger number means higher priority, locked by LOCK_CFG field
19.6.2.8.1 Offset
Register Offset
SP_PRIORITY_8_15 44h
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19.6.2.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SYS_SP15_PRIORITY
SYS_SP14_PRIORITY
SYS_SP13_PRIORITY
SYS_SP12_PRIORITY
W
Reset 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SYS_SP11_PRIORITY
SYS_SP10_PRIORITY
SYS_SP9_PRIORIT
SYS_SP8_PRIORIT
W
Y
Reset 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0
19.6.2.8.3 Fields
Field Description
31-28 priority of Setpoint 15
SYS_SP15_PRI
ORITY
27-24 priority of Setpoint 14
SYS_SP14_PRI
ORITY
23-20 priority of Setpoint 13
SYS_SP13_PRI
ORITY
19-16 priority of Setpoint 12
SYS_SP12_PRI
ORITY
15-12 priority of Setpoint 11
SYS_SP11_PRI
ORITY
11-8 priority of Setpoint 10
SYS_SP10_PRI
ORITY
7-4 priority of Setpoint 9
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1882 NXP Semiconductors
Chapter 19 General Power Controller (GPC)
Field Description
SYS_SP9_PRIO
RITY
3-0 priority of Setpoint 8
SYS_SP8_PRIO
RITY
19.6.2.9 SP SSAR save control (SP_SSAR_SAVE_CTRL)
Locked by LOCK_CFG field.
19.6.2.9.1 Offset
Register Offset
SP_SSAR_SAVE_CTRL 100h
19.6.2.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.2.9.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1883
Memory Map and register definition
Field Description
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.10 SP LPCG off control (SP_LPCG_OFF_CTRL)
Locked by LOCK_CFG field.
19.6.2.10.1 Offset
Register Offset
SP_LPCG_OFF_CTRL 110h
19.6.2.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1884 NXP Semiconductors
Chapter 19 General Power Controller (GPC)
19.6.2.10.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.11 SP group down control (SP_GROUP_DOWN_CTRL)
Locked by LOCK_CFG field.
19.6.2.11.1 Offset
Register Offset
SP_GROUP_DOWN_CT 120h
RL
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1885
Memory Map and register definition
19.6.2.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.2.11.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.12 SP root down control (SP_ROOT_DOWN_CTRL)
Locked by LOCK_CFG field.
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1886 NXP Semiconductors
Chapter 19 General Power Controller (GPC)
19.6.2.12.1 Offset
Register Offset
SP_ROOT_DOWN_CTR 130h
L
19.6.2.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.2.12.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1887
Memory Map and register definition
19.6.2.13 SP PLL off control (SP_PLL_OFF_CTRL)
Locked by LOCK_CFG field.
19.6.2.13.1 Offset
Register Offset
SP_PLL_OFF_CTRL 140h
19.6.2.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.2.13.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1888 NXP Semiconductors
Chapter 19 General Power Controller (GPC)
Field Description
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.14 SP ISO on control (SP_ISO_ON_CTRL)
Locked by LOCK_CFG field.
19.6.2.14.1 Offset
Register Offset
SP_ISO_ON_CTRL 150h
19.6.2.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
19.6.2.14.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
Table continues on the next page...
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1889
Memory Map and register definition
Field Description
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.15 SP reset early control (SP_RESET_EARLY_CTRL)
Locked by LOCK_CFG field.
19.6.2.15.1 Offset
Register Offset
SP_RESET_EARLY_CT 160h
RL
19.6.2.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNT_MODE
Reserved
Reserved
DISABL
W
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
STEP_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
1890 NXP Semiconductors
Chapter 19 General Power Controller (GPC)
19.6.2.15.3 Fields
Field Description
31 Disable this step
DISABLE When setting to 1, GPC will skip this step and not send any request
30 Reserved
—
29-28 Count mode
CNT_MODE Configure the step counter working mode
00 - Counter disable mode: not use step counter, step completes once receiving step_done
01 - Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
10 - Ignore step_done response, the counter starts to count once step begins, when counter reaches
STEP_CNT value, the step completes
11 - Time out mode, the counter starts to count once step begins, the step completes when either
step_done received or counting to STEP_CNT value
27-16 Reserved
—
15-0 Step count, useage is depending on CNT_MODE
STEP_CNT Must be greater than 2 under CNT_MODE 2 and 3
19.6.2.16 SP power off control (SP_POWER_OFF_CTRL)
Locked by LOCK_CFG field.
19.6.2.16.1 Offset
Register Offset
SP_POWER_OFF_CTRL 170h
i.MX RT1170 Processor Reference Manual, Rev. 1, 05/2021
NXP Semiconductors 1891
Memory Map and register definition
19.6.2.16.2 Diagram
Bits 31 30
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