M 24LC08B/16B MODULES

8K/16K I2C™ Serial EEPROMs in ISO Micromodules

FEATURES ISO MODULE LAYOUT
• ISO 7816 compliant contact locations
• Single supply with operation from 2.5-5.5V
• Low power CMOS technology
- 1 mA active current typical VDD VSS
- 10 µA standby current typical at 5.5V
• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)
• 2-wire serial interface bus, I2C compatible
• Schmitt trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
SCL SDA
• 100 kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• ESD protection > 4,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
BLOCK DIAGRAM
• Temperature range
- Commercial (C): 0˚C to +70˚C HV GENERATOR

DESCRIPTION I/O MEMORY EEPROM

CONTROL CONTROL ARRAY
The Microchip Technology Inc. 24LC08B/16B are 8K LOGIC LOGIC XDEC
and 16K bit Electrically Erasable PROMs in ISO mod- PAGE LATCHES
ules for smart card applications. The device is orga-
SDA SCL
nized as four or eight blocks of 256 x 8-bit memory with
a 2-wire serial interface. The 24LC08B and 24LC16B YDEC
also have a page-write capability for up to 16 bytes of
data. VCC SENSE AMP
VSS R/W CONTROL

I2C is a trademark of Philips Corporation.

 1997 Microchip Technology Inc. DS21224A-page 1

24LC08B/16B MODULES
1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE

1.1 Maximum Ratings* Name Function

VCC...................................................................................7.0V VSS Ground

All inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0V
SDA Serial Data
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C SCL Serial Clock
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins ..................................................≥ 4 kV VCC +2.5V to 5.5V Power Supply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2 DC CHARACTERISTICS

All Parameters apply across the speci- Commercial (C): Tamb = 0˚C to +70˚C, VCC = 2.5V to 5.5V
fied operating ranges unless otherwise
noted.
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High level input voltage VIH 0.7 VCC V (Note)
Low level input voltage VIL 0.3 VCC V (Note)
Hysteresis of Schmitt trigger inputs VHYS 0.05 VCC — V Vcc ≥ 2.5V (Note)
Low level output voltage VOL 0.40 V IOL = 3.0 mA, VCC = 4.5V
IOL = 2.1 mA, VCC = 2.5V
Input leakage current ILI -10 10 µA VIN = VCC or VSS
Output leakage current ILO -10 10 µA VOUT = VCC or VSS
Pin capacitance (all inputs/outputs) CIN, — 10 pF VCC = 5.0V (Note)
COUT Tamb = 25˚C, f = 1 MHz
Operating current ICC Write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS — 100 µA VCC = 5.5V, SDA = SCL = VCC
Note: This parameter is periodically sampled and not 100% tested.

DS21224A-page 2  1997 Microchip Technology Inc.

 24LC08B/16B MODULES
TABLE 1-3 AC CHARACTERISTICS

All parameters apply across the specified operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted. Commercial (C): Tamb = 0 °C to +70°C
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
Parameter Symbol STD MODE FAST MODE Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time THD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH TOF — 250 20 +0.1 250 ns (Note 1), CB ≤ 100 pF
minimum to VIL maximum CB
Input filter spike suppression TSP — 50 — 50 ns (Notes 1, 3)
(SDA and SCL pins)
Write cycle time TWC — 10 — 10 ms Byte or Page mode
Endurance 1M — 1M — cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: BUS TIMING DATA

TF TR
THIGH
TLOW

SCL
TSU:STA
THD:DAT TSU:DAT TSU:STO
THD:STA
SDA
IN TSP

TAA TAA TBUF

THD:STA

SDA
OUT

 1997 Microchip Technology Inc. DS21224A-page 3

24LC08B/16B MODULES
2.0 PAD DESCRIPTIONS 4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
2.1 SDA (Serial Data)
• Data transfer may be initiated only when the bus
This is a Bi-directional pin used to transfer addresses is not busy.
and data into and data out of the device. It is an open • During data transfer, the data line must remain
drain terminal, therefore the SDA bus requires a pull-up stable whenever the clock line is HIGH. Changes
resistor to VCC (typical 10Ω). in the data line while the clock line is HIGH will be
For normal data transfer SDA is allowed to change only interpreted as a START or STOP condition.
during SCL low. Changes during SCL high are Accordingly, the following bus conditions have been
reserved for indicating the START and STOP condi- defined (Figure 5-2).
tions.
4.1 Bus not Busy (A)
2.2 SCL (Serial Clock)
Both data and clock lines remain HIGH.
This input is used to synchronize the data transfer from
and to the device. 4.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
3.0 FUNCTIONAL DESCRIPTION clock (SCL) is HIGH determines a START condition.
The 24LC08B/16B supports a Bi-directional 2-wire bus All commands must be preceded by a START condi-
and data transmission protocol. A device that sends tion.
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be 4.3 Stop Data Transfer (C)
controlled by a master device which generates the
A LOW to HIGH transition of the SDA line while the
serial clock (SCL), controls the bus access, and gener-
clock (SCL) is HIGH determines a STOP condition. All
ates the START and STOP conditions, while the
operations must be ended with a STOP condition.
24LC08B/16B works as slave. Both, master and slave
can operate as transmitter or receiver but the master 4.4 Data Valid (D)
device determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.

DS21224A-page 4  1997 Microchip Technology Inc.

 24LC08B/16B MODULES
4.5 Acknowledge 5.0 DEVICE ADDRESSING
Each receiving device, when addressed, is obliged to A control byte is the first byte received following the
generate an acknowledge after the reception of each start condition from the master device. The control byte
byte. The master device must generate an extra clock consists of a 4-bit control code, for the 24LC08B/16B
pulse which is associated with this acknowledge bit. this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
Note: The 24LC08B/16B does not generate any select bits (B2, B1, B0). They are used by the master
acknowledge bits if an internal program- device to select which of the eight 256 word blocks of
ming cycle is in progress. memory are to be accessed. These bits are in effect the
The device that acknowledges, has to pull down the three most significant bits of the word address.
SDA line during the acknowledge clock pulse in such a The last bit of the control byte defines the operation to
way that the SDA line is stable LOW during the HIGH be performed. When set to one a read operation is
period of the acknowledge related clock pulse. Of selected, when set to zero a write operation is selected.
course, setup and hold times must be taken into Following the start condition, the 24LC08B/16B moni-
account. During reads, a master must signal an end of tors the SDA bus checking the device type identifier
data to the slave by NOT generating an acknowledge being transmitted, upon a 1010 code the slave device
bit on the last byte that has been clocked out of the outputs an acknowledge signal on the SDA line.
slave. In this case, the slave (24LC08B/16B) will leave Depending on the state of the R/W bit, the 24LC08B/
the data line HIGH to enable the master to generate the 16B will select a read or write operation.
STOP condition.
Control
Operation Block Select R/W
Code
Read 1010 Block Address 1
Write 1010 Block Address 0

FIGURE 5-1: CONTROL BYTE

ALLOCATION
START READ/WRITE

SLAVE ADDRESS R/W A

1 0 1 0 B2 B1 B0

FIGURE 5-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

START ADDRESS OR DATA STOP

CONDITION ACKNOWLEDGE ALLOWED CONDITION
VALID TO CHANGE

 1997 Microchip Technology Inc. DS21224A-page 5

24LC08B/16B MODULES
6.0 WRITE OPERATIONS 6.2 Page Write

6.1 Byte Write The write control byte, word address and the first data
byte are transmitted to the 24LC08B/16B in the same
Following the start condition from the master, the way as in a byte write. But instead of generating a stop
device code (4 bits), the block address (3 bits), and the condition the master transmits up to 16 data bytes to
R/W bit which is a logic low is placed onto the bus by the 24LC08B/16B which are temporarily stored in the
the master transmitter. This indicates to the addressed on-chip page buffer and will be written into the memory
slave receiver that a byte with a word address will follow after the master has transmitted a stop condition. After
after it has generated an acknowledge bit during the the receipt of each word, the four lower order address
ninth clock cycle. Therefore the next byte transmitted by pointer bits are internally incremented by one. The
the master is the word address and will be written into higher order seven bits of the word address remains
the address pointer of the 24LC08B/16B. After receiv- constant. If the master should transmit more than 16
ing another acknowledge signal from the 24LC08B/16B words prior to generating the stop condition, the
the master device will transmit the data word to be writ- address counter will roll over and the previously
ten into the addressed memory location. The 24LC08B/ received data will be overwritten. As with the byte write
16B acknowledges again and the master generates a operation, once the stop condition is received an inter-
stop condition. This initiates the internal write cycle, nal write cycle will begin (Figure 6-2).
and during this time the 24LC08B/16B will not generate
acknowledge signals (Figure 6-1).

FIGURE 6-1: BYTE WRITE

S S
T CONTROL WORD T
BUS ACTIVITY A
MASTER BYTE ADDRESS DATA O
R P
T

SDA LINE S P

A A A
BUS ACTIVITY C C C
K K K

FIGURE 6-2: PAGE WRITE

S S
BUS ACTIVITY T T
MASTER A CONTROL WORD O
R BYTE ADDRESS (n) DATA n DATA n + 1 DATA n + 15 P
T

SDA LINE S P
A A A A A
BUS ACTIVITY C C C C C
K K K K K

DS21224A-page 6  1997 Microchip Technology Inc.

 24LC08B/16B MODULES
7.0 ACKNOWLEDGE POLLING 8.0 READ OPERATIONS
Since the device will not acknowledge during a write Read operations are initiated in the same way as write
cycle, this can be used to determine when the cycle is operations with the exception that the R/W bit of the
complete (this feature can be used to maximize bus slave address is set to one. There are three basic types
throughput). Once the stop condition for a write com- of read operations: current address read, random
mand has been issued from the master, the device ini- read, and sequential read.
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send- 8.1 Current Address Read
ing a start condition followed by the control byte for a
The 24LC08B/16B contains an address counter that
write command (R/W = 0). If the device is still busy with
maintains the address of the last word accessed, inter-
the write cycle, then no ACK will be returned. If the
nally incremented by one. Therefore, if the previous
cycle is complete, then the device will return the ACK
access (either a read or write operation) was to
and the master can then proceed with the next read or
address n, the next current address read operation
write command. See Figure 7-1 for flow diagram.
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the
FIGURE 7-1: ACKNOWLEDGE POLLING 24LC08B/16B issues an acknowledge and transmits
FLOW the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
Send 24LC08B/16B discontinues transmission (Figure 8-1).
Write Command
8.2 Random Read
Random read operations allow the master to access
Send Stop
any memory location in a random manner. To perform
Condition to
Initiate Write Cycle this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC08B/16B as part of a write operation. After the
word address is sent, the master generates a start con-
Send Start dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The 24LC08B/
Send Control Byte 16B will then issue an acknowledge and transmits the
with R/W = 0 8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC08B/16B discontinues transmission (Figure 8-2).
Did Device NO 8.3 Sequential Read
Acknowledge
(ACK = 0)?
Sequential reads are initiated in the same way as a ran-
YES dom read except that after the 24LC08B/16B transmits
the first data byte, the master issues an acknowledge
Next as opposed to a stop condition in a random read. This
Operation directs the 24LC08B/16B to transmit the next sequen-
tially addressed 8 bit word (Figure 8-3).
To provide sequential reads the 24LC08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

8.4 Noise Protection

The 24LC08B/16B employs a VCC threshold detector
circuit which disables the internal erase/write logic if
the VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

 1997 Microchip Technology Inc. DS21224A-page 7

24LC08B/16B MODULES
FIGURE 8-1: CURRENT ADDRESS READ
S
T CONTROL S
BUS ACTIVITY A T
MASTER BYTE DATA n
R O
T P

SDA LINE S P

A N
BUS ACTIVITY C O
K
A
C
K

FIGURE 8-2: RANDOM READ

S S
T T S
BUS ACTIVITY A CONTROL WORD A CONTROL T
MASTER R BYTE ADDRESS (n) R BYTE DATA (n) O
T T P
S S P
SDA LINE
A A A N
C C C O
K K K
BUS ACTIVITY A
C
K

FIGURE 8-3: SEQUENTIAL READ

S
T
O
BUS ACTIVITY CONTROL P
MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X

SDA LINE P
A A A A N
BUS ACTIVITY C C C C O
K K K K
A
C
K

DS21224A-page 8  1997 Microchip Technology Inc.

 24LC08B/16B MODULES
9.0 SHIPPING METHOD
The micromodules will be shipped to customers in
clear plastic trays. Each tray holds 150 modules, and
the trays can be stacked in a manner similar to shipping
die in waffle packs. A tray drawing with dimensions is
shown in Figure 9-1.

FIGURE 9-1: TRAY DIMENSIONS

9.374 [238.09]

8.145 [206.88]

0.500 [12.70]
0.980 [24.89] TYP

0.860 [21.84] TYP.

14.000 [355.60]
12.040 [305.82]

SMART CARD MODULES ANTISTATIC

R 0.300 [7.62] TYP
R 0.270 [6.86] TYP

0.905 [22.99]
0.617 [15.68]

 1997 Microchip Technology Inc. DS21224A-page 9

 DEVICE SIDE
0.465 ± 0.002
[11.80 ± 0.05]
FIGURE 9-2:

0.090 [2.29] MIN EPOXY 0.285 [7.24] MAX

DS21224A-page 10
FREE AREA (TYP.)
0.146 ± 0.002 0.174 ± 0.002
R. 0.059 [1.50] (4X) [3.71 ± 0.05] [4.42 ± 0.05]

VIA HOLES (8x)

I.D. ¯ 0.026 [0.66]
O.D. ¯ 0.042 [1.06]

0.1043 ± 0.002
[2.65 ± 0.05] TYP.

0.270 [6.86] MAX.

MODULE DIMENSIONS

0.419 ± 0.002 A A
[10.63 ± 0.05]

0.209 ± 0.002
[5.31 ± 0.05]
24LC08B/16B MODULES

0.1043 ± 0.002
[2.65 ± 0.05]
(8x)

0.232 ± 0.002 CONTACT SIDE

[5.90 ± 0.05]

DIE 0.0235 [0.60] MAX.

SECTION A-A
GLOB SIZE
0.015 [0.38] MAX.
FR4 TAPE 0.004 [0.10] MAX.

0.007 [0.18] MAX.

COPPER BASE NICKEL PLATED, 150 MIN m IN

GOLD FLASH 3-7 m IN

 1997 Microchip Technology Inc.

 24LC08B/16B MODULES
24LC08B/16B MODULES PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24LC08B/16B — /MT

Package: MT = Micromodules in trays

Temperature
Blank = 0˚C to +70˚C
Range:

24LC08B 8K bit 2.5V I 2C Serial EEPROM in ISO Module

Device:
24LC16B 16K bit 2.5V I 2C Serial EEPROM in ISO Module

Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office.
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

 1997 Microchip Technology Inc. DS21224A-page 11

M
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All rights reserved. © 1997, Microchip Technology Incorporated, USA. 9/97 Printed on recycled paper.

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DS21224A-page 12  1997 Microchip Technology Inc.