ispLSI and pLSI 1032E ® ®

High-Density Programmable Logic

Features Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates Output Routing Pool
— 64 I/O Pins, Eight Dedicated Inputs
D7 D6 D5 D4 D3 D2 D1 D0
— 192 Registers
— High Speed Global Interconnect A0 C7
— Wide Input Gating for Fast Counters, State D Q
A1 C6

Output Routing Pool

Output Routing Pool

Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic A2 D Q C5
Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY A3 Array GLB C4
D Q

— fmax = 125 MHz Maximum Operating Frequency A4 C3

— tpd = 7.5 ns Propagation Delay A5 D Q
C2
— TTL Compatible Inputs and Outputs A6 C1
— Electrically Erasable and Reprogrammable Global Routing Pool (GRP)
A7 C0
— Non-Volatile
— 100% Tested at Time of Manufacture B0 B1 B2 B3 B4 B5 B6 B7
— Unused Product Term Shutdown Saves Power CLK
Output Routing Pool
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable (ISP™) 5-Volt Only 0139A(A1)-isp

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality Description
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM The ispLSI and pLSI 1032E are High Density Program-
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY mable Logic Devices containing 192 Registers, 64
OF FIELD PROGRAMMABLE GATE ARRAYS Universal I/O pins, eight Dedicated Input pins, four Dedi-
— Complete Programmable Device Can Combine Glue cated Clock Input pins and a Global Routing Pool (GRP).
Logic and Structured Designs The GRP provides complete interconnectivity between
— Enhanced Pin Locking Capability all of these elements. The ispLSI 1032E features 5-Volt
— Four Dedicated Clock Input Pins in-system programmability and in-system diagnostic ca-
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
pabilities. The ispLSI 1032E device offers non-volatile
Minimize Switching Noise reprogrammability of the logic, as well as the intercon-
— Flexible Pin Placement nects to provide truly reconfigurable systems. It is
— Optimized Global Routing Pool Provides Global architecturally and parametrically compatible to the pLSI
Interconnectivity 1032E device, but multiplexes four input pins to control
• ispLSI DEVELOPMENT TOOLS in-system programming. A functional superset of the
ispVHDL™ Systems ispLSI and pLSI 1032 architecture, the ispLSI and pLSI
— VHDL/Verilog-HDL/Schematic Design Options 1032E devices add two new global output enable pins.
— Functional/Timing/VHDL Simulation Options The basic unit of logic on the ispLSI and pLSI 1032E
ispDS™ Software devices is the Generic Logic Block (GLB). The GLBs are
— Lattice HDL or Boolean Logic Entry labeled A0, A1…D7 (see Figure 1). There are a total of 32
— Functional Simulator and Waveform Viewer GLBs in the ispLSI and pLSI 1032E devices. Each GLB
ispDS+™ HDL Synthesis-Optimized Logic Fitter has 18 inputs, a programmable AND/OR/Exclusive OR
— Supports Leading Third-Party Design Environments array, and four outputs which can be configured to be
for Schematic Capture, Synthesis and Timing
either combinatorial or registered. Inputs to the GLB
Simulation
— Static Timing Analyzer come from the GRP and dedicated inputs. All of the GLB
ISP Daisy Chain Download Software outputs are brought back into the GRP so that they can
be connected to the inputs of any GLB on the device.

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com

1032E_05 1
 Specifications ispLSI and pLSI 1032E

Functional Block Diagram

Figure 1. ispLSI and pLSI 1032E Functional Block Diagram

I/O 63
I/O 62
I/O 61
I/O 60

I/O 59
I/O 58
I/O 57
I/O 56

I/O 55
I/O 54
I/O 53
I/O 52

I/O 51
I/O 50
I/O 49
I/O 48

IN 7
IN 6
RESET

Input Bus

Generic Output Routing Pool (ORP)

Logic Blocks
(GLBs)
D7 D6 D5 D4 D3 D2 D1 D0 GOE 1/IN 5
GOE 0/IN 4

I/O 47
C7 I/O 46
I/O 0 I/O 45
I/O 1
A7
C6 I/O 44
I/O 2

Output Routing Pool (ORP)

I/O 3 A6 I/O 43
C5
I/O 42
Output Routing Pool (ORP)

I/O 4 I/O 41
A5

lnput Bus
I/O 5 C4
I/O 6
Global I/O 40

Routing
lnput Bus

I/O 7 A4
C3 I/O 39
Pool I/O 38
I/O 8 A3 (GRP) I/O 37
I/O 9 C2 I/O 36
I/O 10
I/O 11 A2
C1 I/O 35
I/O 34
I/O 12 A1 I/O 33
I/O 13 C0
I/O 32
I/O 14
A0
I/O 15

*SDI/IN 0
B0 B1 B2 B3 B4 B5 B6 B7 CLK 0
*MODE/IN 1 CLK 1
Clock
Distribution CLK 2
Network IOCLK 0
Output Routing Pool (ORP) IOCLK 1
Megablock
Input Bus
*ispEN/NC
*SDO/IN 2
*SCLK/IN 3

I/O 16
I/O 17
I/O 18
I/O 19

I/O 20
I/O 21
I/O 22
I/O 23

I/O 24
I/O 25
I/O 26
I/O 27

I/O 28
I/O 29
I/O 30
I/O 31

Y0
Y1
Y2
Y3

*ISP Control Functions for ispLSI 1032E Only

The devices also have 64 I/O cells, each of which is The GRP has, as its inputs, the outputs from all of the
directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells.
individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the
registered input, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. The signal levels are TTL minimize timing skew.
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed Clocks in the ispLSI and pLSI 1032E devices are se-
independently for fast or slow output slew rate to mini- lected using the Clock Distribution Network. Four
mize overall output switching noise. dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into
the distribution network, and five clock outputs (CLK 0,
Eight GLBs, 16 I/O cells, two dedicated inputs and one CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to
ORP are connected together to make a Megablock (see route clocks to the GLBs and I/O cells. The Clock Distri-
figure 1). The outputs of the eight GLBs are connected to bution Network can also be driven from a special clock
a set of 16 universal I/O cells by the ORP. Each ispLSI GLB (C0 on the ispLSI and pLSI 1032E devices). The
and pLSI 1032E device contains four Megablocks. logic of this GLB allows the user to create an internal
clock from a combination of internal signals within the
device.

2
 Specifications ispLSI and pLSI 1032E

Absolute Maximum Ratings 1

Supply Voltage Vcc ...................................-0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to VCC +1.0V

Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V

Storage Temperature ................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion
is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

SYMBOL PARAMETER MIN. MAX. UNITS

Commercial TA = 0°C to + 70°C 4.75 5.25 V
VCC Supply Voltage
Industrial TA = -40°C to + 85°C 4.5 5.5 V
VIL Input Low Voltage 0 0.8 V
VIH Input High Voltage 2.0 Vcc+1 V
Table 2-0005/1032E

Capacitance (TA=25oC, f=1.0 MHz)

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C1 Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 8 pf VCC = 5.0V, VPIN = 2.0V
(Commercial/Industrial)
C2 Y0 Clock Capacitance 15 pf VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1032E

Data Retention Specifications

PARAMETER MINIMUM MAXIMUM UNITS

Data Retention 20 – Years
ispLSI Erase/Reprogram Cycles 10000 – Cycles
pLSI Erase/Reprogram Cycles 100 – Cycles
Table 2-0008/1032E

3
 Specifications ispLSI and pLSI 1032E

Switching Test Conditions

Input Pulse Levels GND to 3.0V Figure 2. Test Load

Input Rise and Fall Time -125 ≤ 2 ns

+ 5V
10% to 90% Others ≤ 3 ns
Input Timing Reference Levels 1.5V R1
Ouput Timing Reference Levels 1.5V
Output Load See Figure 2 Device Test
Table 2-0003/1032E Output Point
3-state levels are measured 0.5V from
steady-state active level.
R2 CL *
Output Load Conditions (see Figure 2)

TEST CONDITION R1 R2 CL
A 470Ω 390Ω 35pF *CL includes Test Fixture and Probe Capacitance.
0213a

Active High ∞ 390Ω 35pF

B
Active Low 470Ω 390Ω 35pF
Active High to Z ∞ 390Ω 5pF
at VOH -0.5V
C
Active Low to Z 470Ω 390Ω 5pF
at VOL +0.5V
Table 2-0004/1032E

DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
VOL Output Low Voltage IOL= 8 mA – – 0.4 V
VOH Output High Voltage IOH = -4 mA 2.4 – – V
IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 µA
IIH Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 µA
IIL-isp ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 µA
IIL-PU I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 µA
IOS1 Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA
VIL = 0.5V, VIH = 3.0V Commercial – 190 – mA
ICC2, 4 Operating Power Supply Current
fCLOCK = 1 MHz Industrial – 190 – mA
Table 2-0007/1032E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .

4
 Specifications ispLSI and pLSI 1032E

External Timing Parameters

Over Recommended Operating Conditions
4 -125 -100
TEST 2 1
PARAMETER # DESCRIPTION UNITS
COND. MIN. MAX. MIN. MAX.
tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 ns
tpd2 A 2 Data Propagation Delay, Worst Case Path – 10.0 – 12.5 ns
fmax (Int.) A 3 Clock Frequency with Internal Feedback 3
125 – 100 – MHz
1
fmax (Ext.) – 4 Clock Frequency with External Feedback ( )
tsu2 + tco1 91.0 – 71.0 – MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle ( twh 1+ tw1 ) 167 – 125 – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass 5.0 – 7.0 – ns
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 5.0 – 6.0 ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clock 6.0 – 8.0 – ns
tco2 – 10 GLB Reg. Clock to Output Delay – 6.0 – 7.0 ns
th2 – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay – 10.0 – 13.5 ns
trw1 – 13 Ext. Reset Pulse Duration 5.0 – 6.5 – ns
tptoeen B 14 Input to Output Enable – 12.0 – 15.0 ns
tptoedis C 15 Input to Output Disable – 12.0 – 15.0 ns
tgoeen B 16 Global OE Output Enable – 7.0 – 9.0 ns
tgoedis C 17 Global OE Output Disable – 7.0 – 9.0 ns
twh – 18 External Synchronous Clock Pulse Duration, High 3.0 – 4.0 – ns
twl – 19 External Synchronous Clock Pulse Duration, Low 3.0 – 4.0 – ns
tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 – 3.5 – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 – 0.0 – ns
Table 2-0030A/1032E
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

5
 Specifications ispLSI and pLSI 1032E

External Timing Parameters

Over Recommended Operating Conditions
4 -90 -80 -70
TEST 2 1
PARAMETER # DESCRIPTION UNITS
COND. MIN. MAX. MIN. MAX. MIN. MAX.
tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 12.0 – 15.0 ns
tpd2 A 2 Data Propagation Delay, Worst Case Path – 12.5 – 15.0 – 17.5 ns
fmax (Int.) A 3 Clock Frequency with Internal Feedback 3 90.0 – 80.0 – 70.0 – MHz
1
fmax (Ext.) – 4 Clock Frequency with External Feedback ( )
tsu2 + tco1 69.0 – 61.0 – 56.0 – MHz

DES 0 FOR
1
fmax (Tog.) – 5 Clock Frequency, Max. Toggle ( twh + tw1 ) 125 – 111 – 100 – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass 7.5 – 8.5 – 9.0 – ns

S
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 6.0 – 6.5 – 7.0 ns

IGN
NEW 2E-10
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clock 8.5 – 10.0 – 11.0 – ns
tco2 – 10 GLB Reg. Clock to Output Delay – 7.0 – 7.5 – 8.0 ns
th2 – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – 0.0 – ns

103
tr1 A 12 Ext. Reset Pin to Output Delay – 13.5 – 14.0 – 15.0 ns
trw1 – 13 Ext. Reset Pulse Duration 6.5 – 8.0 – 10.0 – ns

USE
tptoeen B 14 Input to Output Enable – 15.0 – 16.5 – 18.0 ns
tptoedis C 15 Input to Output Disable – 15.0 – 16.5 – 18.0 ns
tgoeen B 16 Global OE Output Enable – 9.0 – 10.0 – 12.0 ns
tgoedis C 17 Global OE Output Disable – 9.0 – 10.0 – 12.0 ns
twh – 18 External Synchronous Clock Pulse Duration, High 4.0 – 4.5 – 5.0 – ns
twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 – 4.5 – 5.0 – ns
tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5 – 3.5 – 4.0 – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 – 0.0 – 0.0 – ns
Table 2-0030B/1032E
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.

6
 Specifications ispLSI and pLSI 1032E

Internal Timing Parameters1

2
-125 -100
PARAM. # DESCRIPTION UNITS
MIN. MAX. MIN. MAX.
Inputs
tiobp 22 I/O Register Bypass – 0.3 – 0.3 ns
tiolat 23 I/O Latch Delay – 1.9 – 2.3 ns
tiosu 24 I/O Register Setup Time before Clock 3.0 – 3.5 – ns
tioh 25 I/O Register Hold Time after Clock 0.0 – 0.0 – ns
tioco 26 I/O Register Clock to Out Delay – 4.6 – 5.0 ns
tior 27 I/O Register Reset to Out Delay – 4.6 – 5.0 ns
tdin 28 Dedicated Input Delay – 2.3 – 2.7 ns
GRP
tgrp1 29 GRP Delay, 1 GLB Load – 1.8 – 1.9 ns
tgrp4 30 GRP Delay, 4 GLB Loads – 2.0 – 2.4 ns
tgrp8 31 GRP Delay, 8 GLB Loads – 2.3 – 2.4 ns
tgrp16 32 GRP Delay, 16 GLB Loads – 2.8 – 3.0 ns
tgrp32 33 GRP Delay, 32 GLB Loads – 3.8 – 4.2 ns
GLB
t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial) – 3.9 – 5.3 ns
t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered) – 4.0 – 5.3 ns
t1ptxor 36 1 Prod.Term/XOR Path Delay – 3.6 – 4.6 ns
t20ptxor 37 20 Prod. Term/XOR Path Delay – 5.0 – 5.8 ns
txoradj 38 XOR Adjacent Path Delay 3 – 5.0 – 6.3 ns
tgbp 39 GLB Register Bypass Delay – 0.4 – 1.0 ns
tgsu 40 GLB Register Setup Time before Clock 0.1 – 0.5 – ns
tgh 41 GLB Register Hold Time after Clock 4.5 – 5.8 – ns
tgco 42 GLB Register Clock to Output Delay – 2.3 – 2.5 ns
tgro 43 GLB Register Reset to Output Delay – 4.9 – 6.2 ns
tptre 44 GLB Prod.Term Reset to Register Delay – 3.9 – 4.5 ns
tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay – 5.4 – 7.2 ns
tptck 46 GLB Prod. Term Clock Delay 2.9 4.0 3.5 4.7 ns
ORP
torp 47 ORP Delay – 1.0 – 1.0 ns
torpbp 48 ORP Bypass Delay – 0.0 – 0.0 ns
Table 2-0036A/1032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

7
 Specifications ispLSI and pLSI 1032E

Internal Timing Parameters1

2 -90 -80 -70

PARAM. # DESCRIPTION UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tiobp 22 I/O Register Bypass – 0.3 – 0.3 – 0.3 ns
tiolat 23 I/O Latch Delay – 2.3 – 2.7 – 3.3 ns
tiosu 24 I/O Register Setup Time before Clock 3.5 – 3.5 – 4.0 – ns
tioh 25 I/O Register Hold Time after Clock 0.0 – 0.0 – 0.0 – ns
tioco 26 I/O Register Clock to Out Delay – 5.0 – 5.4 – 6.1 ns
tior 27 I/O Register Reset to Out Delay – 5.0 – 5.4 – 6.0 ns
tdin 28 Dedicated Input Delay – 2.6 – 2.8 – 2.8 ns
GRP
tgrp1 29 GRP Delay, 1 GLB Load – 2.1 – 2.2 – 2.5 ns

DES 0 FOR
tgrp4 30 GRP Delay, 4 GLB Loads – 2.3 – 2.5 – 2.5 ns
tgrp8 31 GRP Delay, 8 GLB Loads – 2.6 – 2.8 – 3.2 ns

S
IGN
tgrp16 32 GRP Delay, 16 GLB Loads – 3.2 – 3.5 – 4.0 ns

NEW 2E-10
tgrp32 33 GRP Delay, 32 GLB Loads – 4.4 – 4.8 – 5.6 ns
GLB
t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial) – 5.7 – 7.1 – 8.8 ns

103
t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered) – 6.1 – 6.7 – 7.2 ns
t1ptxor 36 1 Prod.Term/XOR Path Delay – 5.6 – 6.6 – 8.3 ns
t20ptxor 37 20 Prod. Term/XOR Path Delay – 6.8 – 7.8 – 8.7 ns
USE

txoradj 38 XOR Adjacent Path Delay 3 – 7.1 – 8.2 – 9.2 ns

tgbp 39 GLB Register Bypass Delay – 0.4 – 1.3 – 1.6 ns
tgsu 40 GLB Register Setup Time before Clock 0.2 – 0.5 – 0.5 – ns
tgh 41 GLB Register Hold Time after Clock 6.8 – 7.9 – 8.8 – ns
tgco 42 GLB Register Clock to Output Delay – 2.9 – 2.9 – 2.9 ns
tgro 43 GLB Register Reset to Output Delay – 6.3 – 6.4 – 6.8 ns
tptre 44 GLB Prod.Term Reset to Register Delay – 5.1 – 5.5 – 5.8 ns
tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay – 7.1 – 8.0 – 9.0 ns
tptck 46 GLB Prod. Term Clock Delay 4.1 5.3 4.5 5.8 4.8 6.2 ns
ORP
torp 47 ORP Delay – 1.0 – 1.0 – 1.0 ns
torpbp 48 ORP Bypass Delay – 0.0 – 0.0 – 0.0 ns
Table 2-0036B/1032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

8
 Specifications ispLSI and pLSI 1032E

Internal Timing Parameters1

-125 -100
PARAM. # DESCRIPTION UNITS
MIN. MAX. MIN. MAX.
Outputs
tob 49 Output Buffer Delay – 1.3 – 2.0 ns
tsl 50 Output Buffer Delay, Slew Limited Adder – 9.9 – 10.0 ns
toen 51 I/O Cell OE to Output Enabled – 4.3 – 5.1 ns
todis 52 I/O Cell OE to Output Disabled – 4.3 – 5.1 ns
tgoe 53 Global OE – 2.7 – 3.9 ns
Clocks
tgy0 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) 1.4 1.4 1.5 1.5 ns
tgy1/2 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line 1.4 1.4 1.5 1.5 ns
tgcp 56 Clk Delay, Clock GLB to Global GLB Clk Line 0.8 1.8 0.8 1.8 ns
tioy2/3 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line 0.0 0.0 0.0 0.0 ns
tiocp 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line 0.8 1.8 0.8 1.8 ns
Global Reset
tgr 59 Global Reset to GLB and I/O Registers – 2.8 – 4.3 ns
Table 2-0037A/1032E
1. Internal Timing Parameters are not tested and are for reference only.

9
 Specifications ispLSI and pLSI 1032E

Internal Timing Parameters1

-90 -80 -70

PARAM. # DESCRIPTION UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Outputs
tob 49 Output Buffer Delay – 1.7 – 2.1 – 2.6 ns

DES 0 FOR
tsl 50 Output Buffer Delay, Slew Limited Adder – 10.0 – 10.0 – 10.0 ns
toen 51 I/O Cell OE to Output Enabled – 5.3 – 5.7 – 6.2 ns

S
todis 52 I/O Cell OE to Output Disabled – 5.3 – 5.7 – 6.2 ns

IGN
tgoe 3.7 4.3

NEW 2E-10
53 Global OE – – – 5.8 ns
Clocks
tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.4 1.4 1.5 1.5 1.5 1.5 ns
tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.4 2.9 2.6 3.1 1.5 1.5 ns

103
tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 1.8 0.8 1.8 0.8 1.8 ns
tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 0.0 0.0 0.0 0.0 0.0 ns

USE
tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 1.8 0.8 1.8 0.8 1.8 ns
Global Reset
tgr 59 Global Reset to GLB and I/O Registers – 4.5 – 4.5 – 4.6 ns
Table 2-0037B/1032E
1. Internal Timing Parameters are not tested and are for reference only.

10
 Specifications ispLSI and pLSI 1032E

ispLSI and pLSI 1032E Timing Model

I/O Cell GRP GLB ORP I/O Cell

Feedback

Ded. In #34 Comb 4 PT Bypass

#28
I/O Reg Bypass GRP4 Reg 4 PT Bypass GLB Reg Bypass ORP Bypass
I/O Pin #49, 50 I/O Pin
#22 #30 #35 #39 #48
(Input) (Output)
Input GRP Loading 20 PT GLB Reg ORP
D Register Q Delay XOR Delays Delay Delay #51, 52
RST D Q
#59 #23 - 27 #29, 31 - 33 #36 - 38 #47
RST
#59
Reset #40 - 43

Clock Control RE
Distribution
PTs OE
0491
Y1,2,3 #55 - 58 #44 - 46 CK

#54
Y0
#53
GOE 0,1

Derivations of tsu, th and tco from the Product Term Clock 1

tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)

th = Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
3.5 ns = (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)

tco = Clock (max) + Reg co + Output

= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#47 + #49)
10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)

Derivations of tsu, th and tco from the Clock GLB 1

tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
2.9 ns = (0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)

th = Clock (max) + Reg h - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
2.7 ns = (1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)

tco = Clock (max) + Reg co + Output

= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#54 + #42 + #56) + (#42) + (#47 + #49)
5.5 ns = (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)

1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032E-125.
Table 2-0042a/1032E

11
 Specifications ispLSI and pLSI 1032E
Maximum GRP Delay vs GLB Loads

6.0
ispLSI and pLSI 1032E-70
5.0

GRP Delay (ns)

ispLSI and pLSI 1032E-80
ispLSI and pLSI 1032E-90/100
4.0 ispLSI and pLSI 1032E-125

3.0

2.0

1.0
1 4 8 16 32
GLB Load
GRP/GLB/1032E

Power Consumption
Power consumption in the ispLSI and pLSI 1032E device used. Figure 3 shows the relationship between power
depends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of product terms

Figure 3. Typical Device Power Consumption vs fmax

350

300 ispLSI and pLSI 1032E

ICC (mA)

250

200

150

100

0 20 40 60 80 100 125 150

fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C

I CC can be estimated for the ispLSI and pLSI 1032E using the following equation:
I CC (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)

The I CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating
conditions and the program in the device, the actual I CC should be verified.
0127/1032E

12
 Specifications ispLSI and pLSI 1032E

Pin Description

PLCC PIN TQFP PIN

NAME DESCRIPTION
NUMBERS NUMBERS
I/O 0 - I/O 3 26, 27, 28, 29, 17, 18, 19, 20, Input/Output Pins - These are the general purpose I/O pins used by the logic
I/O 4 - I/O 7 30, 31, 32, 33, 21, 22, 23, 28, array.
I/O 8 - I/O 11 34, 35, 36, 37, 29, 30, 31, 32,
I/O 12 - I/O 15 38, 39, 40, 41, 33, 34, 35, 36,
I/O 16 - I/O 19 45, 46, 47, 48, 40, 41, 42, 43,
I/O 20 - I/O 23 49, 50, 51, 52, 44, 45, 46, 47,
I/O 24 - I/O 27 53, 54, 55, 56, 48, 53, 54, 55,
I/O 28 - I/O 31 57, 58, 59, 60, 56, 57, 58, 59,
I/O 32 - I/O 35 68, 69, 70, 71, 67, 68, 69, 70,
I/O 36 - I/O 39 72, 73, 74, 75, 71, 72, 73, 78,
I/O 40 - I/O 43 76, 77, 78, 79, 79, 80, 81, 82,
I/O 44 - I/O 47 80, 81, 82, 83, 83, 84, 85, 86,
I/O 48 - I/O 51 3, 4, 5, 6, 90, 91, 92, 93,
I/O 52 - I/O 55 7, 8, 9, 10, 94, 95, 96, 97,
I/O 56 - I/O 59 11, 12, 13, 14, 98, 3, 4, 5,
I/O 60 - I/O 63 15, 16, 17, 18 6, 7, 8, 9

GOE 0/IN 4 67 66 This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.

GOE 1/IN 5 84 87 This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.

IN 6, IN 7 2, 19 89, 10 Dedicated input pins to the device.

ispEN**/NC 23 14 Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK options become active.
SDI*/IN 0 25 16 Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 is also
used as one of the two control pins for the isp state machine. It is a
dedicated input pin when ispEN is logic high.
MODE*/IN 1 42 37 Input - This pin performs two functions. When ispEN is logic low, it functions
as pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
SDO*/IN 2 44 39 Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
SCLK*/IN 3 61 60 Input - This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. It is a dedicated input pin when
ispEN is logic high.

RESET 24 15 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the
device.
Y0 20 11 Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Y1 66 65 Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB on the device.

Y2 63 62 Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any GLB and/or any I/O cell on the
device.
Y3 62 61 Dedicated Clock input. This clock input is brought into the clock distribution
network, and can optionally be routed to any I/O cell on the device.

GND 1, 22, 43, 64 13, 38, 63, 88 Ground (GND)

VCC 21, 65 12, 64 Vcc

NC 1, 2, 24, 25, No connect.

26, 27, 49, 50,
51, 52, 74, 75,
76, 77, 99, 100
Table 2-0002A/1032E
* ispLSI 1032E only
** ispEN for ispLSI 1032E; NC for pLSI 1032E, must be left floating or tied to VCC, must not be grounded or tied
to any other signal.

13
 Specifications ispLSI and pLSI 1032E

Pin Configurations

ispLSI and pLSI 1032E 84-Pin PLCC Pinout Diagram

**GOE 1/IN 5
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48

I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
GND
IN 6
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

I/O 57 12 74 I/O 38
I/O 58 13 73 I/O 37
I/O 59 14 72 I/O 36
I/O 60 15 71 I/O 35
I/O 61 16 70 I/O 34
I/O 62 17 69 I/O 33
I/O 63 18 68 I/O 32
IN 7 19 67 **GOE 0/IN 4
Y0 20 66 Y1
VCC 21 ispLSI 1032E 65 VCC
GND 22 pLSI 1032E 64 GND
*ispEN/NC 23 Top View 63 Y2
RESET 24 62 Y3
*SDI/IN 0 25 61 *SCLK/IN 3
I/O 0 26 60 I/O 31
I/O 1 27 59 I/O 30
I/O 2 28 58 I/O 29
I/O 3 29 57 I/O 28
I/O 4 30 56 I/O 27
I/O 5 31 55 I/O 26
I/O 6 32 54 I/O 25

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*MODE/IN 1
GND
*SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24

* Pins have dual function capability for ispLSI 1032E only (except pin 23, which is ispEN only).
** Pins have dual function capability which is software selectable.
0123-32-isp

14
 Specifications ispLSI and pLSI 1032E

Pin Configurations

ispLSI 1032E 100-Pin TQFP Pinout Diagram

**GOE 1/IN 5
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48

I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
GND
IN 6
NC
NC

NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC 1 75 NC
NC 2 74 NC
I/O 57 3 73 I/O 38
I/O 58 4 72 I/O 37
I/O 59 5 71 I/O 36
I/O 60 6 70 I/O 35
I/O 61 7 69 I/O 34
I/O 62 8 68 I/O 33
I/O 63 9 67 I/O 32
IN 7 10 66 **GOE 0/IN 4
Y0 11 ispLSI 1032E 65 Y1
VCC 12 64 VCC
GND 13 Top View 63 GND
ispEN 14 62 Y2
RESET 15 61 Y3
*SDI/IN 0 16 60 *SCLK/IN 3
I/O 0 17 59 I/O 31
I/O 1 18 58 I/O 30
I/O 2 19 57 I/O 29
I/O 3 20 56 I/O 28
I/O 4 21 55 I/O 27
I/O 5 22 54 I/O 26
I/O 6 23 53 I/O 25
NC 24 52 NC
NC 25 51 NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*MODE/IN1
GND
*SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
NC
NC

* Pins have dual function capability.

** Pins have dual function capability which is software selectable.
0766A-32E-isp

15
 Specifications ispLSI and pLSI 1032E

Part Number Description

(is)pLSI 1032E – XXX X X X

Device Family Grade
Blank = Commercial
I = Industrial
Device Number
Package
J = PLCC
T = TQFP
Speed
Power
125 = 125 MHz fmax
L = Low
100 = 100 MHz fmax
0212/1032E
90 = 90 MHz fmax
80 = 80 MHz fmax
70 = 70 MHz fmax

ispLSI and pLSI 1032E Ordering Information

COMMERCIAL

s.
FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
125 7.5 ispLSI 1032E-125LJ 84-Pin PLCC

gn
125 7.5 ispLSI 1032E-125LT 100-Pin TQFP

si
100 10 ispLSI 1032E-100LJ 84-Pin PLCC
100 10 ispLSI 1032E-100LT 100-Pin TQFP
de
ispLSI
90 10 ispLSI 1032E-90LJ* 84-Pin PLCC
90 10 ispLSI 1032E-90LT* 100-Pin TQFP
w

80 12 ispLSI 1032E-80LJ* 84-Pin PLCC

ne

80 12 ispLSI 1032E-80LT* 100-Pin TQFP

70 15 ispLSI 1032E-70LJ 84-Pin PLCC
l
al

70 15 ispLSI 1032E-70LT 100-Pin TQFP

125 7.5 pLSI 1032E-125LJ 84-Pin PLCC
r
fo

100 10 pLSI 1032E-100LJ 84-Pin PLCC

pLSI 90 10 pLSI 1032E-90LJ* 84-Pin PLCC
SI

80 12 pLSI 1032E-80LJ* 84-Pin PLCC

pL

70 15 pLSI 1032E-70LJ 84-Pin PLCC

Table 2-0041A/1032E
*ispLSI 1032E-100 recommended for new designs.
is

INDUSTRIAL
se

FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE

U

70 15 ispLSI 1032E-70LJI 84-Pin PLCC

ispLSI
70 15 ispLSI 1032E-70LTI 100-Pin TQFP
e:

Table 2-0041B/1032E
ot
N

16
Copyright © 1997 Lattice Semiconductor Corporation.

E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice
Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation.
Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispDS, ispDS+, ispGDS, ispGDX, ispHDL, ispJTAG, ispStarter,
ispSTREAM, ispTEST, ispTURBO, ispVECTOR, ispVerilog, ispVHDL, Latch-Lock, LHDL, pDS+, RFT, Total ISP and Twin
GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All
brand names or product names mentioned are trademarks or registered trademarks of their respective holders.

Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international
patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296
US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US,
5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US,
5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US,
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represent that products described herein are free from patent infringement or from any third-party right.

The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC)
reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors
contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers
obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is
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LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard
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LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of
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LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such
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