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 EC8691
MICROPROCESSORS
&
MICROCONTROLLERS
Department: CSE & IT

Batch/Year: 2019-23 / III YEAR

Created by:
S.D. Lalitha, Assistant Professor

Date: 01.9.2021
 Table of Contents
Course Objectives
Pre Requisites
Syllabus
Course outcomes
CO- PO/PSO Mapping
Lecture Plan
Activity based learning
Unit 1 :
Lecture Notes
Lecture Notes – Links to Videos
Lecture Notes – e book reference
Lecture Notes – PPTs
Lecture Notes - Quiz
Lecture Notes - References
Assignments
Part A Q & A (with K level and CO)
Part B Qs (with K level and CO)
Supportive online Certification courses
Real time Applications in day to day life and to Industry
Contents beyond the Syllabus
Assessment Schedule
Prescribed Text Books & Reference Books
Mini Project suggestions
 Course Objectives

To understand the Architecture of 8086 microprocessor.

To learn the design aspects of I/O and Memory Interfacing

circuits.

To interface microprocessors with supporting chips.

To study the Architecture of 8051 microcontrollers.

To design a microcontroller based system

 Pre Requisites
GE8151 Problem Solving and Python Programming

GE8161 Problem Solving and Python Programming Lab

CS8251 Programming in C

CS8261 C Programming Lab

CS8491 Computer Architecture

CS8493 Operating System

 Syllabus
EC8691 MICROPROCESSORS AND MICROCONTROLLERS 3003

UNIT I THE 8086 MICROPROCESSOR

Introduction to 8086 – Microprocessor architecture – Addressing modes – Instruction
set and assembler directives – Assembly language programming – Modular
Programming – Linking and Relocation – Stacks – Procedures – Macros – Interrupts
and interrupt serv ice routines – Byte and String Manipulation.

UNIT II 8086 SYSTEM BUS STRUCTURE

8086 signals – Basic configurations – System bus timing –System design using 8086
– I/O programming – Introduction to Multiprogramming – System Bus Structure –
Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled
configurations – Introduction to advanced processors.

UNIT III I/O INTERFACING

Memory Interfacing and I/O interfacing – Parallel communication interface – Serial
communication interface – D/A and A/D Interface – Timer – Keyboard /display
controller – Interrupt controller –DMA controller – Programming and applications
Case studies: Traffic Light control, LED display , LCD display, Keyboard display
interface and Alarm Controller.

UNIT IV MICROCONTROLLER
Architecture of 8051 – Special Function Registers(SFRs) – I/O Pins Ports and Circuits
– Instruction set – Addressing modes – Assembly language
programming.

UNIT V INTERFACING MICROCONTROLLER

Programming 8051 Timers – Serial Port Programming – Interrupts Programming –
LCD & Keyboard Interfacing – ADC, DAC & Sensor Interfacing – External Memory
Interface- Stepper Motor and Waveform generation – Comparison of Microprocessor,
Microcontroller, PIC and ARM processors.
 Course outcomes
1. Understand and execute programs based on 8086
microprocessor.

2. Understand the configurations of 8086 and able to design a

system.

3. Design Memory Interfacing circuits with 8086.

4. Design and interface I/O circuits with 8086.

5. Understand and execute programs based on 8051

microcontroller.

6. Design and implement 8051 microcontroller based systems.

 CO- PO/PSO Mapping

CO PO PO PO PO PO PO PO PO PO PO PO PO PS PS PS

1 2 3 4 5 6 7 8 9 10 11 12 O1 O2 O3

1 3 3 3 - - - - - - - - - 3 - -

2 3 2 2 - - - - - - - - - 3 - -

3 3 3 3 - - - - - - - - - 3 - -

4 3 3 3 - - - - - - - - - 3 - -

5 3 2 2 - - - - - - - - - 3 - -

6 3 3 3 - - - - - - - - - 3 - -
 Unit I - THE 8086
MICROPROCESSOR
 Lecture Plan
per
Ses No. Proposed Actual tai Taxon Mode
Topics to be
sion of date Lecture nin omy of
covered
No. Per Date g level Deliver
iod CO y
s

Introduction to 8086 &

1 Microprocessor 9 20.08.2021 20.08.2021 1 K1 PPT

architecture

2 Addressing modes 9 23.08.2021 23.08.2021 1 K2 PPT

3 Instruction set 9 24.08.2021 24.08.2021 1 K2 PPT

4 Instruction set 9 25.08.2021 25.08.2021 1 K2 PPT

5 Assembler directives 9 26.08.2021 26.08.2021 1 K2 PPT

Assembly language
6 9 27.08.2021 27.08.2021 1 K3 PPT
programming

Modular Programming

7 – Linking and 9 28.08.2021 28.08.2021 1 K2 PPT

Relocation

Stacks – Procedures –

Macros – Interrupts
8 9 31.08.2021 31.08.2021 1 K2 PPT
and interrupt service

routines

Byte and String

9 9 01.09.2021 01.09.2021 1 K3 PPT
Manipulation.
 Activity based learning
1. The Students actively involved in solving the cross-word
puzzles.

Link to the activity :

https://drive.google.com/file/d/1P0Z7tY2dNhWc0oOalD0ROIO7wKUCRo
bI/view?usp=sharing

2. Component Based Learning:

YouTube Link:

https://www.youtube.com/watch?v=Uh7jx_Feq4w

3. Project Based Learning

YouTube Link:

https://www.youtube.com/watch?v=0e52QKSE1YU
 Lecture Notes
THE 8086 MICROPROCESSOR

1.1 Introduction to 8086

What is a microprocessor?

A microprocessor is a computer processor which incorporates the functions of a computer's

central processing unit (CPU) on a single integrated circuit (IC), or at most a few integrated
circuits. The microprocessor is a multipurpose, c lock driven, register based, programmable
electronic device which accepts digital or binary data as input, processes it according to
instructions stored in its memory, and provides results as output. Microprocessors contain
both combinational logic and sequential digital logic.

Microprocessors operate on numbers and symbols represented in the binary numeral

system. Microprocessor is the controlling unit or CPU of a micro-computer, fabricated on a
very small chip capable of performing ALU operations and communicating with the external
word connected to it. It forms a micro-computer when combined with memory and
Input/output devices.

Microprocessors of different word size with varying decrease of capabilities are available.
Microprocessor comprises of all the functional components of the central processing unit of
a general purpose computer. In other words, functionally it is equivalent to a CPU.

• Cost: The most important characteristics of a microcomputer is its low cost. Because of the
widespread use of microprocessors, the volume of production is very high. That is why,
microprocessor chips are available at fairly low prices.

• Reliability: Another important property of VLSI devices which has also been in
herniated by microprocessors is extreme reliability. It has been established that the
failure rate of an IC is fairly uniform at the package level, regardless of its
complexity.
 Lecture Notes
• Size: The second important features of a microprocessor is its small size. As a
result of improvement in fabrication technology, VLSI, electronic circuitry has
become so dense that a minute silicon chip can contain hundred and thousands of
transistors constituting the microprocessor. Its size does not exceed a few inches on
any side, even in the packaged form.

• Power Consumption: The another important characteristics is its low power

consumption microprocessors are normally manufactured by Metal-Ox ide
semiconductor technology.

• Versatility: The versatility of a microprocessor results from its stored program

mode of operation. Keeping the same basic hardware, a microprocessor-based
system can be configured for a number of applications simplify altering the software
program. This also makes it very flexible.

OVERVIEW OF A SIMPLE MICRO COMPUTER:

Fig. Block diagram of simple computer or microcomputer

 Lecture Notes
The major parts are the central processing unit or CPU, memory, and the input and
output circuitry or I/O. Connecting these parts together are three sets of parallel
lines called buses. The three buses are the address bus, the data bus, and the
control bus.

i) MEMORY: The memory section usually consists of a mixture of RAM and ROM. It
may also have magnetic floppy disks, magnetic hard disks, or laser optical disks.
Memory has two purposes. The first purpose is to store the binary codes for the
sequence of instructions you want the computer to carry out. When you write a
computer program, what you are really doing is just writing a sequential list of
instructions for the computer. The second purpose of the memory is to store the
binary-coded data with which the computer is going to be working.

ii) INPUT/OUTPUT: The input/output or I/O section allows the computer to take in
data from the outside world or send data to the outside world. These allow the user
and the computer to communicate with each other. The actual physical dev ices used
to interface the computer buses to external systems are often called ports.

iii) CPU: The central processing unit or CPU controls the operation of the computer.
It fetches binary-coded instruction of the computer. It fetches binary-coded
instructions from memory, decodes the instructions into a series of simple actions,
and carries out these actions. The CPU contains an arithmetic logic unit, or ALU.
Which can perform add, subtract, OR, AND, invert, or exclusive-OR operations on
binary words when instructed to do so. The CPU also contains an address counter
which is used to hold the address of the next instruction or data to be fetched from
memory, general-purpose registers which are used for temporary storage of binary
data, and circuitry which generates the control bus signals
 Lecture Notes
iv) ADDRESS BUS: The address bus consists of 16, 20, 24, or more parallel signal
lines. On these lines the CPU sends out the address of the memory location that is
to be written to or read from. The number of address lines determines the number
of memory locations that the CPU can address. If the CPU has N address lines, then
it can directly address 2N memory locations.

v) DATA BUS: The data bus consists of 8, 16, 32 or more parallel signal lines. As
indicated by the double-ended arrows on the data bus line, the data bus lines are bi-
directional. This means that the CPU can read data in on these lines from memory or
from a port as well as send data out on these lines to memory location or to a port.
Many devices in a system will have their outputs connected to the data bus, but the
outputs of only one device at a time will be enabled.

vi) CONTROL BUS: The control bus consists of 4-10 parallel signal lines. The CPU
sends out signals on the control bus to enable the outputs of addressed memory
devices or port dev ices. Typical control bus signals are memory read, memory write,
I/O read, and I/O writer. To read a byte of data from a memory location, for
example, the CPU sends out the address of the desired byte on the address bus and
then sends out a memory read signal on the control bus.
 Lecture Notes
1.2 Microprocessor Architecture

The architecture of 8086 provide a number of improvements over 8085 architecture.

It supports 16bit ALU, a set of 16 bit registers and provides segmented memory
addressing capability, a rich instruction set, a powerful interrupt structure,
fetched instruction queue for overlapped fetching and execution etc.

The complete architecture of 8086 can be divided into two parts:

BIU Bus interface unit

(EU) Execution unit

 Lecture Notes
BIU: The bus interface unit contains the circuit for physical address calculations and a pre
coding instruction byte queue (6 bytes long).

The BIU makes the system bus signals available for external inter fac ing of devices. The
other words, this unit is responsible for establishing communications with external devices
and peripherals including memory via bus. The incomplete physical address which is 20 bits
long is generated using segment and offset registers each 16bit long.

For generating a physical address from contents of these 2 registers, the content of a
segment register is also called as offset address is added to produce 20bit physical address.

For e.g. if the segment address is 1005H & the offset is 5555H then the physical address is
calculated as

Segment address -> 1005H Offset address -> 5555H

Segment address -> 1005H - 0001 0000 0000 0101

Shifted by 4bits position - 0001 0000 0000 0101 0000

Offset address - 0101 0101 0101 0101

on adding both,

Physical address - 0001 0101 0101 1010 0101

i.e. 1 5 5 A 5 H

The segment register indicates the base address of a particular segment while the offset
indicates the distance of the required memory location in the segment from the base
address. the segment address value is to be taken from an appropriate segment register
depending upon whether code, data or stack are to be accessed, while the offset may be
the content of IP, BX, SI, DI, SP or an immediate 16-bit value, depending upon the
addressing mode.

In 8086 it is possible to achieve the overlapped fetch & the execution cycles. While the
fetched instruction is executed internally, the external bus is used to fetch the machine code
of next instruction & arrange it in a queue called pre coded instruction byte queue.
 Lecture Notes
It is a 6 byte long First In First Out structure. The instruction from the queue are
taken for decoding sequentially once the byte is decoded the queue is rearranged by
pushing it out & the queue status is checked for the possibility of next opcode fetch
cycle. While the opcode is fetched by the BIU the EU executes the previously
decoded instruction concurrently. The BIU along with the EU thus forms a
PIPELINE. The bus interface unit manages the complete interface of execution unit
memory & input devices of course under the control of timing & control unit.

EU (EXECUTION UNIT):

The execution unit contains register set of 8086 except segment register & IP. It has
a 16 bit ALU able to perform arithmetic & logic operations. The 16-bit flag register
reflects the result of execution by ALU. The decoding unit decodes the opcode bytes
issued from the instruction byte queue.

The timing & control unit derives the necessary control signals to execute the
instruction opcode retrieved from the queue depending upon the information unit
may pass the results to the BIU for storing them in memory.

Register organization of 8086:

All the registers of 8086 are 16-bit registers. The general purpose registers, can be
used either 8- bit registers or 16-bit registers used for holding the data, variables
and intermediate results temporarily or for other purpose like counter or for storing
offset address for some
 Lecture Notes
Fig. 1. Register set of 8086

particular addressing modes etc. The special purpose registers are used as segment
registers, pointers, index registers or as offset storage registers for particular
addressing modes.

AX Register: Accumulator register consists of two 8-bit registers AL and AH, which
can be combined together and used as a 16- bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte. Accumulator
can be used for I/O operations, rotate and string manipulation.

BX Register: This register is mainly used as a base register. It holds the starting
base location of a memory region within a data segment. It is used as offset storage
for forming physical address in case of certain addressing mode.

CX Register: It is used as default counter - count register in case of string and loop
instructions.
 Lecture Notes
DX Register: Data register can be used as a port number in I/O operations and
implicit operand or destination in case of few instructions. In integer 32-bit multiply
and div ide instruction the DX register contains high-order word of the initial or
resulting number.

Segment registers: 1Mbyte memory is div ided into 16 logical segments. The
complete 1Mbyte memory segmentation is as shown in fig 1.4. Each segment
contains 64Kbyte of memory. There are four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot be
changed directly. The CS register is automatically updated during far jump, far call
and far return instructions. It is used for addressing a memory location in the code
segment of the memory, where the executable program is stored.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the
stack pointer (SP) and base pointer (BP) registers is located in the stack segment.
SS register can be changed directly using POP instruction. It is used for addressing
stack segment of memory. The stack segment is that segment of memory, which is
used to store stack data.

Data segment (DS) is a 16-bit register containing address of 64KB segment with
program data. By default, the processor assumes that all data referenced by general
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and LDS instructions. It points to the
data segment memory where the data is resided.
 Lecture Notes
Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions. ES register can be
changed directly using POP and LES instructions. It also refers to segment which
essentially is another data segment of the memory. It also contains data.

Pointers and index registers: The pointers contain within the particular
segments. The pointers IP, BP, SP usually contain offsets within the code, data and
stack segments respectively.

Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP

register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data addresses in string
manipulation instructions. Destination

Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation
instructions.

Flag Register:

Flag Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the
type of the result, and to determine conditions to transfer control to other parts of
the program.
 Lecture Notes
The 8086 flag register as shown in the fig. 8086 has 9 active flags and they are
divided into two categories: 1. Conditional Flags 2. Control Flags

Conditional Flags

Carry Flag (CY): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from

lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry
given by D3 bit to D4 is AC flag. This is not a general-purpose flag; it is used
internally by the Processor to perform Binary to BCD conversion.

Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
of the result contains even number of 1’s, the Parity Flag is set and for odd number
of 1’s, the Parity flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it
is reset.

Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the execution
unit. Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one
instruction of a program at a time for debugging. When trap flag is set, program can
be run in single step mode.
 Lecture Notes
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable
interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set
by executing instruction sit and can be cleared by executing CLI instruction.

Direction Flag (DF): It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is reset,
the string bytes are accessed from lower memory address to higher memory
address.

Fig. The complete bit configuration of 8086 flag register is shown below:
 Lecture Notes
Memory Segmentation:

The memory in an 8086 based system is organised as segmented memory. In this

scheme the complete physically available memory may be div ided into a number of
logic segments. Each segment is 64 bytes in size & is addressed by one of the
segments of registers.

The 16bit content of segment register actually points to the starting location of
particular segment. To address a specific given location within a segment, we need
an offset address. The offset is also a 16 bit long so that the max offset value can be
FFFFH & the max size of any segment is thus 64K locations. The segment may be
overlapped in some cases.

Suppose a segment starts at a particular address and its max size can be 64K bytes.
But If another segments starts before its 64K bytes location of the first segment, the
2 segments are said to be OVERLAPPING SEGMENTS The area of memory from
the start of second segment to the possible end of the first segment is called as
overlapped segment area. The main advantages of segmented memory are

* Allows the memory capacity to be 1M byte although the actual address to be

handled are of 16-bit size

*allows the placing oh code, data &stack portions of the same program in different
parts of memory for data & code protection

*Permits a program &/or its data to be into different areas of memory each time
program is executed i.e. provision for relocation may be done.
Lecture Notes
Fig. Memory Segmentation
 Lecture Notes
Fig: Non-Overlapping and Overlapping Segments

8086 Microprocessor features:

1. It is 16-bit microprocessor

2. It has a 16-bit data bus, so it can read data from or write data to memory and
ports either 16-bit or 8-bit at a time.

3. It has 20-bit address bus and can access up to 220 memory locations (1 MB).

4. It can support up to 64K I/O ports

5. It provides 14, 16-bit registers

6. It has multiplexed address and data bus AD0-AD15 & A16-A19

7. It requires single phase clock with 33% duty cycle to provide internal timing.

8. Prefetches up to 6 instruction bytes from memory and queues them in order to

speed up the processing.
 Lecture Notes
9. 8086 supports 2 modes of operation

a. Minimum mode

b. Maximum mode

3. Addressing modes of 8086:

Addressing mode indicates a way of locating data or operands.

The addressing modes describe the types of operands and the way they are
accessed for executing an instruction.

According to the flow of instruction execution, the instructions may be categorized

as

i) Sequential control flow instructions and

ii) Control transfer instructions

Sequential control flow instructions are the instructions, which after execution,
transfer control to the next instruction appearing immediately after it (in the
sequence) in the program. For example, the arithmetic, logic, data transfer and
processor control instructions are sequential control flow instructions.

The control transfer instructions, on the other hand, transfer control to some
predefined address or the address somehow specified in the instruction, after their
execution. For example, INT, CALL, RET and JUMP instructions fall under this
category.
 Lecture Notes
The addressing modes for sequential control transfer instructions are:

1. Immediate: In this type of addressing, immediate data is a part of instruction and

appears in the form of successive byte or bytes.

Ex: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-
bit or 16-bit in size.

2. Direct: In the direct addressing mode a 16-bit memory address (offset) is directly
specified in the instruction as a part of it.

Ex: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective
address may be completed using 5000H as the offset address and content of DS as
segment address. The effective address here, is 10H * DS + 5000H.

3. Register: In register addressing mode, the data is stored in a register and is

referred using the particular register. All the registers, except IP, may be used in this
mode.

Ex: MOV BX, AX

Register Indirect: Sometimes, the address of the memory location, which contains
data or operand, is determined in an indirect way, using the offset register. This
mode of addressing is known as register indirect mode. In this addressing mode, the
offset address of data is in either BX or SI or DI register. The default segment is
either DS or ES.
 Lecture Notes
The data is supposed to be available at the address pointed to by the content of any
of the above registers in the default data segment.

Ex: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset address is in BX. The
effective address of the data is given as 10H * DS+[BX].

5. Indexed: In this addressing mode, offset of the operand is stored in one of the
index registers. DS and ES are the default segments for index registers, SI and DI
respectively. This is a special case of register indirect addressing mode.

Ex: MOV AX, [SI]

Here, data is available at an offset address stored in SI in DS. The effective address,
in this case, is computed as 10*DS+[SI].

6. Register Relative: In this addressing mode, the data is available at an effective

address formed by adding an 8-bit or 16-bit displacement with the content of any
one of the registers BX, BP, SI and DI in the default (either DS or ES) segment.

Ex: MOV AX, 50H[BX]

Here, the effective address is given as 10H *DS+50H+[BX]

7. Based Indexed: The effective address of data is formed, in this addressing mode,
by adding content of a base register (any one of BX or BP) to the content of an
index register (any one of SI or DI). The default segment register may be ES or DS.

Ex: MOV AX, [BX][SI]

 Lecture Notes
Here, BX is the base register and SI is the index register the effective address is
computed as 10H * DS + [BX] + [SI].

Relative Based Indexed: The effective address is formed by adding an 8 or 16-bit

displacement with the sum of the contents of any one of the base register (BX or
BP) and any one of the index register, in a default segment.

Ex: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is base register and SI is an index

register the effective address of data is computed as

10H * DS + [BX] + [SI] + 50H

For control transfer instructions, the addressing modes depend upon whether the
destination is within the same segment or different one. It also depends upon the
method of passing the destination address to the processor.

Basically, there are two addressing modes for the control transfer instructions,
intersegment addressing and intrasegment addressing modes.

If the location to which the control is to be transferred lies in a different segment

other than the current one, the mode is called intersegment mode.

If the destination location lies in the same segment, the mode is called intrasegment
mode.
 Lecture Notes
Fig. Addressing modes for Control Transfer Instructions

9. Intrasegment Direct Mode: In this mode, the address to which the control is to be
transferred lies in the same segment in which the control transfer instruction lies
and appears directly in the instruction as an immediate displacement value. In this
addressing mode, the displacement is computed relative to the content of the
instruction pointer IP.

The effective address to which the control will be transferred is given by the sum of
8 or 16-bit displacement and current content of IP. In the case of jump instruction, if
the signed displacement (d) is of 8-bits (i.e. –128<d<+128) we term it as short
jump and if it is of 16-bits (i.e-32, 768<d<+32,768) it is termed as long jump.

10. Intrasegment Indirect Mode: In this mode, the displacement to which the control
is to be transferred, is in the same segment in which the control transfer instruction
lies, but it is passed to the instruction indirectly. Here, the branch address is found
as the content of a register or a memory location. This addressing mode may be
used in unconditional branch instructions.
 Lecture Notes
11. Intersegment Direct: In this mode, the address to which the control is to be
transferred is in a different segment.

This addressing mode provides a means of branching from one code segment to
another code segment. Here, the CS and IP of the destination address are specified
directly in the instruction.

12. Intersegment Indirect: In this mode, the address to which the control is to be
transferred lies in a different segment and it is passed to the instruction indirectly,
i.e. contents of a memory block containing four bytes, i.e. IP (LSB), IP(MSB),
CS(LSB) and CS (MSB) sequentially. The starting address of the memory block may
be referred using any of the addressing modes, except immediate mode.

Forming the effective Addresses:

The following examples explain forming of the effective addresses in the different
modes.

Ex: 1. The contents of different registers are given below. Form effective addresses
for different addressing modes.

Offset (displacement)=5000H

[AX]-1000H, [BX]- 2000H, [SI]-3000H, [DI]-4000H, [BP]-5000H, [SP]-6000H, [CS]-

0000H, [DS]-1000H, [SS]-2000H, [IP]-7000H

Shifting segment address four bits to the left is equivalent to multiplying it by 16D or
10H
 Lecture Notes
i. Direct addressing mode:

MOV AX,[5000H]

DS : OFFSET  1000H : 5000H

10H*DS 10000 —segment address

offset  +5000 ---offset address

_______

15000H – Effective address

_______

ii. Register indirect:

MOV AX, [BX]

DS: BX  1000H: 2000H

10H*DS  10000 —segment address

[BX] +2000 ---offset address

________

12000H – Effective address

_______
 Lecture Notes
iii. Register relative:

MOV AX, 5000 [BX]

DS : [5000+BX]

10H*DS  10000

offset  +5000

[BX]  +2000

________

17000H – Effective address

________

iv. Based indexed:

MOV AX, [BX] [SI]

DS : [BX + SI]

10H*DS  10000

BX]  +2000

[SI]  +3000

_______

15000H – Effective address

_______
 Lecture Notes
v. Relative based index:

MOV AX, 5000[BX][SI]

DS : [BX+SI+5000]

10H*DS  10000

[BX]  +2000

[SI]  +3000 +5000

___________

1A000H – Effective address

___________

Instruction Formats

A machine language format has one or more no of fields associated with it. The first
field is called as operation code field or opcode field, which indicates the type of
operation to be performed by the CPU. The other is the operand field. The processor
executes the instruction using the information which resides in the fields.

There are size general formats of instructions in 8086 instruction set. the length of
the instruction may vary from one byte to 6 bytes. The instruction formats are
described as follows:
 Lecture Notes
One-byte instruction

This format is only one byte long & may have the implied data or register operands.

E.g. LOCK, LAHF

Register To Register

This format is 2 bytes long, the first byte of the code specifies opcode & width of the operand
specifies by 'w' bit if 'w' bit is 0, the operand is of 8 bits & if w is 1, then the operand is of 16 bits the
second byte shows the register operand & R/M fields.

E.g. MOV AX, BX

Register to/from Memory with No Displacement

This format is also 2 bytes long similar to the register to register format except for the mod field.

The MOD field shows the mode of addressing

MOD Indications

00 No displacement

01 8-bit displacement

10 16-bit displacement

11 Register operands

E.g. MOV AX, [2000]

Register to/from memory with displacement:

This type of instruction format contains one or two additional bytes for displacement along with 2-
byte format of the register to/from memory without displacement.

E.g. MOV AX, 10H[2000H]

 Lecture Notes
Immediate Operand to Register:

In this format the first byte as well as the 3bits from the second byte are used
for opcode. It contains one or two byte of immediate data.

E.g. MOV AL,50H or MOV AX,5000H

Immediate Operand to memory with 16 bit displacement:

This type of instruction format requires 5 or 6 bytes for coding the first 2 bytes
contains the information regarding opcode, MOD & R/M fields. The remaining 4-
bytes contains 2bytes of displacement & 2bytes of data.
E.g. MOV 1000H[2000H], 20H

Fig. Instruction Formats

 Lecture Notes
1.4.1 Instruction set of 8086:

The 8086 instructions are classified into the following main types:

Data copy/transfer instructions

Arithmetic & logical instructions

Branch instructions

Loop instructions

Machine control instructions

Flag manipulation instructions

Shift & rotate instructions

String instructions

Data Copy/transfer instructions:

These instructions are used to transfer data from source operand to destination
operand

MOVE: transfers data from one register /memory location to another

register/memory location

Direct loading of segments register with immediate data is not permitted

 Lecture Notes
e.g..

MOV AX ,5000H ->immediate adding mode

MOV DS,AX- >register

MOV AX, BX -> register

MOV AX, [ SI] -> indexed

MOV AX , [2000H] -> direct

MOV AX , 50H [BX] -> Based relative

PUSH :Push to Stack

This instruction pushes the contents of the specified Register /memory location on
to the stack .The higher byte is pushed first followed by lower byte

e.g..

PUSH AX

PUSH DS

PUSH [5000H]

POP: Pop from Stack

The instruction loads the specified register /memory location with the content of the
memory location of which the address is formed using the current stack segment &
stack pointer as usual. IT is exactly opposite to PUSH instruction

e.g.. POP AX

POP DS

POP [5000H]
 Lecture Notes
XCHG - Exchange:

Exchanges the contents of specified source &destination operands, which may be

registers or one of them may be memory locations. exchange of data contents of
two memory locations is not permitted.

e.g.. XCHG [5000H]

XHG BX <- here AX is implicit

IN : Input to the port

It is used for reading input port . The address of the input port may be specified in
the instruction directly or indirectly.

e.g., IN AL ,O3OOH

OUT : Output to the port

This instruction is used for writing to an output port .The address of output port may
be specified in instruction directly or implicitly in DX.

e.g.. OUT 0300H, AL

XLAT Translate

This instructions is used for finding out the codes in case of code conversion
problems offset of an operand in the specified register.

LDS/LES : Load point to DS/ES :

This instruction loads the DS or ES register & the specified destination register in the
instruction with the content of memory location specified as a source in the
instruction.
 Lecture Notes
LAHF :Load from lower byte of flag:

Loads am register with the lower byte of flag register. This instruction may be used
to observe the status of all the conditions code flags at a time

SAHF :Store AH to the lower byte of flag register

This instruction sets or resets the condition code flags in the lower byte of the flag
register depending upon the corresponding bit positions in AH.

PUSHF: Push flag to stack:

This instruction pushes the flag register on to the stack . first the upper byte & the
lower byte will be pushed on to the stack

POPF : Pop flag from stack

The pop flag instruction loads the flag register completely from the word contents of
the memory location currently addressed by SP &SS

Arithmetic Instruction:

These instructions usually perform the arithmetic operations like addition subtraction
,multiplication &div ision along with respective ASCII & decimal adjust instructions.
The increment &decrement operations belongs to this type of instructions.

ADD:

This instruction adds an immediate data or content of a memory location specified in

the instruction or a register to the content of register or memory location. Result is
in the destination operand. Memory to memory addition is not possible. Contents of
segment register cannot be coded.
 Lecture Notes
e.g.. ADD AX, 0100 -> immediate

ADD AX, BX -> register

ADD AX, [SI] -> indexed

ADD AX,[5000H] -> direct

ADD [7000], 0100H -> Immediate

ADC : Add with carry

This instruction performs the same operation as ADD instruction, but adds the carry
flag bit to the result.

e.g.. ADC AX, BX

ADC AX, [SI]

INC : increment

This instruction increments the contents of the specified register or memory location
by 1

e.g.. INC AX

INC [BX]

INC [5000H]
 Lecture Notes
DEC :Decrement

This instruction subtracts one from the contents specified register or memory
location.

DEC [5000H]

DEC [BX]

SUB :Subtract

The subtract instruction subtracts the source operand from the destination operand.
Source may be a register or a memory location or immediate data. Destination
operand may be a register or memory location. Memory to memory subtraction is
not possible.

e.g. SUB AX, EX

SUB [E000H] ,0100

Subtract with borrow:

This subtract with borrow instruction subtracts the source operand &borrow flag (EF) from
the destination operand

e.g. SUBB AX ,BX

SUBB AX,[5000H]

SUBB [5000H], 0150H

 Lecture Notes
CMP Compare

This instruction compares the source operand which may be a register or an

immediate data or a memory location ,with a destination operand that may be a
register or a memory location. If source operand is greater than the destination
operand, carry flag is set or else carry flag is reset.

e.g. CMP BX,0100H

CMP [5000H], 100H

CMP BX, CX

AAA:ASCII Adjust after addition :

This instruction is executed after an ADD instruction that adds two ASCII coded
operands to give a byte of result in AL. This instruction converts the resulting
contents of AL to unpacked decimal digits

AAS: ASCII Adjust after subtraction:

AAS instruction corrects the result in AL register after subtracting two operands
unpacked ASCII operands. the result is unpacked decimal formats.

AAM:ASCII Adjust for multiplication:

This instruction after execution converts the product available in AL into unpacked
BCD format. This follows a multiplication instruction

AAD :ASCII Adjust for division

The AAD instruction converts two unpacked BCD digits in AH & AL to the equivalent
binary number in AL .This adjustment must be made before dividing the two
unpacked BCD digits in AX by an unpacked BCD byte.
 Lecture Notes
DAA Decimal adjust accumulator

This instruction is used to convert the result of addition of two packed BCD numbers
to a valid BCD number

DAS Decimal Adjust after subtraction

This instruction converts the result of subtraction of two packed BCD numbers to a
valid BCD number.

Negative:

NEG: This negate instruction forms 2’s compliment of specified destination in the
instruction.

MUL unsigned multiplication byte or word:

This instruction multiplies unsigned byte or word by the contents of AL. This most
significant word of the results is stored in AX.

e.g.. MUL BH : AX = AL X BH

MUL CX :(DX) (AX) = (AX) X (CX)

MUL [SI] : (DX) (AX) = (AX) X([SI])

 Lecture Notes
IMUL : Signed multiplication

This instruction multiplies a signed byte in source operand by a signed in AL or signed word
is source operand by single word in AXCS

e.g., IMUL BH

DIV Unsigned division

This instruction performs unsigned division. It divides an unsigned word or double word by
a 16 bit or 8-bit operand. The dividend must be in AX for 16-bit operation & divisor may be
specified using one of the addressing modes except immediate data. The quotient will be in
AL white AH will contain the remainder.

E.g. DIV BL ; AX/BL and After execution, AL = Quotient & AH = Remainder

IDIV Signed Division:

This instruction performs the same operation as the D IV instruction, but with signed
operands.

Logical Instructions

This type of instructions are used for carrying out bit by bit shift, rotate or basic logical
operations .All the condition code flags are affected depending upon the result .

AND Logical AND

This instruction logically AND the source operand that may be an immediate a register or a
memory location .Both operands cannot be memory locations or immediate operands

e.g. AND AX, 0008H

AND AX, BX

AND [0500H], DX
 Lecture Notes
OR: Logical OR

The OR instruction carries out the OR operation in the same way as in the case of
AND operation

e.g. OR AX, BX

OR [5000H], 0008

OR AX ,0099H

NOT: Logical invert

This instruction complements (inverts) the contents of an operand register or a

memory location bit by bit.

e.g. NOT AX

NOT [5000H]

XOR :Logical EXCULISVE OR

This instruction is also similar to that of AND & OR OPERATION

e.g. XOR AX, 0019H

XOR AX, BX
 Lecture Notes
TEST -Logical compile instruction:

This performs a bit by bit logical AND operation on the two operands. Each bit of the
result is then set to 1, if the corresponding bits of both operands are 1, else the
result bit is reset to 0. the result is not available for future use, bit flags are affected.
The affected flags are of CF, SF, ZF & PF. The operands may be register, memory or
immediate data.

e.g.. TEST AX,BX

SHL/SAL: Shift logical/ Arithmetic left

These instructions shifts the operand word or byte bit by bit to the left & insert zeros
in the newly introduced least significant bits. The count is either 1 or specified by
register CL

Bit positions CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
operand 1 010110000110010
SHL result 0 101100001100100

SHR : Shift Logical right

This instruction performs bit wise rights on the operand word or byte that may
reside in a register or a memory location by the specified count in the instruction &
inserts zero in the shifted position.

Bit positions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CF
Operand 1110001001010001 0
After SHR with count=1 0111000100101000 1
 Lecture Notes
SAR : Shift Arithmetic Right

This instruction performs rights shifts on the operand word or byte may be a register
or a memory location by the specified count in the instruction & inserts the most
significant bit if operand in the newly inserted positions.

operand 1 0 1 0 1 1 1 0 0 0 1 0 0 1 0 1 CF
count=1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 0 1
Count=2 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 0

ROR :Rotate right without carry

This instruction rotates the contents of the destination operand to the right
(bitwise)either by one or count specified in CL, excluding carry. The LSB is pushed
into the carry flag & simultaneously it is transferred into the MSB position at each
operation.

operand 1010111000100101 x (CF- not considered)

count=1 1101011100010010 1

ROL: Rotate left without carry-

This instruction rotates the contents of destination operand to the left by the
specified count excluding carry

operand CF 1010111000100101
count=1 1 0 101110001001011
 Lecture Notes
RCR -Rotate right through carry

This instruction rotates the contents (bitwise) of the destination operand right by the count
through CF. For each operation CF is passed into MSB of the operand & LSB is pushed into
carry flag.

operand 10 101 11 00 01 00 1 00 1 (CF)

After RCR 1101011100010010 0 (CF)

RCL Rotate left through carry

This instruction rotates 16bit the contents of destination operand left by the specified count
through the CF. For each operation, the carry flag is pushed into the LSB & MSB is pushed
into CF.

operand 1 (CF) 1010111000100100

After RCL 0 1101011100010010

String manipulation Instruction:

A series of data bytes or words available in memory at consecutive locations to be referred

to collectively or individually are called as byte strings. for referring to a string two
parameters are required starting or end address of a string length of the string -usually
stored in CX register.

1.REP: Repeat instruction prefix:

This instruction is used as a prefix to other instruction. The instruction to which the REP
prefix is provided is executed repeatedly till CX register becomes zero (at each iteration CX
is automatically decremented by 1.

REPE/REPZ - repeat operation while zero/equal equal/zero

REPNE/REPNZ-repeat operation while not equal/not zero

 Lecture Notes
MOVSB/MOVSW- Move string byte or string word

This instruction is used to move a string byte or word from one location (specified
by segment name & source index [SI] ) to another location ( specified by segments
name & destination index DI )

CMPS : Compare sting byte or string word:

This can be used to compare two strings of bytes or words. I they are equal, ZF is
set.

SCAS: Scan String Byte or String Word:

This instruction scans a string of bytes or words, for an operand byte or word
specified in register AL or AX. The string is pointed to by ES: DI register pair. The
length of the string is stored in CX. The DF collides the made of scanning (auto
incrementing or decrementing). Whenever a match is found, execution stops and ZF
is set. If no match is found ZF is reset.

LODS Load string byte or string word

This LODS loads the AL/AX register by the content of a string pointed to by DS:SI
Register pair

STOS- Store string byte or word

The STOS stores the AL/AX register contents to a location in the string pointed by
ES: DI register pair.
 Lecture Notes
Branching Instruction:

The branching or control instructions transfer the flow of the execution of the
program to an address specified in the instruction directly or indirectly. This can be
classified into two types

Conditional Branching

The execution control is transferred to the specified location provided the result of
the prev ious operation satisfies a particular condition otherwise the execution control
is normal flow sequence

Unconditional Branching:

The execution control is transferred to specified location independent of any status

or condition

Unconditional Branching instructions:

CALL:

This instruction is used to call a subroutine from a main program. The address of the
subroutine may be specified directly or indirectly depending upon the addressing
mode. There are two types of subroutine depending upon whether it is available in
the same segment. ( intra segment) or in another segment (inter segment).

RET: Return From the procedure/subroutine:

This instruction is used to transfer the control from the subroutine to main program.
 Lecture Notes
INTO: Interrupt or overflow:

This is executed, when the overflow flag is set.

JMP Unconditional jump:

This instruction unconditionally transfers the control of execution to the specified

address the control of execution to the specified address using an 8 bit or 16-bit
displacement.

IRET: Return from interrupt service routine (ISR):

This instruction is used to transfer the control from the interrupt serv ice routine to
the main program.

LOOP:

This execute the part of the program from label or address specified in the
instruction up to the loop instruction, CX number of times.

1.4.2 ASSEMBLER DIRECTIVES AND OPERATORS:

An assembler need some hints from the programmer i.e., the required storage for a
particular constant or a variable, logical names of the segment, types of different
routines and modules, end of file etc.

These types of hints are given to the assembler using some predefined alphabetical
strings called assembler directives.

Another type of hint which helps the assembler to assign a particular constant with a
label or initialize particular memory locations or labels with constant is called an
operator.
 Lecture Notes
DB: Define Byte:

Used to reserve byte or byte, of memory locations in the available memory.

E.g.: RANKS DB 01H, 02H, 03H, 04H -> directs the assembler to reserve 4 memory
locations for a list named ‘RANKS’ and initialize them with specified values.

E.g.: VALUE DB 50H -> to reserve 50H memory bytes and leave them uninitialized
for the variable named VALUE.

DW: Define Word: to reserve the number of memory words. E.g.: WORDS DW
1234H, 4567H, 78ABH, 304CH

E.g.: WDATA DW 5 DUP (6006H) ->reserves four words and initializes all words with
the value 6006H.

Define Quadword: (DQ): used to reserve 4 words (8-bytes) of memory for the
specified variable and may initialize it with the specified values.

DT: Define Ten bytes: used to reserve 10bytes of memory for the specified
variable.

ASSUME – Assume Logical Segments Name: used to inform the assembler, the
names of the logical segments to be assumed for different segments used in the
program.

E.g.: ASSUME CS:CODE -> directs the assembler that the machine codes are
available in a segment named CODE, and hence the CS register is to be loaded with
the address allotted by the operating system for the label CODE, while loading.

END: End of program: marks the end of the assembly language program.
 Lecture Notes
ENDP: End of procedure: to indicate the end of the procedure (subroutine).

E.g.: PROCEDURE STAR

...

STAR ENDP

ENDS: End of Segment: marks the end of logical segments.

E.g.: DATA SEGMENT

…...

DATA ENDS

E.g.: MODULE1 SEGMENT PUBLIC FACTORIAL

…..

MODULE1 ENDS

MODULE2 SEGMENT EXTRN FACTORIAL

…..

MODULE2 ENDS

GROUP: Group the Related Segments: used to form logical groups of segments
with similar purpose or type.

E.g.: PROGRAM GROUP CODE, DATA, and STACK

 Lecture Notes
LABEL: used to assign a name to the current content of the location counter. At the
start of the assembly process, the assembler initializes a location counter to keep
track of memory locations assigned to the program. As the program assemble
proceeds, the content of location counter are updated. Whenever the assembler
come across the LABEL directive, it assigns the declared label with the current
contents of location counter.

LENGTH: Byte Length of a label: used to refer to the length of a data array or a
string.

E.g.: MOV CX, LENGTH ARRAY – Reg. CX is loaded with the value which is the
length of the array.

LOCAL: the labels, variables, consists of procedures declared LOCAL in a module

are to be used only by that module.

E.g.: LOCAL a, b, DATA, ARRAY, ROUTINE

EVEN: Align on Even Memory address: The assembler, while starting the
assembling procedure of any program initialize a location counter and goes on
updating it, as the assembly proceeds the EVEN directive updates the location
counter to the next even address, if the current location counter contents are not
even and assigns the following routine or variable or constant to that address.

E.g.: EVEN PROCEDURE FACT

……………………….

FACT ENDP
 Lecture Notes
EQU: Equate: Used to assign a label with a value or a symbol.

E.g.: LABEL EQU 0500H -> assign 0500H to ‘LABEL’

ADDITION EQU ADD -> assigns another label ‘ADDITION’ with mnemonic ADD

PUBLIC: informs the assembler that the labels, variables constants or procedures
declared PUBLIC may be accessed by other modules.

EXTRN: Extern: informs the assembler that the names, procedure and label
declared after this directive have already been defined as some other assembly
language module.

NAME: logical name of a module: used to assign a name to an assembly language

program module.

OFFSET: offset of a label: when the assembler comes across the OFFSET operator
along with a label, it first computes the 16bit displacement (also called as offset) of
the particular label, and replaces the string OFFSET LABEL by the computed
displacement.

E.g.: DATA SEGMENT LIST DB 10H DATA ENDS CODE SEGMENT

MOV SI, OFFSET LIST CODE ENDS

ORG: origin: Directs the assembler to stack the memory allotment for the
particular segment, block or code from the declared address in the ORG statement.

E.g.: ORG 2000H

 Lecture Notes
PROC: procedure: This marks the start of a named procedure in the statement.
Also, the types NEAR or FAR specifies the type of procedure, i.e. whether it is to be
called by main program located within 64k of physical memory or not.

E.g.: RESULT PROC NEAR

ROUTINE PROC FAR

SEG: Segment of a label: The SEG operator is used to decide the segment
address of the label, variable or procedure and substitutes the segment base
address in the place of ‘SEG LABEL’.

E.g.: MOV AX, SEG ARRAY -> moves the segment address of ARRAY in which it is
appearing to register AX and then to DS.

SEGMENT: Logical Segment: This directive marks the starting of a logical

segment. The segment is also assigned a name i.e. label by this statement.

E.g.: CODE SEGMENT

…….

CODE ENDS

SHORT: indicates to the assembler that only one byte is required to code the
displacement for a jump.

E.g.: JMP SHORT LABEL

 Lecture Notes
TYPE: Directs the assembler to decide the data type of the specified label and replaces the
‘TYPE LABEL’ by the decided data type.

GLOBAL: The labels, variables, constants or procedures declared GLOBAL may be used by
other modules of the program. Once a variable is declared GLOBAL, it can be used by any
module in the program.

E.g.: ROUTINE PROC GLOBAL

1.5. ASSEMBLY LANGUAGE PROGRAMMING

ALP for 8 BIT ADDITION

MOV DL,00

MOV AL,[1100]

MOV BL,[1101]

ADD AL,BL

JNC L1

INC DL

L1: MOV [1102],AL

MOV [1103],DL

HLT

ALP for 8 BIT DIVISION

MOV AL,[1100]

MOV BL,[1101]
 Lecture Notes
DIV AL,BL

MOV [1102],AX

HLT

ALP for Sum of N numbers

MOV AX,0000

MOV SI,1100

MOV DI,1200

MOV CX,0005 ; 5 NUMBERS TO BE TAKEN TO SUM

MOV DX,0000

L1: ADD AX, [SI]

INC SI

INC SI

INC DX

CMP CX, DX

JNZ L1

MOV [1200],AX

HLT
 Lecture Notes
ALP for Subtraction of two 16-bit numbers

ASSUME CS: CODE

CODE SEGMENT

START: ORG 1000H

MOV SI, 1200H

MOV DI, 1300H

MOV CL, 00H

MOV AX, [SI]

MOV BX, [SI+02]

SUB AX, BX

JNC L1

MOV CL, 01H

L1: MOV [DI], AX

MOV [DI+02], CL

INT 3H

CODE ENDS

END START
 Lecture Notes
ALP for Multiplication of two 16-bit numbers

ASSUME CS: CODE

CODE SEGMENT

START: MOV SI, 1200H

MOV DI, 1300H

MOV AX, [SI]

MOV BX, [SI+02]

MUL BX

MOV [DI], AX

MOV [DI+02], DX

INT 3H

CODE ENDS

END START
 Lecture Notes
ALP for 2’s Complement 16-bit number

ASSUME CS: CODE

CODE SEGMENT

START : ORG 1000H

MOV SI, 1200H

MOV AX, [SI]

NOT AX

INC AX

MOV [1300], AX

MOV AH,4CH

INT 21H

CODE ENDS

END START

ALP for Display String

ASSUME CS: CODE , DS: DATA

DATA SEGMENT

MSG DB "LIFE IS WONDERFUL$"

DATA ENDS
 Lecture Notes
CODE SEGMENT

START: MOV AX, DATA ; MOVE SEGMENT ADDRESS OF MSG TO AX

MOV DS, AX ; LOAD IT TO DS

MOV DX, OFFSET MSG ; MOVE OFFSET OF MSG TO DX

MOV AH,09H ; 09 DOS FUNCTION : DISPLAY MESSAGE

INT 21H ; CALL DOS FUNCTION

MOV AH,4CH ; 4C DOS FUNCTION : TERMINATE PRM

INT 21H ; CALL DOS FUNCTION

CODE ENDS

END START

1.6 MODULAR PROGRAMMING

Complex programs are div ided into many parts and each sub-part are known as
modules. All the modules perform a well-defined task. Formulation of computer code
using a module is known as modular programming.

The reason for breaking a program into small parts are

Modules are easier to understand.

Different modules can be assigned to different programmers.
The debugging and testing can be done in a more orderly fashion.

Documentation can be more easily understood.

Modifications may be localized.

Most assembler languages are used in modularization process in three ways such as,
 Lecture Notes
1.Allow data to be structured so that they can be accessed by several modules

2.Provide for procedures or subroutines

3.Permit sections of code, known as macros.

To perform modular programming, the following tasks must be performed.

 Linking and relocation

 Stack Operation

 Procedures

 Interrupt process

1.7 Linking and Relocation

The assembly language program can be written with an ordinary text editor such as
word star, editor etc. The assembly language program text is an input to the
assembler. The assembler translates assembly language statements to their binary
equivalent known as object code. During assembling process assembler checks for
syntax errors and displays them before giv ing object code module. The object code
module contains the information about where the program or module to be loaded
in memory. If the object module is to be linked with other separate modules, then it
contains additional linkage information.

At link time, separately assembled modules are combined into one single load
module by the linker. The linker also SUBs any required initialization or finalization
code to allow the OS to start the program running and to return control to OS after
the program is completed.
 Lecture Notes
At load time, the program loader copies the program into computer main memory
and at execution time, the program execution begins. If the modules in the program
they are assembled separately, then there is one main module and other modules.
This main module has the first instruction to be executed and it is terminated by an
END statement with entry point satisfied. Other modules are terminated by an END
statement with no operand.

Fig. Creation and Execution of Assembly language program

Segment combination

In addition to the linker commands, the assembler prov ides a means of regulating
the way segments in different object modules are organized by the linker. Segments
with same name are joined together by using the modifiers attached to the
SEGMENT directives.
 Lecture Notes
SEGMENT directive may have the form

Segment name SEGMENT Combination-type

where the combine-type indicates how the segment is to be located within the
load module. Segments that have different names cannot be combined and
segments with the same name but no combine-type will cause a linker error.

The possible combine-types are:

PUBLIC – If the segments in different modules have the same name and combine- type
PUBLIC, then they are concatenated into a single element in the load module. The
ordering in the concatenation is specified by the linker command.

COMMON – If the segments in different object modules have the same name and the
combine-type is COMMON, then they are overlaid so that they have the same starting
address. The length of the common segment is that of the longest segment being
overlaid.

STACK – If segments in different object modules have the same name and the combine
type STACK, then they become one segment whose length is the sum of the lengths of
the individually specified segments. In effect, they are combined to form one large stack

AT – The AT combine-type is followed by an expression that evaluates to a constant

which is to be the segment address. It allows the user to specify the exact location of the
segment in memory.

MEMORY – This combine-type causes the segment to be placed at the last of the load
module. If more than one segment with the MEMORY combine-type is being linked, only
the first one will be treated as having the MEMORY combine type; the others will be
overlaid as if they had COMMON combine-type.
 Lecture Notes
Fig. Segment combinations resulting from the PUBLIC and
Common Combination types
 Lecture Notes
Fig. Formation of a stack from two segments

Access to External Identifiers

If an identifier is defined in an object module, then it is said to be a local (or

internal) identifier relative to the module. If it is not defined in the module but is
defined in one of the

other modules being linked, then it is referred to as an external (or global) identifier
relative to the module. Two lists are implemented by the EXTRN and PUBLIC
directives, which have the forms:
 Lecture Notes
EXTRN Identifier: Type …. Identifier: Type

and

PUBIC Identifier, …., Identifier

where the identifiers are the variables and labels being declared or as being
available to other modules.

The assembler must know the type of all external identifiers before it can generate
the proper machine code, a type specifier must be associated with each identifier in
an EXTRN statement.

For a variable the type may be BYTE, WORD, or DWORD and for a label it may be
NEAR or FAR.

One of the primary tasks of the linker is to verify that every identifier appearing in
an EXTRN statement is matched by one in a PUBLIC statement. If this is not the
case, then there will be an undefined reference and a linker error will occur. The
offsets for the local identifier will be inserted by the assembler, but the offsets for
the external identifiers and all segment addresses must be inserted by the linking
process. The offsets associated with all external references can be assigned once all
of the object modules have been found and their external symbol tables have been
examined.

The assignment of the segment addresses is called relocation and is done after the
linking process has determined exactly where each segment is to be put in memory.
 Lecture Notes
1.8 STACKS

The stack is a block of memory that may be used for temporarily storing the
contents of the registers inside the CPU. It is a top-down data structure
whose elements are accessed using the stack pointer (SP) which gets
decremented by two as we store a data word into the stack and gets
incremented by two as we retrieve a data word from the stack back to the
CPU register.

The process of storing the data in the stack is called ‘pushing into’ the stack
and the reverse process of transferring the data back from the stack to the
CPU register is known as ‘popping off’ the stack. The stack is essentially Last-
In-First -Out (LIFO) data segment. This means that the data which is pushed
into the stack last will be on top of stack and will be popped off the stack first.

The stack pointer is a 16-bit register that contains the offset address of the
memory location in the stack segment. The stack segment, like any other
segment, may have a memory block of a maximum of 64 Kbytes locations,
and thus may overlap with any other segments. Stack Segment register (SS)
contains the base address of the stack segment in the memory.

The Stack Segment register (SS) and Stack pointer register (SP) together
address the stack- top as explained below:

SS ===== 5000 H

SP===== 2050 H
 Lecture Notes
If the stack top points to a memory location 52050H, it means that the location
52050H is already occupied with the prev iously pushed data. The next 16 bit push
operation will decrement the stack pointer by two, so that it will point to the new
stack-top 5204EH and the decremented contents of SP will be 204EH. This location
will now be occupied by the recently pushed data.

Thus for a selected value of SS, the maximum value of SP=FFFFH and the segment
can have maximum of 64K locations. If the SP starts with an initial value of FFFFH, it
will be decremented by two whenever a 16-bit data is pushed onto the stack. After
successive push operations, when the stack pointer contains 0000H, any attempt to
further push the data to the stack will result in stack overflow.

After a procedure is called using the CALL instruction, the IP is incremented to the
next instruction. Then the contents of IP, CS and flag register are pushed
automatically to the stack. The control is then transferred to the specified
Addressing the CALL instruction i.e. starting Address of the procedure. Then the
procedure is executed.

Fig. Stack –top Address calculation

 Lecture Notes
1.9 PROCEDURES

A procedure is a set of code that can be branched to and returned from in such a
way that the code is as if it were inserted at the point from which it is branched to.
The branch to procedure is referred to as the call, and the corresponding branch
back is known as the return. The return is always made to the instruction
immediately following the call regardless of where the call is located.

Calls, Returns, and Procedure Definitions

The CALL instruction not only branches to the indicated address, but also pushes the
Return Address onto the stack. The RET instruction simply pops the return Address
from the stack. The registers used by the procedure need to be stored before their
contents are changed, and then restored just before their contents are changed, and
then restored just before the procedure is excited.

A CALL may be direct or indirect and intrasegment or intersegment. If the CALL is

intersegment, the return must be intersegment. Intersegment call must push both
(IP) and(CS) onto the stack. The return must correspondingly pop two words from
the stack. In the case of intrasegment call, only the contents of IP will be saved and
retrieved when call and return instructions are used.

Procedures are used in the source code by placing a statement of the form at the
beginning of the procedure

Procedure name PROC Attribute

--------

----------

Procedure name ENDP

 Lecture Notes
Types of Procedures:

• Near Procedure: Procedure is present in the same code segment where

the main program is stored.

• Far Procedure: Procedure is present in the different code segment from

the main program.

Procedure or subroutine may require input data or constants for their execution.
Their data or constants may be passed to the subroutine by main program or some
subroutine may access readily available data of constants available in memory.

Passing parameters to Procedures:

Generally, the following technique are used to pass input / parameter to procedures
in ALP

a) Using Global declared variable

b) Using registers of CPU architecture

c) Using memory location

d) Using stack

e) Using PUBLIC and EXTERN

 Lecture Notes
a) Using Global declared variable

A variable or a parameter label may be declared global in the main program and the
same variable or parameter label can be used by all the procedures of the
application.

Examples of passing parameters

ASSUME CS: CODE, DS: DATA

DATA SEGMENT

NUMBER EQY 77H GLOBAL

DATA ENDS

CODE1 SEGMENT

START : MOV AX,DATA

MOV DS,AX

--

CODE1 ENDS

ASSUME CS: CODE2

CODE2 SEGMENT

START: MOV AX, DATA

MOV DS, AX

--

CODE2 ENDS

END START
 Lecture Notes
b) Using registers of CPU architecture

The CPU general purpose registers may be used to pass parameters to the
procedures. The main program may store the parameters to be passed to the
procedure in the variable CPU registers and the procedure may use the same
register content for execution. The original content of the used CPU register may
change during execution of the procedure. This may be avoided by pushing all the
register content to be used to the stack sequentially at the start of the procedure
and popping all the register contents at the end of the procedure in opposite
sequence.

ASSUME CS : CODE,DS : DATA

CODE SEGMENT

START : MOV AX , 5555H

MOV BX , 5456H

--

PROCEDURE P1 NEAR

--

ADD AX , BX

--

RET

P1 ENDP

CODE ENDS

END START
 Lecture Notes
c)Using memory location

Memory location may also be used to pass parameter to a procedure in the same
way as registers. A main program may store the parameter to be passed to a
procedure at known memory address location and the procedure may use the same
location for accessing the parameter.

Example:

ASSUME CS: CODE, DS: DATA

DATA SEGMENT

NUM DB (55H)

COUNT EQY 77H

DATA ENDS

CODE SEGMENT

START : MOV AX,DATA

MOV DS,AX

--

CALL ROUTINE

--

PROCEDURE ROUTINE NEAR

MOV BX , NUM

MOV CX , COUNT

--
 Lecture Notes
ROUTINE ENDP

CODE ENDS

END START

d)Using stack

Stack memory can also be used to pass parameters to procedure. A main program
may store the parameters to be passed to a procedure in its CPU registers. The
registers will further be pushed on to the stack. The procedure during its execution
pops back the appropriate parameters as and when required. This procedure of
popping back the parameters must be implemented carefully because besides the
parameters to be passed to the procedure the stack contains other important
information like contents of other pushed registers, return addresses from the
current procedure and other procedure or interrupt service routines.

Example:

ASSUME CS: CODE, SS: STACK

STACK SEGMENT

STACKDATA DB 200H DUP ( ? )

STACK ENDS

CODE SEGMENT

START : MOV AX , STACK

MOV SS,AX
 Lecture Notes
MOV BX , 55H

MOV CX , 10H

--

PUSH AX

PUSH CX

CALL ROUTINE

--

PROCEDURE ROUTINE NEAR

--

MOV DX , SP

ADD SP ,02H

POP CX

POP BX

MOV SP , DX

--

ROUTINE ENDP

CODE ENDS

END START
 Lecture Notes
e)Using PUBLIC and EXTERN

For passing the parameters to procedures using the PUBLIC & EXTERN directives , must be
declared PUBLIC (for all routine) in the main routine and the same should be declared
EXTERN in the procedure Thus the main program can pass the PUBLIC parameter to a
procedure in which it is declared EXTERN(external)

Example:

ASSUME CS: CODE, DS: DATA

DATA SEGMENT

PUBLIC NUMBER EQY 77H

DATA ENDS

CODE SEGMENT

START: MOV AX, DATA

MOV DS, AX

--

CALL ROUTINE

--

PROCEDURE ROUTINE NEAR

EXTERN NUMBER

MOV AX , NUMBER

--
 Lecture Notes
ROUTINE ENDP

CODE ENDS

END START

1.10 MACROS:

Suppose, a number of instructions are appearing again and again in the main
program, the listings become lengthy. So a macro definition i.e., a label, is assigned
with the repeatedly appearing string of instructions. The process of assigning a label
or macro name to the string is called defining a macro. A macro within a macro is
called a nested macro.

The difference between a macro and a subroutine is that, in case of macro the
complete code of instructions string is inserted at each place where the macro-name
appears. Hence the EXE file becomes lengthy. There is no question of transfer of
control as the program using the macro inserts the complete code of the macro at
every reference of the macro-name.

on the other hand, subroutine is called whenever necessary, i.e. the control of
execution is transferred to the subroutine, every time it is called. The executable
code in case of the subroutines becomes smaller as the subroutine appears only
once in the complete code. The control is transferred to a subroutine whenever it is
called, and this utilizes the stack service. The program using subroutine requires less
memory space for execution that that using macro. Macro, requires less time for
execution, as it does not contain CALL and RET instructions as the subroutines do.
 Lecture Notes
Defining a MACRO:

A macro can be defined anywhere in a program using the directives MACRO and
ENDM. The label prior to MACRO is the macro-name which should be used in the
actual program. The ENDM directive marks the end of the instructions or statements
sequence assigned with the macro name. The following macro DISPLAY displays the
message MSG on the CRT. The syntax is as given.

DISPLAY MACRO

MOV AX, SEG MSG

MOV DS, AX

MOV DX, OFFSET MSG

MOV AH, 09H

INT 21H

ENDM

The above definition of a macro assigns the name DISPLAY to the instruction
sequence between the directives MACRO and ENDM. While assembling, the above
sequence of instructions will replace the label ‘DISPLAY’, whenever it appears in the
program.

A macro may also be used in a data segment. In other words, a macro may be used
to represent statements and directives. The concept of macro remains the same
independent of its contents.
 Lecture Notes
E.g.:

STRINGS MACRO

MSG1 DB 0AH, 0DH, “Pgm terminated normally”, 0AH, 0DH, “$”

MSG2 DB 0AH, 0DH, “Retry, Abort, Fail”, 0AH, 0DH, “$”

ENDM

A macro may be called by quoting its name, along with any values to be passed to
the macro.

Passing Parameters to a MACRO:

Using parameters in a definition, the programmer specifies the parameters of the

macro those are likely to be changed each time the macro is called. For example,
the DISPLAY macro written above (in the prev ious topic) can be made to display two
different messages MSG1 and MSG2, as shown.

DISPLAY MACRO

MOV AX, SEG MSG

MOV DS, AX

MOV DX, OFFSET MSG

MOV AH, 09H

INT 21H

ENDM
 Lecture Notes
This parameter MSG can be replaced by MSG1 or MSG2 while calling the MACRO as
shown.

ASSUME CS: CODE, DS: DATA

CODE SEGMENT

START: MOV AX, DATA

……..

DISPLAY MSG1

…...

DISPLAY MSG2

………

CODE ENDS

END START

MSG1 DB 0AH, 0DH, “Pgm terminated normally”, 0AH, 0DH, “$”

MSG2 DB 0AH, 0DH, “Retry, Abort, Fail”, 0AH, 0DH, “$”

There may be more than one parameter appearing in the macro definition, meaning
thereby that there may be more than one parameters to be passed to the macro,
and each of them is liable to be changed. All the parameters are specified in the
definition sequentially and
 Lecture Notes
also in the call with the same sequence. A macro may be defined in another macro or in
other words a macro may be called from inside a macro. This is called nested macro.

Difference between Procedures and Macros:

Procedures Macros
Accessed by CALL & RET instruction Accessed during assembly with name
during program Execution given to MACRO when defined.
Machine code for instruction is put Machine code is generated for
only once in a memory. instruction each time when MACRO is
called
Less memory is required More memory is required
Parameters can be passed in Parameters can be passed as a part of
registers, memory locations or stack statement which calls MACRO

1.11 INTERRUPTS AND INTERRUPT ROUTINES

Interrupt and its Need:

The microprocessors allow normal program execution to be interrupted in order to

carry out a specific task/work. The processor can be interrupted in the following
ways

 by an external signal generated by a peripheral,

 by an internal signal generated by a special instruction in the program,

 by an internal signal generated due to an exceptional condition which

occurs while executing an instruction.

(For example, in 8086 processor, div ide by zero is an exceptional condition which
initiates type 0 interrupt and such an interrupt is also called execution). The process
of interrupting the normal program execution to carry out a specific task/work is
referred to as interrupt. The interrupt is initiated by a signal generated by an
external device or by a signal generated internal to the processor.
 Lecture Notes
When a microprocessor receives an interrupt signal it stops executing current
normal program, save the status (or content) of various registers (IP, CS and flag
registers in case of 8086) in stack and then the processor executes a
subroutine/procedure in order to perform the specific task/work requested by the
interrupt. The subroutine/procedure that is executed in response to an interrupt is
also called Interrupt Serv ice Subroutine (ISR). At the end of ISR, the stored status
of registers in stack is restored to respective registers, and the processor resumes
the normal program execution from the point {instruction) where it was interrupted.

The external interrupts are used to implement interrupt driven data transfer scheme.
The interrupts generated by special instructions are called software interrupts and
they are used to implement system services/calls (or monitor serv ices/calls). The
system/monitor services are procedures developed by system designer for various
operations and stored in memory. The user can call these services through software
interrupts. The interrupts generated by exceptional conditions are used to
implement error conditions in the system.

Interrupt Driven Data Transfer Scheme The interrupts are useful for efficient data
transfer between processor and peripheral. When a peripheral is ready for data
transfer, it interrupts the processor by sending an appropriate signal. Upon receiv ing
an interrupt signal, the processor suspends the current program execution, save the
status in stack and executes an ISR to perform the data transfer between the
peripheral and processor.

At the end of ISR the processor status is restored from stack and processor resume
its normal program execution. This type of data transfer scheme is called interrupt
driven data transfer scheme.

The data transfer between the processor and peripheral dev ices can be implemented
either by polling technique or by interrupt method. In polling technique, the
processor has to periodically poll or check the status/readiness of the device and can
perform data transfer only when the device 'is ready. In polling technique, the
processor time is wasted, because the processor has to suspend its work and check
the status of the device in predefined intervals.
 Lecture Notes
If the device interrupts the processor to initiate a data transfer whenever it is ready,
then the processor time is effectively utilized because the processor need not
suspend its work and check the status of the device in predefined intervals.

For an example, consider the data transfer from a keyboard to the processor.
Normally a keyboard has to be checked by the processor once in every 10
milliseconds for a key press. Therefore, once in every 10 milliseconds the processor
has to suspend its work and then check the keyboard for a valid key code.
Alternatively, the keyboard can interrupt the processor, whenever a key is pressed
and a valid key code is generated. In this way the processor need not waste its time
to check the keyboard once in every 10 milliseconds.

Classification of Interrupts

In general, the interrupts can be classified in the following three ways:

1. Hardware and software interrupts

2. Vectored and Non Vectored interrupt:

3. Maskable and Non Maskable interrupts.

The interrupts initiated by external hardware by sending an appropriate signal to the

interrupt pin of the processor is called hardware interrupt. The 8086 processor has
two interrupt pins INTR and NMI.

The interrupts initiated by applying appropriate signal to these pins are called
hardware interrupts of 8086.

The software interrupts are program instructions. These instructions are inserted at
desired locations in a program. While running a program, if software interrupt
instruction is encountered then the processor initiates an interrupt. The 8086 processor has
256 types of software interrupts. The software interrupt instruction is INT n, where n is the
type number in the range 0 to 255.
 Lecture Notes
When an interrupt signal is accepted by the processor, if the program control
automatically branches to a specific Address (called vector Address) then the
interrupt is called vectored interrupt.

The automatic branching to vector Address is predefined by the manufacturer of

processors. (In these vector Addresses the interrupt serv ice subroutines (ISR) are
stored). In non-vectored interrupts the interrupting dev ice should supply the
Address of the ISR to be executed in response to the interrupt.

All the 8086 interrupts are vectored interrupts. The vector Address for an 8086
interrupt is obtained from a vector table implemented in the first 1kb memory space
(00000h to 03FFFh).

The processor has the facility for accepting or rejecting hardware interrupts.
Programming the processor to reject an interrupt is referred to as masking or
disabling and programming the processor to accept an interrupt is referred to as
unmasking or enabling. In 8086 the interrupt flag (IF) can be set to one to unmask
or enable all hardware interrupts and IF is cleared to zero to mask or disable a
hardware interrupts except NMI.

The interrupts whose request can be either accepted or rejected by the processor
are called maskable interrupts. The interrupts whose request has to be definitely
accepted (or cannot be

rejected) by the processor are called non-maskable interrupts. Whenever a request

is made by nonmaskable interrupt, the processor has to definitely accept that
request and service that interrupt by suspending its current program and executing
an ISR. In 8086 processor all the hardware interrupts initiated through INTR pin are
maskable by clearing interrupt flag (IF). The interrupt initiated through NMI pin and
all software interrupts are non-maskable.

Sources of Interrupts in 8086

An interrupt in 8086 can come from one of the following three sources.
 Lecture Notes
1. One source is from an external signal applied to NMI or INTR input pin of the
processor. The interrupts initiated by apply ing appropriate signals to these input pins
are called hardware interrupts.

2. A second source of an interrupt is execution of the interrupt instruction "INT n",

where n is the type number. The interrupts initiated by "INT n" instructions are
called software interrupts.

3. The third source of an interrupt is from some condition produced in the 8086 by
the execution of an instruction. An example of this type of interrupt is divide by zero
interrupt. Program execution will be automatically interrupted if you attempt to
divide an operand by zero. Such conditional interrupts are also known as exceptions.

Interrupts of 8086

The 8086 microprocessor has 256 types of interrupts. INTEL has assigned a type
number to each interrupt. The type numbers are in the range of 0 to 255. The 8086
processor has dual facility of initiating these 256 interrupts. The interrupts can be
initiated either by executing "INT n" instruction where n is the type number or the
interrupt can be initiated by sending an appropriate signal to INTR input pin of the
processor.

In general, the interrupts can be classified as following:

1.External Hardware Interrupts

2.Non Maskable Interrupts

3.Software Interrupts

4.Internal Interrupts

5.Reset

Interrupts Priority

Hardware, software and internal interrupts are serviced on a priority basis.

Each interrupt is given a different priority level by assigning a type number. Type 0
identifies highest priority and type 255 identifies the lowest priority interrupt.
 Lecture Notes
The interrupt priority follows,

 Reset

 Internal interrupts

 Software interrupts

 Non maskable interrupts

 External hardware interrupts

Interrupt Vector Table

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for
storing the starting addresses of Interrupt Service Procedures(ISP). Since 4-bytes
are required for storing starting addresses of ISPs, the table can hold 256 Interrupt
procedures.

The starting Address of an ISP is often called the Interrupt Vector or Interrupt
Pointer. Therefore, the table is referred as Interrupt Vector Table. In this table, IP
value is put in as low word of the vector & CS is put in high vector.

The operation of an interrupt on the 8086 microprocessor

1.External interface sends an interrupt signal, to the Interrupt Request (INTR) pin,
or an internal interrupt occurs.

2.The CPU finishes the present instruction and sends Interrupt Acknowledge (INTA)
to hardware interface.

3. The interrupt type N is sent to the Central Processing Unit (CPU) v ia the data bus
from hardware interface.

4. The contents of the flag registers are pushed onto the stack.
 Lecture Notes
5. Both interrupts (IF) and (TF) flags are cleared. This disables the INTR pin and the
trap or single step feature.

6. The contents of the code segment register (CS) are pushed onto the stack.

7. The contents of the instruction pointer (IP) are pushed onto the stack.

8. The interrupt vector contents are fetched, from(4*N) and then placed into the IP
and from(4*N+2) into the CS so that the next instruction executes at the interrupt
service procedure addressed by the interrupt vector.

9.While returning from the interrupt service routine by the Interrupt return (IRET)
instruction, The IP, CS and Flag registers are popped from the stack and return their
state prior to the interrupt.

Fig. 8086 Interrupt Instructions

 Lecture Notes
Fig. Interrupt Vector Table of 8086
 Lecture Notes
1.12 BYTE AND STRING HANDLING INSTRUCTIONS

The 8086 microprocessor is equipped with special instructions to handle string

operations. By string we mean a series of data words or bytes that reside in
consecutive memory locations. The string instructions of the 8086 permit a
programmer to implement operations such as to move data from one block of
memory to a block elsewhere in memory. A second type of operation that is easily
performed is to scan a string and data elements stored in memory looking for a
specific value.

Other examples are to compare the elements and two strings together in order to
determine whether they are the same or different.

Move String: MOVSB, MOVSW

An element of the string specified by the source index (SI) register with respect to
the current data segment (DS) register is moved to the location specified by the
destination index (DI) register with respect to the current extra segment (ES)
register. The move can be performed on a byte (MOVSB) or a word (MOVSW) of
data. After the move is complete, the contents of both SI & DI are automatically
incremented or decremented by 1 for a byte move and by 2 for a word move.
Address pointers SI and DI increment or decrement depends on how the direction
flag DF is set.

Load and store strings: (LODSB/LODSW and STOSB/STOSW)

LODSB: Loads a byte from a string in memory into AL. The Addressing SI is used
relative to DS to determine the Address of the memory location of the string
element.

(AL) = [(DS) + (SI)]

[SI] = [SI] + 1

LODSW: The word string element at the physical Address derived from DS and SI is
to be loaded into AX. SI is automatically incremented by 2.
 Lecture Notes
AX = [(DS) + (SI)]

[SI] = [SI] + 2

STOSB:

Stores a byte from AL into a string location in memory. This time the contents of ES
and DI are used to form the Address of the storage location in memory.

[ES + DI] = AL

DI = DI + 1

STOSW:

[ES + DI] = AX

DI = DI + 2

Repeat String: REP

The basic string operations must be repeated to process arrays of data. This is done
by inserting a repeat prefix before the instruction that is to be repeated. Prefix REP
causes the basic string operation to be repeated until the contents of register CX
become equal to zero. Each time the instruction is executed, it causes CX to be
tested for zero, if CX is found to be nonzero it is decremented by 1 and the basic
string operation is repeated.

Example:

Clearing a block of memory by repeating

STOSB

MOV AX, 0

MOV ES, AX

MOV DI, A000

 Lecture Notes
STOSB

MOV AX, 0

MOV ES, AX

MOV DI, A000

MOV CX, O FFFFF

REP STOSB

The prefixes REPE and REPZ stand for same function. They are meant for use with
the CMPS and SCAS instructions. With REPE/REPZ the basic compare or scan
operation can be repeated as long as both the contents of CX are not equal to zero
and zero flag is 1.

REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is
repeated as long as CX ≠ 0 and ZF=0. Comparison or scanning is to be performed
as long as the string elements are unequal (ZF=0) and the end of the string is not
yet found (CX ≠ 0).

Auto Indexing for String Instructions:

SI & DI addresses are either automatically incremented or decremented based on

the setting of the direction flag DF.

When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1.
When STD (Set Direction Flag) is executed DF=1 permits auto decrement by 1.
Lecture Notes - Links to Videos

https://drive.google.com/file/d/18SGrGgu1EoUOvuntxPbAI0Lttu9wfLC
H/view?usp=sharing
https://drive.google.com/file/d/19yRuBkcB4Yx2tSavyBIUYTF_yW1ma
UOv/view?usp=sharing
https://drive.google.com/file/d/1EzEHcBZFHb6gDzskrsQe8ZCb70ax0U
E4/view?usp=sharing
https://drive.google.com/file/d/1jizz79YcBuMx227TohdzbzPh12VsNzZ
G/view?usp=sharing

History of INTEL processors :

https://www.youtube.com/watch?v=Qu2njWY3Hjk
Chip Manufacturing :
https://www.youtube.com/watch?v=bor0qLifjz4&t=4s
 Lecture Notes - e-book reference

1. Yu-Cheng Liu, Glenn A.Gibson, ―Microcomputer Systems: The 8086 /

8088 Family – Architecture, Programming and Design, Second Edition,
Prentice Hall of India, 2007.

Link:

https://drive.google.com/file/d/1O3H8WHOIyGKqsjTItS-
gySXsymqzDgqx/view?usp=sharing
 Lecture Notes - PPTs

https://drive.google.com/file/d/1wwogZRYhYoVR6t69VQCG5HiMbRld4
p4p/view?usp=sharing

https://drive.google.com/file/d/1pSb4ovcYLcUJuXmjsHQb2_qMnHzhB0
ms/view?usp=sharing
 Lecture Notes – Quiz
Link for Quiz1
https://docs.google.com/forms/d/e/1FAIpQLSfWFiJfXfjIm5bFEY9oqZd
3aRuGqFvkt9P08hDpffIvJ0NZ9g/viewform?usp=pp_url

Link for Quiz2

https://docs.google.com/forms/d/111ETwQubkFlfssQCUCO-
ecW9vimirrqRD2QRiuNjcgU/edit?usp=sharing
 Lecture Notes – References
NPTEL Lecture Materials References

Microprocessor and Peripheral Devices by Dr. Pramod Agarwal , IIT

Roorkee

Link: http://nptel.ac.in/courses/108107029/

Microprocessors and Microcontrollers by Prof. Krishna Kumar IISc

Bangalore

link: http://nptel.ac.in/courses/106108100/
 Assignments
Write a 8086 Assembly Language Program to convert ASCII to Binary &

vice versa and Hexa Decimal to Decimal & vice versa with detailed

explanation and set of input and output cases.

Write a 8086 Assembly Language Program to find and replace a word

on a string using Assembler Directives .

Write a 8086 Assembly Language Program to read inputs from keyboard

during execution and sort the inputs then display the result in the

monitor using Assembler Directives.

Explain in detail about various DOS/BIOS functions used in 8086 with

its with its number notations and how it is called by INT 21H instruction.

Write a delay program to generate a delay of 120ms in an 8086 – based

system that runs on a 10Mhz frequency clock and Explain.

 Part A Q & A (with K level and CO)
1. What is microprocessor? K1 – CO1
A microprocessor is a multipurpose, programmable, clock-driven, register-based
electronic device that reads binary information from a storage device called
memory, accepts binary data as input and processes data according to those
instructions, and provides result as output.

2. What is stack? K1 – CO1

The stack is a group of memory locations in the R/W memory that is used for
temporary storage of binary information during the execution of a program.

3. Define addressing mode. K1 – CO1

Addressing mode is used to specify the way in which the address of the operand is
specified within the instruction.

4. Define instruction cycle. K1 – CO1

It is defined as the time required to complete the execution of an instruction.

5. What are the different types of addressing modes of 8086 instruction

set? K1 – CO1
The different addressing modes are:
Immediate MOV AX,1000H
Direct MOV AX,[1500H]
Register MOV AX,BX
Register indirect MOV AX, [DX]
Indexed MOV AX,[SI]
Register relative MOV AX, 05[BX]
Based indexed MOV AX,[BX][SI]
Relative based indexed MOV AX,05[BX][SI]
6. What is assembly language programming? K1 – CO1
A program called assembler is used to convert the mnemonics of instruction and
data into their equivalent object code modules. The object code modules are further
converted into executable code using linker and loader programs. This type of
programming is called assembly level programming.
 Part A Q & A (with K level and CO)
7. How is the stack top address calculated? K1 – CO1
The stack top address is calculated using the contents of the SS and SP register.
The contents of stack segment (SS) register is shifted left by four bit positions
(multiplied by (0h)) and the resulted 20-bit content is added with the 16-bit offset
value of the stack pointer (SP) register.

8. What are macros? K1 – CO1

Macros are small routines that are used to replace strings in the program. They can
have parameters passed to them, which enhances the functionality of the micro
itself.

9. How are constants declared? K2 – CO1

Constants are declared in the same way as variables, using the format:
Label EQU 012h
When the constants label is encountered, the constant numeric value is exchanged
for the string.

10. What is the difference between the microprocessor and

microcontroller? K2 – CO1
Microprocessor does not contain RAM, ROM and I/O ports on the chip. But a
microcontroller contains RAM, ROM and I/O ports and a timer all on a single chip.

11. What is loader? K1 – CO1

The loader copies the program into the computer’s main memory at load time and
begins the program execution at execution time.

12. What is linker? K1 – CO1

A linker is a program used to join together several object files into one large object
file. For large programs it is more efficient to div ide the large program modules into
smaller modules. Each module is indiv idually written, tested & debugged. When all
the modules work they are linked together to form a large functioning program.
 Part A Q & A (with K level and CO)
13. Define Segment Override Prefix. K1 – CO1
The segment override prefix allows the programmer to deviate from the default
segment E.g. : MOV CS: [BX] , AL

14. What are procedures? K1 – CO1

Procedures are a group of instructions stored as a separate program in memory and
it is called from the main program whenever required. The type of procedure
depends on where the procedures are stored in memory. If it is in the same code
segment as that of the main program, then it is a near procedure otherwise it is a
far procedure.

15. Explain the linking process. K1 – CO1

A linker is a program used to join together several object files into one large object
file. The linker produces a link file which contains the binary codes for all the
combined modules. It also produces a link map which contains the address
information about the link files. The linker does not assign Absolute addresses but
only relative address starting from zero, so the programs are relocatable & can be
put anywhere in memory to be run.

16. Compare Procedure & Macro. K2 – CO1

17. How is the physical address calculated? K1 – CO1

The segment register is shifted left bit wise four times and offset address is added
to this to produce a 20 bit physical address.
 Part A Q & A (with K level and CO)
17. What is meant by memory segmentation? K1 – CO1
Memory segmentation is the process of completely div iding the physically available
memory into a number of logical segments. Each segment is 64 Kbytes in size and is
addressed by one of the segment register.

18. What is pipelining? K1 – CO1

Fetching the next instructions while the current instruction executes is called
pipelining.

19. What is NMI (nonmaskable interrupt)? K1 – CO1

 NMI is an edge triggered input, which causes a type 2 interrupt. It is not
maskable internally by software and transition from low to high
 initiates the interrupt response at the end of the current instruction.

20. Write the instruction classification of 8086. K1 – CO1

Data Transfer instructions
Arithmetic instructions.
Bit Manipulation instructions.
String instructions.
Program Execution Transfer instructions.
Processor Control instructions.
21. What is meant by instruction queue? K1 – CO1
To speed up program execution ,the BIU fetches six instruction bytes ahead of time
from the memory. These prefetched instruction bytes are held for the execution unit
in a group of registers called Queue.
22. Write the advantages of memory segmentations. K2 – CO1
It allows the memory addressing capacity to be 1Mbyte even though the
address associated with indiv idual instructions is only16 bit. It allows instruction
code, data, stack, and portion of program to be more than 64KB long by using
more than one code, data ,stack segment and extra segment. It facilitates use
of separate memory areas for program, data and stack.
 Part A Q & A (with K level and CO)
23. What is the clock rate of 8086? K1 – CO1
5 MHZ for 8086
8 MHZ for 8086-2
10 MHZ for 8086-1

24. What is meant by base address or segment base? K1 – CO1

The starting address of the segment is called base address or segment base.

25. What is the use of source index(SI)? K1 – CO1

Source index(SI) can be used to hold the offset of a data word in the data segment.

26. What is the use of destination index(DI)? K1 – CO1

String instructions always use ES and DI to determine the 20 bit physical address for
the destination.

27. What is meant by effective address? K1 – CO1

When the EU needs to access a memory location ,it sends an offset value to the
BIU. This offset is called effective address.

28. What is the similarity and difference between subtract and compare
instructions? K2 – CO1
Similarity : Both the subtraction and comparison are performed by subtracting two
data in ALU and flags are altered depending upon the result.

Difference : After subtract operation, the result is stored in destination register/

memory, but after compare operation the result is discarded.

29. Write about the list of interrupts supported by 8086. K1 – CO1

The various interrupts are
1. Type 0 – Division by zero.
2. Type 1 – Single step interrupt.
3. Type 2 – Non maskable external interrupt.
4. Type 3 – interrupt instruction INT
5. Type 4 – Interrupt on overflow , INTO
Instructions that initiates interrupt are called as software interrupts.
 Part A Q & A (with K level and CO)
30. Calculate the physical address, when segment address is 1085H and
effective address is 4537H . K3 – CO1
Physical Address = Left shift segment address by 4 bits + effective address
Segment Address = 0001 0000 1000 0101 = 1085 H
After Left shift = 0001 0000 1000 0101 0000 = 10850 H
Effective Address = 0100 0101 0011 0111 = 4537 H
__________________________
Physical Address = 0001 0100 1101 1000 0111 = 14D87 H
___________________________
31.List the flags of 8086. K1 – CO1
CF-Carry flag
PF-Parity flag
AF-Auxiliary Carry flag
ZF-Zero flag
SF-Sign flag
TF-Single step Trap flag
DF-Direction flag
IF-Interrupt enable flag
OF-Overflow flag
32. List the different segment registers. K1 – CO1
Code segment register (CS)
Data segment register (DS)
Extra segment register(ES)
Stack segment register(SS)

33. What is Stack Pointer (SP) ? K1 – CO1

SP will point the top offset address of stack segment of 8086.

34. The offset address of a data is 341BH and the data segment register
value is 123AH . What is the physical address of the data? K3-CO1
Segment Address shifted by 4 bits towards left = 123A0H
Offset Address is = 341BH
20 bit Physical Address = 157BBH
 Part B Qs (with K level and CO)
1. Explain the features of 8086 microprocessor. (8) - K1 - CO1

2. Explain the register organization of 8086 in detail. (8) – K1 - CO1

3. Explain about segmented memory organization of 8086 in detail.(8) – K1 - CO1

4. Explain the architecture of 8086 processor with the help of neat block diagram.
(13) – K1 - CO1

5. Explain the addressing modes of 8086 in detail.(10) – K1 - CO1

6. Write notes on addressing I/O devices in 8086.(3) – K1 - CO1

7. Give three examples for the following 8086 microprocessor instructions: String,
Processor Control, Program execution transfer instructions and bit manipulation
instructions. (13) – K2 - CO1

8. Briefly explain instruction set of 8086 in detail with examples. (13). – K1 - CO1

9. Give an example for the 8086 instructions: AAA, CWD, JNBE, LAHF, MOVS, RCL,
ROL and SAHF.(8) – K2 - CO1

10. Explain the following assembler directives in detail: 1) ASSUME 2) EQU 3)DD
4)DW (8) – K1 - CO1

11. What are assembler directives and Give examples with explanation.(13) – K1 -
CO1

12. Explain the following assembler directives DD,ENDS, EVEN & EXTRN (8) – K1 -
CO1

13. Explain the following assembler directives. SHORT, TYPE, FAR (3) – K1 - CO1

14. Explain the steps of Linking and Relocation of a program during execution in
detail. – K1 - CO1
 Part B Qs (with K level and CO)
15. Explain the detail the stack structure of 8086. Write a simple program to
illustrate the concept of programming the stack. – K3 - CO1

16. Explain in detail about Stack and its applications.(8) – K1 - CO1

17. Explain in detail about Procedures with examples.(8) – K1 - CO1

18. Explain in detail about Macros with examples.(8) – K1 - CO1

19. Write an assembly language program in 8086 to search the largest data in an
array.(13) – K3 - CO1

20. Write an ALP to find summation of numbers in the array. – K3 - CO1

21. Write short notes on interrupts, the sequence of steps during the interrupt and
interrupt service routines.(8) – K1 - CO1

22. Explain the interrupt structure of an 8086 microprocessor with its interrupt
vector table with its types.(8) – K1 - CO1

23. Write a program to multiply 2 digit numbers by getting an input from the
keyboard using BIOS interrupt call. (13) – K3 - CO1

24. Write an 8086 ALP to get an input from the keyboard for 2 digits and convert
that input into hexa decimal number using BIOS int. (13) – K3 – CO1

25. Explain how instruction pipeline works in 8086 and mention how it helps in
improving CPU’s performance. (8) – K4 – CO1

26. Distinguish between the following pairs: NEAR and FAR procedures, macros
and subroutines. (8) – K3 – CO1

27. Explain the role of the following: (4 + 4) - K1 – CO1

(1) Address Conversion Mechanism
(2) Instruction queue.

28. Write a 8086 ALP to convert BCD Data to Binary Data. (13) – K3 – CO1
 Part B Qs (with K level and CO)
29. Write an 8086 program that checks whether a multi-byte number that satisfies
even parity or not. (4) – K4 – CO1

30. Write an 8086 assembly language program using string primitives to find out
whether a given name is present in a list of names. (8) – K3 – CO1

31. Explain how BIOS function calls are invoked in assembly language programs. (8)
– K2 – CO1
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courses
NPTEL:

Microprocessors and Microcontrollers.

https://nptel.ac.in/courses/106/108/106108100/

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8086 Microprocessor Architecture In One Video-In Easy Way

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Real time Applications in day to day
life and to Industry
Gaming devices.

Mobile phones, Laptops and some electronic gadgets.

Traffic Lights Controller

Washing Machines, Microwave ovens.

Frequency counters and synthesizers.

Digital Clocks.

Scientific Calculators

Microcomputers
Contents beyond the Syllabus

Comparison of 8086, 80186, 80286 and 80386

8087 Numeric Data Processor

https://drive.google.com/file/d/1m94L4FebpyTmpTuc6pOyMOBivmulLj

NR/view?usp=sharing
Lecture Notes - Links to Videos

8086 Signal Diagram and Minimum & Maximum mode Configurations

https://drive.google.com/file/d/1LsDFrvRDC60oY7HmW9ijVX9ef2mdRpO
9/view?usp=sharing

Understanding the Bus Timing Diagram Video:

https://www.youtube.com/watch?v=yXahWYYNPXE

How CPU works:

https://www.youtube.com/watch?v=cNN_tTXABUA&t=349s
 Lecture Notes - e-book reference

1. Yu-Cheng Liu, Glenn A.Gibson, ―Microcomputer Systems: The 8086 /

8088 Family – Architecture, Programming and Design, Second Edition,
Prentice Hall of India, 2007.

Link:

https://drive.google.com/file/d/1O3H8WHOIyGKqsjTItS-
gySXsymqzDgqx/view?usp=sharing
 Lecture Notes - PPTs
https://drive.google.com/file/d/1efGPi2H--
Qv76RUy3SUvOFSETNIyNGEp/view?usp=sharing

https://drive.google.com/file/d/1LLuzfxqn1BCaKMM-zhh-
czDN7ykVZ80-/view?usp=sharing
 Lecture Notes – Quiz

https://docs.google.com/forms/d/1j-
IEljj7YeVaJbzUo9LRVwsOdKjKsNrdPQdrvupl2F8/edit?usp=sharing

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_Ft82Gz57H81wZqHI_1S8KJR3bww/viewform?usp=pp_url
 Assignments
Write a procedure to calculate the volume of a sphere using MASM.
(Hint. Use 8087 instructions along with 8086 instructions)

Write program to convert a fractional binary number to its decimal

equivalent. (Hint. Use 8087 instructions along with 8086 instructions)

Describe in detail about software aspects of multimicroprocessor

systems.

Write down steps of interconnection between 8086 and 8089 IOP.

Design a PC based Multimicroprocessor system.

Explain in detail about Protected Virtual Addressing Mode and address

calculation in PVAM mode of 80286.
 Supportive online Certification
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NPTEL:

Microprocessors and Interfacing

https://nptel.ac.in/courses/108/103/108103157/

Microcontrollers and Applications

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UDEMY:

Learn Microprocessor From Basic to Advanced

https://www.udemy.com/course/learn-js-easily/
Real time Applications in day to day
life and to Industry
3D graphics with audio/video compression.

Digital Signal Processors.

Gaming devices.

Mobile phones, Laptops and some electronic gadgets.

Traffic Lights Controller

Washing Machines, Microwave ovens.

Frequency counters and synthesizers.

Digital Clocks.

Scientific Calculators

Microcomputers
Contents beyond the Syllabus

Protection Mode Mechanism of 8086

https://drive.google.com/file/d/1m94L4FebpyTmpTuc6pOyMOBivmulLj

NR/view?usp=sharing
 Assessment Schedule

Assessment I

Proposed Date : 20.9.2021

Actual Date : 20.9.2021

Prescribed Text Books & Reference
Books
Text Books:

Yu-Cheng Liu, Glenn A.Gibson, ―”Microcomputer Systems: The 8086 /

8088 Family - Architecture “, Programming and Design, Second Edition,
Prentice Hall of India, 2007. (UNIT I- III).

Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, ―”The 8051
Microcontroller and Embedded Systems: Using Assembly and C”, Second
Edition, Pearson education, 2011. (UNIT IV-V).

REFERENCES:

1. Doughlas V.Hall, ―”Microprocessors and Interfacing, Programming

and Hardware”,TMH,2012.

2. A.K.Ray,K.M.Bhurchandi, "Advanced Microprocessors and Peripherals"

3rd edition, Tata McGrawHill, 2012.
 Mini Project suggestions
Auto Intensity Control of Street Lights

Automatic Railway Gate Controller with High Speed Alerting System

Boolean Algebra Calculator

DC Motor Interfacing with 8051 Microcontroller

Interfacing 7 Segment Display to 8051

LED Interfacing with 8051

Password Based Door Lock System using 8051 Microcontroller

Street Lights that Glow on Detecting Vehicle Movement

Water Level Controller using 8051 Microcontroller:

Simple Toll Plaza

Color Sensing Robot:

Automatic College Bell System Using AT89S52

Microcontroller Based Public Garden Automation

Digital Calendar Using 8051

Microcontroller Based Digital Stop Watch

Microcontroller Based Advanced Automatic City Street Control System

 Thank you

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