a Rail-to-Rail High Output

Current Operational Amplifiers

OP179/OP279
FEATURES PIN CONFIGURATIONS
Rail-to-Rail Inputs and Outputs
5-Lead SOT-23-5
High Output Current: ⴞ60 mA
(RT-5)
Single Supply: +5 V to +12 V
Wide Bandwidth: 5 MHz
High Slew Rate: 3 V/␮s OP179
OUT A 1 5 V–
Low Distortion: 0.01%
V+ 2
Unity-Gain Stable
No Phase Reversal +IN A 3 4 2IN A
Short Circuit Protected
Drives Capacitive Loads: 10 nF
APPLICATIONS 8-Lead SOIC and TSSOP
Multimedia SO-8 (R) and RU-8
Telecom
DAA Transformer Driver
OUT A 1 8 V+
LCD Driver 2IN A 2 7 OUT B
Low Voltage Servo Control OP279
+IN A 3 6 2IN B
Modems V2 4 5 +IN B
FET Drivers

8-Lead Plastic DIP

GENERAL DESCRIPTION (N-8)
The OP179 and OP279 are rail-to-rail, high output current,
single-supply amplifiers. They are designed for low voltage
applications that require either current or capacitive load drive OUT A OP279 +V
capability. The OP179/OP279 can sink and source currents of –IN A OUT B
± 60 mA (typical) and are stable with capacitive loads to 10 nF.
+IN A –IN B
Applications that benefit from the high output current of the
OP179/OP279 include driving headphones, displays, transform- –V +IN B

ers and power transistors. The powerful output is combined with a

unique input stage that maintains very low distortion with
wide common-mode range, even in single supply designs.
The OP179/OP279 can be used as a buffer to provide much Very good audio performance can be attained when using the
greater drive capability than can usually be provided by CMOS OP179/OP279 in +5 volt systems. THD is below 0.01% with a
outputs. CMOS ASICs and DAC often have outputs that can 600 Ω load, and noise is a respectable 21 nV/√Hz. Supply cur-
swing to both the positive supply and ground, but cannot drive rent is less than 3.5 mA per amplifier.
more than a few milliamps. The single OP179 is available in the 5-lead SOT-23-5 package.
Bandwidth is typically 5 MHz and the slew rate is 3 V/µs, mak- It is specified over the industrial (–40°C to +85°C) temperature
ing these amplifiers well suited for single supply applications range.
that require audio bandwidths when used in high gain configu- The OP279 is available in 8-lead plastic DIP, TSSOP and
rations. Operation is guaranteed from voltages as low as 4.5 V, SO-8 surface mount packages. They are specified over the
up to 12 V. industrial (–40°C to +85°C) temperature range.

REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999
OP179/OP279–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V S CM = 2.5 V, –40ⴗC ≤ T A ≤ +85ⴗC unless otherwise noted)
Parameter␣ Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS␣
Offset Voltage
OP179 VOS VOUT = 2.5 V ±5 mV
OP279 VOS VOUT = 2.5 V ±4 mV
Input Bias Current IB VOUT = 2.5 V, TA = +25°C ± 300 nA
VOUT = 2.5 V ± 700 nA
Input Offset Current IOS VOUT = 2.5 V, TA = +25°C ± 50 nA
VOUT = 2.5 V ± 100 nA
Input Voltage Range VCM 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 5 V 56 66 dB
Large Signal Voltage Gain A VO RL = 1 kΩ, 0.3 V ≤ VOUT ≤ 4.7 V 20 V/mV
Offset Voltage Drift ∆VOS/∆T 4 µV/°C
OUTPUT CHARACTERISTICS␣
Output Voltage High VOH IL = 10 mA Source +4.8 V
Output Voltage Low VOL IL = 10 mA Sink, TA = +25°C 75 mV
IL = 10 mA Sink 100 mV
Short Circuit Limit ISC TA = +25°C ± 40 mA
Output Impedance ZOUT f = 1 MHz, AV = 1 22 Ω
POWER SUPPLY␣
Power Supply Rejection Ratio PSRR VS = +4.5 V to +12 V 70 88 dB
Supply Current/Amplifier ISY VOUT = 2.5 V 3.5 mA
Supply Voltage Range VS +4.5 +12 V
DYNAMIC PERFORMANCE␣
Slew Rate SR RL = 1 kΩ, 1 nF 3 V/µs
Gain Bandwidth Product GBP 5 MHz
Phase Margin φm 60 Degrees
Capacitive Load Drive No Oscillation 10 nF
AUDIO PERFORMANCE␣
Total Harmonic Distortion THD 0.01 %
Voltage Noise Density en f = 1 kHz 22 nV/√Hz

ELECTRICAL SPECIFICATIONS (@ V = ⴞ5.0 V, –40ⴗC ≤ T ≤ +85ⴗC unless otherwise noted)

S A
Parameter␣ Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS␣
Offset Voltage
OP179 VOS VOUT = 0 ±5 mV
OP279 VOS VOUT = 0 ±4 mV
Input Bias Current IB TA = +25°C ± 300 nA
± 700 nA
Input Offset Current IOS TA = +25°C ± 50 nA
± 100 nA
Input Voltage Range VCM –5 +5 V
Common-Mode Rejection Ratio CMRR VCM = –5 V to +5 V 56 66 dB
Large Signal Voltage Gain A VO RL = 1 kΩ, –4.7 V ≤ VOUT ≤ 4.7 V 20 V/mV
Offset Voltage Drift ∆VOS/∆T 3 µV/°C
OUTPUT CHARACTERISTICS␣
Output Voltage High VOH IL = 10 mA Source +4.8 V
Output Voltage Low VOL IL = 10 mA Sink –4.85 V
Short Circuit Limit ISC TA = +25°C ± 50 mA
Open-Loop Output Impedance ZOUT f = 1 MHz, AV = +1 22 Ω
POWER SUPPLY␣
Supply Current/Amplifier ISY VS = ±6 V, V OUT = 0 V 3.75 mA
DYNAMIC PERFORMANCE␣
Slew Rate SR RL = 1 kΩ, 1 nF 3 V/µs
Full-Power Bandwidth BWp 1% Distortion kHz
Gain Bandwidth Product GBP 5 MHz
Phase Margin φm 69 Degrees
NOISE PERFORMANCE␣
Voltage Noise e n p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 22 nV/√Hz
Current Noise Density in 1 pA/√Hz
Specifications subject to change without notice.

–2– REV. F
 OP179/OP279
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Package Types ␪JA2 ␪JC Unit
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V 5-Lead SOT-23 (RT) 256 81 °C/W
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite 8-Lead Plastic DIP (P) 103 43 °C/W
Storage Temperature Range 8-Lead SOIC (S) 158 43 °C/W
P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C 8-Lead TSSOP (RU) 240 43 °C/W
Operating Temperature Range NOTES
OP179G/OP279G . . . . . . . . . . . . . . . . . . . . –40°C to +85°C 1
The inputs are clamped with back-to-back diodes. If the differential input voltage
Junction Temperature Range exceeds 1 volt, the input current should be limited to 5 mA.
2
θ JA is specified for the worst case conditions, i.e., θJA is specified for device in socket
P, S, RT, RU Package . . . . . . . . . . . . . . . . –65°C to +150°C
for P-DIP, packages; θJA is specified for device soldered in circuit board for SOIC
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C packages.

ORDERING GUIDE

Package Temperature Range␣ Package Description Package Option Brand Code

OP179GRT –40°C to +85°C 5-Lead SOT-23 RT-5 A2G
OP279GP –40°C to +85°C 8-Lead Plastic DIP N-8
OP279GS –40°C to +85°C 8-Lead SOIC SO-8
OP279GRU –40°C to +85°C 8-Lead TSSOP RU-8

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the OP179/OP279 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. F –3–
OP179/OP279
Typical Performance Graphs
160 90 400
VS = +5V VS = +5V
140 TA = +258C 300

SHORT CIRCUIT CURRENT – mA

620 x OP AMPS, –408C

INPUT BIAS CURRENT – nA

PDIP 80
120 200
–ISC
100 100 +258C
70
UNITS

80 +ISC 0 +858C
60
60 –100

40 –200
50 VS = +5V
20 VCM = +2.5V
–300

0 40 –400
–2.5 –1.5 –0.5 0.5 1.5 2.5 –50 –25 0 25 50 75 100 0 1 2 3 4 5
INPUT OFFSET – mV TEMPERATURE – 8C COMMON-MODE VOLTAGE – Volts

Figure 1. Input Offset Distribution Figure 2. Short Circuit Current vs. Figure 3. Input Bias Current
Temperature vs. Common-Mode Voltage

3.0 100 7

VS = +5V VS = +5V
–ISC 6 TA = +258C
SHORT CIRCUIT CURRENT – mA

2.5 TA = +258C
90
OFFSET VOLTAGE – mV

BANDWIDTH – MHz
2.0
80 4
1.5 +ISC
3
70
1.0
2

60
0.5 1
VS = 65V

0 50 0
0 1 2 3 4 5 –50 –25 0 25 50 75 100 0 1 2 3 4 5
COMMON-MODE VOLTAGE – Volts
COMMON-MODE VOLTAGE – Volts TEMPERATURE – 8C

Figure 4. Offset Voltage vs. Figure 5. Short Circuit Current vs. Figure 6. Bandwidth vs.
Common-Mode Voltage Temperature Common-Mode Voltage

1000 5 120 270

VS 62.5V
RL= 2kV
100 TA –408C 225
800 4 RL = 2kV
OPEN-LOOP GAIN – V/mV

+EDGE 80 180
OPEN-LOOP GAIN – dB
SLEW RATE – V/ms

GAIN
PHASE – Degrees
600 VS = 15V 135
3 60
0.3 VOUT 4.7V
–EDGE
40 90
400 PHASE
2
20 45
RL= 1kV VS = +5V
200 0 0
1 RL = 1kV
CL = +1nF –45
–20
0 0 –40 –90
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 100 1k 10k 100k 1M 10M
TEMPERATURE – 8C TEMPERATURE – 8C FREQUENCY – Hz

Figure 7. Open-Loop Gain vs. Figure 8. Slew Rate vs. Figure 9. Open-Loop Gain and
Temperature Temperature Phase vs. Frequency

–4– REV. F
 OP179/OP279
6.5 5 120 270
VS 62.5V
+EDGE 100 TA –408C 225
6.0 4 RL = 2kV
VS = 66V
SUPPLY CURRENT – mA

180

OPEN-LOOP GAIN – dB
80 CL = 500pF

SLEW RATE – V/ms

–EDGE GAIN

PHASE – Degrees
60 135
5.5 3
VS = 65V 90
40
PHASE
5.0 2
20 45
VS = +5V
VS = 65V 0 0
4.5 VCM = +2.5V 1 RL = 1kV
CL = +1nF –20 –45

4.0 0 –40 –90

–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 100 1k 10k 100k 1M 10M
TEMPERATURE – 8C TEMPERATURE – 8C FREQUENCY – Hz

Figure 10. Supply Current vs. Figure 11. Slew Rate vs. Temperature Figure 12. Open-Loop Gain and
Temperature Phase vs. Frequency

120 6 180
VS 62.5V TA = +258C
TA = +258C 160
VS = 62.5V OR 65V
POWER SUPPLY REJECTION – dB

MAXIMUM OUTPUT SWING – Volts

100 TA = +258C VS = 62.5V

5
AVCL = +1 140
RL 1kV

IMPEDANCE – V
80 4 120
–PSRR AVCL = 10 OR 100
100
60 3
80
+PSRR
40 2 60

40
20 1
20
AVCL = 1
0 0 0
10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 13. Power Supply Rejection vs. Figure 14. Maximum Output
Frequency Swing vs. Frequency Figure 15. Closed-Loop Output
Impedance vs. Frequency

12 50
TA = +258C AVCL = +100 VS 62.5V 80
TA = +258C TA = +258C
VS = 65V
MAXIMUM OUTPUT SWING – Volts

40
10 RL 1kV 70 AVCL = +1
AVCL = +1
RL 1kV
CLOSED-LOOP GAIN – dB

RL 1kV 30
AVCL = +10 60 VS 62.5V
8 VIN = +100mV p-p
OVERSHOOT – %

20
50
6 10
AVCL = +1 40
0
4 30
–10 POSITIVE EDGE AND
20 NEGATIVE EDGE
2
–20
10
0 –30
1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 100M
0
FREQUENCY – Hz FREQUENCY – Hz 0 2k 4k 6k 8k 10k
LOAD CAPACITANCE – pF
Figure 16. Maximum Output Swing Figure 17. Closed-Loop Gain vs.
vs. Frequency Frequency Figure 18. Small Signal Overshoot
vs. Load Capacitance

REV. F –5–
OP179/OP279
Typical Performance Graphs
100 60 120
VS = +5V
VS = +5V TA = +258C

VOLTAGE NOISE DENSITY – nV/!Hz

VOLTAGE NOISE DENSITY – nV/!Hz

TA = +258C

COMMON-MODE REJECTION – dB
50 TA = +258C 100 VS 62.5V
80
FREQUENCY = 1kHz

40 80
60

30 60
40
20 40

20
10 20

0 0 0
1 10 100 1k 10k 0 1 2 3 4 5 100 1k 10k 100k 1M
FREQUENCY – Hz COMMON-MODE VOLTAGE – Volts FREQUENCY – Hz

Figure 19. Voltage Noise Density vs. Figure 20. Voltage Noise Density vs. Figure 21. Common-Mode
Frequency Common-Mode Voltage Rejection vs. Frequency

THEORY OF OPERATION VPOS

The OP179/OP279 is the latest entry in Analog Devices’ ex-
panding family of single-supply devices, designed for the multi- R1 R2
media and telecom marketplaces. It is a high output current 6kV 3kV
drive, rail-to-rail input /output operational amplifier, powered Q2 Q3
from a single +5 V supply. It is also intended for other low
supply voltage applications where low distortion and high out- Q4
R3 R4
put current drive are needed. To combine the attributes of high 2.5kV 2.5kV
output current and low distortion in rail-to-rail input/output
D5 D6
operation, novel circuit design techniques are used. Q6
Q1 Q5 Q9
IN+ IN–
For example, Figure 1 illustrates a simplified equivalent circuit
for the OP179/OP279’s input stage. It is comprised of two PNP D1
D7 D8
D3
differential pairs, Q5-Q6 and Q7-Q8, operating in parallel, with D2
R5 R6
D4
diode protection networks. Diode networks D5-D6 and D7-D8 Q7 4kV 4kV Q8
serve to clamp the applied differential input voltage to the I1 I2 – VO +
OP179/OP279, thereby protecting the input transistors against R7 R8 I3
avalanche damage. The fundamental differences between these 2.2kV 2.2kV

two PNP gain stages are that the Q7-Q8 pair are normally OFF
and that their inputs are buffered from the operational amplifier VNEG
inputs by Q1-D1-D2 and Q9-D3-D4. Operation is best under-
stood as a function of the applied common-mode voltage: Figure 22. OP179/OP279 Equivalent Input Circuit
When the inputs of the OP179/OP279 are biased midway be- The key issue here is the behavior of the input bias currents in
tween the supplies, the differential signal path gain is controlled this stage. The input bias currents of the OP179/OP279 over
by the resistively loaded (via R7, R8) Q5-Q6. As the input the range of common-mode voltages from (VNEG + 1 V) to
common-mode level is reduced toward the negative supply (VPOS – 1 V) are the arithmetic sum of the base currents in Q1-
(VNEG or GND), the input transistor current sources, I1 and I3, Q5 and Q9-Q6. Outside of this range, the input bias currents
are forced into saturation, thereby forcing the Q1-D1-D2 and are dominated by the base current sum of Q5-Q6 for input
Q9-D3-D4 networks into cutoff; however, Q5-Q6 remain signals close to VNEG, and of Q1-Q5 (Q9-Q6) for input signals
active, providing input stage gain. On the other hand, when the close to VPOS. As a result of this design approach, the input bias
common-mode input voltage is increased toward the positive currents in the OP179/OP279 not only exhibit different ampli-
supply, Q5-Q6 are driven into cutoff, Q3 is driven into satura- tudes, but also exhibit different polarities. This input bias cur-
tion, and Q4 becomes active, providing bias to the Q7-Q8 dif- rent behavior is best illustrated in Figure 3. It is, therefore, of
ferential pair. The point at which the Q7-Q8 differential pair paramount importance that the effective source impedances
becomes active is approximately equal to (VPOS – 1 V). connected to the OP179/OP279’s inputs are balanced for opti-
mum dc and ac performance.

–6– REV. F
 OP179/OP279
In order to achieve rail-to-rail output behavior, the OP179/OP279 ensure optimum dc and ac performance, it is important to bal-
design employs a complementary common-emitter (or gm RL) ance source impedance levels. For more information on general
output stage (Q15-Q16), as illustrated in Figure 23. These overvoltage characteristics of amplifiers refer to the 1993 Seminar
amplifiers provide output current until they are forced into Applications Guide, available from the Analog Devices Literature
saturation which occurs at approximately 50 mV from either Center.
supply rail. Thus, their saturation voltage is the limit on the 5
maximum output voltage swing in the OP179/OP279. The
4
output stage also exhibits voltage gain, by virtue of the use of
common-emitter amplifiers; and, as a result, the voltage gain of 3

the output stage (thus, the open-loop gain of the device) exhib-

INPUT CURRENT – mA
2
its a strong dependence to the total load resistance at the output 1
of the OP179/OP279 as illustrated in Figure 7.
0

VPOS –1

–2

–3
105V
Q13
–4
I1 Q3 Q7 I3
–5
Q15 –2.0 –1.0 0 1.0 2.0
INPUT VOLTAGE – V
Q4 Q8
Q1 150V Q11 Figure 24. OP179/OP279 Input Overvoltage Characteristic
VOUT
Q2 Q12 Output Phase Reversal
Q5 Q9 Some operational amplifiers designed for single supply opera-
tion exhibit an output voltage phase reversal when their inputs
Q16
are driven beyond their useful common-mode range. Typically
I2 Q6 Q10 I4 for single-supply bipolar op amps, the negative supply deter-
105V Q14
mines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to
ground and the cathode to the inputs, input signal excursions
VNEG are prevented from exceeding the device’s negative supply (i.e.,
GND), preventing a condition that could cause the output
Figure 23. OP179/OP279 Equivalent Output Circuit
voltage to change phase. JFET input amplifiers may also
Input Overvoltage Protection exhibit phase reversal and, if so, a series input resistor is usually
As with any semiconductor device, whenever the condition required to prevent it.
exists for the input to exceed either supply voltage, the device’s
The OP179/OP279 is free from reasonable input voltage range
input overvoltage characteristic must be considered. When an
restrictions provided that input voltages no greater than the
overvoltage occurs, the amplifier could be damaged, depending
supply voltages are applied. Although the device’s output will
on the magnitude of the applied voltage and the magnitude of
not change phase, large currents can flow through the input
the fault current. Figure 24 illustrates the input overvoltage
protection diodes, shown in Figure 22. Therefore, the tech-
characteristic of the OP179/OP279. This graph was generated
nique recommended in the Input Overvoltage Protection sec-
with the power supplies at ground and a curve tracer connected
tion should be applied in those applications where the
to the input. As can be seen, when the input voltage exceeds
likelihood of input voltages exceeding the supply voltages is
either supply by more than 0.6 V, internal pn-junctions ener-
possible.
gize, which allows current to flow from the input to the supplies.
As illustrated in the simplified equivalent input circuit (Figure Capacitive Load Drive
22), the OP179/OP279 does not have any internal current limit- The OP179/OP279 has excellent capacitive load driving capa-
ing resistors, so fault currents can quickly rise to damaging bilities. It can drive up to 10 nF directly as the performance
levels. graph titled Small Signal Overshoot vs. Load Capacitance (Fig-
ure 18) shows. However, even though the device is stable, a
This input current is not inherently damaging to the device as
capacitive load does not come without a penalty in bandwidth.
long as it is limited to 5 mA or less. For the OP179/OP279,
As shown in Figure 25, the bandwidth is reduced to under 1 MHz
once the input voltage exceeds the supply by more than 0.6 V,
for loads greater than 3 nF. A “snubber” network on the out-
the input current quickly exceeds 5 mA. If this condition con-
put won’t increase the bandwidth, but it does significantly re-
tinues to exist, an external series resistor should be added. The
duce the amount of overshoot for a given capacitive load. A
size of the resistor is calculated by dividing the maximum over-
snubber consists of a series R-C network (RS, C S), as shown in
voltage by 5 mA. For example, if the input voltage could reach
Figure 26, connected from the output of the device to ground.
100 V, the external resistor should be (100 V/5 mA) = 20 kΩ.
This network operates in parallel with the load capacitor, CL, to
This resistance should be placed in series with either or both
provide phase lag compensation. The actual value of the resis-
inputs if they are exposed to an overvoltage. Again, in order to
tor and capacitor is best determined empirically.

REV. F –7–
OP179/OP279
7 Table I. Snubber Networks for Large Capacitive Loads
VS = 65V
6 RL = 1kV Load Capacitance (CL ) Snubber Network (RS, CS)
TA = +258C

5
10 nF 20 Ω, 1 µF
5 Ω, 10 µF
BANDWIDTH – MHz

100 nF
4 1 µF 0 Ω, 10 µF

3 Overload Recovery Time

Overload, or overdrive, recovery time of an operational amplifier
2 is the time required for the output voltage to recover to its linear
region from a saturated condition. This recovery time is impor-
1
tant in applications where the amplifier must recover after a
0
large transient event. The circuit in Figure 28 was used to
0.01 0.100 1 10 evaluate the OP179/OP279’s overload recovery time. The
CAPACITIVE LOAD – nF
OP179/OP279 takes approximately 1 µs to recover from positive
Figure 25. OP179/OP279 Bandwidth vs. Capacitive Load saturation and approximately 1.2 µs to recover from negative
saturation.
+5V
R2 R3
1kV 10kV

1/2 +5V
VOUT
VIN
OP279 RS
100mV p-p 20V CL
1/2
CS 10nF R1 VOUT
909V
OP279
1mF RL
2V p-p 499V
@ 100Hz –5V
Figure 26. Snubber Network Compensates for Capacitive
Load
The first step is to determine the value of the resistor, RS . A Figure 28. Overload Recovery Time Test Circuit
good starting value is 100 Ω (typically, the optimum value will Output Transient Current Recovery
be less than 100 Ω). This value is reduced until the small-signal In many applications, operational amplifiers are used to provide
transient response is optimized. Next, CS is determined—10 µF moderate levels of output current to drive the inputs of ADCs,
is a good starting point. This value is reduced to the smallest small motors, transmission lines and current sources. It is in
value for acceptable performance (typically, 1 µF). For the case these applications that operational amplifiers must recover
of a 10 nF load capacitor on the OP179/OP279, the optimal quickly to step changes in the load current while maintaining
snubber network is a 20 Ω in series with 1 µF. The benefit is steady-state load current levels. Because of its high output
immediately apparent as seen in the scope photo in Figure 27. current capability and low closed-loop output impedance, the
The top trace was taken with a 10 nF load and the bottom trace OP179/OP279 is an excellent choice for these types of applica-
with the 20 Ω, 1 µF snubber network in place. The amount of tions. For example, when sourcing or sinking a 25 mA steady-
overshot and ringing is dramatically reduced. Table I illustrates state load current, the OP179/OP279 exhibits a recovery time of
a few sample snubber networks for large load capacitors. less than 500 ns to 0.1% for a 10 mA (i.e., 25 mA to 35 mA and
35 mA to 25 mA) step change in load current.
A Precision Negative Voltage Reference
10nF LOAD 100 In many data acquisition applications, the need for a precision
ONLY 90
negative reference is required. In general, any positive voltage
reference can be converted into a negative voltage reference
through the use of an operational amplifier and a pair of matched
resistors in an inverting configuration. The disadvantage to that
SNUBBER
10
approach is that the largest single source of error in the circuit is
IN CIRCUIT 0% the relative matching of the resistors used.
50mV 2ms The circuit illustrated in Figure 29 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
Figure 27. Overshoot and Ringing Is Reduced by Adding a this circuit, the output of the voltage reference provides the
“Snubber” Network in Parallel with the 10 nF Load input drive for the integrator. The integrator, to maintain cir-
cuit equilibrium, adjusts its output to establish the proper rela-
tionship between the reference’s VOUT and GND. Thus, various
negative output voltages can be chosen simply by substituting
for the appropriate reference IC (see table). To speed up the

–8– REV. F
 OP179/OP279
ON-OFF settling time of the circuit, R2 can be reduced to The low dropout performance of this circuit is provided by stage
50 kΩ or less. Although the integrator’s time constant chosen U2, one-half of an OP179/OP279 connected as a follower/buffer
here is 1 ms, room exists to trade-off circuit bandwidth and for the basic reference voltage produced by U1. The low voltage
noise by increasing R3 and decreasing C2. The SHUTDOWN saturation characteristic of the OP179/OP279 allows up to 30 mA
feature is maintained in the circuit with the simple addition of a of load current in the illustrated use, as a 5 V to 3.3 V converter
PNP transistor and a 10 kΩ resistor. One caveat with this ap- with high dc accuracy. In fact, the dc output voltage change for
proach should be mentioned: although rail-to-rail output ampli- a 30 mA load current delta measures less than 1 mV. This
fiers work best in the application, these operational amplifiers corresponds to an equivalent output impedance of < 0.03 Ω. In
require a finite amount (mV) of headroom when required to this application, the stable 3.3 V from U1 is applied to U2
provide any load current. The choice for the circuit’s negative through a noise filter, R1-C1. U2 replicates the U1 voltage
supply should take this issue into account. within a few mV, but at a higher current output at VOUT1 , with
the ability to both sink and source output current(s)—unlike
U1 VOUT (V) most IC references. R2 and C2 in the feedback path of U2
+5V REF192 2.5 provide bias compensation for lowest dc error and additional
REF193 3.0
R5 REF196 3.3 C2
noise filtering.
10kV REF194 4.5
SHUTDOWN 1mF
TTL/CMOS
2N3904 2 Transient performance of the reference/regulator for a 10 mA
R3 +5V
step change in load current is also quite good and is determined
U1 1kV
3 6 R4 largely by the R5-C5 output network. With values as shown, the
REF195 10V
1/2 –VREF
transient is about 10 mV peak and settles to within 2 mV in
GND C1
1mF
OP279
8 µs, for either polarity. Although room exists for optimizing the
4 transient response, any changes to the R5-C5 network should be
R1 R2
100kV –10V
10kV verified by experiment to preclude the possibility of excessive
ringing with some capacitor types.
To scale VOUT2 to another (higher) output level, the optional
Figure 29. A Negative Precision Voltage Reference That resistor R3 (shown dotted) is added, causing the new VOUT1 to
Uses No Precision Resistors Exhibits High Output Current become:
Drive
A High Output Current, Buffered Reference/Regulator  R2 
V OUT 1 = V OUT 2 × 1 + 
Many applications require stable voltage outputs relatively close  R3 
in potential to an unregulated input source. This “low dropout”
type of reference/regulator is readily implemented with a rail-to- As an example, for a VOUT1 = 4.5 V, and VOUT2 = 2.5 V from a
rail output op amp, and is particularly useful when using a REF192, the gain required of U2 is 1.8 times, so R2 and R3
higher current device such as the OP179/OP279. A typical would be chosen for a ratio of 0.8:1, or 18 kΩ:22.5 kΩ. Note
example is the 3.3 V or 4.5 V reference voltage developed from that for the lowest VOUT1 dc error, the parallel combination of
a 5 V system source. Generating these voltages requires a three- R2 and R3 should be maintained equal to R1 (as here), and the
terminal reference, such as the REF196 (3.3 V) or the REF194 R2-R3 resistors should be stable, close tolerance metal film
(4.5 V), both of which feature low power, with sourcing outputs types.
of 30␣ mA or less. Figure 30 shows how such a reference can be The circuit can be used as shown as either a 5 V to 3.3 V refer-
outfitted with an OP179/OP279 buffer for higher currents and/ ence/regulator, or it can be used with ON/OFF control. By
or voltage levels, plus sink and source load capability. driving Pin 3 of U1 with a logic control signal as noted, the
output is switched ON/OFF. Note that when ON/OFF control
+VS
+5V
U2 is used, resistor R4 should be used with U1 to speed ON-OFF
1/2 OP279
switching.
C1 VOUT1 =
0.1mF 3.3V @ 30mA Direct Access Arrangement for Telephone Line Interface
R2 Figure 31 illustrates a +5 V only transmit/receive telephone line
R1
10kV interface for 110 Ω transmission systems. It allows full duplex
1%
10kV transmission of signals on a transformer coupled 110 Ω line in a
1%
C2 differential manner. Amplifier A1 provides gain that can be
0.1mF
R3 adjusted to meet the modem output drive requirements. Both
C3
(SEE TEXT) C5 A1 and A2 are configured to apply the largest possible signal on a
0.1mF 2 10mF/25V
6 TANTALUM single supply to the transformer. Because of the OP179/
U1
3 REF196 VOUT2 = R4 OP279’s high output current drive and low dropout voltage, the
VC 3.3kV
ON/OFF
3.3V
C4
R5 largest signal available on a single +5 V supply is approximately
4
CONTROL 1mF
1V
4.5 V p-p into a 110 Ω transmission system. Amplifier A3 is
INPUT CMOS HI
(OR OPEN) = ON configured as a difference amplifier to extract the receive signal
LO = OFF
VOUT
from the transmission line for amplification by A4. A4’s gain
VS
COMMON
COMMON can be adjusted in the same manner as A1’s to meet the modem’s
input signal requirements. Standard resistor values permit the
Figure 30. A High Output Current Reference/Regulator use of SIP (Single In-line Package) format resistor arrays. Couple
this with the OP179/OP279’s 8-lead SOIC footprint and this
circuit offers a compact, cost-sensitive solution.
REV. F –9–
OP179/OP279
P1 The AMP04 is configured for a gain of 100, producing a circuit
TX GAIN
ADJUST R2 sensitivity of 80 mV/Ω. Capacitor C2 is used across the AMP04’s
9.09kV
R1
C1 TRANSMIT Pins 8 and 6 to provide a 16-Hz noise filter. If additional noise
TO TELEPHONE 2kV 0.1mF TXA
LINE
R3 2 10kV filtering is required, an optional capacitor, CX, can be used
55V 1
1:1 A1 3
across the AMP04’s input to provide differential-mode noise
R5 rejection.
ZO 6.2V
10kV
110V R4
6.2V
55V +5V DC
A Single Supply, Balanced Line Driver
T1
R6
The circuit in Figure 33 is a unique line driver circuit topology
6
10kV
7 R7 used in professional audio applications and has been modified
A2 10kV
5 for automotive audio applications. On a single +12 V supply,
10mF
R8 the line driver exhibits less than 0.02% distortion into a 600 Ω
10kV
load across the entire audio band (not shown). For loads greater
R9
10kV
R10
10kV P2
than 600 Ω, distortion performance improves to where the cir-
RX GAIN cuit exhibits less than 0.002%. The design is a transformerless,
R13 R14 ADJUST RECEIVE
R11
2
1 10kV 9.09kV RXA balanced transmission system where output common-mode
10kV 3
A3 rejection of noise is of paramount importance. Like the trans-
6 2kV C2
R12 7 0.1mF former-based system, either output can be shorted to ground for
A4
A1, A2 = 1/2 OP279 10kV 5 unbalanced line driver applications without changing the circuit
A3, A4 = 1/2 OP279
gain of 1. Other circuit gains can be set according to the equa-
tion in the diagram. This allows the design to be easily config-
Figure 31. A Single Supply Direct Access Arrangement for
ured for noninverting, inverting, or differential operation.
Modems
A Single Supply, Remote Strain Gage Signal Conditioner R3
10kV
The circuit in Figure 32 illustrates a way by which the OP179/ C3
OP279 can be used in a +12 V single supply, 350 Ω strain gage 2
1
R5
50V 47mF
signal conditioning circuit. In this circuit, the OP179/OP279 A2 VO1
3 R6
serves two functions: (1) By servoing the output of the REF43’s 10kV
+2.5 V output across R1, it provides a 20 mA drive to the 350 Ω R2
10kV R7
strain gage. In this way, small changes in the strain gage pro- 10kV +12V
duce large differential output voltages across the AMP04’s in- +12V +12V
2 6
puts. (2) To maximize the circuit’s dynamic range, the other C1
1 7
R8
22mF 100kV RL
A1
half of the OP179/OP279 is configured as a supply-splitter VIN
3 A1 5 600V
connected to the AMP04’s REF terminal. Thus, tension or R9 C2
compression in the application can be measured by the circuit. 100kV 1mF
R1 R11 R12
10kV 10kV 10kV
A1, A2 = 1/2 OP279
+12V C4
R14
GAIN = R3 6 47mF
R2 7 50V
A2 VO2
5
2 SET: R7, R10, R11 = R2 R13
0.1mF
8 3 +2.5V 6 10kV
REF43 SET: R6, R12, R13 = R3
1
A1 2
4
F+ 4 Figure 33. A Single Supply, Balanced Line Driver for
+12V R4 C2 Automotive Applications
1kV 0.1mF
7
20mA DRIVE
3 1
S+ 8
6
S– CX AMP04
2 VO
5
4 80mV/V
R1
124V
100-ft TWISTED PAIR 0.1%, LOW TCR VO
BELDEN TYPE 9502 COMMON
F– +12V
350V 6
STRAIN GAGE R2 7
10kV A2 +6V
5

C1 R3
10mF 10kV A1, A2 = 1/2 OP279

Figure 32. A Single Supply, Remote Strain Gage Signal

Conditioner

–10– REV. F
 OP179/OP279
A Single Supply Headphone Amplifier UNITY-GAIN, SALLEN-KEY (VCVS) FILTERS
Because of its high speed and large output drive, the OP179/ High Pass Configurations
OP279 makes for an excellent headphone driver, as illustrated In Figure 35a is the HP form of a unity-gain 2-pole SK filter
in Figure 34. Its low supply operation and rail-to-rail inputs using an OP179/OP279 section. For this filter and its LP coun-
and outputs give a maximum signal swing on a single +5 V terpart, the gain in the passband is inherently unity, and the
supply. To ensure maximum signal swing available to drive the signal phase is noninverting due to the follower hookup. For
headphone, the amplifier inputs are biased to V+/2, which is in simplicity and practicality, capacitors C1-C2 are set equal, and
this case 2.5 V. The 100 kΩ resistor to the positive supply is resistors R2-R1 are adjusted to a ratio “N,” which provides the
equally split into two 50 kΩ with their common point bypassed filter damping “α” as per the design expressions. A HP design
by 10 µF to prevent power supply noise from contaminating the is begun with selection of standard capacitor values for C1 and
audio signal. C2 and a calculation of N; then R1 and R2 are calculated as per
the figure expressions.
+V + 5V
In these examples, α (or 1/Q) is set equal to √2, providing a
Butterworth (maximally flat) response characteristic. The filter
50kV
+V + 5V corner frequency is normalized to 1 kHz, with resistor values
shown in both rounded and (exact) form. Various other 2-pole
10mF 220mF
50kV 1/2 16V response shapes are also possible with appropriate selection of
LEFT
OP279
LEFT
HEADPHONE
α. For a given response type (α), frequency can be easily scaled,
INPUT 50kV
10mF using proportional R or C values.
100kV

R1
C1 11kV
0.01mF (11.254kV)
IN OUT
+V C2 +VS U1A
0.01mF
3 8 OP279
GIVEN: ALPHA, F
50kV 1
R2 2 SET C1 = C2 = C
22kV 4 ALPHA = 2/(N^0.5) = 1/Q
10mF 220mF (22.508kV) N = 4/(ALPHA)^2 = R2/R1
50kV 1/2 16V RIGHT –VS
OP279 HEADPHONE R1 = 1/(2*PI*F*C* (N^0.5))
RIGHT
INPUT 50kV R = R2 R2 = N*R1
10mF
100kV 1kHz BW SHOWN
0.1mF

Zf (HIGH PASS)
Figure 34. A Single Supply, Stereo Headphone Driver
a. High Pass
R1
The audio signal is then ac-coupled to each input through a 11kV C1
10 µF capacitor. A large value is needed to ensure that the IN
(11.254kV) 0.02mF
OUT
20 Hz audio information is not blocked. If the input already has R2
11kV U1B
the proper dc bias, the ac coupling and biasing resistors are not (11.254kV) OP279 GIVEN: ALPHA, F
5
required. A 220 µF capacitor is used at the output to couple the 7
SET R1 = R2 = R
amplifier to the headphone. This value is much larger than that C2 6 ALPHA = 2/(M^0.5) = 1/Q
0.01mF N = 4/(ALPHA)^2 = C2/C1
used for the input because of the low impedance of the head-
phones, which can range from 32 Ω to 600 Ω. An additional PICK C1
C1 = M*C1
16 Ω resistor is used in series with the output capacitor to pro- R = R1+R2 R = 1/(2*P1*F*C1* (M^0.5))
tect the op amp’s output stage by limiting capacitor discharge 1kHz BW SHOWN
current. When driving a 48 Ω load, the circuit exhibits less than 0.1mF
0.02% THD+N at low output drive levels (not shown). The Zf (LOW PASS)
OP179/OP279’s high current output stage can drive this heavy
load to 4 V p-p and maintain less than 1% THD+N. b. Low Pass
Active Filters
Several active filter topologies are useful with the OP179/OP279. Figure 35. 2-Pole Unity-Gain Sallen Key HP/LP Filters
Among these are two popular architectures, the familiar Sallen- Low Pass Configurations
Key (SK) voltage controlled voltage source (VCVS) and the In the LP SK arrangement of Figure 35b, R and C elements are
multiple feedback (MFB) topologies. These filter types can be interchanged, and the resistors are made equal. Here the C2/C1
arranged for high pass (HP), low pass (LP), and bandpass (BP) ratio “M” is used to set the filter α, as noted. This design is begun
filters. The SK filter type uses the op amp as a fixed gain voltage with the choice of a standard capacitor value for C1 and a calcu-
follower at unity or a higher gain, while the MFB structure uses lation of M, which forces a value of “M × C1” for C2. Then, the
it as an inverting stage. Discussed here are simplified, 2-pole value “R” for R1 and R2 is calculated as per the expression.
forms of these filters, highly useful as system building blocks.
For highest performance, the passive components used for tun-
ing active filters deserve attention. Resistors should be 1%, low
TC, metal film types of the RN55 or RN60 style, or similar.

REV. F –11–
OP179/OP279
Capacitors should be 1% or 2% film types preferably, such as reactive, and limits overall practicality of this filter. The dire
polypropylene or polystyrene, or NPO (COG) ceramic for effect of C1 loading can be tempered somewhat by using a small
smaller values. Somewhat lesser performance is available with series input resistance of about 100 Ω, but can still be an issue.
the use polyester capacitors.
C1 C2
Parasitic Effects in Sallen-Key Implementations 0.01mF 0.01mF
In designing these circuits, moderately low (10 kΩ or less) val- IN OUT
C3
ues for R1-R2 can be used to minimize the effects of Johnson 0.01mF
R2
33.6kV GIVEN:
noise when critical, with of course practical tradeoffs of capaci- ALPHA, F AND H (PASSBAND GAIN)
ALPHA = 1/Q
tor size and expense. DC errors will result for larger values of 6
R1 7
resistance, unless bias current compensation is used. To add 7.5kV 5 PICK A STD C1 VALUE, THEN:
C3 = C1, C2 = C1/H
bias compensation in the HP filter of Figure 35a, a feedback U1B R1 = ALPHA / ((2*PI*F*C1)*(2+(1/H)))
OP279
compensation resistor with a value equal to R2 is used, shown R2 = (H*(2+(1/H))) / (ALPHA*(2*PI*F*C1))
R = R2
optionally as Zf. This will minimize bias induced offset, reduc- 1kHz BW EXAMPLE SHOWN
ing it to the product of the OP179/OP279’s IOS and R2. Similar (NOTE: SEE TEXT ON C1 LOADING
compensation is applied to the LP filter, using a Zf resistance of 0.1mF CONSIDERATIONS)
R1 + R2. Using dc compensation and relatively low filter val- Zb
ues, filter output dc errors using the OP179/OP279 will be
dominated by VOS, which is limited to 4 mV or less. A caveat Figure 36. Two-Pole, High Pass Multiple Feedback Filters
here is that the additional resistors increase noise substantially—
for example, an unbypassed 10 kΩ resistor generates ≈ 12 nV/ In this example, the filter gain is set to unity, the corner fre-
√Hz of noise. However, the resistance can be ac-bypassed to quency is 1 kHz, and the response is a Butterworth type. For
eliminate noise with a simple shunt capacitor, such as 0.1 µF. applications where dc output offset is critical, bias current com-
pensation can be used for the amplifier. This is provided by
Sallen-Key Implementations in Single Supply Applications network Zb, where R is equal to R2, and the capacitor provides
The hookups shown illustrate a classical dual supply op amp a noise bypass.
application, which for the OP179/OP279 would use supplies up
to ± 5 V. However, these filters can also use the op amp in a Low Pass Configurations
single-supply mode, with little if any alteration to the filter itself. Figure 37 is a LP MFB 2-pole filter using an OP179/OP279
To operate single-supply, the OP179/OP279 is powered from section. For this filter, the gain in the pass band is user config-
+5 V at Pin 8 with Pin 4 grounded. The input dc bias for the urable over a wide range, and the pass band signal phase is
op amp must be supplied from a dc source equal to 1/2 supply, inverting. Given the design parameters for α, F, and H, a sim-
or 2.5 V in this case. plified design process is begun by picking a standard value for
C2. Then C1 and resistors R1-R3 are selected as per the rela-
For the HP section, dc bias is applied to the common end of R2. tionships noted. Optional dc bias current compensation is pro-
R2 is simply returned to an ac ground that is a well-bypassed vided by Zb, where R is equal to the value of R3 plus the parallel
2:1 divider across the 5 V source. This can be as simple as a equivalent value of R1 and R2.
pair of 100 kΩ resistors with a 10 µF bypass cap. The output
from the stage is then ac coupled, using an appropriate coupling R1 R2
cap from U1A to the next stage. For the LP section dc bias is 11.3kV 11.3kV
IN OUT
applied to the input end of R1, in common with the input sig- R3 C2
GIVEN:
nal. This dc can be taken from an unbypassed dual 100 kΩ 5.62kV 0.01mF
ALPHA, F AND H (PASSBAND GAIN)
divider across the supply, with the input signal ac coupled to the ALPHA = 1/Q
5
divider and R1. C1 7 PICK A STD C2 VALUE, THEN:
0.04mF 6 C1 = C2 • (4 • (H +1))/ALPHA^2
Multiple Feedback Filters R1 = ALPHA/(4 • H • PI • F • C2)
U1B R2 = H • R1
MFB filters, like their SK relatives, can be used as building OP279 R3 = ALPHA/(4 • (H + 1) • PI • F • C2)
blocks as well. They feature LP and HP operation as well, but (R1 R2)+R3 1kHz BW EXAMPLE SHOWN
can also be used in a bandpass BP mode. They have the prop- (NOTE: SEE TEXT ON C1 LOADING
erty of inverting operation in the pass band, since they are based CONSIDERATIONS)
0.1mF
on an inverting amplifier structure. Another useful asset is their Zb
ability to be easily configured for gain.
High Pass Configurations Figure 37. Two-Pole, Low-Pass Multiple Feedback Filters
Figure 36 shows an HP MFB 2-pole filter using an OP179/
OP279 section. For this filter, the gain in the passband is user Gain of this filter, H, is set here by resistors R2 and R1 (as in a
configurable, and the signal phase is inverting. The circuit uses standard op amp inverter), and can be just as precise as these
one more tuning component than the SK types. For simplicity, resistors allow at low frequencies. Because of this flexible and
capacitors C1 and C3 are set to equal standard values, and accurate gain characteristic, plus a low range of component
resistors R1-R2 are selected as per the relationships noted. Gain value spread, this filter is perhaps the most practical of all the
of this filter, H, is set by capacitors C1 and C2, and this factor MFB types. Capacitor ratios are best satisfied by paralleling
limits both gain selectability and precision. Also, input capaci- two or more common types, as in the example, which is a 1 kHz
tance C1 makes the load seen by the driving stage highly unity gain Butterworth filter.

–12– REV. F
 OP179/OP279
Bandpass Configurations C1 R1 R3
The MFB bandpass filter using an OP179/OP279 section is 0.01mF 31.6kV 49.9V
HI
shown in Figure 38. This filter provides reasonably stable me- +VS
C2 500Hz AND UP
dium Q designs for frequencies of up to a few kHz. For best 0.01mF U1A
predictability and stability, operation should be restricted to 3 OP279
applications where the OP179/OP279 has an open-loop gain in 1
2
excess of 2Q2 at the filter center frequency. VIN
R2
4
31.6kV
–VS
R1
26.4kV C1 R5 R6 R4
(264kV) 0.1mF 31.6kV 31.6kV 49.9V
IN OUT LO
C2 R7 C3
R3 DC – 500Hz
0.1mF 15.8kV 0.01mF
530kV GIVEN:
Q, F, AND AO (PASSBAND GAIN)
6 ALPHA = 1/Q, H = AO/Q C4 6
R2
1.4kV 7 0.02mF 7
(1.33kV) 5 PICK A STD C1 VALUE, THEN: 5
U1B C2 = C1 U1B
OP279 R1 = 1/(H*(2*PI*F*C1))
R2 = 1/(((2*Q) –H)*(2*PI*F*C1))
OP279
R = R3 R3 = Q/(PI*F*C1) +VS +5V

EXAMPLE: 60Hz, Q = 10, 0.1mF 100mF/25V

AO = 10 (OR 1)
TO U1 COM
0.1mF AO = 1 FOR '( )' VALUES
Zb 0.1mF 100mF/25V
–VS –5V

Figure 38. Two-Pole, Bandpass Multiple Feedback Filters

Given the bandpass design parameters for Q, F, and pass band Figure 39. Two-Way Active Crossover Networks
gain AO, the design process is begun by picking a standard value In the filter sections, component values have been selected for
for C1. Then C2 and resistors R1-R3 are selected as per the good balance between reasonable physical/electrical size, and
relationships noted. This filter is subject to a wide range of lowest noise and distortion. DC offset errors can be minimized
component values by nature. Practical designs should attempt by using dc compensation in the feedback and bias paths, ac
to restrict resistances to a 1 kΩ to 1 MΩ range, with capacitor bypassed with capacitors for low noise. Also, since the network
values of 1 µF or less. When needed, dc bias current compensa- input is reactive, it should driven from a directly coupled low
tion is provided by Zb, where R is equal to R3. impedance source at VIN.
Two-Way Loudspeaker Crossover Networks Figure 40 shows this filter architecture adapted for single supply
Active filters are useful in loudspeaker crossover networks for operation from a 5 V dc source, along the lines discussed
reasons of small size, relative freedom from parasitic effects, and previously.
the ease of controlling low/high channel drive, plus the con-
trolled driver damping provided by a dedicated amplifier. Both C1 R1 R3 500Hz
0.01mF 49.9V 10mF AND UP
Sallen-Key (SK) VCVS and multiple-feedback (MFB) filter 31.6kV +
HI
architectures are useful in implementing active crossover net- +VS
VIN C2
works (see Reference 4), and the circuit shown in Figure 39 is 0.01mF U1A
100kV
RIN
a two-way active crossover which combines the advantages of 3 OP279
100kV 1
both filter topologies. This active crossover exhibits less than 2
R2
0.01% THD+N at output levels of 1 V rms using general pur- 31.6kV 4
pose unity gain HP/LP stages. In this two-way example, the LO CIN
10mF
signal is a dc-500 Hz LP woofer output, and the HI signal is the R5 R6 R4 DC –
500Hz
HP (> 500 Hz) tweeter output. U1B forms a MFB LP section 31.6kV 31.6kV 49.9V 10mF
+
LO
at 500 Hz, while U1A provides a SK HP section, covering fre- C3
quencies ≥ 500 Hz.
R7
15.8kV 0.01mF 100kV
+VS
This crossover network is a Linkwitz-Riley type (see Reference 6
C4
5), with a damping factor or α of 2 (also referred to as 100kV 0.02mF 7
5
“Butterworth squared”). A hallmark of the Linkwitz-Riley type
U1B
of filter is the fact that the summed magnitude response is flat 100kV 10mF OP279
across the pass band. A necessary condition for this to happen
is the relative signal polarity of the HI output must be inverted
with respect to the LOW outputs. If only SK filter sections +VS +5V
were used, this requires that the connections to one speaker be 0.1mF 100mF/25V
reversed on installation. Alternately, with one inverting stage TO U1 COM
used in the LO channel, this accomplishes the same effect. In
the circuit as shown, stage U1B is the MFB LP filter which
provides the necessary polarity inversion. Like the SK sections, Figure 40. A Single Supply, Two-Way Active Crossover
it is configured for unity gain and an α of 2. The cutoff frequency
is 500 Hz, which complements the SK HP section of U4.
REV. F –13–
OP179/OP279
The crossover example frequency of 500 Hz can be shifted References on Active Filters and Active Crossover Networks
lower or higher by frequency scaling of either resistors or capaci- 1. Sallen, R.P.; Key, E.L., “A Practical Method of Designing
tors. In configuring the circuit for other frequencies, comple- RC Active Filters,” IRE Transactions on Circuit Theory, vol.
mentary LP/HP action must be maintained between sections, CT-2, March 1955.
and component values within the sections must be in the same 2. Huelsman, L.P.; Allen, P.E., Introduction to the Theory and
ratio. Table II provides a design aid to adaptation, with sug- Design of Active Filters, McGraw-Hill, 1980.
gested standard component values for other frequencies.
3. Zumbahlen, H., “Chapter 6: Passive and Active Analog
Table II. RC Component Selection for Various Crossover Filtering,” within 1992 Analog Devices Amplifier Applications
Frequencies Guide.
4. Zumbahlen, H., “Speaker Crossovers,” within Chapter 8 of
R1/C1 (U1A)* 1993 Analog Devices System Applications Guide.
Crossover Frequency (Hz) R5/C3 (U1B)**
5. Linkwitz, S., “Active Crossover Networks for Noncoincident
100 160 kΩ/0.01 µF Drivers,” JAES, Vol. 24, #1, Jan/Feb 1976.
200 80.6 kΩ/0.01 µF
319 49.9 kΩ/0.01 µF
500 31.6 kΩ/0.01 µF
1k 16 kΩ/0.01 µF
2k 8.06 kΩ/0.01 µF
5k 3.16 kΩ/0.01 µF
10 k 1.6 kΩ/0.01 µF
Table notes (applicable for α = 2).
* For SK stage U1A: R1 = R2, and C1 = C2, etc.
** For MFB stage U1B: R6 = R5, R7 = R5/2, and C4 = 2C3.

–14– REV. F
 OP179/OP279
OP179/OP279 Spice Macro Model R10 16 98 10
* OP179/OP279 SPICE Macro-model Rev. A, 5/94 C3 15 16 15.915E-12
*
* ARG / ADI * ZERO AT 1.5 MHz
* *
E1 14 98 (9,39) 1E6
* Copyright 1994 by Analog Devices
R5 14 18 1E6
* R6 18 98 1
* Refer to “README.DOC” file for License Statement. Use of C4 14 18 106.103E-15
*
* this model indicates your acceptance of the terms and pro-
* BIAS CURRENT-VS-COMMON-MODE VOLTAGE
* visions in the License Statement. *
* EP 97 0 (99,0) 1
EN 51 0 (50,0) 1
* Node assignments V3 20 21 1.6
* noninverting input V4 22 23 2.8
* | inverting input R12 97 20 530
R13 23 51 1E3
* | | positive supply D13 15 21 DX
* | | | negative supply D14 22 15 DX
FIB 98 24 POLY(2) V3 V4 0 –1 1
* | | | | output
RIB 24 98 10E3
* | | | | | E3 97 25 POLY(1) (99,39) –1.63 1
.SUBCKT OP179/OP279 3 2 99 50 45 E4 26 51 POLY(1) (39,50) –2.73 1
D15 24 25 DX
*
D16 26 24 DX
* INPUT STAGE AND POLE AT 6 MHz *
* * POLE AT 6 MHz
*
I1 1 50 60.2E-6 G6 98 40 (18,39) 1E 6
Q1 5 2 7 QN R20 40 98 1E6
Q2 6 4 8 QN C10 40 98 26.526E-15
D1 4 2 DX *
D2 2 4 DX * OUTPUT STAGE
R1 1 7 1.628E3 *
R2 1 8 1.628E3 RS1 99 39 6.0345E3
R3 5 99 2.487E3 RS2 39 50 6.0345E3
R4 6 99 2.487E3 RO1 99 45 40
C1 5 6 5.333E-12 RO2 45 50 40
EOS 4 3 POLY(1) (16,39) 0.25E-3 50.118 G7 45 99 (99,40) 25E-3
IOS 2 3 5E-9 G8 50 45 (40,50) 25E-3
GB1 2 98 (24,98) 100E-9 G9 98 60 (45,40) 25E-3
GB2 4 98 (24,98) 100E-9 D9 60 61 DX
CIN 2 3 1E-12 D10 62 60 DX
* V7 61 98 DC 0
* GAIN STAGE AND DOMINANT POLE AT 16 Hz V8 98 62 DC 0
* FSY 99 50 POLY(2) V7 V8 1.711E-3 1 1
EREF 98 0 (39,0) 1 D11 41 45 DZ
G1 98 9 (5,6) 402.124E-6 D12 45 42 DZ
R7 9 98 497.359E6 V5 40 41 1.54
C2 9 98 20E-12 V6 42 40 1.54
V1 99 10 0.58 .MODEL DX D()
V2 11 50 0.47 .MODEL DZ D(IS=1E-6)
D5 9 10 DX .MODEL QN NPN(BF=300)
D6 11 9 DX .ENDS
*
* COMMON-MODE STAGE WITH ZERO AT 10 kHz
*
ECM 15 98 POLY(2) (3,39) (2,39) 0 0.5 0.5
R9 15 16 1E6

REV. F –15–
OP179/OP279
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP 8-Lead Narrow-Body SO

(N-8) (SO-8)
0.430 (10.92) 0.1968 (5.00)
0.348 (8.84) 0.1890 (4.80)

C3497a–0–10/99
8 5
8 5
0.280 (7.11) 0.1574 (4.00) 0.2440 (6.20)
0.240 (6.10) 0.1497 (3.80) 1 4 0.2284 (5.80)
1 4 0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
PIN 1 0.0688 (1.75) 0.0196 (0.50)
0.015 (0.38) 0.195 (4.95) x 45°
0.210 (5.33) 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
MAX 0.115 (2.93)
0.130 0.0040 (0.10)
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381) 8°
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.0500 0.0192 (0.49) 0° 0.0500 (1.27)
PLANE 0.008 (0.204) SEATING (1.27) 0.0098 (0.25)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
BSC 0.0160 (0.41)

8-Lead TSSOP 5-Lead SOT-23

(RU-8) (RT-5)
0.122 (3.10) 0.1220 (3.100)
0.1063 (2.700) PIN 1
0.114 (2.90)

8 3 2 1
5 0.0709 (1.800) 0.1181 (3.000)
0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)

0.0590 (1.500) 4 5
0.0984 (2.500)

1 0.0374 (0.950) REF

4
0.0748 (1.900)
PIN 1 REF
0.0079 (0.200)
0.0256 (0.65) 0.0512 (1.300) 0.0571 (1.450) 0.0035 (0.090)
0.006 (0.15) BSC
0.0354 (0.900) 0.0354 (0.900)
0.002 (0.05) 0.0433
(1.10) 108
MAX 0.0197 (0.500) SEATING
88 0.028 (0.70) 0.0590 (0.150) PLANE 08 0.0236 (0.600)
0.0118 (0.30) 08 0.020 (0.50) 0.0000 (0.000) 0.0118 (0.300) 0.0039 (0.100)
SEATING 0.0079 (0.20)
PLANE 0.0075 (0.19) NOTE:
0.0035 (0.090)
PACKAGE OUTLINE INCLUSIVE AS SOLDER PLATING.

PRINTED IN U.S.A.

–16– REV. F