INSTRUCTION SET ARCHITECTURE
AND DESIGN
For the students to be able to:
➢ Identify and define the parts of the Processor
➢ List the steps in fetching or reading data or
instruction from the main memory
➢ List the steps in writing or storing data into memory
➢ Define the finite steps of the processor in executing
program instruction
Introduction to Computer Systems
Technological Advances
Two major forces:
◼ Academia (University Research Centers)
◼ Industry (Computer Companies)
General Purpose Machines
machines that are built with no specific application in
mind, but rather are capable of performing computation
needed by a diversity of applications
Special Purpose Machines
built to serve (tailored to) specific applications
Introduction to Computer Systems
Layered Abstraction Levels
application programs,
the high-level languages, and
the set of machine instructions
Interfaces
language architecture
◼ interface between the application programs and a high-
level language
instruction set architecture
◼ interface between the basic machine instruction set and the
runtime and I/O control
Introduction to Computer Systems
Four basic viewpoints.
the structure
◼ defines the interconnection of various hardware components
the organization
◼ defines the dynamic interplay and management of the various
components
the implementation
◼ defines the detailed design of hardware components
the performance
◼ specifies the behavior of the computer system
ISA – Instruction Set Architecture
the part of the processor that is visible to the programmer or
compiler writer
serves as the boundary between software and hardware
can be described using 5 categories:
Operand Storage in the CPU
◼ Where are the operands kept other than in memory?
Number of explicit named operands
◼ How many operands are named in a typical instruction?
Operand location (Memory)
◼ Can any ALU instruction operand be located in memory? Or must all
operands be kept internally in the CPU?
Operations (Opcode)
◼ What operations are provided in the ISA.
Type and size of operands (Instruction length)
◼ What is the type and size of each operand and how is it specified?
Architectural Development and
Styles
Complex Instructions Set Computers (CISCs)
philosophy that by doing more in a single instruction, one can
use a smaller number of instructions to perform the same job
Examples:
◼ Intel PentiumTM
◼ Motorola MC68000TM
◼ IBM & Macintosh PowerPCTM
Reduced Instructions Set Computers (RISCs)
philosophy promotes the optimization of architectures by
speeding up those operations that are most frequently used
while reducing the instruction complexities and the number of
addressing modes
Examples:
◼ SPARCTM
◼ MIPSTM
RISC
Why is this architecture called RISC?
What is Reduced about it?
CISC
So why are there still CISC CPUs being
developed?
The 3 most common types of ISAs are:
1. Stack
▪ The operands are implicitly on top of the stack.
2. Accumulator
▪ One operand is implicitly the accumulator.
3. General Purpose Register (GPR)
▪ All operands are explicitly mentioned, they are
either registers or memory locations.
Lets look at the assembly code of
C = A + B;
in all 3 architectures:
Stack
C=A+B Stack
PUSH A
PUSH B
ADD
POP C
Advantages: Simple Model of expression evaluation
(reverse polish). Short instructions.
Disadvantages: A stack can't be randomly accessed
This makes it hard to generate efficient code. The stack
itself is accessed every operation and becomes a
bottleneck.
Accumulator
Accumulator
C=A+B
LOAD A
ADD B
STORE C
Advantages: Short instructions.
Disadvantages: The accumulator is only temporary
storage so memory traffic is the highest for this
approach.
GPR
GPR
C=A+B
LOAD R1, A
ADD R1, B
STORE R1, C
Advantages: Makes code generation easy. Data can be
stored for long periods in registers.
Disadvantages: All operands must be named leading to
longer instructions.
Instruction types
The following are representative of instruction types:
➢ 0 - address instructions
➢ 1 - address instructions
➢ 1 ½ - address instructions
➢ 2 - address instructions
➢ 2 ½ - address instructions
➢ 3 - address instructions
0 - address instructions
This type of instruction is found in machines
where many general-purpose registers are
available
R[A] R[B] operator R[C]
1 - address instructions
In this type of instruction a single memory
address is found in the instruction.
operator M[address]
1 ½ - address instructions
The typical instruction performs an operation
on a memory location's contents with that of a
general register
Add R[A], M[100]
2 - address instructions
Two address instructions utilize two memory
locations to perform an instruction
Move N, M[100], M[1000]
2 ½ - address instructions
This format uses two memory locations and a
general register in the instruction
R[A] M [100 ] operator M[1000]
M[1000] M [100] operator R[A]
3 - address instructions
These instructions involve three memory
locations
M[200] M[100] operator M[300]
Processor and the Main Memory
Main Memory
MAR MDR CONTROL
UNIT
Reg0
PC
Reg1
. ALU
IR .
.
RegN-1
CPU General Purpose Registers
Fetch/Read Data or
Instruction from Main Memory
1. The CPU first sends the address of the memory
location to be read.
2. The CPU then issues or sends the read signal to
the memory.
3. The word is then read out of memory and is
loaded into a CPU internal register.
Write/Store Data into Main
Memory
1. The CPU first sends the address of the
memory location to be written.
2. The CPU then sends the write signal together
with the data or word to be written to
memory.
Examples:
MOV Reg, [Loc-A]
Copy the contents at memory location Loc-A
into a register in the processor, Reg.
ADD Reg, [Loc-A]
Add the operand at memory location Loc-A to
the operand in a register in the processor, Reg
and place the result into register Reg
Operating Steps
1.) PC (Program Counter) is set to point to the first
instruction of the program.
Operating Steps
2.) The contents of the PC are transferred to the
MAR (Memory Address Register) and a Read
signal is sent to the MM (Main Memory).
Operating Steps
3.) The addressed word is read out of MM and
loaded into the MDR (Memory Data Register).
Operating Steps
4.) The contents of MDR are transferred to the IR. The
instruction is ready to be decoded and executed.
Operating Steps
5.) During execution, the content of the PC is
incremented or updated to point to the next
instruction.
