Concurrent Process

Course Code: NCP 3201 Program:

Course Title: Introduction to HDL Date Performed: May 05, 2021
Section: Date Submitted: May 05, 2021
Leader: 1. Alpuerto, Danica Mae V. Instructor: Prof. Onofre Corpuz
Members:
1. Objective(s):
The activity aims to demonstrate the procedures on how to simulate the
concurrent process statement in Model Sim.
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
2.1 Test the step by step procedure in running the use of
concurrent process statement VHDL codes to Model Sim.
3. Discussion:

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ModelSim PE Student Edition is a free download of the industry-leading
ModelSim HDL simulator for use by students in their academic coursework

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(www.mentor.com).

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Figure 3.1. Model Sim Environment

This application can be downloaded through the website but the license
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must request individually through sending it to your email.

A concurrent statement in VHDL is a signal assignment within the
architecture, but outside of a normal process construct. The concurrent
statement is also referred to as a concurrent assignment or concurrent
process. When you create a concurrent statement, you are creating a
process with certain, clearly defined characteristics.

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 Review of signed and unsigned:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signedunsigned12 is
end entity;

architecture sim of signedunsigned12 is

signal unscnt : unsigned(7 downto 0) := (others =>'0');
signal sigcnt : signed(7 downto 0) := (others =>'0');

signal uns4 : unsigned(3 downto 0) := "1000";

signal sig4 : signed(3 downto 0) := "1000";

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signal uns8 : unsigned(7 downto 0) := (others =>'0');

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signal sig8 : signed(7 downto 0) := (others =>'0');

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begin

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process is
begin rs e
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wait for 10 ns;
--wrapping counter
unscnt <= unscnt +1;
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sigcnt <= sigcnt +1;

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--adding signals
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uns8 <= uns8 + uns4;

sig8 <= sig8 + sig4;
end process;
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end architecture;
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0 8 16 32 ……. Signed identify 1 as negative while unsigned normally

adding numbers. Then 1000 equals 8 in decimal.

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 4. Resources:
Computer System with internet access

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Model Sim Installer capacity is 345MB while it needs 400MB space

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memory to your OS drive

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5. Procedure:

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1. Install notepad++, must add the VHDL .dll plugins
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2. Open the notepad++, create new file
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Copy the following codes:
library ieee;
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity T13_ConcurrentProcsTb is
end entity;

architecture sim of T13_ConcurrentProcsTb is

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signal Uns : unsigned(5 downto 0) := (others => '0'); --Uns is

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unsigned variable which was initialized to zero

--The statement "Others => '0'" is a feature of the VHDL when the coder
want to defined several items in an array with the same value.
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signal Mul1 : unsigned(7 downto 0);

signal Mul2 : unsigned(7 downto 0);
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signal Mul3 : unsigned(7 downto 0);

begin
process is
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begin
Uns <= Uns + 1; --increment by 1 every 10 ns

wait for 10 ns;

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 end process;
--Process multiplying Uns by 4
process is

begin
Mul1 <= Uns & "00"; --the Uns 6 bits was added two zeros to
have 8 bits

wait on Uns; --the program will wait here until the 6-bit signal
changes
--when this happens it will wake up

end process;
--Equivalent process using sensitivity list
process(Uns) is

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begin

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Mul2 <= Uns & "00"; --the Uns 6 bits was added two zeros
to have 8 bits

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end process; rs e
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--Equivalent process using a concurrent statement and is the same as
the other process with wait statement
Mul3 <= Uns & "00";
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end architecture;
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3. Change the file name by adding 13 to T13_ConcurrentProcsTb then save

as T13_ConcurrentProcsTb13.vhd
4. Open Model Sim
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5. Open the created T13_ConcurrentProcsTb13.vhd existing file to the

Model Sim project.
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6. Compile T13_ConcurrentProcsTb13 until the green check appears which

means no error.
8. Once there is no error after compiling the vhd file click simulate.
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9. Collapse the work library and choose the T13_ConcurrentProcsTb13 file

you just simulated then click ok.
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10. Drag the signal to the wave first column and hit run icon beside the
100 ns, you can see Fig. 5.2.
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 m
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Figure 5.1 Toggled Leaf Names of the Signal

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You can toggle the signal names located at the lower part of the signal
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Figure 5.2 Working Collapsed Signal Variable

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Figure 5.3 without radix output

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Figure 5.4 can be seen by typing “radix noshowbase” at the transcript
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window(from fig.5.3 it is beside the VSIM 25>).
Learnings:
In multiplying the unsigned numbers by 4 you can use “& ”00”.
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Something like when you add 1 plus 00 becomes “100” which is 4. This is
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what you called bit shifting as shown on the next figure

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0010 => 1000

0011 => 1100
And so on…
As noticed, the program process used a sensitivity list and another process
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way of writing a process but the output is still the same. However, there
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will be an error if the sensitivity list process has a wait statement.

The concurrent process is simply an assignment to a signal with an
architecture part of the VHDL file but outside the process like “Mul3 <=
Uns & “00”. This concurrent signal is equivalent to the process and
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sensitivity list.
11. For Exercise No. 8-1, what if the bits will shift to the right? What will you
do?
Clue: you may or not change the following:
7 downto 0
Uns <= Uns + 1;

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 12. subtype NATURAL is integer range 0 to integer'high;

6. Activity
6.1 Create Exercise No. 8-1 by referring to step number 11 above.
After running it without errors, paste the screenshot of the codes
and the Modelsim Waveform in the next row below. Differentiate
the codes from the first waveform output and the last waveform
output. What makes it different?

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 m
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There were changes on the output waveform as the bits shift from
left going to the right.
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