Computer Architecture

1. __________ is used to reduce cache hit time.

A. Pseudo-associative caches
B. Avoiding address translation during cache indexing
C. Early restart and critical word first
D. Giving priority to read misses over writes

2. What does drive D or E symbolise?

A. Floppy drive
B. Hard disk
C. Second floppy drive
D. CD-ROM drive

3. The beginning of the architecture of Itanium processor took place at ________.

A. Intel
B. Microsoft
C. Hewlett-Packard
D. Dell

4. In the year 1834, Babbage attempted to build a digital computer, called ___________.
A. IAS machine
B. Difference engine
C. Analytical engine
D. Pascaline

5. In pipelining, the CPU executes each instruction in a series of following stages: Instruction Fetching (IF) ----->
Instruction Decoding (ID) -----> Instruction Execution (EX) ----->__ and Register Write back (WB).
A. Linear pipelines
B. Non-linear pipelines
C. Structural hazards
D. Memory access (MEM)

6. The core element of parallel processing is __________.

A. Data sequencing.
B. CPU’s
C. Instruction execution
D. Printer

7. Ease-of-use and extensive graphic capabilities are the important characteristics of ___________.
A. Servers
B. Desktop computers
C. Minicomputers
D. Micro-computers

8. _______ is a memory-memory vector machine and fetches vectors directly from memory to load the pipelines
as well as stores the pipeline outcomes directly to memory.
A. CCF Cyber 205 B. CCD Cyber 205
C. CDC Cyber 205 D. CFC Cyber 205

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9. Fine-grain threading is considered as a ______ threading.
A. Instruction-level
B. Loop level
C. Task-level
D. Function-level

10. Define Mapping Process?

A. It is a process of transforming data from main memory to cache memory.
B. It is a process that signifies the validity of locality of reference.
C. It is a process, which translates main memory address to cache memory address.
D. It is a process of detecting a word in cache.

11. __________ is the logical structure of a computer’s Random-Access Memory (RAM).

A. Memory addressing
B. Operation field
C. Address field
D. Addressing mode

12. ___________ the pipeline solution is considered attractive due to its simplicity for hardware and software.
A. Instruction count - 0xFF01
B. Flush
C. Load-stall count - 0xFF02
D. Program counter

13. In dynamic scheduling, the hardware ______________ the instruction execution to reduce stalling of
pipeline.
A. Rearranges
B. Bypasses
C. Forwards
D. Unhide

14. The ALU performs the indicated operation on the operands prepared in the prior cycle and store the result in
the specified destination operand location.
A. Fetch instruction
B. Decode instruction
C. Execute instruction
D. Fetch operand

15. ___________ states that “the performance improvement to be gained from using some faster mode of
execution is limited by the fraction of the time the faster mode can be used.”
A. Principle of locality
B. Hybrid technique
C. Variable length technique
D. Amdahl’s Law

16. _____________ is an operation that fetches the non-zero elements of a sparse vector from memory.
A. Strip mining
B. ETA-10
C. Scatter
D. Gather

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17. ___________ execution is the temporal behavior of the N-client 1-server model where one client is served at
any given moment.
A. Single data
B. Concurrent
C. Parallel
D. Multiple data

18. In which command, the interface responds by transmitting data?

A. Data input
B. Status
C. Data output
D. Control

19. Registers that are maintained by some of the processors for recording the condition of arithmetic as well as
logical operations are called as _____________.
A. Condition code registers
B. Non-condition code registers
C. Re-locatable code
D. Branch registers

20. __________ mapping is used in cache organisation which is the quickest and most supple organisation.
A. Set associative
B. Direct
C. Sequential
D. Associative

21. The high-level attributes of a computer’s architecture, such as the memory system, the memory integration
and the architecture of the internal processor or CPU, are components of the term ___________.
A. Organisation
B. Hardware
C. Software
D. Instruction set

22. The smallest unit of memory that the CPU can read or write is ____________.
A. Word
B. Mode
C. Cell
D. Field

23. In which of the following cases, any completing instruction may not be permitted to write its result?
A. One of the operands is the same as the result of the completing instruction
B. Existence of any instruction which has read its operand
C. Operands which do not have the same register as destination
D. If the scoreboard has not detected any WAR hazard

24. _____________ is collecting the group of data elements distributed in memory and after that placing them in
linear sequential register files.
A. Vectorisation
B. Pipelining
C. Memory
D. Vector register

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25. The configuration, in which no difference between memory and I/O devices is seen by the CPU, is referred to
as ________.
A. Memory unit
B. Memory-mapped I/O
C. Memory address register
D. Memory unit

26. ___________ address of the operand calculated during the prior cycle is used to access memory.
A. Memory access completion cycle
B. Instruction decode fetch cycle
C. Instruction fetch cycle
D. Memory access fetch cycle

27. A normal CPU operates on __________.

A. Multiple scalars
B. Multiple vectors
C. Vector
D. One scalar at a time.

28. How many distinct functional units are present in CDC6600?

A. 16
B. 7
C. 5
D. 4

29. The fourth generation of computers (1978-till date) was marked by use of _________.
A. Integrated Circuits
B. Large-Scale Integrated (LSI) circuits
C. Transistors
D. Vacuum Tubes

30. __________ occur when an instruction depends on the result of a previous instruction in a way that is
exposed by the overlapping of instructions in the pipeline.
A. Data hazards
B. Control hazards
C. Structural hazards
D. Hazard in pipeline

31. In _____________ each address field determines two address fields i.e. either a memory word or the
processor register.
A. Zero-address instructions
B. Two-address instructions
C. One-address instructions
D. Three-address instructions

32. What was used to store small amount of bytes of data?

A. RAM
B. Disks
C. Punch cards
D. Tape drives

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33. The scalar registers are also linked to the functional units with the help of the pair of_____________.
A. Crossbars
B. Vertical bars
C. Horizontal bars
D. Straight bars

34. ______________ must be able to deal with both register and memory operands as well as destinations.
A. CISC pipelines
B. RISC pipelines
C. Load/Store by-passing
D. Branch instructions

35. ____________ design separates the testing for condition as well as branching. It is followed by Pentium
which makes use of flag register for recording the outcome of test condition.
A. Test-and-jump
B. Condition code register
C. Set-then-jump
D. PC-relative

36. In _______________ operation a vector moves from memory to vector register.

A. Integer operation
B. Logical operation
C. Load vector operation
D. Store vector operation

37. Which function can fetch and issue instructions from a queue or latch?
A. IF
B. DLX
C. ID
D. EX

38. _________ consists of a variety expert instruction and may just not be frequently used in practical programs.
A. Complex instruction set computer
B. Reduced instruction set computer
C. Very long instruction word
D. Very short instruction word

39. The term RISC stands for _______________.

A. Random Instruction Set Computing
B. Register Instruction Set Computing
C. Reduced Instruction Set Computing
D. Reduced Instruction Set Compiler

40. For using ________ technique, compiler should have the entire knowledge of system and its timings.
A. Pre-fetching
B. Non-blocking writes
C. Multithreading
D. Application of cache memory

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41. _________ in a dataflow graph represent data paths.
A. Nodes
B. Sticky tokens
C. Edges
D. Data links

42. CPA stands for _____________.

A. Carry-processor adder
B. Carry-propagation adder
C. Complex-process application
D. Computer-propagation adder

43. Consider the design aspects of a CM5 system with 32 processor and state which of the below options is true?
A. Memory of 32 Gbyte
B. 128 data paths
C. 3.0 synchronisation time
D. Peak speed of 128

44. ___________ units are generally floating-point units that are completely pipelined.
A. Scalar registers
B. Vector load and store unit
C. Vector functional unit
D. Control unit

45. Which is the simplest scheme to handle branches?

A. Freeze or Flush the pipeline
B. Assume each branch as not-taken
C. Predict-not-taken or predict-untaken scheme
D. Assume each branch as taken

46. It deals with the issue of selection of hardware components and interconnecting them to create computers that
achieve specified functional, performance and cost goals.
A. Von-Neumann Architecture
B. Computational Model
C. Execution Model
D. Computer Architecture

47. In this mode, the instruction specifies a register in the CPU that contains the address of the operand and not
the operand itself.
A. Register Indirect Mode
B. Auto-increment or Auto-decrement Mode
C. Register Mode
D. Immediate Mode

48. Layout and ________ are the two aspects of branch processing.
A. Handling of unresolved conditional branches
B. Accessing the branch target path
C. Branch detection
D. Micro-architectural implementation

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49. Which of the following storage devices require constant electricity?
A. Hard drive
B. Disks
C. Tape drive
D. RAM

50. ___________ is used to reduce cache hit time.

A. Giving priority to read misses over writes
B. Early restart and critical word first
C. Avoiding address translation during cache indexing
D. Pseudo-associative caches

51. The equation of average memory access time = Hit time + ___________ x _______________.
A. Miss rate, Miss penalty
B. Miss penalty, Cache size
C. Miss penalty, Hit time
D. Cache size, Miss penalty

52. 1. _____________ is a register that temporarily stores the data that is to be written in the memory or the data
received from the memory.
2. ______________ identifies the address of memory location from where the data or instruction is to be accessed
or where the data is to be stored.
A. Memory Address Register, Instruction Register
B. Memory Buffer Register, Memory Address Register
C. Memory Address Register, Memory Buffer Register
D. Instruction Register, Memory Address Register

53. 1. The ____________ should be checked for correctness.

2. ______________ means either stores can bypass loads or vice versa, without violating the memory data
dependencies.
A. Reorder buffer, Load and store reordering
B. Processor consistency, Reorder buffer
C. Speculative loads, Load/Store bypassing
D. Memory consistency, LMD

54. 1. In the late 1970s, we observed the emerging of ___________ that were high-performance computers for
scientific computing.
2. In 1960s, the ____________ used to be the most prevalent ones.
A. Main-frame computers, Microcomputers
B. Supercomputers, Main-frame computers
C. Microcomputers, Supercomputers
D. Processors, Microprocessors

55. Consider the following statements with respect to RAIDS:

1. BIP is an acronym for Block-interleaved parity and is equivalent to RAID 3.
2. Magnetic disks help provide information when the disk fails as the information is recorded in each sector that
helps detect errors.
State True or False:
A. 1- False, 2- False B. 1- True, 2- True
C. 1- False, 2- True D. 1- True, 2- False

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56. 1. In pipelining, two or more instructions that are independent of each other can overlap. This possibility of
overlap is known as ____________.
2. In case of DLX (DLX is a RISC processor architecture) pipeline, the structural & data hazards are examined
during the ____________.
A. Instruction level parallelism, Instruction decode
B. Floating point registers, Structural hazards
C. Structural hazards, Data hazard
D. Instruction decode, Instruction level parallelism

57. Consider the following statements with respect to MPP:

1. If a fault occurs during computation, the sequence of instructions following the last dump to local memory
must be repeated after replacement of the fault-containing column.
2. The processing elements are linked by a 2-dimension near-neighbor mesh and this gives an advantage of high
bandwidth.
State True or False:
A. 1- False, 2- False
B. 1- True, 2- True
C. 1- False, 2- True
D. 1- True, 2- False

58. 1. A common foundation or paradigm that links the computer architect

2. The __________ operates by manipulating symbols on a tape.
A. Computational model, Turing machine architecture
B. Turing machine architecture, Computational Model
C. Von-Neumann architecture, Dataflow architecture
D. Turing machine architecture, Von-Neumann architecture

59. Consider the following statements with respect to data hazards:

1. In pipelining, the control hazards arise when the sequence of read/write accesses to operands.
2. Pipelining has a major effect on changing the relative timing of instructions by executing them at the same
time. This leads to data and control hazards.
State True or False:
A. 1- True, 2- True
B. 1- False, 2- True
C. 1- True, 2- False
D. 1- False, 2- False

60. Consider the following statements with respect to instructions for control flow:
1. In a program control type of instruction, execution of instruction may change the address value in the program
counter and cause the flow of control to be altered.
2. Once a data transfer or data manipulation instruction is executed, control returns to the decode cycle with the
program counter containing the address of the instruction next in sequence.
State True or False:
A. 1- True, 2- True
B. 1- False, 2- False
C. 1- False, 2- True
D. 1- True, 2- False

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61. 1. __________ is systems with multiple CPUs, which are capable of independently executing different tasks
in parallel.
2. In this category every processor and memory module has similar access time.
A. Multiprocessor, UMA
B. UMA, Microprocessor
C. Microprocessor, Multiprocessor
D. UMA, NUMA

62. The Cray-1usually had a performance of about ______________, but with up to three chains running, it could
hit the highest point at ___________.
A. 80 MFLOPS, 140 MFLOPS
B. 80 MFLOPS, 120 MFLOPS
C. 80 MFLOPS, 240 MFLOPS
D. 120 MFLOPS, 240 MFLOPS

63. Consider the below mentioned statements with respect to virtual address mode.
1. In the virtual address mode, cache access efficiency is faster than physical addressing mode.
2. In the virtual address mode, cache lookup is delayed.
State True or False:
A. 1- True, 2- False
B. 1- True, 2- True
C. 1- False, 2- False
D. 1- False, 2- True

64. 1. __________ executes only the instructions that are commonly used in programs and thus, makes the
processor simpler.
2. __________ consists of variety expert instructions and may just not be frequently used in practical programs.
A. Complex instruction set computer (CISC), Very long instruction word (VLIW)
B. Reduced instruction set computer (RISC), Complex instruction set computer (CISC)
C. Reduced instruction set computer (RISC), Very long instruction word (VLIW)
D. Very long instruction word (VLIW), Reduced instruction set computer (RISC)

65. Consider the below mentioned statements with respect to dataflow graph:
1. Dataflow graph is also called as flow dependency graph.
2. Dataflow graph is asynchronous as execution of a node starts when matching data is available at a node's input
ports.
State True or False:
A. 1- True, 2- True
B. 1- True, 2- False
C. 1- False, 2- True
D. 1- False, 2- False

66. Consider the following statements with respect to the number of pipeline stages used to perform a given task:
1. Specification of the subtasks to be performed in only first stage of the pipeline.
2. Layout of the stage sequence, i.e., whether the stages are used in a strict sequential manner or some stages are
recycled.
State True or False:
A. 1- True, 2- True
B. 1- True, 2- False
C. 1- False, 2- False
D. 1- False, 2- True

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67. 1. _________ is a method which is basically utilised for handling the problems related to branch.
2. ___________ helps in instruction execution. It receives branch instructions and resolves the conditional
branches as early as possible.
A. Branch processing, Intel IA-64 architecture
B. Branch prediction, Branch processing
C. Intel IA-64 architecture, RISC
D. PC register, Branch prediction

68. 1. __________ occur from resource conflicts when the hardware cannot support all possible combinations of
instructions in simultaneous overlapped execution.
2. __________ occurs when an instruction depends on the result of a previous instruction in a way that is exposed
by the overlapping of instructions in the pipeline.
A. Structural hazards, Data hazards
B. Control hazards, Structural hazards
C. Cache miss, Hazard in pipeline
D. Control hazards, Cache miss

69. Consider the following statements with respect to parallelism in pipelining:

1. When two or more instructions that are independent of each other, overlap, they are called Dynamic
Scheduling.
2. Straight line parallelism is always greater than loop level parallelism.
State True or False:
A. 1- True, 2- True
B. 1- True, 2- False
C. 1- False, 2- False
D. 1- False, 2- True

70. Consider the following statements with respect to I/O performance measures:
1. Throughput is the average number of tasks completed by the server over a period of time.
2. The two most common measures of I/O performance, used currently, are throughput and response time.
State True or False:
A. 1- True, 2- True
B. 1- False, 2- False
C. 1- True, 2- False
D. 1- False, 2- True

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