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Difference Between Von Neumann and Harvard Architecture

The document discusses Harvard and Princeton memory architectures. [1] Harvard architecture stores instructions and data in separate memory blocks and uses separate buses to allow simultaneous access, while Princeton architecture stores instructions and data in the same memory block and uses a common bus. [2] Harvard is used more for microcontrollers and signal processing as it allows single cycle execution, while Princeton is simpler but requires two cycles per instruction and is used in PCs and small computers. [3] The advantages of Harvard include parallel access and faster execution, while Princeton is cheaper but introduces bottlenecks when accessing instructions and data simultaneously.

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142 views

Difference Between Von Neumann and Harvard Architecture

The document discusses Harvard and Princeton memory architectures. [1] Harvard architecture stores instructions and data in separate memory blocks and uses separate buses to allow simultaneous access, while Princeton architecture stores instructions and data in the same memory block and uses a common bus. [2] Harvard is used more for microcontrollers and signal processing as it allows single cycle execution, while Princeton is simpler but requires two cycles per instruction and is used in PCs and small computers. [3] The advantages of Harvard include parallel access and faster execution, while Princeton is cheaper but introduces bottlenecks when accessing instructions and data simultaneously.

Uploaded by

ramadan hundessa
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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JIMMA UNIVERSITY

INSTITUTE OF TECHNOLOGY
SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING

Advanced Embedded System


Reading Assignment3 On: HARVARD VERSUS PRINCETON
MEMORY ARCHITECTURE

Name Id
Ramadan Hundessa………………RM0046/13-0

Submitted To: Instructor Yihenew Wondie (PhD)

Date:August/25/2021

Jimma, Ethiopia
HARVARD VERSUS PRINCETON MEMORY ARCHITECTURE
As we have seen in embedded systems type of processors ,Microcontrollers 8051 is one of that
work with 8-bit data bus. From this we can understand that they can support external data
memory up to 64K and external program memory of 64k . Additionally , 8051 microcontrollers
can address 128k of external memory.
Harvard architecture is digital computer architecture when data and code placed in different
memory blocks.
princeton architecture is also part of digital computer architecture that , when data and code
placed in the same memory block.

Princeton architecture
The Princeton architecture was first proposed by a computer scientist John von Neumann
and the other name of this architecture is von Neumann .
In this architecture:-
❖ one data path or bus exists for both instruction and data.
❖ As a result, the CPU does one operation at a time.
❖ It either fetches an instruction from memory, or performs read/write operation on
data.
❖ So an instruction fetch and a data operation cannot take place at the same time,
sharing a common bus.
❖ Princeton architecture supports simple hardware. It allows the use of a single,
sequential memory.

Today's processing speeds vastly outpace memory access times, and we employ a
very fast but small amount of memory (cache) local to the processor.
➢ Used in: 80X86 (PCs), 8051, 68HC11, etc.)
➢ Only one bus between CPU and memory
➢ RAM and program memory share the same bus and the same
➢ memory, and so must have the same bit width
➢ Bottleneck: Getting instructions interferes with accessing RAM
Harvard Architecture

The Harvard architecture offers different storage and signal buses for instructions and data.
This architecture has data storage entirely contained within the CPU, and there is no access
to the instruction storage as data. Computers have separate memory areas for program
instructions and data using internal data buses, allowing simultaneous access to both
instructions and data. Programs needed to be loaded by an operator; the processor could not boot
itself. In a Harvard architecture, there is no need to make the two memories share properties.

➢ Used mostly in RISC(Reduced Instruction Set Computer) CPUs .RISC is useful in most
of the instructions for computer processes are relatively simple and computers are
designed to handle those simple instructions extremely quickly.
➢ Separate program bus and data bus can be different widths!

PRINCETON ARCHITECTURE HARVARD ARCHITECTURE


It is ancient computer architecture based on It is modern computer architecture based on
stored program computer concept. Harvard Mark I relay based model.
Same physical memory address is used for Separate physical memory address is used for
instructions and data. instructions and data.
There is common bus for data and instruction Separate buses are used for transferring data
transfer. and instruction.
Two clock cycles are required to execute An instruction is executed in a single cycle.
single instruction.
It is cheaper in cost. It is costly than Princeton architecture.
CPU can not access instructions and CPU can access instructions and read/write at
read/write at the same time. the same time.
It is used in personal computers and small It is used in micro controllers and signal
computers. processing.
Advantages of the two architectures can be explained as follows :

✓ The Princeton architecture's largest advantage is that it simplifies the microcontroller chip
design because only one memory is accessed.
✓ For microcontrollers, its biggest asset is that the contents of RAM (random-access
memory) can be used for both variable (data) storage as well as program instruction
storage.
✓ An advantage for some applications is the program counter stack contents that are
available for access by the program.
✓ This allows greater flexibility in developing software, primarily in the areas of real-time
operating systems.
✓ The Harvard architecture executes instructions in fewer instruction cycles than the
Princeton architecture.
✓ This is because a much greater amount of instruction parallelism is possible in the
Harvard architecture.
✓ Parallelism means that fetches for the next instruction can take place during the execution
of the current instruction, without having to either wait for a "dead" cycle of the
instruction's execution or stop the processor's operation while the next instruction is being
fetched.

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