LTC2460/LTC2462

Ultra-Tiny, 16-Bit ΔΣ ADCs

with 10ppm/°C Max
Precision Reference
Features Description
n 16-Bit Resolution, No Missing Codes The LTC®2460/LTC2462 are ultra tiny, 16-Bit analog-to-
n Internal Reference, High Accuracy 10ppm/°C (Max) digital converters with an integrated precision reference.
n Single-Ended (LTC2460) or Differential (LTC2462) They use a single 2.7V to 5.5V supply and communicate
n 2LSB Offset Error through an SPI Interface. The LTC2460 is single-ended
n 0.01% Gain Error with a 0V to VREF input range and the LTC2462 is dif-
n 60 Conversions Per Second ferential with a ±VREF input range. Both ADC’s include
n Single Conversion Settling Time for Multiplexed a 1.25V integrated reference with 2ppm/°C drift per-
Applications formance and 0.1% initial accuracy. The converters are
n Single-Cycle Operation with Auto Shutdown available in a 12-pin DFN 3mm × 3mm package or an
n 1.5mA Supply Current MSOP-12 package. They include an integrated oscillator
n 2µA (Max) Sleep Current and perform conversions with no latency for multiplexed
n Internal Oscillator—No External Components Required applications. The LTC2460/LTC2462 include a proprietary
n SPI Interface input sampling scheme that reduces the average input
n Ultra-Tiny 12-Lead 3mm × 3mm DFN and MSOP current several orders of magnitude when compared to
Packages conventional delta sigma converters.

Applications Following a single conversion, the LTC2460/LTC2462

automatically power down the converter and can also be
n System Monitoring
configured to power down the reference. When both the
n Environmental Monitoring
n Direct Temperature Measurements
ADC and reference are powered down, the supply current
n Instrumentation
is reduced to 200nA.
n Industrial Process Control The LTC2460/LTC2462 can sample at 60 conversions per
n Data Acquisition second, and due to the very large oversampling ratio,
n Embedded ADC Upgrades have extremely relaxed antialiasing requirements. Both
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
include continuous internal offset and fullscale calibration
No Latency ∆∑ is a trademark of Linear Technology Corporation. All other trademarks are the algorithms which are transparent to the user, ensuring
property of their respective owners. Protected by U.S. Patents including 6208279, 6411242,
7088280, 7164378. accuracy over time and the operating temperature range.

Typical Application
VREF vs Temperature
2.7V TO 5.5V 1.2520

1.2515
REFERENCE OUTPUT VOLTAGE (V)

0.1µF 0.1µF 0.1µF 10µF

1.2510
0.1µF 1.2505
REFOUT COMP VCC
+ SCK 1.2500
IN
10k 10k SPI
LTC2462 SDO
INTERFACE 1.2495
IN– CS
0.1µF 1.2490
10k R REF– GND
1.2485
24602 TA01a

1.2480
–50 –30 –10 10 30 50 70 90
TEMPERATURE (°C)
24602 TA01b

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LTC2460/LTC2462
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V Storage Temperature Range................... –65°C to 150°C
Analog Input Voltage Operating Temperature Range
(IN+, IN–, IN, REF –, LTC2460C/LTC2462C................................ 0°C to 70°C
COMP, REFOUT)............................–0.3V to (VCC + 0.3V) LTC2460I/LTC2462I..............................–40°C to 85°C
Digital Voltage
(VSDI, VSDO, VSCK, VCS).................–0.3V to (VCC + 0.3V)

Pin Configuration
LTC2462 LTC2462
TOP VIEW
TOP VIEW
REFOUT 1 12 VCC
COMP 2 11 GND REFOUT 1 12 VCC
COMP 2 11 GND
CS 3 10 IN–
CS 3 10 IN–
SDI 4 9 IN+ SDI 4 9 IN+
SCK 5 8 REF– SCK 5 8 REF–
SDO 6 7 GND SDO 6 7 GND

DD PACKAGE MS PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN 12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 43°C/W TJMAX = 125°C, θJA = 120°C/W
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL
LTC2460 LTC2460
TOP VIEW
TOP VIEW
REFOUT 1 12 VCC
COMP 2 11 GND REFOUT 1 12 VCC
COMP 2 11 GND
CS 3 10 GND
CS 3 10 GND
SDI 4 9 IN SDI 4 9 IN
SCK 5 8 REF– SCK 5 8 REF–
SDO 6 7 GND SDO 6 7 GND

DD PACKAGE MS PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN 12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 43°C/W TJMAX = 125°C, θJA = 120°C/W
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL

order information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2460CDD#PBF LTC2460CDD#TRPBF LFDQ 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C
LTC2460IDD#PBF LTC2460IDD#TRPBF LFDQ 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C
LTC2460CMS#PBF LTC2460CMS#TRPBF 2460 12-Lead Plastic MSOP-12 0°C to 70°C
LTC2460IMS#PBF LTC2460IMS#TRPBF 2460 12-Lead Plastic MSOP-12 –40°C to 85°C
LTC2462CDD#PBF LTC2462CDD#TRPBF LDXM 12-Lead Plastic (3mm × 3mm) DFN 0°C to 70°C
LTC2462IDD#PBF LTC2462IDD#TRPBF LDXM 12-Lead Plastic (3mm × 3mm) DFN –40°C to 85°C
LTC2462CMS#PBF LTC2462CMS#TRPBF 2462 12-Lead Plastic MSOP-12 0°C to 70°C
LTC2462IMS#PBF LTC2462IMS#TRPBF 2462 12-Lead Plastic MSOP-12 –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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 LTC2460/LTC2462
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) (Note 3) l 16 Bits
Integral Nonlinearity (Note 4) l 1 10 LSB
Offset Error l 2 15 LSB
Offset Error Drift 0.02 LSB/°C
Gain Error Includes Contributions of ADC and Internal Reference l ±0.01 ±0.25 % of FS
Gain Error Drift Includes Contributions of ADC and Internal Reference
C-Grade l ±2 ±10 ppm/°C
I-Grade l ±5 ppm/°C
Transition Noise 2.2 µVRMS
Power Supply Rejection DC 80 dB

Analog
The Inputs l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN + Positive Input Voltage Range LTC2462 l 0 VREF V
VIN– Negative Input Voltage Range LTC2462 l 0 VREF V
VIN Input Voltage Range LTC2460 l 0 VREF V
VOR +, V + Overrange/Underrange Voltage, IN+ VIN– = 0.625V (See Figure 3) 8 LSB
UR
VOR–, VUR– Overrange/Underrange Voltage, IN– VIN+ = 0.625V (See Figure 3) 8 LSB
CIN IN+, IN–, IN Sampling Capacitance 0.35 pF
IDC_LEAK(IN+, IN–, IN) IN+, IN– DC Leakage Current (LTC2462) VIN = GND (Note 8) l –10 1 10 nA
IN DC Leakage Current (LTC2460) VIN = VCC (Note 8) l –10 1 10 nA
IDC_LEAK(IN–) IN– DC Leakage Current VIN = GND (Note 8) l –10 1 10 nA
VIN = VCC (Note 8) l –10 1 10 nA
ICONV Input Sampling Current (Note 5) 50 nA
VREF Reference Output Voltage l 1.247 1.25 1.253 V
Reference Voltage Coefficient (Note 11)
C-Grade l ±2 ±10 ppm/°C
I-Grade ±5 ppm/°C
Reference Line Regulation 2.7V ≤ VCC ≤ 5.5V –90 dB
Reference Short Circuit Current VCC = 5.5, Forcing Output to GND l 35 mA
COMP Pin Short Circuit Current VCC = 5.5, Forcing Output to GND l 200 µA
Reference Load Regulation 2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing 3.5 mV/mA
Reference Output Noise Density CCOMP= 0.1μF, CREFOUT = 0.1μF, At f = 1kHz 30 nV/√Hz

Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l 2.7 5.5 V
ICC Supply Current
Conversion l 1.5 2.5 mA
Nap l 800 1500 µA
Sleep l 0.2 2 µA

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LTC2460/LTC2462
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the full
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l VCC – 0.3 V
VIL Low Level Input Voltage l 0.3 V
IIN Digital Input Current l –10 10 µA
CIN Digital Input Capacitance 10 pF
VOH High Level Output Voltage IO = –800µA l VCC – 0.5 V
VOL Low Level Output Voltage IO = 1.6mA l 0.4 V
IOZ Hi-Z Output Leakage Current l –10 10 µA

Timing
The Characteristics l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time l 13 16.6 23 ms
fSCK SCK Frequency Range l 2 MHz
tlSCK SCK Low Period l 250 ns
thSCK SCK High Period l 250 ns
t1 CS Falling Edge to SDO Low Z (Notes 7, 8) l 0 100 ns
t2 CS Rising Edge to SDO High Z (Notes 7, 8) l 0 100 ns
t3 CS Falling Edge to SCK Falling Edge l 100 ns
tKQ SCK Falling Edge to SDO Valid (Note 7) l 0 100 ns
t4 SDI Setup Before SCK↑ (Note 3) l 100 ns
t5 SDI Hold After SCK↑ (Note 3) l 100 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: CS = VCC. A positive current is flowing into the DUT pin.
may cause permanent damage to the device. Exposure to any Absolute Note 6: SCK = VCC or GND. SDO is high impedance.
Maximum Rating condition for extended periods may affect device Note 7: See Figure 4.
reliability and lifetime.
Note 8: See Figure 5.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
Note 9: Input sampling current is the average input current drawn from the
unless otherwise specified.
input sampling network while the LTC2460/LTC2462 is actively sampling
VREFCM = VREF/2, FS = VREF the input.
VIN = VIN+ – VIN–, –VREF ≤ VIN ≤ VREF; VINCM = (VIN+ + VIN–)/2. Note 10: A positive current is flowing into the DUT pin.
Note 3. Guaranteed by design, not subject to test. Note 11: Temperature coefficient is calculated by dividing the maximum
Note 4. Integral nonlinearity is defined as the deviation of a code from a change in output voltage by the specified temperature range.
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.

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 LTC2460/LTC2462
Typical Performance Characteristics (TA = 25°C, unless otherwise noted)

Integral Nonlinearity Integral Nonlinearity Maximum INL vs Temperature

3 3 3
VCC = 5.5V VCC = 2.7V VCC = 5.5V, 4.1V, 2.7V
TA = –45°C, 25°C, 90°C TA = –45°C, 25°C, 90°C
2 2 2

1 1 1
INL (LSB)

INL (LSB)

INL (LSB)
0 0 0

–1 –1 –1

–2 –2 –2

–3 –3 –3
–1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25 –55 –35 –15 5 25 45 65 85 105 125
DIFFERENTIAL INPUT VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V) TEMPERATURE (°C)
24602 G01 24602 G02 24602 G03

Offset Error vs Temperature ADC Gain Error vs Temperature Transition Noise vs Temperature
5 25 10
4 9
VCC = 5.5V VCC = 5.5V
3 20 8

TRANSITION NOISE RMS (µV)

ADC GAIN ERROR (LSB)
OFFSET ERROR (LSB)

2 VCC = 4.1V 7
1 15 6
0 VCC = 2.7V 5
–1 10 VCC = 4.1V 4
VCC = 2.7V
–2 3
–3 5 2
VCC = 2.7V VCC = 5.5V
–4 1
–5 0 0
–50 –30 –10 10 30 50 70 90 –50 –25 0 25 50 75 100 –50 –30 –10 10 30 50 70 90
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
24602 G04 24602 G05 24602 G06

Conversion Mode Power Supply Sleep Mode Power Supply

Current vs Temperature Current vs Temperature VREF vs Temperature
2.0 350 1.2508
1.9
300
REFERENCE OUTPUT VOLTAGE (V)

1.2507
1.8
CONVERSION CURRENT (mA)

VCC = 5.5V VCC = 5.5V

250
SLEEP CURRENT (nA)

1.7 VCC = 4.1V 1.2506

1.6
200
1.5 1.2505
150
1.4
VCC = 2.7V VCC = 4.1V 1.2504
1.3 100
1.2
50 1.2503
1.1 VCC = 2.7V

1.0 0 1.2502
–50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
24602 G07 24602 G08 24602 G09

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 LTC2460/LTC2462
Typical Performance Characteristics (TA = 25°C, unless otherwise noted)

Power Supply Rejection

vs Frequency at VCC Conversion Time vs Temperature VREF vs VCC
0 21 1.24892
TA = 25°C

20 1.24891
–20
1.24890

CONVERSION TIME (ms)

19
–40
REJECTION (dB)

VCC = 5V, 4.1V, 3V 1.24889

18

VREF (V)
–60 1.24888
17
1.24887
–80
16
1.24886
–100
15 1.24885

–120 14 1.24884
1 10 100 1k 10k 100k 1M 10M –50 –25 0 25 50 75 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FREQUENCY AT VCC (Hz) TEMPERATURE (°C) VCC (V)
24602 G10 24602 G11 24602 G12

Pin Functions
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V, SDO (Pin 6): Three-State Serial Data Output. SDO is used
this voltage sets the fullscale input range of the ADC. For for serial data output during the DATA INPUT/OUTPUT
noise and reference stability connect to a 0.1µF capacitor state and can be used to monitor the conversion status.
tied to GND. This capacitor value must be less than or
GND (Pins 7, 11): Ground. Connect directly to the ground
equal to the capacitor tied to the reference compensation
plane through a low impedance connection.
pin (COMP). REFOUT cannot be overdriven by an external
reference. For applications that require an input range REF– (Pin 8): Negative Reference Input to the ADC. The
greater than 0V to 1.25V, please refer to the LTC2450/ voltage on this pin sets the zero input to the ADC. This
LTC2452. pin should tie directly to ground or the ground sense of
the input sensor.
COMP (Pin 2): Internal Reference Compensation Pin. For
low noise and reference stability, tie a 0.1μF capacitor to IN+ (LTC2462), IN (LTC2460) (Pin 9): Positive input volt-
GND. age for the LTC2462 differential device. ADC input for the
LTC2460 single-ended device.
CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW
on this pin enables the SDO output. A HIGH on this pin IN– (LTC2462), GND (LTC2460) (Pin 10): Negative input
places the SDO output pin in a high impedance state and voltage for the LTC2462 differential device. GND for the
any inputs on SDI and SCK will be ignored. LTC2460 single-ended device.
SDI (Pin 4): Serial Data Input Pin. This pin is used to pro- VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
gram the sleep mode and 30Hz/60Hz output rate (LTC2460). a 10μF capacitor in parallel with a low-series-inductance
0.1μF capacitor located as close to the device as possible.
SCK (Pin 5): Serial Clock Input. SCK synchronizes the
serial data input/output. Once the conversion is complete, Exposed Pad (Pin 13 – DFN Package): Ground. Connect
a new data bit is produced at the SDO pin following each directly to the ground plane through a low impedance
SCK falling edge. Data is shifted into the SDI pin on each connection.
rising edge of SCK.

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 LTC2460/LTC2462
Block Diagram
1 2 12
REFOUT COMP VCC

3
CS
INTERNAL 5
∆Σ A/D REFERENCE SPI SCK
9
IN+ CONVERTER INTERFACE 6
(IN) SDO
DECIMATING 4
– SINC FILTER SDI

∆Σ A/D
10
IN– CONVERTER
(GND) INTERNAL
OSCILLATOR

REF– 7,11,13 (DD PACKAGE) GND

8
24602 BD

( ) PARENTHESIS INDICATE LTC2460

Figure 1. Functional Block Diagram

Applications Information
POWER-ON RESET
Converter Operation
CONVERT
Converter Operation Cycle
The LTC2460/LTC2462 are low power, delta sigma, ana-
SLEEP/NAP
log to digital converters with a simple SPI interface (see
Figure 1). The LTC2462 has a fully differential input while
the LTC2460 is single-ended. Both are pin and software
compatible. Their operation is composed of three distinct NO
CS = LOW?
states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT.
The operation begins with the CONVERT state (see Fig-
ure 2). Once the conversion is finished, the converter YES

automatically powers down (NAP) or under user control,

both the converter and reference are powered down DATA INPUT/OUTPUT

(SLEEP). The conversion result is held in a static register

while the device is in this state. The cycle concludes with
the DATA INPUT/OUTPUT state. Once all 16-bits are read NO
16TH FALLING
EDGE OF SCK YES
or an abort is initiated the device begins a new conversion. OR 24602 F02
CS = HIGH?
The CONVERT state duration is determined by the LTC2460/
LTC2462 conversion time (nominally 16.6 milliseconds).
Figure 2. LTC2460/LTC2462 State Transition Diagram
Once started, this operation can not be aborted except by a
low power supply condition (VCC < 2.1V) which generates While in the SLEEP/NAP state, when chip select input is
an internal power-on reset signal. HIGH (CS = HIGH), the LTC2460/LTC2462’s converters
After the completion of a conversion, the LTC2460/LTC2462 are powered down. This reduces the supply current by
enters the SLEEP/NAP state and remains there until the approximately 50%. While in the Nap state the reference
chip select is LOW (CS = LOW). Following this condition, remains powered up. In order to power down the reference
the ADC transitions into the DATA INPUT/OUTPUT state. in addition to the converter, the user can select the SLEEP
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LTC2460/LTC2462
applications information
mode during the DATA INPUT/OUTPUT state. Once the cycle. If SLP = 1, the reference powers down following
next conversion is complete, the SLEEP state is entered the next conversion cycle. The remaining 12 SDI input
and power is reduced to less than 2μA. The reference is bits are ignored (don’t care).
powered up once CS is brought low. The reference startup SDI may also be tied directly to GND or VDD in order to
time is 12ms (if the reference and compensation capacitor simplify the user interface. In the case of the LTC2460,
values are both 0.1μF). the 60Hz output rate is selected if SDI is tied low and
Upon entering the DATA INPUT/OUTPUT state, SDO outputs the 30Hz output rate is selected if SDI is tied to VDD. The
the sign (D15) of the conversion result. During this state, LTC2462 output rate is always 60Hz independent of SDI
the ADC shifts the conversion result serially through the or SPD. The reference sleep mode is disabled for both
SDO output pin under the control of the SCK input pin. the LTC2460 and LTC2462 if SDI is tied to GND or VDD.
There is no latency in generating this data and the result The DATA INPUT/OUTPUT state concludes in one of two
corresponds to the last completed conversion. A new bit different ways. First, the DATA INPUT/OUTPUT state opera-
of data appears at the SDO pin following each falling edge tion is completed once all 16 data bits have been shifted
detected at the SCK input pin and appears from MSB to out and the clock then goes low. This corresponds to the
LSB. The user can reliably latch this data on every rising 16th falling edge of SCK. Second, the DATA INPUT/OUT-
edge of the external serial clock signal driving the SCK pin. PUT state can be aborted at any time by a LOW-to-HIGH
During the DATA INPUT/OUTPUT state, the LTC2460/ transition on the CS input. Following either one of these
LTC2462 can be programmed to SLEEP or NAP (default) two actions, the LTC2460/LTC2462 will enter the CONVERT
following the next conversion cycle. Data is shifted into the state and initiate a new conversion cycle.
device through the SDI pin on the rising edge of SCK. The
input word is 4 bits. If the first bit EN1 = 1 and the second Power-Up Sequence
bit EN2 = 0 the device is enabled for programming. The When the power supply voltage (VCC) applied to the con-
following two bits (SPD and SLP) will be written into the verter is below approximately 2.1V, the ADC performs a
device. SPD (only used for the LTC2460) to select the 60Hz power-on reset. This feature guarantees the integrity of
output rate, no offset calibration mode (SPD = 0, default). the conversion result.
Set SPD = 1 for 30Hz mode with offset calibration. SPD
is ignored for the LTC2462. The next bit (SLP) enables When VCC rises above this critical threshold, the converter
the sleep or nap mode. If SLP = 0 (default) the reference generates an internal power-on reset (POR) signal for
remains powered up at the end of the next conversion approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2460/LTC2462
20 start a conversion cycle and follow the succession of states
16 shown in Figure 2. The reference startup time following a
12 POR is 12ms (CCOMP = CREFOUT = 0.1μF). The first conver-
8
sion following powerup will be invalid since the reference
OUTPUT CODE

4
voltage has not completely settled. The first conversion
0
following power up can be discarded using the data abort
–4
SIGNALS
command or simply read and ignored. The following con-
–8
BELOW versions are accurate to the device specifications.
–12 GND
–16
Ease of Use
–20
–0.001 –0.005 0 0.005 0.001 0.0015
VIN+/VREF+
The LTC2460/LTC2462 data output has no latency, filter
24602 F03
settling delay or redundant results associated with the
Figure 3. Output Code vs VIN+ with VIN– = 0 (LTC2462) conversion cycle. There is a one-to-one correspondence
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 LTC2460/LTC2462
Applications Information
between the conversion and the output data. Therefore, Input Voltage Range (LTC2462)
multiplexing multiple analog input voltages requires no
As mentioned in the Output Data Format section, the output
special actions.
code is given as 32768 • (VIN+ – VIN–)/VREF + 32768. For
The LTC2460/LTC2462 perform offset calibrations every (VIN+ – VIN–) ≥ VREF, the output code is clamped at 65535
conversion. This calibration is transparent to the user and (all ones). For (VIN+ – VIN–) ≤ –VREF, the output code is
has no effect upon the cyclic operation described previously. clamped at 0 (all zeroes).
The advantage of continuous calibration is stability of the
The LTC2462 includes a proprietary architecture that
ADC performance with respect to time and temperature.
can, typically, digitize each input up to 8 LSBs above VREF
The LTC2460/LTC2462 include a proprietary input sampling and below GND, if the differential input is within ±VREF.
scheme that reduces the average input current by several As an example (Figure 3), if the user desires to measure
orders of magnitude when compared to traditional delta- a signal slightly below ground, the user could set VIN–
sigma architectures. This allows external filter networks = GND, and VREF = 1.25V. If VIN+ = GND, the output code
to interface directly to the LTC2460/LTC2462. Since the would be approximately 32768. If VIN+ = GND – 8LSB =
average input sampling current is 50nA, an external RC –0.305mV, the output code would be approximately 32760.
lowpass filter using 1kΩ and 0.1µF results in <1LSB For applications that require an input range greater than
additional error. Additionally, there is negligible leakage ±1.25V, please refer to the LTC2452.
current between IN+ and IN–.
Output Data Format
Input Voltage Range (LTC2460) The LTC2460/LTC2462 generates a 16-bit direct binary
Ignoring offset and full-scale errors, the LTC2460 will encoded result. It is provided as a 16-bit serial stream
theoretically output an “all zero” digital result when the through the SDO output pin under the control of the SCK
input is at ground (a zero scale input) and an “all one” input pin (see Figure 4).
digital result when the input is at VREF (VREFOUT = 1.25V). The LTC2462 (differential input) output code is given by
In an under-range condition, for all input voltages below 32768 • (VIN+ – VIN–)/VREF + 32768. The first bit output
zero scale, the converter will generate the output code 0. In by the LTC2462, D15, is the MSB, which is 1 for VIN+ ≥
an over-range condition, for all input voltages greater than VIN– and 0 for VIN+ < VIN–. This bit is followed by succes-
VREF, the converter will generate the output code 65535. sively less significant bits (D14, D13, …) until the LSB is
For applications that require an input range greater than output by the LTC2462, see Table 1.
0V to 1.25V, please refer to the LTC2450.

t3
t1 t2

CS

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SDO MSB LSB

SCK

tKQ tlSCK thSCK

EN1 EN2 SPD* SLP

SDI DON’T CARE

24602 F04
t5
t6 *SPD IS A DON’T CARE BIT FOR THE LTC2462

Figure 4. Data Input/Output Timing

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LTC2460/LTC2462
applications information
Table 1. LTC2460/LTC2462 Output Data Format
SINGLE ENDED INPUT VIN DIFFERENTIAL INPUT VOLTAGE D15 D14 D13 D12...D2 D1 D0 CORRESPONDING
(LTC2460) VIN+ – VIN– (LTC2462) (MSB) (LSB) DECIMAL VALUE
≥VREF ≥VREF 1 1 1 1 1 1 65535
VREF – 1LSB VREF – 1LSB 1 1 1 1 1 0 65534
0.75 • VREF 0.5 • VREF 1 1 0 0 0 0 49152
0.75 • VREF – 1LSB 0.5 • VREF – 1LSB 1 0 1 1 1 1 49151
0.5 • VREF 0 1 0 0 0 0 0 32768
0.5 • VREF – 1LSB –1LSB 0 1 1 1 1 1 32767
0.25 • VREF –0.5 • VREF 0 1 0 0 0 0 16384
0.25 • VREF – 1LSB –0.5 • VREF – 1LSB 0 0 1 1 1 1 16383
0 ≤ –VREF 0 0 0 0 0 0 0

The LTC2460 (single-ended input) output code is a direct the next conversion is complete. It will remain powered
binary encoded result, see Table 1. down until CS is pulled low. The reference startup time
During the data output operation the CS input pin must is approximately 12ms. In order to ensure a stable refer-
be pulled low (CS = LOW). The data output process starts ence for the following conversions, either the data input/
with the most significant bit of the result being present at output time should be delayed 12ms after CS goes low or
the SDO output pin (SDO = D15) once CS goes low. A new the first conversion following a reference start up should
data bit appears at the SDO output pin after each falling be discarded. If SDI is tied HIGH (LTC2460 operating in
edge detected at the SCK input pin. The output data can 30Hz mode) the SLP mode is disabled.
be reliably latched on the rising edge of SCK.
Conversion Status Monitor
Data Input Format For certain applications, the user may wish to monitor the
The data input word is 4 bits long and consists of two en- LTC2460/LTC2462 conversion status. This can be achieved
able bits (EN1 and EN2) and two programming bits (SPD by holding SCK HIGH during the conversion cycle. In
and SLP). EN1 is applied to the first rising edge of SCK this condition, whenever the CS input pin is pulled low
after the conversion is complete. Programming is enabled (CS = LOW), the SDO output pin will provide an indication
by setting EN1 = 1 and EN2 = 0. of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
The speed bit (SPD) is only used by the LTC2460. In the indication of a completed conversion cycle. An example
default mode, SPD = 0, the output rate is 60Hz and con- of such a sequence is shown in Figure 5.
tinuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration is Conversion status monitoring, while possible, is not re-
performed and the output rate is reduced to 30Hz. Alterna- quired for the LTC2460/LTC2462 as its conversion time is
tively, SDI can be tied directly to ground (SPD = 0) or VCC fixed and typically 16.6ms (23ms maximum). Therefore,
(SPD = 1), eliminating the need to program the device. The external timing can be used to determine the completion of a
LTC2462 data output rate is always 60Hz and background conversion cycle.
offset calibration is performed (SPD = don’t care).
Serial Interface
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains The LTC2460/LTC2462 transmit the conversion result and
powered up even when the ADC is powered down. If the receive the start of conversion command through a syn-
SLP bit is set HIGH, the reference will power down after chronous 2-, 3- or 4-wire interface. This interface can be
24602fa

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 LTC2460/LTC2462
Applications Information
t1 t2

CS

SDO

SDI = LOW

SCK = HIGH CONVERT NAP

24602 F05

Figure 5. Conversion Status Monitoring Mode

used during the CONVERT and SLEEP states to assess the 4) When SCK = HIGH, it is possible to monitor the conver-
conversion status and during the DATA OUTPUT state to sion status by pulling CS low and watching for SDO to
read the conversion result, and to trigger a new conversion. go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Serial Interface Operation Modes
The modes of operation can be summarized as follows: Serial Clock Idle-High (CPOL = 1) Examples

1) The LTC2460/LTC2462 function with SCK idle high In Figure 6, following a conversion cycle the LTC2460/
(commonly known as CPOL = 1) or idle low (commonly LTC2462 automatically enter the NAP mode with the ADC
known as CPOL = 0). powered down. The ADC’s reference will power down if the
SLP bit was set high prior to the just completed conversion
2) After the 16th bit is read, a new conversion is started and CS is HIGH. Once CS goes low, the device powers up.
if CS is pulled high or SCK is pulled low. The user can monitor the conversion status at convenient
3) At any time during the Data Output state, pulling CS intervals using CS and SDO.
high causes the part to leave the I/O state, abort the Pulling CS LOW while SCK is HIGH tests whether
output and begin a new conversion. or not the chip is in the CONVERT state. While in
the CONVERT state, SDO is HIGH while CS is LOW.
Once the conversion is complete, SDO is LOW

CS

D15 D14 D13 D12 D2 D1 D0

SD0

SCK

clk1 clk2 clk3 clk4 clk15 clk16

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F06

Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.

The Rising Edge of CS Starts a New Conversion
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11
LTC2460/LTC2462
Applications Information
while CS is LOW. These tests are not required op- The timing diagram in Figure 9 is identical to that of Figure  8,
erational steps but may be useful for some applications. except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
When the data is available, the user applies 16 clock cycles
and the CS signal is subsequently pulled high.
to transfer the result. The CS rising edge is then used to
initiate a new conversion. Examples of Aborting Cycle using CS
The operation example of Figure 7 is identical to that of For some applications, the user may wish to abort the I/O
Figure 6, except the new conversion cycle is triggered by cycle and begin a new conversion. If the LTC2460/LTC2462
the falling edge of the serial clock (SCK). are in the data output state, a CS rising edge clears the
remaining data bits from the output register, aborts the out-
Serial Clock Idle-Low (CPOL = 0) Examples
put cycle and triggers a new conversion. Figure 10 shows
In Figure 8, following a conversion cycle the LTC2460/ an example of aborting an I/O with idle-high (CPOL = 1)
LTC2462 automatically enters the NAP state. The device and Figure 11 shows an example of aborting an I/O with
reference will power down if the SLP bit was set high idle-low (CPOL = 0).
prior to the just completed conversion and CS is HIGH.
A new conversion cycle can be triggered using the CS
Once CS goes low, the reference powers up. The user
signal without having to generate any serial clock pulses
determines data availability (and the end of conversion)
as shown in Figure 12. If SCK is maintained at a low logic
based upon external timing. The user then pulls CS low
level, after the end of a conversion cycle, a new conver-
(CS = ↓) and uses 16 clock cycles to transfer the result.
sion operation can be triggered by pulling CS low and
Following the 16th rising edge of the clock, CS is pulled high
then high. When CS is pulled low (CS = LOW), SDO will
(CS = ↑), which triggers a new conversion.

CS

D15 D14 D13 D12 D2 D1 D0

SD0

SCK

clk1 clk2 clk3 clk4 clk15 clk16 clk17

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F07

Figure 7. Idle-High (CPOL = 1) Clock Operation Example.

A 17th Clock Pulse is Used to Trigger a New Conversion Cycle

CS

D15 D14 D13 D12 D2 D1 D0

SD0

SCK

clk1 clk2 clk3 clk4 clk14 clk15 clk16

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F08

Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion

24602fa

12
 LTC2460/LTC2462
applications information
CS

D15 D14 D13 D12 D2 D1 D0

SD0

SCK

clk1 clk2 clk3 clk4 clk14 clk15 clk16

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F09

Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion

CS

D15 D14 D13

SD0

SCK

clk1 clk2 clk3 clk4

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F10

Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example

CS

D15 D14 D13

SD0

SCK

clk1 clk2 clk3

EN1 EN2 SPD SLP

SDI

CONVERT NAP DATA OUTPUT CONVERT

24602 F11

Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example

CS

D15
SD0

SDI = DON’T CARE

SCK = LOW

CONVERT NAP DATA OUTPUT CONVERT

24602 F12

Figure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
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13
LTC2460/LTC2462
applications information
output the sign (D15) of the result of the just completed Figure 13 shows a 2-wire operation sequence which uses
conversion. While a low logic level is maintained at SCK an idle-high (CPOL = 1) serial clock signal. The conversion
pin and CS is subsequently pulled high (CS = HIGH) the status can be monitored at the SDO output. Following a
remaining 15 bits of the result (D14:D0) are discarded conversion cycle, the ADC enters the data output state
and a new conversion cycle starts. and the SDO output transitions from HIGH to LOW. Sub-
Following the aborted I/O, additional clock pulses in the sequently 16 clock pulses are applied to the SCK input in
CONVERT state are acceptable, but excessive signal tran- order to serially shift the 16 bit result. Finally, the 17th
sitions on SCK can potentially create noise on the ADC clock pulse is applied to the SCK input in order to trigger
during the conversion, and thus may negatively influence a new conversion cycle.
the conversion accuracy. Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
2-Wire Operation status cannot be monitored at the SDO output. Following
The 2-wire operation modes, while reducing the number of a conversion cycle, the LTC2460/LTC2462 enters the DATA
required control signals, should be used only if the LTC2460/ OUTPUT state. At this moment the SDO pin outputs the
LTC2462 low power sleep capability is not required. In ad- sign (D15) of the conversion result. The user must use
dition the option to abort serial data transfers is no longer external timing in order to determine the end of conversion
available. Hardwire CS to GND for 2-wire operation. For and result availability. Subsequently 16 clock pulses are
the LTC2460, tie SDI LOW for 60Hz output rate and HIGH applied to SCK in order to serially shift the 16-bit result.
for 30Hz output rate, for the LTC2462 tie SDI low. The 16th clock falling edge triggers a new conversion
cycle. For the LTC2460 tie SDI LOW for 60Hz output rate
and HIGH for 30Hz output rate.

CS = LOW

SD0 D15 D14 D13 D12 D2 D1 D0

SCK

clk1 clk2 clk3 clk4 clk15 clk16 clk17

CONVERT DATA OUTPUT CONVERT

SDI = 0 OR 1 24602 F13

Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example

CS = LOW

SD0 D15 D14 D13 D12 D2 D1 D0

SCK
clk1 clk2 clk3 clk4 clk14 clk15 clk16
CONVERT DATA OUTPUT CONVERT

SDI = 0 OR 1 24602 F14

Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example

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14
 LTC2460/LTC2462
Applications Information
PRESERVING THE CONVERTER ACCURACY through these two decoupling capacitors, and returning
The LTC2460/LTC2462 are designed to minimize the conver- to the converter GND pin. The area encompassed by this
sion result’s sensitivity to device decoupling, PCB layout, circuit path, as well as the path length, should be minimized.
antialiasing circuits, line and frequency perturbations. As shown in Figure 15, REF– is used as the negative refer-
Nevertheless, in order to preserve the high accuracy capa- ence voltage input to the ADC. This pin can be tied directly
bility of this part, some simple precautions are desirable. to ground or kelvined to sensor ground. In the case where
REF– is used as a sense input, it should be bypassed to
Digital Signal Levels ground with a 0.1μF ceramic capacitor in parallel with a
Due to the nature of CMOS logic, it is advisable to keep input 10μF low ESR ceramic capacitor.
digital signals near GND or VCC. Voltages in the range of Very low impedance ground and power planes, and star
0.5V to VCC – 0.5V may result in additional current leakage connections at both VCC and GND pins, are preferable. The
from the part. Undershoot and overshoot should also be VCC pin should have two distinct connections: the first to
minimized, particularly while the chip is converting. It is the decoupling capacitors described above, and the second
thus beneficial to keep edge rates of about 10ns and limit to the ground return for the power supply voltage source.
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output REFOUT and COMP
under 2-wire operation. In particular, it is possible to get The on chip 1.25V reference is internally tied to the con-
the LTC2460/LTC2462 into an unknown state if an SCK verter’s reference input and is output to the REFOUT pin.
pulse is missed or noise triggers an extra SCK pulse. A 0.1μF capacitor should be placed on the REFOUT pin.
In this situation, it is impossible to distinguish SDO = 1 It is possible to reduce this capacitor, but the transition
(indicating conversion in progress) from valid “1” data
bits. As such, CPOL = 1 is recommended for the 2-wire INTERNAL
VCC
mode. The user should look for SDO = 0 before reading REFERENCE RSW
15k
data, and look for SDO = 1 after reading data. If SDO does ILEAK
(TYP)
not return a “0” within the maximum conversion time (or REFOUT
ILEAK
return a “1” after a full data read), generate 16 SCK pulses
to force a new conversion.
VCC
RSW
15k
Driving VCC and GND ILEAK
(TYP)
IN+
In relation to the VCC and GND pins, the LTC2460/LTC2462 ILEAK
combines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity VCC
RSW
CEQ
0.35pF
to PCB layout and external components. Nevertheless, ILEAK 15k (TYP)
(TYP)
the very high accuracy of this converter is best pre- IN–
served by careful low and high frequency power supply ILEAK
decoupling.
VCC
A 0.1µF, high quality, ceramic capacitor in parallel with RSW
15k
ILEAK
a 10µF low ESR ceramic capacitor should be connected (TYP)
REF–
24602 F15

between the VCC and GND pins, as close as possible to the

ILEAK
package. The 0.1µF capacitor should be placed closest to
the ADC package. It is also desirable to avoid any via in the
circuit path, starting from the converter VCC pin, passing Figure 15. LTC2460/LTC2462 Analog Input/Reference
Equivalent Circuit
24602fa

15
LTC2460/LTC2462
applications information
noise increases. A 0.1μF capacitor should also be placed layout, CPAR has typical values between 2pF and 15pF. In
on the COMP pin. This pin is tied to an internal point in the addition, the equivalent circuit of Figure 16 includes the
reference and is used for stability. In order for the refer- converter equivalent internal resistor RSW and sampling
ence to remain stable the capacitor placed on the COMP capacitor CEQ.
pin must be greater than or equal to the capacitor tied to VCC
the REFOUT pin. The REFOUT pin cannot be overridden IN
(LTC2460)
RSW
15k
ILEAK
by an external voltage. If a reference voltage greater than RS
IN+
(TYP)

1.25V is required, the LTC2450/LTC2452 should be used. + CIN

(LTC2462)
ILEAK
CEQ
SIG+ ICONV
– 0.35pF
Depending on the size of the capacitors tied to the REFOUT CPAR
(TYP)
and COMP pins, the internal reference has a correspond- VCC
ing start up time. This start up time is typically 12ms ILEAK
RSW
15k
when 0.1μF capacitors are used. At initial power up, the RS
IN– (TYP)
(LTC2462)
first conversion result can be aborted or ignored. At the SIG– + CIN ILEAK
CEQ ICONV
–
completion of this first conversion, the reference has CPAR 0.35pF
(TYP)
settled and all subsequent conversions are valid. 24602 F16

If the reference is put to sleep (program SLP = 1 and Figure 16. LTC2460/LTC2462 Input Drive Equivalent Circuit
CS = 1) the reference is powered down after the next
conversion. This conversion result is valid. On CS falling There are some immediate trade-offs in RS and CIN without
edge, the reference is powered up. In order to ensure the needing a full circuit analysis. Increasing RS and CIN can
reference output has settled before the next conversion, give the following benefits:
the power up time can be extended by delaying the data 1) Due to the LTC2460/LTC2462’s input sampling algorithm,
read 12ms after the falling edge of CS. Once all 16 bits the input current drawn by either VIN+ or VIN– over a
are read from the device or CS is brought HIGH, the next conversion cycle is typically 50nA. A high RS • CIN at-
conversion automatically begins. In the default operation, tenuates the high frequency components of the input
the reference remains powered up at the conclusion of the current, and RS values up to 1k result in <1LSB error.
conversion cycle.
2) The bandwidth from VSIG is reduced at the input pins
Driving VIN+ and VIN– (IN+, IN– or IN). This bandwidth reduction isolates the
The input drive requirements can best be analyzed using ADC from high frequency signals, and as such provides
the equivalent circuit of Figure 16. The input signal VSIG is simple antialiasing and input noise reduction.
connected to the ADC input pins (IN+ and IN–) through an 3) Switching transients generated by the ADC are attenu-
equivalent source resistance RS. This resistor includes both ated before they go back to the signal source.
the actual generator source resistance and any additional
optional resistors connected to the input pins. Optional 4) A large CIN gives a better AC ground at the input pins,
input capacitors CIN are also connected to the ADC input helping reduce reflections back to the signal source.
pins. This capacitor is placed in parallel with the ADC 5) Increasing RS protects the ADC by limiting the current
input parasitic capacitance CPAR. Depending on the PCB during an outside-the-rails fault condition.

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16
 LTC2460/LTC2462
Applications Information
There is a limit to how large RS • CIN should be for a given through low value sense resistors, temperature measure-
application. Increasing RS beyond a given point increases ments, low impedance voltage source monitoring, and so
the voltage drop across RS due to the input current, on. The resultant INL vs VIN is shown in Figure 18. The
to the point that significant measurement errors exist. measurements of Figure 18 include a capacitor CPAR cor-
Additionally, for some applications, increasing the RS • CIN responding to a minimum sized layout pad and a minimum
product too much may unacceptably attenuate the signal width input trace of about 1 inch length.
at frequencies of interest.
Signal Bandwidth, Transition Noise and Noise
For most applications, it is desirable to implement CIN as
Equivalent Input Bandwidth
a high-quality 0.1µF ceramic capacitor and RS ≤ 1k. This
capacitor should be located as close as possible to the The LTC2460/LTC2462 include a sinc1 type digital filter
actual VIN package pin. Furthermore, the area encompassed with the first notch located at f0 = 60Hz. As such, the
by this circuit path, as well as the path length, should be 3dB input signal bandwidth is 26.54Hz. The calculated
minimized. LTC2460/LTC2462 input signal attenuation vs frequency
over a wide frequency range is shown in Figure 19. The
In the case of a 2-wire sensor that is not remotely
calculated LTC2460/LTC2462 input signal attenuation vs
grounded, it is desirable to split RS and place series
frequency at low frequencies is shown in Figure 20. The
resistors in the ADC input line as well as in the sensor
converter noise level is about 2.2µVRMS and can be mod-
ground return line, which should be tied to the ADC GND eled by a white noise source connected at the input of a
pin using a star connection topology. noise-free converter.
Figure 17 shows the measured LTC2462 INL vs Input On a related note, the LTC2462 uses two separate A/D
Voltage as a function of RS value with an input capacitor converters to digitize the positive and negative inputs. Each
CIN = 0.1µF.
of these A/D converters has 2.2µVRMS transition noise.
In some cases, RS can be increased above these guidelines. If one of the input voltages is within this small transition
The input current is zero when the ADC is either in sleep noise band, then the output will fluctuate one bit, regard-
or I/O modes. Thus, if the time constant of the input RC less of the value of the other input voltage. If both of the
circuit t = RS • CIN, is of the same order of magnitude or input voltages are within their transition noise bands, the
longer than the time periods between actual conversions, output can fluctuate 2 bits.
then one can consider the input current to be reduced
For a simple system noise analysis, the VIN drive circuit can
correspondingly. be modeled as a single-pole equivalent circuit character-
These considerations need to be balanced out by the input ized by a pole location fi and a noise spectral density ni.
signal bandwidth. The 3dB bandwidth ≈ 1/(2pRSCIN). If the converter has an unlimited bandwidth, or at least a
Finally, if the recommended choice for CIN is unacceptable bandwidth substantially larger than fi, then the total noise
contribution of the external drive circuit would be:
for the user’s specific application, an alternate strategy is to
eliminate CIN and minimize CPAR and RS. In practical terms, Vn = n i p / 2 • f i
this configuration corresponds to a low impedance sensor
directly connected to the ADC through minimum length Then, the total system noise level can be estimated as
traces. Actual applications include current measurements the square root of the sum of (Vn2) and the square of the
LTC2460/LTC2462 noise floor (~2.2µV2).

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17
LTC2460/LTC2462
applications information
3 3
CIN = 0.1µF CIN = 0
VCC = 5V VCC = 5V
2 TA = 25°C 2 TA = 25°C
RS = 10k RS = 10k
1 RS = 1k 1
RS = 0k
INL (LSB)

INL (LSB)
0 0
RS = 0k RS = 1k
–1 –1

–2 –2

–3 –3
–1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25
DIFFERENTIAL INPUT VOLTAGE (V) DIFFERENTIAL INPUT VOLTAGE (V)
24602 F17 24602 F18

Figure 17. Measured INL vs Input Voltage Figure 18. Measured INL vs Input Voltage

0 0
–5
INPUT SIGNAL ATTENUATIOIN (dB)
INPUT SIGNAL ATTENUATION (dB)

–20 –10
–15
–40 –20
–25
–60 –30
–35
–80 –40
–45
–100 –50
0 2.5 5.0 7.5 1.00 1.25 1.50 0 60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (MHz) INPUT SIGNAL FREQUENCY (Hz)
24602 F19 24602 F20

Figure 19. LTC2462 Input Signal Attentuation vs Frequency Figure 20. LTC2462 Input Signal Attenuation
vs Frequency (Low Frequencies)

24602fa

18
 LTC2460/LTC2462
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package
12-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)

0.70 ±0.05

3.50 ±0.05 2.38 ±0.05

2.10 ±0.05 1.65 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05
0.45 BSC
2.25 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.115 0.40 ± 0.10
TYP
7 12

2.38 ±0.10
3.00 ±0.10
(4 SIDES) 1.65 ± 0.10
PIN 1 PIN 1 NOTCH
TOP MARK R = 0.20 OR
(SEE NOTE 6) 0.25 × 45°
CHAMFER
6 1
0.200 REF 0.75 ±0.05 0.23 ± 0.05
0.45 BSC
2.25 REF (DD12) DFN 0106 REV A

0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

24602fa

19
LTC2460/LTC2462
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS Package
MS Package
12-Lead Plastic MSOP
12-Lead
(Reference Plastic
LTC DWG MSOP Rev Ø)
# 05-08-1668
(Reference LTC DWG # 05-08-1668 Rev Ø)

0.889 ± 0.127
(.035 ± .005)

5.23
(.206) 3.20 – 3.45
MIN (.126 – .136)

4.039 ± 0.102
0.42 ± 0.038 0.65 (.159 ± .004)
(.0165 ± .0015) (.0256) (NOTE 3) 0.406 ± 0.076
TYP BSC
12 11 10 9 8 7 (.016 ± .003)
RECOMMENDED SOLDER PAD LAYOUT REF

DETAIL “A” 3.00 ± 0.102

0.254 4.90 ± 0.152
(.118 ± .004)
(.010) (.193 ± .006) (NOTE 4)
0° – 6° TYP
GAUGE PLANE

0.53 ± 0.152
1 2 3 4 5 6
(.021 ± .006) 1.10 0.86
(.043) (.034)
DETAIL “A”
MAX REF
0.18 SEATING
(.007) PLANE

0.22 – 0.38 0.1016 ± 0.0508

(.009 – .015) (.004 ± .002)
TYP 0.650
NOTE: (.0256)
MSOP (MS12) 1107 REV Ø

1. DIMENSIONS IN MILLIMETER/(INCH) BSC

2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

24602fa

20
 LTC2460/LTC2462
Revision History
REV DATE DESCRIPTION PAGE NUMBER
A 09/11 Updated Offset Error Maximum in the Electrical Characteristics table. 3

24602fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 21
LTC2460/LTC2462
Typical Application
10µF

VCC V+
0.1µF VCC 0.1µF 1µF 1 10V
CS SCK SDO 2
5V µC
1 12 U1*
6
1k REFOUT VCC 3 CS
10 CS 4
IN+ IN+ 5 SCK/SCL
SCK 7
LTC2462 MOSI/SDA
1k 0.1µF 6 5
SDO MISO/SDO
IN– IN– 4
9 SDI GND GND GND
0.1µF 0.1µF COMP REF– GND
3 8 13
2 8 7, 11
0.1µF
24602 TA02

Related Parts
PART NUMBER DESCRIPTION COMMENTS
LTC1860/LTC1861 12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages
LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages
LTC2360 12-Bit, 100ksps SAR ADC 3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages
LTC2440 24-Bit No Latency DS™ ADC 200nVRMS Noise, 4kHz Output Rate, 15ppm INL
LTC2480 16-Bit, Differential Input, No Latency DS ADC, with PGA, Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Temp. Sensor, SPI Tiny 10-Lead DFN Package
LTC2481 16-Bit, Differential Input, No Latency DS ADC, with PGA, Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Temp. Sensor, I2C Tiny 10-Lead DFN Package
LTC2482 16-Bit, Differential Input, No Latency DS ADC, SPI Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2483 16-Bit, Differential Input, No Latency DS ADC, I2C Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Tiny 10-Lead DFN Package
LTC2484 24-Bit, Differential Input, No Latency DS ADC, SPI with Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Temp. Sensor Tiny 10-Lead DFN Package
LTC2485 24-Bit, Differential Input, No Latency DS ADC, I2C with Easy-Drive Input Current Cancellation, 600nVRMS Noise,
Temp. Sensor Tiny 10-Lead DFN Package
LTC6241 Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp 550nVP-P Noise, 125µV Offset Max
LTC2450 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input 2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,
Range 30Hz Output Rate
LTC2450-1 Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V Input 2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,
Range 60Hz Output Rate
LTC2451 Easy-to-Use, Ultra-Tiny 16-Bit ADC, I2C, 0V to 5.5V Input 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Range Package, Programmable 30Hz/60Hz Output Rates
LTC2452 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI, ±5.5V 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Input Range Package
LTC2453 Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I2C, ±5.5V 2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT
Input Range Package

24602fa

22 Linear Technology Corporation

LT 0911 REV A • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com  LINEAR TECHNOLOGY CORPORATION 2009