DECADE OF

EXCELLENCE
IN
VLSI TRAINING

HANDS-ON LEARNING WITH INDUSTRY STANDARD EDA TOOLS

BLENDED LEARNING VLSI PROGRAM

MAVEN SILICON
Evolved in VLSI Technologies, Maven Silicon is a VLSI Training company that offers a wide range of corporate and professional training services. Maven Silicon is
the only training company in India that offers SystemVerilog and UVM based advanced verification courses and holds the credit of training 500+ engineers per
year. With shrinking process technologies, ever-growing design sizes, and increasing integration of IP to a single chip, verification has become an extremely
complex and critical part of any SoC design today. As chip verification consumes 60% of the design cycle, most of the VLSI companies hire fresh VLSI engineers
who have extensively been trained on ASIC verification methodologies and technologies and have dedicated themselves only to chip verification.

Usually, 70% of the engineers in any product or services company dedicated only to functional verification, and the remaining 30% of the engineers work on
RTL design, STA and Analog, etc. So there are plenty of job opportunities for fresh VLSI engineers who are highly skilled in ASIC verification. We at Maven Silicon
have designed the courses keeping this fact in our mind. You can leverage our expertise and be a part of a world-class training infrastructure to learn the VLSI
technologies and then get a job into the best semiconductor companies.

Our CEO, Sivakumar P R, has 22+ years of experience in the engineering and semiconductor industries. He has worked as a Verification Consultant in the top
EDA companies like Synopsys, Cadence, and Mentor Graphics. During this tenure, he worked very closely with various ASIC and FPGA design houses and helped
them to use the EDA solutions effectively for the successful tape-outs of multi-million gate designs.

To know more about our CEO, visit https://www.linkedin.com/in/sivapr/

FIVE REASONS TO MUSE ON MAVEN SILICON INCLUDES,

1. SystemVerilog and UVM based Advanced Verification
Maven Silicon, as the training centre, edifies engineers on the advanced ASIC Verification methodologies and SystemVerilog. In addition to these advanced
technologies, we also impart the basic VLSI technologies like Advanced Digital Design Methodology, Verilog, ASIC & FPGA's design flow, STA & CMOS
fundamentals.

2. Course Delivered by Industry Experts

As the courses are composed of advanced VLSI design and verification technologies, only experienced VLSI engineers can deliver and give an enriched learning
experience. At Maven Silicon, industry experts share their experience and guide you on enhancing your skills in VLSI Industries.

3. Superior Training Methodology

At Maven Silicon, the experienced engineers who work in the top semiconductor industries share their experiences with you and simulate their expertise to help
you learn via real-time scenarios. Only 30% of 900 hours of VLSI-RN course is dedicated to imparting concepts, and the remaining 70% for labs, mini-projects,
and final projects.

4. Excellent Placement Assistance

Maven Silicon offers placement support through a non-commercial placement cell, which regularly taps job opportunities in leading semiconductor companies.
We work closely with various VLSI product and services companies and identify the right opportunities for the students who successfully complete our training
program.
Most of our students have been successfully placed in renowned semiconductor companies. We're dedicated to the success of our trainees.

5. Excellent work environment

We provide an excellent work environment, which has adequate hardware and software infrastructure. Maven Silicon has chosen Mentor Graphics as its EDA
partner and provides great opportunities to engineers to work on verification platforms like Questa and explore the advanced ASIC verification technologies and
methodologies.

Maven Silicon has set the benchmark for VLSI Training by offering the best-curated package comprised of a holistic curriculum, standard
training methodologies, modern infrastructure, and excellent customer service.

EDA PARTNER - MENTOR GRAPHICS

Mentor Graphics is a leader in Electronic Design Automation. Its innovative products and solutions help engineers conquer design challenges in the seemingly
daunting world of board and chip design.
To know more about Mentor Graphics, please visit https://eda.sw.siemens.com/en-US

Delivered by Industry Experts Certification on completion Live Q&A sessions

WhatsApp Support Group 24/7 Lab Access

 ADVANCED VLSI DESIGN AND VERIFICATION COURSE
MODULE 1 MODULE 6 MODULE 9
Introduction to VLSI Verilog HDL - RTL Coding and Synthesis Code Coverage
VLSI Design Flow Statement coverage
[1] Introduction to Verlog HDL
ASIC Vs FPGA Branch Coverage
Applications of Verilog HDL
RTL Design Methodologies Expression Coverage
Verilog HDL language concept
Introduction to ASIC Verification Methodologies Path Coverage
Verilog language basics and constructs
VLSI Design Flow Steps – Demo Toggle Coverage
Abstraction levels
FSM - State, Transition and Sequence coverage
[2] Data Types
MODULE 2
Type Concept MODULE 10
Introduction to Linux Nets and registers
Non-hardware equivalent variables Verilog Mini Project RTL Coding and Synthesis
Components of UNIX system
Arrays
Directory Structure Project Specification Analysis
Utilities and Commands Understanding the architecture
Vi Editor [3] Verilog Operators
Module level implementation and verification
Logical operators
Building the top-level module
Bitwise and Reduction operators
MODULE 3 Concatenation and conditional
Implementing the design into FPGA

Advanced Digital Design Relational and arithmetic

Shift and Equality operators MODULE 11
Introduction to Digital Electronics Operators precedence RISC V Processor
Arithmetic Circuits
[4] Assignments [1] RISC-V Instruction Set Architecture
Data processing Circuits
Type of assignments RISC-V processor overview
Universal Logic Elements
Continuous assignments RISC-V ISA Overview
Combinational Circuits - Design and Analysis
Timing references
Latches and Flip flops RV32I – R and I Type Instruction
Procedures
Shift Registers and Counters RV32I – S and B Type Instructions
Blocking and Non-Blocking assignments
Sequential Circuits - Design and Analysis RV32I – J and U Type Instructions
Execution branching
Memories and PLD RV32I – Assembly Programs
Tasks and Functions
Finite State Machine [2] RISC-V RV32I RTL Architecture Design
Microcontroller Design [5] Finite State Machine RISC-V Execution Stages and Flow
Basic FSM structure RISC-V Register File and RV32I Instructions
Moore Vs Mealy
MODULE 4 Format
Common FSM coding styles RV32I – R and I Type ALU Datapath
Static Timing Analysis Registered outputs RV32I – S Type ALU Datapath - Load and Store
Introduction to STA [6] Advanced Verilog for Verification RV32I – B and U Type ALU Datapath
Comparison with DTA System Tasks RV32I – J Type ALU Datapath – JAL
Timing Path and Constraints Internal variable monitoring and JALR
Different types of clocks Compiler directives [3] RISC-V RV32I 5 Stage Pipelined
Clock domain and Variations File input and output RTL Design
Clock Distribution Networks [7] Synthesis Coding Style CPU Performance and RISC-V 5 Stage Pipeline
How to fix timing failure Registers in Verilog Overview
Methods to improve timing Unwanted latches RISC-V 5 Stage Pipeline – Data Hazards and
Operator synthesis Design Approach
MODULE 5 RTL Coding style RISC-V 5 Stage Pipeline – Control Hazards and
FPGA Architecture Design Approach

[1] PLD MODULE 7

General Structure and Classification CMOS Fundamentals
CPLD Vs FPGA MODULE 12
Non-Ideal characteristics
[2] Xilinx CPLD - Xc9500 ASIC Verification Methodologies
BJT vs FET
Block Diagram of CPLD
CMOS Characteristics
Detailed study of each block Directed Vs Random
CMOS circuit design
Endurance limits Functional verification process
Transistor sizing
Timing Model Stimulus Generation
Layout and Stick Diagrams
[3] Xilinx FPGA Bus function model
CMOS Processing Steps
FPGA Architecture Monitors and reference models
Fabrication Process Overview
CLBs and Input/Output Blocks Coverage Driven Verification
CMOS Technology - Current Trends
Luts, SLICE DFFs Verification Planning and management
Dedicated MUXes
Programmable Interconnects
MODULE 8
Architectural Resources Design Automation using Scripts - Perl
Power Distribution and Configuration Introduction to Perl
Functions and Statements
[4] FPGA Architecture of Xilinx Families
Numbers, Strings, and Quotes
[5] Netlist and Timing simulation
Comments and Loops
 ADVANCED VLSI DESIGN AND VERIFICATION COURSE
MODULE 13 MODULE 16 MODULE 19
SystemVerilog HVL Verification Mini Project: Assertion Based Verification - SVA
[1] Introduction to SystemVerilog Verification and RTL sign-off Introduction to ABV
New Data types Immediate Assertions
Project specification analysis
Tasks and Functions Simple Assertions
Defining verification plan
Interfaces Sequences
Creating Testbench architecture
Clocking blocks Sequence Composition
Defining Transaction
[2] Object Oriented Programming and Advanced SVA Features
Implementing the transactors - Generator,
Randomization Assertion Coverage
Driver, Receiver and Scoreboard
OOP Basics
Implementing the coverage model
Classes - Objects and handles MODULE 20
Building the top level verification environment
Polymorphism and Inheritance
Building regression test suite
Randomization Business communication
Coverage Analysis and Coverage Closure
Constraints Transition from College to Corporate
[3] Threads and Virtual Interfaces MODULE 17 Interpersonal skills and Presentation Skills
Fork Join Email Etiquette
Verification Planning and Management Resume writing
Fork Join_any
Fork Join_none Verification Plan Interview Skills: Group Discussion and HR
Event controls TB Architecture Round Preparation
Mailboxes and semaphores Coverage Model Mockup Interviews Technical/HR
Virtual Interfaces Tracking the simulation process
Transactors Building regression testsuite
Testsuite optimization
MODULE 21
Building verification environment
Testcases Industry Standard Project

[4] Callbacks MODULE 18 Design specification analysis

Creating the design architecture
Facade Class
UVM - Universal Verification Methodology Partitioning the design
Building Reusable Transactors
Introduction to UVM Methodology RTL coding in Verilog
Inserting Callbacks
Overview of Project RTL functional verification
Registering Callbacks
UVM TB Architecture RTL Synthesis
[5] Direct Programming Interface Building regression test suite
Stimulus Modeling
[6] Functional Coverage Creating UVCs and Environment Coverage Analysis and Coverage Closure
Coverage models UVM Simulation Phases
Coverpoints and bins Testcase Classes
Cross coverage TLM Overview
ELECTIVE MODULE
Regression testing Configuring TB Environment Design for Testability - DFT
UVM Sequences
Introduction to DFT
MODULE 14 UVM Sequencers
Types of Testing
Connecting DUT- Virtual Interface
Advanced SystemVerilog Basic Testing Principles
Virtual Sequences and Sequencers
Environment Configuration Fault Collapsing
Creating TB Infrastructure
Reference Models and Predictor Logics DFT Techniques - Ad-hoc Techniques
Connecting multiple UVCs
Using Legacy BFMs Building a Scoreboard Structured Techniques
Scenario Generation Introduction to Register Modeling BIST & boundary Scan
Testcases - Random, Directed and corner case Building reusable environments Introduction to Tessent Shell
Coding styles for VIP System Modes and TSDB

EDA TOOLS
MODULE 15
Mentor Graphics OPERATING SYSTEM
Interfaces and Protocols
Xilinx
Lectures by Industry Experts Linux - Ubuntu
Aldec

REACH US ASSOCIATION & PARTNERSHIPS

# 21/1A, III Floor, Marudhar Avenue,
Gottigere, Uttarahalli Hobli, South Taluk,
DESIGN PARTNER TECHNOLOGY PARTNER
Bannerghatta Road, Bangalore - 560076

+91 - 95133 98555 / +91 - 97415 19977

[email protected] /
TRAINING PARTNER
[email protected]
* Logos are the trademarks of the respective companies.

Copyright 2021 Maven Silicon, All Rights Reserved.