INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF40194B
MSI
4-bit bidirectional universal shift
register
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification

HEF40194B
4-bit bidirectional universal shift register
MSI

DESCRIPTION Serial and parallel operation are edge-triggered on the

LOW to HIGH transition of CP. The inputs at which the
The HEF40194B is a 4-bit bidirectional shift register with
data are to be entered and S0, S1 must be stable for a
two mode control inputs (S0 and S1), a clock input (CP), a
set-up time before the LOW to HIGH transition of CP.
serial data shift left input (DSL), a serial data shift right input
(DSR), four parallel data inputs (P0 to P3), an overriding
asynchronous master reset input (MR), and four buffered
parallel outputs (O0 to O3). When LOW, MR resets all
stages and forces O0 to O3 LOW, overriding all other input
conditions. When MR is HIGH, the operation mode is
controlled by S0 and S1 as shown in the function table.

Fig.2 Pinning diagram.

HEF40194BP(N): 16-lead DIL; plastic

(SOT38-1)
HEF40194BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40194BT(D): 16-lead SO; plastic
Fig.1 Functional diagram.
(SOT109-1)
( ): Package Designator North America

PINNING FAMILY DATA, IDD LIMITS category MSI

S0, S1 mode control inputs See Family Specifications
P0 to P3 parallel data inputs
DSR serial data shift right input
DSL serial data shift left input
CP clock input (LOW to HIGH edge-triggered)
MR master reset input (active LOW)
O0 to O3 buffered parallel outputs

January 1995 2
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January 1995

Philips Semiconductors
4-bit bidirectional universal shift register
3

HEF40194B
Product specification
MSI
Fig.3 Logic diagram.
Philips Semiconductors Product specification

HEF40194B
4-bit bidirectional universal shift register
MSI

FUNCTION TABLE

INPUTS (MR = HIGH) OUTPUTS AT Tn + 1

OPERATING MODE S1 S0 DSR DSL P0 TO P3 O0 O1 O2 O3
hold L L X X X O0 O1 O2 O3
H L X L X O1 O2 O3 L
shift left
H L X H X O1 O2 O3 H
L H L X X L O0 O1 O2
shift right
L H H X X H O0 O1 O2
H H X X L L L L L
parallel load
H H X X H H H H H

Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4. tn + 1 = state after next LOW to HIGH transition of CP

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns

VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 1 500 fi + ∑ (foCL) × VDD2 where
dissipation per 10 6 900 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz)
package (P) 15 18 900 fi + ∑ (foCL) × VDD2 fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)

January 1995 4
Philips Semiconductors Product specification

HEF40194B
4-bit bidirectional universal shift register
MSI

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
Propagation delays
CP → On 5 100 205 ns 73 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 40 85 ns 29 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
5 80 165 ns 53 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 35 70 ns 24 ns + (0,23 ns/pF) CL
15 25 55 ns 17 ns + (0,16 ns/pF) CL
MR → On 5 85 175 ns 58 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL
15 30 60 ns 22 ns + (0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL

January 1995 5
Philips Semiconductors Product specification

HEF40194B
4-bit bidirectional universal shift register
MSI

VDD TYPICAL EXTRAPOLATION

SYMBOL MIN. TYP. MAX.
V FORMULA
Set-up times 5 80 40 ns
Pn, DSR, DSL → CP 10 tsu 30 15 ns
15 20 10 ns
5 140 70 ns
Sn → CP 10 tsu 60 30 ns
15 40 20 ns
Hold times 5 10 −30 ns
Pn, DSR, DSL → CP 10 thold 5 −10 ns
15 5 −5 ns
5 25 −45 ns
Sn → CP 10 thold 15 −15 ns
15 10 −10 ns see also waveforms
Minimum clock 5 50 25 ns Figs 4 and 5
pulse width; LOW 10 tWCPL 20 10 ns
15 20 10 ns
Minimum MR 5 80 40 ns
pulse width; LOW 10 tWMRL 40 20 ns
15 30 15 ns
Recovery time 5 30 10 ns
for MR 10 tRMR 15 5 ns
15 15 5 ns
Maximum clock 5 6 12 MHz
pulse frequency 10 fmax 15 30 MHz
15 20 40 MHz

January 1995 6
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January 1995

Philips Semiconductors
4-bit bidirectional universal shift register
7

HEF40194B
Product specification
Fig.4 Waveforms showing set-up times, hold times for DSR, DSL and Pn inputs; minimum MR pulse width, MR to output delays and MR to CP
recovery time; minimum CP pulse width and CP to output delays. Set-up and hold times are shown as positive values but may be

MSI
specified as negative values.
Philips Semiconductors Product specification

HEF40194B
4-bit bidirectional universal shift register
MSI

Fig.5 Waveforms showing set-up times and hold times for S0 and S1 inputs. Set-up and hold times are shown
as positive values but may be specified as negative values.

APPLICATION INFORMATION
Some examples of applications for the HEF40194B are:
• Arithmetic unit register
• Serial/parallel converter.

January 1995 8