BINARY ADDITION

REPRESENTING SIGNED

NUMBERS
1’s-Complement Form

2’s Complement Form

Representing Signed Numbers
Using 2’s Complement
Represent each of following signed decimal numbers
as a signed binary number in the 2’s-complement
system. Use a total of five bits, including the sign bit.
(a) +13 (b) -9 (c) +3 (d) -2 (e) -8 (a)

(b) The number (-9) is negative, so the magnitude (9)

must be represented in 2’scomplement form:

Attach sign bit of 1, complete signed

number becomes
Procedure we have just followed required
two steps.
(c)
(d) -2; Start by writing using five bits :
(e) Start with +8:

Sign Extension
To store 5-bit negative numbers in an 8 bit
register, 2’s- complement binary
representation for -9 is 1 0111

Negation
Start with 00001001 +9 2’s complement
(negate) 11110111 ₋9 negate again 00001001
+9
Thus, we negate a signed binary number
by 2’s complementing it.
(6.2) Tocci; Each of the following numbers
is a five bit signed binary number in the
2’s-complement system. Determine the
decimal value in each case: (a) 01100 (b)
 11010 (c)10001 P-303 Tocci
Special Case in 2’s-Complmnt
Representation Whenever a signed number has a 1
in the sign bit and all 0s for the magnitude bits, its
decimal equivalent is ₋2N, where N is the number of
bits in magnitude, e.g.,
N
1000 = ₋2 -8
N
10000 = ₋2 -16
100000 = ₋2N -32
Complete range of values that can be represented in
2’s-complement system having N magnitude bits is-
N N
₋2 to + (2 - 1)
N+1
There are a total of different 2 values, including
zero
For example, Table 6-1 lists all signed numbers that
can be represented in four bits using the 2’s
complement system (note there are three magnitude
N
bits, so N = 3 ). Note that the sequence starts at ₋2 =

₋23 = -8 = 1000 and proceeds upward to +(2N - 1) = +23

– 1= +7 = 0111 by adding 0001 at each step as in an up
counter.
6.3 Tocci; What is the range of unsigned decimal
values that can be represented in a byte?

to
6.4 Tocci; What is the range of signed decimal values
that can be represented in a byte?

ADDITION IN 2’s-COMPLEMENT
SYSTEM Case I: Two Positive Numbers.
The addition of two positive numbers is
straightforward. Consider the addition of +9
and +4
Case II: +ve Number and Smaller –ve number
Consider the addition of +9 and -4. Remember that the
-4 will be in its 2’s-complement form. Thus, +4
(00100) must be converted to -4 (11100).
 The result is 00101 = (sum +5).
Case III: +ve Number & Larger -ve
Number. Consider the addition of -9 and +4
Sum has a sign bit of 1, indicating a negative number.
Because sum is negative, it is in 2’s-complement form
Case IV: Two Negative
Numbers

Result is 10011 (Sum = -13) Final result is

again negative and in 2’s-complement form
with a sign bit of 1. Negating (2’s
 complementing) this result produces 01101
= +13.
Case V: Equal & Opposite Numbers

Result
is 00000 (sum = + 0)The result is obviously +0, as
expected
SUBTRACTION IN 2’s-COMPLEMENT SYSTM
Subtraction opn using 2’s-complement system actually
involves the operation of addition and is really no
different from the various cases for addition. In
subtracting one binary number (subtrahend) from another
binary number (minuend), use the procedure: 1. Negate
the subtrahend. This will change the subtrahend to its
equivalent value of opposite sign. 2. Add this to the
minuend. Result of this addition will represent difference
between subtrahend and minuend
Consider case where +4 is to be subtracted
from +9

Negate subtrahend to produce 11100, which

represents -4, Now add this to the minuend.
 the result is
00101= + 5
Another example showing +9 subtracted
from -4 11100 (-4)
- 01001 (+9)
Negate the subtrahend (+9 ) to produce
10111 (-9 ) and add this to the minuend (-4)
Verify the results of using the above procedure for
the following subtractions:

(a) +9 – (-4);
(b) -9 – (+4)
(c) -9 – (-4)
(d) +4 – (-4)
Remember that when the result has a sign bit of 1, it is
negative and in 2’s-complement form.
MULTIPLICATION OF BINARY NUMBERS
Multiplication in 2’s-Complement
System
BINARY DIVISION
 BCD ADDITION
Sum Equals 9 or Less; Consider adding 5 and 4
using BCD to represent each digit

The addition is carried out as in normal binary

addition, and the sum is 1001,
Addition is carried out as in normal binary addition,
and the sum is 1001, which is the BCD code for 9
Another example, take 45 added to 33
Sum > 9: Consider addition of 6 and 7 in
BCD
 invalid code group for BCD
Another example, take 47 + 35 in BCD
Consider addition of 59 and 38 in BCD
Perform the addition of 275 + 641
HEXADECIMAL ARITHMETIC Hex
Addition Addition of Hex numbers is done in same
way as decimal addition (largest hex digit is F instead
of 9). 1. Add two hex digits in decimal, mentally
inserting
decimal equivalent for those digits larger than 9
2. If sum is 15 or less, it is directly expressed as hex
digit
3. If the sum is greater than or equal to 16, subtract 16
and carry a 1 to the next digit position.
Adding the LSDs (8 and 4) produces 12, which is C in
hex. There is no carry into the next digit position.
Adding 5 and 2 produces 7
Hex Subtraction
2’s complement of hex subtrahend will be
taken & then added to the minuend, & any
carry out of MSD position will be
disregarded. To get 2’s complement of a hex
number, convert it to binary, take 2’s
 complement of binary equivalent, & then
convert it
back to hex.

A quicker procedure: subtract each hex digit from F;

then add 1.

Try either of the procedures above on the hex number

E63. The correct result for the 2’s complement is 19D.
Ex 6.9 Tocci: Subtract 3A516 from 59216
First, convert subtrahend (3A5) to its
2’s-complement
form. Result is C5B

Ignore carry out of MSD addition; result is

1ED. Proof: Add 1ED to 3A5 & check to
see that it equals P 317 Tocci
Pg-319 Tocci
Block diagram of a five-bit parallel adder
circuit using full adders Pg-319 Tocci

DESIGN OF A FULL ADDER

Pg-320 Tocci
 Pg-321
Tocci
Expression
for S can’t
be

simplified map
using K
K map for as from
algebraic
Cout
method.
gives same Pg-322 Tocci

expression

Pg-322 Tocci
Cout
Block symbol for 74HC283 four-bit parallel
adder;
Cascading two 74HC283s
Parallel adder used to add and subtract numbers
in2’s-complement system.
Subtracting +6
from +4 in 2’s
complement system
BINARY ADDER-SUBTRACTOR
Half Adder

Pg-134 Mano
FULL ADDER

Implementation of full adder with 2

half adders & an OR gate

Example: consider the two binary numbers A = 1011
and B = 0011. Their sum S = 1110 is formed with the
four-bit adder as follows:,

Carry Propagation
 ,,

Giis called a carry generate, & it produces a carry of 1

when both Ai & Biare 1, regardless of i/p carry Ci. Piis

called a carry propagate, because it determines

whether a carry into stage i will propagate into stage i

+ 1 (i.e., whether an assertion of Ci will propagate to

an assertion of Ci +1)

Writing Boolean fns for carry outputs of each stage &

substituting value of each Ci from previous equations:
C0 = input carry

C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C0)
C2 = G1 + P1G0 + P1P0C0 Similarly
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 Hence,
C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
Carry
Lookahea
d
Generator
4-bit Adder
With Carry
Lookahead
Binary Multiplier
Binary Multiplier
 4-bit by 3-bit Binary Multiplier

B3 B2 B1 B0
A2 A1 A0
------------------------------------------------------------------------------
- A0B3 A0B2 A0B1 A0B0
A1B3 A1B2 A1B1 A1B0
A1B3 A1B2 A1B1 A1B0
--------------------------------------------------------------------------------------
- C6 C5 C4 C3 C2 C1 C0
--------------------------------------------------------------------------------------
-
4-bit by Multipli
3-bit er 3
10
32
0
Binary 2
Adder A
1

CA4
(Carry)
ΣA1 ΣA3 ΣA2 ΣA0
CA4ΣA3 ΣA2
ΣA1
3 2 rB 3 0
1
Adde 0 21
 ΣB2 ΣB1 ΣB0 ΣB3
ΣA0
Carry CB4
4-bit adder–
subtractor
with
overflow
detection

Truth Table
For M = 0 X=B 1=
X = B 0 = B B′
For M = of X-OR gate M
1
BCD
Adde
r
 C=K
+
Z8Z4 +
Z8Z2
Block diagram
of a BCD
adder
 Magnitude Comparator
A magnitude comparator is a combinational circuit
that compares two numbers A and B and determines
their relative magnitudes. The outcome of the
comparison is specified by three binary variables that
indicate whether A > B, A = B, or A < B.
A comparator circuit possesses an inherent well
defined regularity can be designed by means of an
algorithm—a procedure which specifies a finite set of
steps that, if followed, give solution to a problem. We
illustrate this method here by deriving an algorithm for
design of a four-bit magnitude comparator. Algorithm
is a direct application of the procedure a person uses to
compare the relative magnitudes of two numbers.
Consider two numbers, A and B, with 4 digits each A
= A 3 A2 A1 A0

B = B3 B2 B1 B0
Each subscripted letter represents one of digits in no.
Two numbers are equal if all pairs of significant digits
are equal: A 3 = B3, A 2 = B2, A 1 = B1, and A 0 = B0
When the numbers are binary, the digits are either 1 or
0, and equality of each pair of bits can be expressed
logically with an exclusive-NOR function as xi = A iBi
+ A i′Bi′ for i = 0, 1, 2, 3
xi = 1 only if the pair of bits in position i are equal
(i.e., if both are 1 or both are 0).
(A = B) = x3x2x1x0
The binary variable (A = B) is equal to 1 only if all
pairs of digits of the two numbers are equal For (A >
B)

(A > B) = A 3B′3 + x3 A2B′2 + x3x2 A1B′1 + x3x2x1A0B′0

For (A < B)
(A < B) = A′ 3B3 + x3 A′2B2 + x3x2 A′1B1 + x3x2x1A′0B0
A = A 3 A2 A1 A0 1 1 0 1 1
B = B3 B2 B1 B0 0 1 0 1
4-bit
Magnitude
Comparato
r