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Anadolu University: Engineering and Architecture Faculty Department of Electrical and Electronics Engineering

1. The document summarizes a lab report for a "Digital Systems II" course where students used Xilinx ISE software to design digital circuits on an FPGA. They created half adder, full adder, and 4-bit adder circuits by adding logic gates and simulation. 2. The students followed the lab instructions to create a new project, add sources for schematics, and design the half adder, full adder, and 4-bit adder circuits. They simulated the designs and observed the output waveforms. 3. In conclusion, the students gained experience using Xilinx ISE but had some difficulties changing inputs or outputs after simulation that prevented completing the full 4

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Serkan Yilmaz III
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36 views

Anadolu University: Engineering and Architecture Faculty Department of Electrical and Electronics Engineering

1. The document summarizes a lab report for a "Digital Systems II" course where students used Xilinx ISE software to design digital circuits on an FPGA. They created half adder, full adder, and 4-bit adder circuits by adding logic gates and simulation. 2. The students followed the lab instructions to create a new project, add sources for schematics, and design the half adder, full adder, and 4-bit adder circuits. They simulated the designs and observed the output waveforms. 3. In conclusion, the students gained experience using Xilinx ISE but had some difficulties changing inputs or outputs after simulation that prevented completing the full 4

Uploaded by

Serkan Yilmaz III
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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ANADOLU UNIVERSITY

ENGINEERING AND ARCHITECTURE FACULTY

DEPARTMENT OF ELECTRICAL AND ELECTRONICS


ENGINEERING

(SPRING 2011)

EEM 334 - Digital Systems II

REPORT
( 05. 03. 2011 )

LAB 1 - INTRODUCTION TO XILINX ISE


SOFTWARE AND FPGA
NAME OF INSTRUCTOR: Araş. Gör. İSMAİL SAN

NAME OF STUDENTS : 24010073434 SERKAN YILMAZ

40474250860 AHMET ÇELİK

20848630900 OKAN IŞINTAN


SUBJECT: The subject of the “Digital Systems II ” lecture which is studied as a
group in the Department of Electrical Electronics Engineering of Anadolu University
in the Spring term of the 2010-2011 academic year is “Introduction to Xilinx Ise
Software And FPGA”. That is performed with Good Laboratory Practices.
1. The Purpose
In this lab, the main purpose is learn to use the basic functionality of ISE platform
practically and understand to simulate given design on ISE. Like this, we aimed to
learn better the simulation and building digital designs by using Xilinx Ise Software.
2. Experiment
In this experiment, we tried to applied given instructions in the procedure step by step
as a group. First of all, we chose new project from file to obtain a project. We opened
the Xilinx ISE Project Navigator and we saw Xilinx ISE working place. In addition we
chose New Project from File Menu. Then, we obtained a project named Adder and
established a Project Location. At the same time, Top-Level Source was preferred as
Schematic. Furthermore, we set the device properties exactly on following screen.
We were sure the one that device properties set certainly, and we skipped 3 screens
with using Next and Finish button. After these steps, there were two sources files.
And we would make a design like given. Then, we added a new source to our project
from Project Menu. Also, we chose Schematic by using New Source Wizard-Select
Source Type that was on following screen. We established its name as half_adder,
and wrote Adder Location. We pushed on next, next and finish button. Like this,
Creating Schematic completed successfully. In addition, we could see the “Sources”.
It provided to add some logic element into the workspace. Finally, It is seen our
projects steps one by one.
Firstly, we added “xor2” and “and2” gates that are included by “Logic categories” for
half adder circuit. Also, we added “I/O maker” and ” wire” by using Add Menu.

Figure1.
Secondly , we added New Source as Schematic to our Project and its name was
“full_adder” that set as a top module. Moreover, after selecting “haf adder” we used
“Create schematic symbol” so, we obtained our half adder for using on full adder
design. Furthermore, we could use our new symbol from created objects. In short, we
designed a full adder by using our haff adder that has new symbol.

Figure2.

Thirdly, after we complete the design, we tested it by using Simulator. Like this, we
aimed to understand the behavior exactly. For this, we added “Test Bench Wave
Form” and we called it as “test_full_adder”. After, we selected as combinational .
because of this, we do not use clock for this project. We simulated and observed by
using “Simulate Behavioral Model” from Xilinx ISE Simulator.

Finally, we wanted to build 4 bit adder by using Full Adder. Thşs situation is so
similar with getting full adder by using half adder that was designed by us. First of all,
we created new schematic symbol of full adder. Then, we tried to build 4 bit adder
with combining 4 full adders.

CONCLUSION

In this experiment, we spended time before laboratory. That is, we had some
information about Xilix ISE. In lesson time, we appilied given instructions clearly . We
practiced on schematic screen with Xilinx ISE and we learned how to design by
using schematic in this software programme. Then, we tried to understand the
behavior of our design effectly. It was performed by using simulation. In other words,
this program provides the goodness for test. Moreover, Xilinx ISE was close once.
Also, if we would give same input or output wrongly,that was impossible to change. It
spended our time and we did not complete the last practice. Finally, we had some
experience after laboratory about Xilinx ISE and FBGA.

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