L6932

HIGH PERFORMANCE 2A ULDO LINEAR REGULATOR

■ 2V TO 14V INPUT VOLTAGE RANGE

■ 200mΩ Rdson MAX.
■ 200µA QUIESCENT CURRENT AT ANY LOAD
■ EXCELLENT LOAD AND LINE REGULATION
■ 1.5V, 1.8V AND 2.5V FIXED VOLTAGE
SO-8 (4+4)
■ ADJUSTABLE FROM 1.2V TO 5V (L6932D1.2)
■ 1% VOLTAGE REGULATION ACCURACY ORDERING NUMBERS:
■ SHORT CIRCUIT PROTECTION L6932D1.2 (SO-8) L6932D1.2TR (T&R)
L6932D1.5 (SO-8) L6932D1.5TR (T&R)
■ THERMAL SHUT DOWN
L6932D1.8 (SO-8) L6932D1.8TR (T&R)
■ SO-8 (4+4) PACKAGE L6932D2.5 (SO-8) L6932D2.5TR (T&R)

APPLICATIONS Mosfet, can be usefull for the DC-DC conversion

■ MOTHERBOARDS between 2.5V and 1.5V at 2A in portable applica-
tions reducing the power dissipation.
■ MOBILE PC
L6932 is available in 1.5V, 1.8V, 2.5V and adj ver-
■ HAND-HELD INSTRUMENTS sion from 1.2V and ensure a voltage regulation ac-
■ PCMCIA CARDS curacy of 1%.
■ PROCESSORS I/O The current limit is fixed at 2.5A to control the cur-
■ CHIPSET AND RAM SUPPLY rent in short circuit condition within ±8%. The cur-
rent is sensed in the power mos in order to limit the
power dissipation.
DESCRIPTION The device is also provided of a thermal shut down
The L6932 Ultra Low Drop Output linear regulator that limits the internal temperature at 150°C with
operates from 2V to 14V and is able to support 2A. an histeresys of 20°C. L6932 provides the Enable
Designed with an internal 50mΩ N-channel and the Power good functions.

TYPICAL OPERATING CIRCUIT

VIN IN OUT VOUT
2 3
2V to 14V 1.5V-1.8V-2.5V
L6932D
C1 PGOOD C2
4
5,6,7,8 1

GND
EN

VIN IN OUT VOUT

2 4
2V to 14V 1.2V to 5V
R1
L6932D
C1 ADJ C2
3
5,6,7,8 1
R2
GND
EN

Rev. 9
December 2005 1/11
L6932

PIN CONNECTIONS

EN 1 8 GND EN 1 8 GND

IN 2 7 GND IN 2 7 GND

ADJ 3 6 GND OUT 3 6 GND

OUT 4 5 GND PGOOD 4 5 GND

L6932D1.2 L6932D1.5
L6932D1.8
L6932D2.5

PIN FUNCTION
L6232D
L6232D
N° 1.5/1.8/ Description
1.2
2.5

1 EN Enables the device if connected to Vin and disables the device if forced to gnd.

2 IN Supply voltage. This pin is connected to the drain of the internal N-mos. Connect this
pin to a capacitor larger than 10µF.

ADJ – Connecting this pin to a voltage divider it is possible to programme the output voltage
between 1.2V and 5V.
3
– OUT Regulated output voltage. This pin is connected to the source of the internal N-mos.
Connect this pin to a capacitor of 10µF.

OUT – Regulated output voltage. This pin is connected to the source of the internal N-mos.
Connect this pin to a capacitor of 10µF.
4
– PGOOD Power good output. The pin is open drain and detects the output voltage. It is forced
low if the output voltage is lower than 90% of the programmed voltage.

5, 6, 7, 8 GND Ground pin.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vin VIN and Pgood 14.5 V

EN, OUT and ADJ -0.3 to (Vin +0.3) V

THERMAL DATA
Symbol Parameter Value Unit

Rth J-amb Thermal Resistance Junction to Ambient 62 (*) °C/W

Tmax Maximum Junction Temperature 150 °C

Tstg Storage Temperature Range -65 to 150 °C

(*) Measured on Demoboard with about 4 cm2 of dissipating area 2 Oz.

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 L6932

BLOCK DIAGRAM (Referred to the Fixed Voltage version)

IN

CHARGE CURRENT
PUMP LIMIT

VREF DRIVER
REFERENCE +
VREF=1.25V -
ERROR
OUT
AMPL.

THERMAL
EN ENABLE
SENSOR
PG
-
0.9 VREF
+
GND

D99IN1100

ELECTRICAL CHARACTERISTCS (Tj = 25°C, VIN = 5V unless otherwise specified)

(*) Specification referred to Tj from -25°C to 125°C.
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vin Operating Supply Voltage 2 14 V
Vo Output voltage L6932D1.2 Io = 0.1A; Vin = 3.3V 1.188 1.2 1.212 V
Output voltage L6932D1.5 Io = 0.1A; Vin = 3.3V 1.485 1.5 1.515 V
Output voltage L6932D1.8 Io = 0.1A; Vin = 3.3V 1.782 1.8 1.818 V
Output voltage L6932D2.5 Io = 0.1A; Vin = 3.3V 2.475 2.5 2.525 V
L6932D1.2 Vin = 2.5V ±10%; Io = 10mA 5 mV
Line Regulation
Vin = 3.3V ±10%; Io = 10mA 5 mV
Vin = 5V ±10%; Io = 10mA 5 mV
L6932D1.5 Vin = 2.5V ±10%; Io = 10mA 5 mV
Line Regulation
Vin = 3.3V ±10%; Io = 10mA 5 mV
Vin = 5V ±10%; Io = 10mA 5 mV
L6932D1.8 Vin = 2.5V ±10%; Io = 10mA 5 mV
Line Regulation
Vin = 3.3V ±10%; Io = 10mA 5 mV
Vin = 5V ±10%; Io = 10mA 5 mV
L6932D2.5 Vin = 3.3V ±10%; Io = 10mA 5 mV
Line Regulation
Vin = 5V ±10%; Io = 10mA 5 mV
L6932D1.2 Load Regulation Vin = 3.3V; 0.1A < Io < 2A 15 mV
L6932D1.5 Load Regulation Vin = 3.3V; 0.1A < Io < 2A 15 mV
L6932D1.8 Load Regulation Vin = 3.3V; 0.1A < Io < 2A 15 mV
L6932D2.5 Load Regulation Vin = 3.3V; 0.1A < Io < 2A 15 mV
Rdson Drain Source ON resistance 200 mΩ

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L6932

ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit
Iocc Current limiting 2.3 2.5 2.7 A
Iq Quiescent current 0.2 0.4 mA
Ish Shutdown current 2V < Vin < 14V * 25 µA
Ripple Rejection f = 120Hz, Io = 1A 60 75 dB
Vin = 5V, ∆Vin = 2Vpp
Ven EN Input Threshold 0.5 0.65 0.8 V
Pgood threshold Vo rise 90 %Vo
Pgood Hysteresis 10 %Vo
Pgood saturation Ipgood =1mA 0.2 0.4 V

Figure 1. Output Voltage vs. Junction Figure 3. Output Voltage vs. Junction
Temperature (L6932D1.2) Temperature (L6932D2.5)
1.213 2.520

1.212
2.515
1.212

1.211 2.510
V
V
1.211
2.505
1.210

2.500
1.210

1.209
2.495
-60 -40 -20 0 20 40 60 80 100 120 140 160
-60 -40 -20 0 20 40 60 80 100 120 140 160
Temp [°C]
Temp [°C]

Figure 2. Output Voltage vs. Junction Figure 4. Quiescent Current vs. Junction
Temperature (L6932D1.8) Temperature
1.808 310

300
1.804
Vin=5V
290
1.800
V Iq 280
1.796 (uA)
270
1.792
260

1.788
-60 -40 -20 0 20 40 60 80 100 120 140 160 250
-40 -20 0 20 40 60 80 100 120 140
Temp [°C]
Temp [°C ]

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 L6932

Figure 5. Shutdown Current vs. Junction TemperatureAPPLICATION INFORMATIONS

7.5

6.5
Vin=5V
Ishdn 6
(uA)
5.5

4.5

4
-40 -20 0 20 40 60 80 100 120 140

Temp [°C ]

APPLICATION CIRCUIT
In figure 6 the schematic circuit of the demoboards are shown.

Figure 6. Demoboards Schematic Circuit

VIN IN OUT VOUT

2 3
L6932D1.5
EN L6932D1.8
1
C1 L6932D2.5 PGOOD C2
4
5 6 7 8

GND

VIN IN OUT VOUT

2 4
1.2V to 5V
EN R1
1 L6932D1.2
C1 ADJ C2
3
1.2
5 6 7 8
VOUT = × (R1+ R2)
GND
R2
R2

COMPONENT LIST

Fixed version
Reference Part Number Description Manufacturer

C1 C34Y5U1E106Z 10uF, 25V TOKIN

C2 C34Y5U1E106Z 10uF, 25V TOKIN

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L6932

Figure 7. Demoboard Layout (Fixed Version)

Adjustable version
Reference Part Number Description Manufacturer

C1 C34Y5U1E106Z 10uF, 25V TOKIN

C2 C34Y5U1E106Z 10uF, 25V TOKIN

R1 5.6K, 1%, 0.25W Neohm

R2 3.3K, 1%, 0.25W Neohm

Figure 8. Demoboard Layout (Adjustable Version)

COMPONENTS SELECTION
Input Capacitor
The input capacitor value depends on a lot of factors such as load transient requirements, input source (battery
or DC/DC converter) and its distance from the input cap. Usually a 47µF is enough for any application but a
much lower value can be sufficient in many cases.

Output Capacitor
The output capacitor choice depends basically on the load transient requirements.
Tantalum, Speciality Polimer, POSCAP and aluminum capacitors are good and offer very low ESR values.

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 L6932

Multilayer ceramic caps have the lowest ESR and can be required for particular applications. Nevertheless in
several applications they are ok, the loop stability issue has to be considered (see loop stability section).
Below a list of some suggested capacitor manufacturers.
Manufacturer Type Cap Value (µF) Rated Voltage (V)

PANASONIC CERAMIC 1 to 47 4 to 16

TAYO YUDEN CERAMIC 1 to 47 4 to 16

TDK CERAMIC 1 to 47 4 to 16

TOKIN CERAMIC 1 to 47 4 to 16

SANYO POSCAP 1 to 47 4 to 16

PANASONIC SP 1 to 47 4 to 16

KEMET TANTALUM 1 to 47 4 to 16

Loop Stability
The stability of the loop is affected by the zero introduced by the output capacitor.
The time constant of the zero is given by:
1
T = ESR ⋅ C OUT F ZERO = --------------------------------------------
2π ⋅ ESR ⋅ C OUT

This zero helps to increase the phase margin of the loop until the time constant is higher than some hundreds
of nsec, depending also on the output voltage and current.
So, using very low ESR ceramic capacitors could produce oscillations at the output, in particular when regulating
high output voltages (adjustable version).
To solve this issue is sufficient to add a small capacitor (e.g. 1nF to 10nF) in parallel to the high side resistor of
the external divider, as shown in figure 9.

Figure 9. Compensation Network

VIN=2V TO 14V IN OUT VOUT=1.2V TO 5V UP to 2A

2 4

L6932D1.2 R1 C3
EN ADJ
1 3
C1 6 C2
5 7 8
R2
GND

Thermal Considerations
Since the device is housed in a small SO(4+2+2) package the thermal issue can be the bottleneck of many ap-
plications. The power dissipated by the device is given by:

PDISS = (VIN - VOUT) · IOUT

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L6932

The thermal resistance junction to ambient of the demoboard is approximately 62°C/W. This mean that, consid-
ering an ambient temperature of 60°C and a maximum junction temperature of 150°C, the maximum power that
the device can handle is 1.5W.
This means that the device is able to deliver a DC output current of 2A only with a very low dropout.
In many applications, high output current pulses are required. If their duration is shorter than the thermal con-
stant time of the board, the thermal impedance (not the thermal resistance) has to be considered.
In figure 10 the thermal impedance versus the duration of the current pulse for the SO(4+2+2) mounted on board
is shown.

Figure 10. Thermal Impedance

Considering a pulse duration of 1sec, the thermal impedance is close to 20°C/W, allowing much bigger power
dissipated.

Example:

Vin = 3.3V
Vout = 1.8V
Iout = 2A
Pulse Duration = 1sec

The power dissipated by the device is:

PDISS = (VIN - VOUT) · IOUT = 1.5 · 2 3W

Considering a thermal impedance of 20°C/W, the maximum junction temperature will be:

TJ = TA + ZTHJA · PDISS = 60 + 60 = 120°C

Obviously, with pulse durations longer than approximately 10sec the thermal impedance is very close to the
thermal resistance (60°C/W to 70°C/W).

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 L6932

Figure 11. SO-8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.35 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.010

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D (1) 4.80 5.00 0.189 0.197

E 3.80 4.00 0.15 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

Note: (1) Dimensions D does not include mold flash, protru-

sions or gate burrs. SO-8
Mold flash, potrusions or gate burrs shall not exceed
0.15mm (.006inch) in total (both side).

0016023 C

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L6932

Table 1. Revision History

Date Revision Description of Changes

February 2003 8 First Issue

December 2005 9 Added new Ordering Numbers: L6932D1.5 & L6932D1.5TR.

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 L6932

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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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