Final Lab
Final Lab
AIM:
To write VHDL code for all logic gates using Xilinx and simulate the results
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
NAND GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nandgate is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end nandgate;
architecture Behavioral of nandgate is
begin
c <=not(a and b);
end Behavioral;
Waveform:
NOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity norgate is
c :out std_logic);
end norgate;
begin
c <=not(a or b);
end Behavioral;
Waveform:
XOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xorgate is
c : out STD_LOGIC);
end xorgate;
begin
c <=a xor b;
end Behavioral;
Waveform:
XNOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xnorgate is
c : out STD_LOGIC);
end xnorgate;
c <=a xnor b;
endBehavioral;
WAVEFORM:
PROCEDURE:
1.Create a new project and new vhdl module write the code and save it in appropriate project.
2.Save the program and check for syntactical errors and rectify errors.
4.Finally simulate using model sim and verify the output waveforms.
RESULT:
Thus, logic gates are realized using VHDL.
PRIORITY ENCODER
AIM:
To write VHDL code for priority encoder and simulate its results.
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prten is
o1,o2,o3:out std_logic);
end prten;
begin
process(y0,y1,y2,y3,y4,y5,y6,y7,en)
begin
if(en='1' and y0='0' and y1='0' and y2='0' and y3='0' and y4='0' and y5='0' and y6='0' and
y7='0')then
o1<='0';o2<='0';o3<='0';
elsif(en='0' and y0='1' and y1='0' and y2='0' and y3='0' and y4='0' and y5='0' and y6='0' and
y7='0')then
o1<='0';o2<='0';o3<='0';
elsif(en='0' and y1='1' and y2='0' and y3='0' and y4='0' and y5='0' and y6='0' and y7='0')then
o1<='0';o2<='0';o3<='1';
elsif(en='0' and y2='1' and y3='0' and y4='0' and y5='0' and y6='0' and y7='0')then
o1<='0';o2<='1';o3<='0';
elsif(en='0' and y3='1' and y4='0' and y5='0' and y6='0' and y7='0')then
o1<='0';o2<='1';o3<='1';
o1<='1';o2<='0';o3<='0';
o1<='1';o2<='0';o3<='1';
o1<='1';o2<='1';o3<='0';
o1<='1';o2<='1';o3<='1';
end if;
end process;
end Behavioral;
Waveforms:
RESULT:
Thus priority encoder is implemented using VHDL
ONE’s COUNTER
AIM:
To write VHDL code for ones counter and simulate its results.
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity ONECOUNT is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
SUM: out STD_LOGIC_VECTOR (4 downto 0));
End ONECOUNT;
Architecture Behavioral of ONECOUNT is
Begin
PROCESS (D)
VARIABLE S:STD_LOGIC_VECTOR( 4 DOWNTO 0);
BEGIN
S:="00000";
FOR I IN 0 TO 7 LOOP
IF D (I) ='1' THEN
S: =S+"00001";
END IF;
END LOOP;
SUM<=S;
END PROCESS;
End Behavioral;
The output wave form for the one’s counter is shown in below
Waveforms:
Result:
Thus one’s counter was implemented using VHDL
SINGLE PORT SYNCHRONOUS RAM
AIM:
To write VHDL code for single port synchronous RAM
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RAM16X4 IS
PORT(DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
R_WRB,ENBAR:IN BIT;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END RAM16X4;
ARCHITECTURE BEH OF RAM16X4 IS
TYPE TRAM IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL RAMDATA:TRAM;
BEGIN
PROCESS(R_WRB,ADDR,DATA,RAMDATA,ENBAR)
BEGIN
IF(ENBAR='0') THEN
IF (R_WRB='0') THEN
RAMDATA(CONV_INTEGER(ADDR))<=DATA;
END IF;
END IF;END PROCESS;
PROCESS(R_WRB,ADDR,DATA,RAMDATA,ENBAR)
BEGIN
IF(ENBAR='0') THEN
IF (R_WRB='1') THEN
Q<=RAMDATA(CONV_INTEGER(ADDR));
ELSE
Q<="ZZZZ";
END IF;
END IF;
END PROCESS;
END BEH;
The output waveform for the RAM is shown in below figure
Result:
Thus RAM was implemented using VHDL
ALU
AIM:
To write VHDL code for ALU and simulate its results.
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu2 is
Cin:in std_logic);
end alu2;
signal a1,b1,m1:integer:=0;
signal t: boolean;
begin
process(s,a,b,cin,a1,b1)
begin
a1<= conv_integer(a);b1<=conv_integer(b);
case s is
end case;
end process;
end Behavioral;
Waveforms:
RESULT: Thus ALU was implemented using VHDL
MOORE MACHINE
AIM:
To write VHDL code for pattern detection using moore machine
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moore is
port(din:in std_logic;
clk:in std_logic;
rst:in std_logic;
q2:out std_logic;
q1:out std_logic;
q0:out std_logic;
detd:out std_logic);
end moore;
signal present_state,next_state:state_type;
begin
process(clk,rst)
begin
if (rst='0')then
present_state<=state0;
present_state<=next_state;
end if;
end process;
process(present_state,din)
begin
case present_state is
if (din ='0')then
next_state<=state0;
else
next_state<=state1;
end if;
if (din ='0')then
next_state<=state2;
else
next_state<=state1;
end if;
if (din ='0')then
next_state<=state3;
else
next_state<=state1;
end if;
if (din ='0')then
next_state<=state0;
else
next_state<=state4;
end if;
if (din ='0')then
next_state<=state0;
else
next_state<=state1;
end if;
end case;
end process;
end Behavioral;
Waveforms:
AIM:
To write VHDL code for finite state machine (FSM) based logic circuit
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seqdet is
port(m,clk:in bit;
p:out bit);
end seqdet;
signal state:state_type;
begin
process(clk)
begin
case state is
when x1=>p<='1';
if m='1'then
state<=x2;
else
state<=x1;
end if;
when x2=>p<='0';
if m='1' then
state<=x3;
else
state<=x2;
end if;
when x3=>p<='0';
if m='1' then
state <=x4;
else
end if;
when x4=>p<='0';
if m='1'then
state<=x1;
else
state<=x4;
end if;
end case;
end if;
end process;
end Behavioral;
Waveforms:
RESULT:
Thus finite state machine is implemented using VHDL
PARITY GENERATOR
AIM:
To write VHDL code for parity generator and simulate its results
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PARITY IS
PORT ( DIN : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
P : OUT STD_LOGIC);
END PARITY;
ARCHITECTURE BEHAVIORAL OF PARITY IS
SIGNAL T: STD_LOGIC:='0';
BEGIN
PROCESS (DIN,T)
BEGIN
T<=DIN (0);
FOR I IN 1 TO 7 LOOP
T<=T XOR DIN (I);
END LOOP;
P<=T;
END PROCESS;
END BEHAVIORAL;
The output wave form for the parity generator is shown in below
Waveforms:
Result:
Thus parity generator was implemented using VHDL
TRAFFIC LIGHT CONTROLLER
AIM:
To write VHDL code for traffic light controller and simulate its results
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity TRF is
Port ( CLK,RST : in STD_LOGIC;
RED,YELLOW,GREEN:OUT STD_LOGIC);
End TRF;
Architecture Behavioral of TRF is
SIGNAL COUNT:INTEGER RANGE 0 TO 10:=0;
SIGNAL STATE:INTEGER RANGE 0 TO 2:=0;
Begin
PROCESS (CLK,RST)
BEGIN
IF (RST='1') THEN
STATE<=0;
RED<='1';
GREEN<='0';
YELLOW<='0';
COUNT<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CASE STATE IS
WHEN 0=>
IF (COUNT=5) THEN
COUNT<=0;
STATE<=1;
ELSE
COUNT<=(COUNT+1);
RED<='1';
GREEN<='0';
YELLOW<='0';
END IF;
WHEN 1=>
IF (COUNT=5) THEN
COUNT<=0;
STATE<=2;
ELSE
COUNT<=COUNT+1;
RED<='0';
GREEN<='1';
YELLOW<='0';
END IF;
WHEN 2=>
IF (COUNT=2) THEN
COUNT<=0;
STATE<=0;
ELSE
COUNT<=COUNT+1;
RED<='0';
GREEN<='0';
YELLOW<='1';
END IF;
WHEN OTHERS=>
STATE<=0;
COUNT<=0;
END CASE;
END IF;
END PROCESS;
End Behavioral;
The output wave form for the traffic light controller is shown in below
Waveforms:
Result:
Thus traffic light controller was implemented using VHDL
CLOCK DIVIDER
AIM:
To write VHDL code for clock divider and simulate its results
APPARATUS:
Xilinx ISE 9.1i,Personal computer
PROGRAM:
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity CLKDIV is
GENERIC (N:POSITIVE:=8);
Port ( CLK,RST : in STD_LOGIC;
CLK_DIV : BUFFER STD_LOGIC);
End CLKDIV;
Architecture Behavioral of CLKDIV is
Begin
PROCESS (CLK,RST)
VARIABLE COUNT:NATURAL;
BEGIN
IF RST='0' THEN
COUNT:=0;
CLK_DIV<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
COUNT:=COUNT+1;
IF COUNT=N THEN
CLK_DIV<=NOT CLK_DIV;
COUNT:=0;
END IF;
END IF;
END PROCESS;
End Behavioral;
The output wave form for the clock divider is shown in below figure
Waveforms:
RESULT:
Thus clock divider was implemented using VHDL