SWARNANDHRA

COLLEGE OF ENGINEERING & TECHNOLOGY

(AUTONOMOUS)
SEETHARAMPURAM,NARSAPUR-534280,W.G DIST

19VL1L02-MOS Layout Design Laboratory

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 Software Requirements
S.No. Software Title Description
1 DSCH The DSCH program is logic editor and
Simulator.DSCH is used to validate the architecture
of logic circuit before the microelectronics design is
started.DSCH provides a user-friendly environment
for hierarchical logic design, and fast simulation with
delay analysis, which allows the design and
validation of complex logic structure. DSCH also
features the symbols, models and assembly support
for 8051 and 80f64. DSCH also includes an interface
to SPICE.

2 Microwind The Microwind program allows the student to design

and simulate an integrated circuit at physical
description level. The package contains a library of
common logic and analog ICs to view and simulate.
Microwind includes all the commands for a mask
editor as well as original tools never gathered before
in a single module (2D and 3D process view Verilog
Compiler, tutorial on MOS devices). You gain access
to circuit simulation by pressing one single key. The
electric extraction of your circuit is automatically
performed and the analog simulator produces voltage
and current curves immediately.

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Exp.No Experiment Title Page no

1. Introduction to Microwind and Analysis of CMOS

0.25 micron Technology MOSFETs
Layout of Basic Gates a n d c o m p l e x c i r c u i t using CMOS
2.
0.25 micron Technology in Microwind.
Layout of XOR and XNOR Gates using CMOS 0.25 micron
3.
Technology in Microwind.

4. Layout of Multiplexer using CMOS 0.25 micron Technology in

Microwind

5. Layout of Demultiplexer using CMOS 0.25 micron Technology

in Microwind

6. Layout of Shifter using CMOS 0.25 micron Technology in

Microwind

7. Design and implementation of Layout of Full Adder using

CMOS 0.25 micron Technology in Microwind
Design and implementation of Layout of 4-bit Subtractor using
8.
CMOS 0.25 micron Technology in Microwind
Design and implementation of Layout of 2-bit Comparator using
9.
CMOS 0.25 micron Technology in Microwind
Design and implementation of Layout of 4x4 bit Multiplier
10.
CMOS 0.25 micron Technology in Microwind
Design and implementation of Layout of RS-Latch in CMOS
11.
0.25 micron Technology inMicrowind
Design and implementation of Layout of D Latch in CMOS
12.
0.25 micron Technology inMicrowind
Design and implementation of Layout of Synchronous Counter
13.
in CMOS 0.25 micron Technologyin Microwind
Design and implementation of Layout of Asynchronous
14.
Counter in CMOS 0.25 micron Technologyin Microwind

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Exp.No:1 Introduction to Microwind and Analysis of
CMOS 0.25 micron Technology MOSFETs

Lab Objective: In this lab students will be introduced to a Layout based EDA
tool “Microwind” and the introduction will be accompanied with analysis of MOS
transistors. The tool used in this lab is Microwind.

The tasks given in the lab include,

1 Familiarity and Hands on Example using the tool.

2 Layout Design using the tool.
3 Study of MOSFET Characteristics.
4 Analog Simulation of MOSFETs.

Tool used: Microwind

Lab Description:
MOSFET
The Metal Oxide Semiconductor Field Effect Transistor is very important part of
Digital Integrated Circuits. It is mostly used as switch in digital design. MOSFET is a
four terminal device. The voltage applied to the gate terminal determine the current
flow between drain and source terminals. The body/substrate of the transistor is the
fourth terminal. Mostly the fourth terminal (body/substrate) of the device is
connected to dc supply that is identical for all devices of the same type (GND fro
nMOS and Vdd for pMOS). Usually this terminal is not shown on the schematics.
nMOS
The nMOS transistor consists of n+ drain and source diffusion regions, which are
embedded in a p-type substrate. The electrons in the channel beneath the gate
between source and drain terminal are responsible for the current flow.
pMOS
The pMOS transistor consists of p+ drain and source diffusion regions, which are
embedded in an n-type substrate. The holes in the channel beneath the gate
between source and drain terminal are responsible for the current flow.
CMOS
The CMOS (Complementary MOS) consist of both p-type and n-type MOS. The
advantage of CMOS is its low power design due its Static behavior.
Design/ Diagram/Circuit

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Lab Instructions
a) Open the Microwind2 by double clicking it located in the installed directory of
microwind2-7

The following screen will be appeared

b) Select the foundry using the command File > Select Foundry

c) Select 0.25-micron process by selecting “cmos025.tec” file. Click Open tab to

continue.

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d) Save the design as “Lab01” using the command File > Save as.
e) Create an nMOS by using the nMOS generator button in the Palette

You can set the width and length of MOS by typing in the fields Width MOS and
Length MOS either in micron or in lambda units as indicated in the above figure.
Click on Generate Device Tab to generate the device.

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f) Apply the voltages and output node using the symbol buttons Vdd, Gnd, Add a
Pulse, and Visible node in the Palette menu, as indicated in the following figure.
You can use the Stretch/Move command button for these actions.

g) Click on the Run Tab on the Tool bar menu to start the simulation or using the
command Simulate > Run Simulation.

h) Now apply the Vdd to the n+ diffusion or drain terminal instead of Vss, run
the simulation again.

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Analyze the simulation waveform, use different values of voltages for Vdd
by double clicking on it and set the voltage level. Now we will make the
above schematics.

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Similarly the nMOS can be analyzed using different widths and different input
voltages.

j) Save the design.

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 Exp.No:2 Layout of Basic Gates and complex circuit
using CMOS 0.25 micron Technology in
Microwind.

Lab Objective: In this lab students will design and implement the layouts of
different CMOS gates, which includes NAND, AND NOR, OR and a Complex Gate. The
tool used in this lab is Microwind.
The tasks given in the lab include,

.
• Design of CMOS NAND, AND, NOR, OR Gates and a Complex Gate.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of transistor
sizing on these parameters.
Tool used: Microwind

Lab Description:

a) NAND Gate
As per discussion and design on white board in the Lab, a NAND gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is
two. pFETs are connected in parallel while nFETs are connected in series, Vdd is
supplied to the parallel combination of pFETs while the series combination of nFETs is
grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is
obtained from the common junction of these series and parallel combinations as
illustrated in NAND circuit under the heading of Design Diagram/Circuit.
b) NOR Gate
As per discussion and design on white board in the Lab, a NOR gate can be implemented
using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is two. pFETs
are connected in series while nFETs are connected in parallel, Vdd is supplied to the
series combination of pFETs while the parallel combination of nFETs is grounded. Inputs
a & b are applied to the gate terminals of all FETs, and the output f is obtained from the
common junction of these parallel and series combinations as illustrated in NOR circuit
under the heading of Design Diagram/Circuit.

c) Complex Gate
The expression for the complex gate is given as under

As per discussion and design on white board in the Lab, this complex gate can be
implemented as under

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For pFETs Array
Group1: Three pFETs with inputs “c”, “d” and “d” at its gate terminals are connected in parallel.
Group2: Two pFETs with inputs “a” and “d” are in parallel and is connected in series with
Group1
For nFETs Array
Group1: Three nFETs with inputs “c”, “d” and “d” at its gate terminals are connected in series.
Group2: Two nFETs with inputs “a” and “d” are in series and is connected in parallel with
Group1

Design/ Diagram/Circuit

(a) Symbol, Truth Table and CMOS circuit of NAND Gate

(b)
Symbol, Truth Table and CMOS circuit of NOR Gate

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 Exp.No:3 Layout of XOR Gates using CMOS 0.25 micron
Technology in Microwind.

Lab Title:

Lab Objective: In this lab students will design and implement the layouts of XOR
and XNOR GateS. The tool used in this lab is Microwind.
.
The tasks given in the lab include,

• Design of XOR and XNOR Gates.

• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of transistor
sizing on these parameters
Tool used: Microwind Lab Description:

Figure: Schematic of XOR Gate

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Exp.No:4 Layout of Multiplexer using CMOS 0.25 micron
Technology in Microwind.
Lab Objective: In this lab students will design and implement the layouts of
Multiplexer. The tool used in this lab is Microwind. .
The tasks given in lab include:
• Design of Multiplexer.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters.

Tools used: Microwind

Lab Description:

Multiplexor
Generally speaking, a multiplexor is used to transmit a large amount of information
through a smaller number of connections. A digital multiplexor is a circuit that selects
binary information from one of many input logic signals and directs it to a single input
line. A behavioral description of the multiplexor is the case statement:The usual symbol
for the multiplexor is given in figure 6-67. It consists of the two multiplexed inputs
in0 and in1 on the left side, the command sel at the bottom of the symbol, and the
output f on the right.

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Exp.No:5 Design and implementation of Layout of Full Adder
using CMOS 0.25 micron Technology in Microwind.
Lab Objective: In this lab students will design and implement the layouts of Full
Adder.Delay, area, power and currents of full adder will be observed. This lab assumed that
students are familiar with Microwind and Lambda Based design rules. The tool used in this
lab is Microwind. .
The tasks given in lab include:
• Design of CMOS Full Adder layout.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters.

Tools used: Microwind Lab

Description:

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Exp.No:6 Design and implementation of Layout of 4-bit
Subtractor using CMOS 0.25 micron
Technology in Microwind..

Lab Objective: In this lab students will design and implement the layouts of 4-bit
Subtractor and 2-bit Comparator .Delay, area, power and currents of 4-bit Subtractor and 2-bit
Comparator will be observed. This lab assumed that students are familiar with Microwind
and Lambda Based design rules. The tool used in this lab is Microwind. .
The tasks given in lab include:
• Design of CMOS 4-bit Subtractor and 2-bit Comparator layout.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters.

Tools used: Microwind

Lab Description:
The substractor circuit can be built easily with a full adder structure as for the
adder circuit. The main difference is the needs for a 2's complement
circuit which inverts the value of b, and the replacement of the half adder
by a full adder, as the initial carry must be 1. The logic circuit corresponding
to the 4-bit substractor is reported in figure Some examples of substractor
results are also listed.

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Exp.No:7 Design and implementation of Layout of 4x4 bit
Multiplier CMOS 0.25 micron Technology in
Microwind.
Lab Objective: In this lab students will design and implement the layouts of 4x4 bit
Multiplier .Delay, area, power and currents of 4x4 bit Multiplier will be observed. This lab
assumed that students are familiar with Microwind and Lambda Based design rules. The tool
used in this lab is Microwind. .
The tasks given in lab include:
• Design of CMOS 4x4 bit Multiplier layout.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters. Lab
Description:

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 Exp.No:8 Design and implementation of Layout of RS-
Latch, D Latch, Dreg, Clock Divider in CMOS
0.25 micron Technology in Microwind.

Lab Objective: In this lab students will design and implement the layouts of RS- Latch, D
Latch, Dreg, Clock Divider .Delay, area, power and currents of RS-Latch, D Latch, Dreg,
Clock Divider will be observed. This lab assumed that students are familiar with Microwind
and Lambda Based design rules. The tool used in this lab is Microwind.
. The tasks
given in lab include:
• Design of CMOS RS-Latch, D Latch, Dreg, Clock Divider layout.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of
transistor sizing on these parameters. Lab
Description:

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